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| k60 sub-family reference manual supports: mk60dn256zvll10, mk60dx256zvll10, mk60dn512zvll10 document number: K60P100M100SF2RM rev. 6, nov 2011
k60 sub-family reference manual, rev. 6, nov 2011 2 freescale semiconductor, inc. contents section number title page chapter 1 about this document 1.1 overview ....................................................................................................................................................................... 57 1.1.1 purpose ......................................................................................................................................................... 57 1.1.2 audience ...................................................................................................................................................... 57 1.2 conventions .................................................................................................................................................................. 57 1.2.1 numbering systems ...................................................................................................................................... 57 1.2.2 typographic notation ................................................................................................................................... 58 1.2.3 special terms ................................................................................................................................................ 58 chapter 2 introduction 2.1 overview ....................................................................................................................................................................... 59 2.2 k60 family introduction............................................................................................................................................... 59 2.3 module functional categories ...................................................................................................................................... 59 2.3.1 arm cortex-m4 core modules .................................................................................................................. 61 2.3.2 system modules ........................................................................................................................................... 61 2.3.3 memories and memory interfaces ............................................................................................................... 62 2.3.4 clocks........................................................................................................................................................... 63 2.3.5 security and integrity modules .................................................................................................................... 63 2.3.6 analog modules ........................................................................................................................................... 64 2.3.7 timer modules ............................................................................................................................................. 64 2.3.8 communication interfaces ........................................................................................................................... 66 2.3.9 human-machine interfaces .......................................................................................................................... 66 2.4 orderable part numbers................................................................................................................................................. 67 chapter 3 chip configuration 3.1 introduction ................................................................................................................................................................... 69 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 3 section number title page 3.2 core modules ................................................................................................................................................................ 69 3.2.1 arm cortex-m4 core configuration.......................................................................................................... 69 3.2.2 nested vectored interrupt controller (nvic) configuration...................................................................... 72 3.2.3 asynchronous wake-up interrupt controller (awic) configuration ......................................................... 78 3.2.4 jtag controller configuration ................................................................................................................... 79 3.3 system modules ............................................................................................................................................................ 80 3.3.1 sim configuration ....................................................................................................................................... 80 3.3.2 mode controller configuration ................................................................................................................... 81 3.3.3 pmc configuration ...................................................................................................................................... 81 3.3.4 low-leakage wake-up unit (llwu) configuration ................................................................................. 82 3.3.5 mcm configuration .................................................................................................................................... 84 3.3.6 crossbar switch configuration .................................................................................................................... 84 3.3.7 memory protection unit (mpu) configuration........................................................................................... 87 3.3.8 peripheral bridge configuration .................................................................................................................. 89 3.3.9 dma request multiplexer configuration ...................................................................................................... 91 3.3.10 dma controller configuration ................................................................................................................... 94 3.3.11 external watchdog monitor (ewm) configuration .................................................................................... 95 3.3.12 watchdog configuration .............................................................................................................................. 96 3.4 clock modules .............................................................................................................................................................. 97 3.4.1 mcg configuration ..................................................................................................................................... 97 3.4.2 osc configuration ...................................................................................................................................... 98 3.4.3 rtc osc configuration............................................................................................................................... 99 3.5 memories and memory interfaces ................................................................................................................................ 99 3.5.1 flash memory configuration ....................................................................................................................... 99 3.5.2 flash memory controller configuration ..................................................................................................... 103 3.5.3 sram configuration ................................................................................................................................... 104 3.5.4 sram controller configuration ................................................................................................................. 108 k60 sub-family reference manual, rev. 6, nov 2011 4 freescale semiconductor, inc. section number title page 3.5.5 system register file configuration ............................................................................................................. 108 3.5.6 vbat register file configuration .............................................................................................................. 109 3.5.7 ezport configuration ................................................................................................................................... 110 3.5.8 flexbus configuration ................................................................................................................................. 111 3.6 security ......................................................................................................................................................................... 114 3.6.1 crc configuration ...................................................................................................................................... 114 3.6.2 mmcau configuration ............................................................................................................................... 115 3.6.3 rng configuration ...................................................................................................................................... 116 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 5 section number title page 3.7 analog ........................................................................................................................................................................... 116 3.7.1 16-bit sar adc with pga configuration ................................................................................................. 116 3.7.2 cmp configuration ...................................................................................................................................... 124 3.7.3 12-bit dac configuration ........................................................................................................................... 126 3.7.4 vref configuration .................................................................................................................................... 127 3.8 timers ........................................................................................................................................................................... 128 3.8.1 pdb configuration ...................................................................................................................................... 128 3.8.2 flextimer configuration ............................................................................................................................. 131 3.8.3 pit configuration ........................................................................................................................................ 135 3.8.4 low-power timer configuration ................................................................................................................... 136 3.8.5 cmt configuration...................................................................................................................................... 138 3.8.6 rtc configuration ....................................................................................................................................... 139 3.9 communication interfaces ............................................................................................................................................ 140 3.9.1 ethernet configuration ................................................................................................................................. 140 3.9.2 universal serial bus (usb) subsystem ....................................................................................................... 142 3.9.3 can configuration ...................................................................................................................................... 148 3.9.4 spi configuration ......................................................................................................................................... 150 3.9.5 i2c configuration ........................................................................................................................................ 153 3.9.6 uart configuration ................................................................................................................................... 154 3.9.7 sdhc configuration.................................................................................................................................... 157 3.9.8 i2s configuration.......................................................................................................................................... 158 3.10 human-machine interfaces (hmi) ................................................................................................................................ 160 3.10.1 gpio configuration ...................................................................................................................................... 160 3.10.2 tsi configuration ........................................................................................................................................ 161 chapter 4 memory map 4.1 introduction ................................................................................................................................................................... 165 4.2 system memory map..................................................................................................................................................... 165 4.2.1 aliased bit-band regions .............................................................................................................................. 166 k60 sub-family reference manual, rev. 6, nov 2011 6 freescale semiconductor, inc. section number title page 4.3 flash memory map ....................................................................................................................................................... 167 4.3.1 alternate non-volatile irc user trim description .................................................................................... 168 4.4 sram memory map ..................................................................................................................................................... 169 4.5 peripheral bridge (aips-lite0 and aips-lite1) memory maps ................................................................................... 169 4.5.1 peripheral bridge 0 (aips-lite 0) memory map ........................................................................................ 169 4.5.2 peripheral bridge 1 (aips-lite 1) memory map ........................................................................................ 173 4.6 private peripheral bus (ppb) memory map.................................................................................................................. 178 chapter 5 clock distribution 5.1 introduction ................................................................................................................................................................... 179 5.2 programming model...................................................................................................................................................... 179 5.3 high-level device clocking diagram ............................................................................................................................ 179 5.4 clock definitions ........................................................................................................................................................... 180 5.4.1 device clock summary ................................................................................................................................. 181 5.5 internal clocking requirements ..................................................................................................................................... 183 5.5.1 clock divider values after reset .................................................................................................................... 184 5.5.2 vlpr mode clocking ................................................................................................................................... 184 5.6 clock gating ................................................................................................................................................................. 185 5.7 module clocks ............................................................................................................................................................... 185 5.7.1 pmc 1-khz lpo clock ................................................................................................................................ 187 5.7.2 wdog clocking .......................................................................................................................................... 187 5.7.3 debug trace clock......................................................................................................................................... 187 5.7.4 port digital filter clocking ......................................................................................................................... 188 5.7.5 lptmr clocking.......................................................................................................................................... 188 5.7.6 ethernet clocking ........................................................................................................................................ 189 5.7.7 usb fs otg controller clocking ............................................................................................................... 189 5.7.8 flexcan clocking ....................................................................................................................................... 190 5.7.9 uart clocking ............................................................................................................................................ 190 5.7.10 sdhc clocking ............................................................................................................................................ 191 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 7 section number title page 5.7.11 i2s clocking ................................................................................................................................................. 191 5.7.12 tsi clocking ................................................................................................................................................. 192 chapter 6 reset and boot 6.1 introduction ................................................................................................................................................................... 193 6.2 reset.............................................................................................................................................................................. 193 6.2.1 power-on reset (por) .................................................................................................................................. 194 6.2.2 system resets ................................................................................................................................................ 194 6.2.3 debug resets ................................................................................................................................................. 197 6.3 boot ............................................................................................................................................................................... 199 6.3.1 boot sources ................................................................................................................................................. 199 6.3.2 boot options ................................................................................................................................................. 199 6.3.3 fopt boot options ....................................................................................................................................... 199 6.3.4 boot sequence .............................................................................................................................................. 200 chapter 7 power management 7.1 introduction ................................................................................................................................................................... 203 7.2 power modes ................................................................................................................................................................. 203 7.3 entering and exiting power modes ............................................................................................................................... 205 7.4 power mode transitions ................................................................................................................................................. 206 7.5 power modes shutdown sequencing ............................................................................................................................. 207 7.6 module operation in low power modes...................................................................................................................... 207 7.7 clock gating ................................................................................................................................................................. 210 chapter 8 security 8.1 introduction ................................................................................................................................................................... 211 8.2 flash security ............................................................................................................................................................... 211 8.3 security interactions with other modules ..................................................................................................................... 212 8.3.1 security interactions with flexbus .............................................................................................................. 212 8.3.2 security interactions with ezport ................................................................................................................ 212 k60 sub-family reference manual, rev. 6, nov 2011 8 freescale semiconductor, inc. section number title page 8.3.3 security interactions with debug ................................................................................................................. 212 chapter 9 debug 9.1 introduction ................................................................................................................................................................... 215 9.1.1 references .................................................................................................................................................... 217 9.2 the debug port ............................................................................................................................................................. 217 9.2.1 jtag-to-swd change sequence ................................................................................................................. 218 9.2.2 jtag-to-cjtag change sequence............................................................................................................... 218 9.3 debug port pin descriptions......................................................................................................................................... 219 9.4 system tap connection................................................................................................................................................ 219 9.4.1 ir codes ....................................................................................................................................................... 219 9.5 jtag status and control registers ................................................................................................................................. 220 9.5.1 mdm-ap control register .......................................................................................................................... 221 9.5.2 mdm-ap status register ............................................................................................................................ 223 9.6 debug resets ................................................................................................................................................................ 224 9.7 ahb-ap........................................................................................................................................................................ 225 9.8 itm ............................................................................................................................................................................... 226 9.9 core trace connectivity ............................................................................................................................................... 226 9.10 embedded trace macrocell v3.5 (etm) ...................................................................................................................... 226 9.11 coresight embedded trace buffer (etb) .................................................................................................................... 227 9.11.1 performance profiling with the etb ........................................................................................................... 227 9.11.2 etb counter control ................................................................................................................................... 228 9.12 tpiu.............................................................................................................................................................................. 228 9.13 dwt ............................................................................................................................................................................. 228 9.14 debug in low power modes ........................................................................................................................................ 229 9.14.1 debug module state in low power modes ................................................................................................. 230 9.15 debug & security ......................................................................................................................................................... 230 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 9 section number title page chapter 10 signal multiplexing and signal descriptions 10.1 introduction ................................................................................................................................................................... 231 10.2 signal multiplexing integration .................................................................................................................................... 231 10.2.1 port control and interrupt module features .................................................................................................. 232 10.2.2 clock gating ................................................................................................................................................. 232 10.2.3 signal multiplexing constraints .................................................................................................................... 232 10.3 pinout ............................................................................................................................................................................ 232 10.3.1 k60 signal multiplexing and pin assignments ........................................................................................... 233 10.3.2 k60 pinouts .................................................................................................................................................. 237 10.4 module signal description tables................................................................................................................................ 238 10.4.1 core modules ............................................................................................................................................... 238 10.4.2 system modules ........................................................................................................................................... 239 10.4.3 clock modules ............................................................................................................................................. 240 10.4.4 memories and memory interfaces ............................................................................................................... 240 10.4.5 analog .......................................................................................................................................................... 241 10.4.6 communication interfaces ........................................................................................................................... 243 10.4.7 human-machine interfaces (hmi) .............................................................................................................. 249 chapter 11 port control and interrupts (port) 11.1 introduction ................................................................................................................................................................... 251 11.1.1 overview ...................................................................................................................................................... 251 11.1.2 features ........................................................................................................................................................ 251 11.1.3 modes of operation ...................................................................................................................................... 252 11.2 external signal description............................................................................................................................................ 253 11.3 detailed signal descriptions .......................................................................................................................................... 253 11.4 memory map and register definition............................................................................................................................. 253 11.4.1 pin control register n (port x _pcr n )....................................................................................................... 260 11.4.2 global pin control low register (port x _gpclr) .................................................................................. 262 k60 sub-family reference manual, rev. 6, nov 2011 10 freescale semiconductor, inc. section number title page 11.4.3 global pin control high register (port x _gpchr) ................................................................................. 263 11.4.4 interrupt status flag register (port x _isfr) ............................................................................................ 263 11.4.5 digital filter enable register (port x _dfer)........................................................................................... 264 11.4.6 digital filter clock register (port x _dfcr) ............................................................................................ 265 11.4.7 digital filter width register (port x _dfwr) .......................................................................................... 265 11.5 functional description................................................................................................................................................... 266 11.5.1 pin control .................................................................................................................................................... 266 11.5.2 global pin control ........................................................................................................................................ 266 11.5.3 external interrupts ........................................................................................................................................ 267 11.5.4 digital filter .................................................................................................................................................. 268 chapter 12 system integration module (sim) 12.1 introduction ................................................................................................................................................................... 269 12.1.1 features ........................................................................................................................................................ 269 12.1.2 modes of operation ...................................................................................................................................... 269 12.1.3 sim signal descriptions .............................................................................................................................. 270 12.2 memory map and register definition............................................................................................................................. 270 12.2.1 system options register 1 (sim_sopt1) .................................................................................................. 272 12.2.2 system options register 2 (sim_sopt2) .................................................................................................. 274 12.2.3 system options register 4 (sim_sopt4) .................................................................................................. 276 12.2.4 system options register 5 (sim_sopt5) .................................................................................................. 279 12.2.5 system options register 6 (sim_sopt6) .................................................................................................. 280 12.2.6 system options register 7 (sim_sopt7) .................................................................................................. 281 12.2.7 system device identification register (sim_sdid)................................................................................... 283 12.2.8 system clock gating control register 1 (sim_scgc1) ............................................................................ 284 12.2.9 system clock gating control register 2 (sim_scgc2) ............................................................................ 285 12.2.10 system clock gating control register 3 (sim_scgc3) ............................................................................ 286 12.2.11 system clock gating control register 4 (sim_scgc4) ............................................................................ 287 12.2.12 system clock gating control register 5 (sim_scgc5) ............................................................................ 290 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 11 section number title page 12.2.13 system clock gating control register 6 (sim_scgc6) ............................................................................ 292 12.2.14 system clock gating control register 7 (sim_scgc7) ............................................................................ 294 12.2.15 system clock divider register 1 (sim_clkdiv1) ................................................................................... 295 12.2.16 system clock divider register 2 (sim_clkdiv2) ................................................................................... 298 12.2.17 flash configuration register 1 (sim_fcfg1) ........................................................................................... 299 12.2.18 flash configuration register 2 (sim_fcfg2) ........................................................................................... 301 12.2.19 unique identification register high (sim_uidh) ..................................................................................... 302 12.2.20 unique identification register mid-high (sim_uidmh) .......................................................................... 303 12.2.21 unique identification register mid low (sim_uidml) ........................................................................... 303 12.2.22 unique identification register low (sim_uidl) ...................................................................................... 304 12.3 functional description................................................................................................................................................... 304 chapter 13 mode controller 13.1 introduction ................................................................................................................................................................... 305 13.1.1 features ........................................................................................................................................................ 305 13.1.2 modes of operation ..................................................................................................................................... 305 13.1.3 mcu reset ................................................................................................................................................... 316 13.2 mode control memory map/register definition ......................................................................................................... 319 13.2.1 system reset status register high (mc_srsh) ........................................................................................ 320 13.2.2 system reset status register low (mc_srsl) ......................................................................................... 321 13.2.3 power mode protection register (mc_pmprot) ..................................................................................... 322 13.2.4 power mode control register (mc_pmctrl) .......................................................................................... 324 chapter 14 power management controller 14.1 introduction ................................................................................................................................................................... 327 14.2 features ......................................................................................................................................................................... 327 14.3 low-voltage detect (lvd) system ............................................................................................................................. 327 14.3.1 lvd reset operation................................................................................................................................... 328 14.3.2 lvd interrupt operation ............................................................................................................................. 328 k60 sub-family reference manual, rev. 6, nov 2011 12 freescale semiconductor, inc. section number title page 14.3.3 low-voltage warning (lvw) interrupt operation..................................................................................... 328 14.4 pmc memory map/register definition ....................................................................................................................... 329 14.4.1 low voltage detect status and control 1 register (pmc_lvdsc1) ........................................................ 329 14.4.2 low voltage detect status and control 2 register (pmc_lvdsc2) ........................................................ 330 14.4.3 regulator status and control register (pmc_regsc) .............................................................................. 332 chapter 15 low-leakage wake-up unit (llwu) 15.1 introduction ................................................................................................................................................................... 335 15.1.1 features ........................................................................................................................................................ 336 15.1.2 modes of operation ...................................................................................................................................... 336 15.1.3 block diagram .............................................................................................................................................. 337 15.2 llwu signal descriptions........................................................................................................................................... 338 15.3 memory map/register definition ................................................................................................................................... 339 15.3.1 llwu pin enable 1 register (llwu_pe1) .............................................................................................. 339 15.3.2 llwu pin enable 2 register (llwu_pe2) .............................................................................................. 340 15.3.3 llwu pin enable 3 register (llwu_pe3) .............................................................................................. 342 15.3.4 llwu pin enable 4 register (llwu_pe4) .............................................................................................. 343 15.3.5 llwu module enable register (llwu_me) ........................................................................................... 344 15.3.6 llwu flag 1 register (llwu_f1) ........................................................................................................... 345 15.3.7 llwu flag 2 register (llwu_f2) ........................................................................................................... 347 15.3.8 llwu flag 3 register (llwu_f3) ........................................................................................................... 349 15.3.9 llwu control and status register (llwu_cs) ....................................................................................... 350 15.4 functional description................................................................................................................................................... 351 15.4.1 lls mode ..................................................................................................................................................... 352 15.4.2 vlls modes ................................................................................................................................................ 352 15.4.3 initialization ................................................................................................................................................. 353 15.4.4 low power mode recovery .......................................................................................................................... 353 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 13 section number title page chapter 16 miscellaneous control module (mcm) 16.1 introduction ................................................................................................................................................................... 355 16.1.1 features ........................................................................................................................................................ 355 16.2 memory map/register descriptions ............................................................................................................................. 355 16.2.1 crossbar switch (axbs) slave configuration (mcm_plasc) .................................................................. 356 16.2.2 crossbar switch (axbs) master configuration (mcm_plamc) .............................................................. 356 16.2.3 sram arbitration and protection (mcm_sramap) ................................................................................. 357 16.2.4 interrupt status register (mcm_isr) ........................................................................................................... 358 16.2.5 etb counter control register (mcm_etbcc) ........................................................................................... 359 16.2.6 etb reload register (mcm_etbrl) .......................................................................................................... 360 16.2.7 etb counter value register (mcm_etbcnt) ........................................................................................... 361 16.3 functional description .................................................................................................................................................. 361 16.3.1 interrupts ...................................................................................................................................................... 361 chapter 17 crossbar switch (axbs) 17.1 introduction ................................................................................................................................................................... 363 17.1.1 features ........................................................................................................................................................ 363 17.2 memory map / register definition............................................................................................................................... 364 17.2.1 priority registers slave (axbs_prs n ) ...................................................................................................... 365 17.2.2 control register (axbs_crs n ) ................................................................................................................. 368 17.2.3 master general purpose control register (axbs_mgpcr n ) ................................................................... 370 17.3 functional description .................................................................................................................................................. 371 17.3.1 general operation ......................................................................................................................................... 371 17.3.2 register coherency ....................................................................................................................................... 372 17.3.3 arbitration .................................................................................................................................................... 372 17.4 initialization/application information ........................................................................................................................... 375 chapter 18 memory protection unit (mpu) 18.1 introduction ................................................................................................................................................................... 377 k60 sub-family reference manual, rev. 6, nov 2011 14 freescale semiconductor, inc. section number title page 18.2 overview ....................................................................................................................................................................... 377 18.2.1 block diagram ............................................................................................................................................. 377 18.2.2 features ........................................................................................................................................................ 378 18.3 memory map/register definition................................................................................................................................. 379 18.3.1 control/error status register (mpu_cesr) .............................................................................................. 382 18.3.2 error address register, slave port n (mpu_ear n ) ................................................................................... 384 18.3.3 error detail register, slave port n (mpu_edr n ) ...................................................................................... 385 18.3.4 region descriptor n, word 0 (mpu_rgd n _word0) .............................................................................. 386 18.3.5 region descriptor n, word 1 (mpu_rgd n _word1) .............................................................................. 387 18.3.6 region descriptor n, word 2 (mpu_rgd n _word2) .............................................................................. 387 18.3.7 region descriptor n, word 3 (mpu_rgd n _word3) .............................................................................. 390 18.3.8 region descriptor alternate access control n (mpu_rgdaac n )........................................................... 391 18.4 functional description .................................................................................................................................................. 393 18.4.1 access evaluation macro............................................................................................................................. 393 18.4.2 putting it all together and error terminations........................................................................................... 394 18.4.3 power management...................................................................................................................................... 395 18.5 initialization information .............................................................................................................................................. 395 18.6 application information................................................................................................................................................ 395 chapter 19 peripheral bridge (aips-lite) 19.1 introduction ................................................................................................................................................................... 399 19.1.1 features ........................................................................................................................................................ 399 19.1.2 general operation ......................................................................................................................................... 399 19.2 memory map/register definition ................................................................................................................................... 400 19.2.1 master privilege register a (aips x _mpra) ............................................................................................. 401 19.2.2 peripheral access control register (aips x _pacr n ) ................................................................................. 405 19.2.3 peripheral access control register (aips x _pacr n ) ................................................................................. 410 19.3 functional description .................................................................................................................................................. 415 19.3.1 access support ............................................................................................................................................. 415 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 15 section number title page chapter 20 direct memory access multiplexer (dmamux) 20.1 introduction ................................................................................................................................................................... 417 20.1.1 overview ...................................................................................................................................................... 417 20.1.2 features ........................................................................................................................................................ 418 20.1.3 modes of operation ...................................................................................................................................... 418 20.2 external signal description............................................................................................................................................ 419 20.3 memory map/register definition ................................................................................................................................... 419 20.3.1 channel configuration register (dmamux_chcfg n ) ........................................................................... 420 20.4 functional description................................................................................................................................................... 421 20.4.1 dma channels with periodic triggering capability...................................................................................... 421 20.4.2 dma channels with no triggering capability ............................................................................................... 424 20.4.3 "always enabled" dma sources ................................................................................................................. 424 20.5 initialization/application information ........................................................................................................................... 425 20.5.1 reset ............................................................................................................................................................. 425 20.5.2 enabling and configuring sources ................................................................................................................ 425 chapter 21 direct memory access controller (edma) 21.1 introduction ................................................................................................................................................................... 429 21.1.1 block diagram .............................................................................................................................................. 429 21.1.2 block parts ................................................................................................................................................... 430 21.1.3 features ........................................................................................................................................................ 432 21.2 modes of operation ....................................................................................................................................................... 433 21.3 memory map/register definition ................................................................................................................................... 433 21.3.1 control register (dma_cr) ....................................................................................................................... 448 21.3.2 error status register (dma_es) ................................................................................................................ 450 21.3.3 enable request register (dma_erq) ....................................................................................................... 452 21.3.4 enable error interrupt register (dma_eei)............................................................................................... 454 21.3.5 clear enable error interrupt register (dma_ceei) .................................................................................. 456 k60 sub-family reference manual, rev. 6, nov 2011 16 freescale semiconductor, inc. section number title page 21.3.6 set enable error interrupt register (dma_seei) ...................................................................................... 457 21.3.7 clear enable request register (dma_cerq) ........................................................................................... 458 21.3.8 set enable request register (dma_serq) ............................................................................................... 459 21.3.9 clear done status bit register (dma_cdne) ........................................................................................ 460 21.3.10 set start bit register (dma_ssrt) ...................................................................................................... 461 21.3.11 clear error register (dma_cerr) ............................................................................................................ 462 21.3.12 clear interrupt request register (dma_cint) ......................................................................................... 463 21.3.13 interrupt request register (dma_int) ...................................................................................................... 463 21.3.14 error register (dma_err) ........................................................................................................................ 466 21.3.15 hardware request status register (dma_hrs) ........................................................................................ 468 21.3.16 channel n priority register (dma_dchpri n ) .......................................................................................... 470 21.3.17 tcd source address (dma_tcd n _saddr) ........................................................................................... 471 21.3.18 tcd signed source address offset (dma_tcd n _soff) ........................................................................ 472 21.3.19 tcd transfer attributes (dma_tcd n _attr) ......................................................................................... 472 21.3.20 tcd minor byte count (minor loop disabled) (dma_tcd n _nbytes_mlno) ................................. 473 21.3.21 tcd signed minor loop offset (minor loop enabled and offset disabled) (dma_tcd n _nbytes_mloffno) ....................................................................................................... 474 21.3.22 tcd signed minor loop offset (minor loop and offset enabled) (dma_tcd n _nbytes_mloffyes) ..................................................................................................... 475 21.3.23 tcd last source address adjustment (dma_tcd n _slast) ................................................................. 476 21.3.24 tcd destination address (dma_tcd n _daddr) ................................................................................... 476 21.3.25 tcd signed destination address offset (dma_tcd n _doff) ................................................................ 477 21.3.26 tcd current minor loop link, major loop count (channel linking enabled) (dma_tcd n _citer_elinkyes)........................................................................................................... 477 21.3.27 tcd current minor loop link, major loop count (channel linking disabled) (dma_tcd n _citer_elinkno) ............................................................................................................ 478 21.3.28 tcd last destination address adjustment/scatter gather address (dma_tcd n _dlastsga) .......... 479 21.3.29 tcd control and status (dma_tcd n _csr) ............................................................................................ 480 21.3.30 tcd beginning minor loop link, major loop count (channel linking enabled) (dma_tcd n _biter_elinkyes)........................................................................................................... 482 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 17 section number title page 21.3.31 tcd beginning minor loop link, major loop count (channel linking disabled) (dma_tcd n _biter_elinkno) ............................................................................................................ 483 21.4 functional description................................................................................................................................................... 484 21.4.1 edma basic data flow ................................................................................................................................. 484 21.4.2 error reporting and handling ........................................................................................................................ 487 21.4.3 channel preemption ..................................................................................................................................... 489 21.4.4 performance ................................................................................................................................................. 489 21.5 initialization/application information ........................................................................................................................... 493 21.5.1 edma initialization ..................................................................................................................................... 493 21.5.2 programming errors ..................................................................................................................................... 495 21.5.3 arbitration mode considerations .................................................................................................................. 496 21.5.4 performing dma transfers .......................................................................................................................... 496 21.5.5 monitoring transfer descriptor status ........................................................................................................... 500 21.5.6 dynamic programming ................................................................................................................................ 502 chapter 22 external watchdog monitor (ewm) 22.1 introduction ................................................................................................................................................................... 505 22.1.1 features ........................................................................................................................................................ 505 22.1.2 modes of operation ..................................................................................................................................... 506 22.1.3 block diagram ............................................................................................................................................. 507 22.2 ewm signal descriptions ............................................................................................................................................ 508 22.3 memory map/register definition................................................................................................................................. 508 22.3.1 control register (ewm_ctrl) ................................................................................................................. 508 22.3.2 service register (ewm_serv) .................................................................................................................. 509 22.3.3 compare low register (ewm_cmpl) ...................................................................................................... 510 22.3.4 compare high register (ewm_cmph) ..................................................................................................... 510 22.4 functional description .................................................................................................................................................. 511 22.4.1 the ewm_out signal .................................................................................................................................. 511 22.4.2 the ewm_in signal .................................................................................................................................... 512 k60 sub-family reference manual, rev. 6, nov 2011 18 freescale semiconductor, inc. section number title page 22.4.3 ewm counter .............................................................................................................................................. 512 22.4.4 ewm compare registers ............................................................................................................................ 512 22.4.5 ewm refresh mechanism ........................................................................................................................... 513 chapter 23 watchdog timer (wdog) 23.1 introduction ................................................................................................................................................................... 515 23.2 features ......................................................................................................................................................................... 515 23.3 functional overview..................................................................................................................................................... 517 23.3.1 unlocking and updating the watchdog ....................................................................................................... 518 23.3.2 the watchdog configuration time (wct)................................................................................................. 519 23.3.3 refreshing the watchdog ............................................................................................................................. 520 23.3.4 windowed mode of operation .................................................................................................................... 520 23.3.5 watchdog disabled mode of operation ...................................................................................................... 520 23.3.6 low power modes of operation .................................................................................................................. 521 23.3.7 debug modes of operation .......................................................................................................................... 521 23.4 testing the watchdog ................................................................................................................................................... 522 23.4.1 quick test .................................................................................................................................................... 522 23.4.2 byte test ...................................................................................................................................................... 522 23.5 backup reset generator ............................................................................................................................................... 524 23.6 generated resets and interrupts ................................................................................................................................... 524 23.7 memory map and register definition .......................................................................................................................... 525 23.7.1 watchdog status and control register high (wdog_stctrlh) ........................................................... 526 23.7.2 watchdog status and control register low (wdog_stctrll) ............................................................ 528 23.7.3 watchdog time-out value register high (wdog_tovalh) ................................................................. 528 23.7.4 watchdog time-out value register low (wdog_tovall) .................................................................. 529 23.7.5 watchdog window register high (wdog_winh) .................................................................................. 529 23.7.6 watchdog window register low (wdog_winl) ................................................................................... 530 23.7.7 watchdog refresh register (wdog_refresh) ...................................................................................... 530 23.7.8 watchdog unlock register (wdog_unlock) ....................................................................................... 530 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 19 section number title page 23.7.9 watchdog timer output register high (wdog_tmrouth) ................................................................. 531 23.7.10 watchdog timer output register low (wdog_tmroutl) .................................................................. 531 23.7.11 watchdog reset count register (wdog_rstcnt) ................................................................................. 532 23.7.12 watchdog prescaler register (wdog_presc) ......................................................................................... 532 23.8 watchdog operation with 8-bit access ......................................................................................................................... 532 23.8.1 general guideline ........................................................................................................................................ 532 23.8.2 refresh and unlock operations with 8-bit access ........................................................................................ 533 23.9 restrictions on watchdog operation ............................................................................................................................ 534 chapter 24 multipurpose clock generator (mcg) 24.1 introduction ................................................................................................................................................................... 537 24.1.1 features ........................................................................................................................................................ 537 24.1.2 modes of operation ..................................................................................................................................... 540 24.2 external signal description .......................................................................................................................................... 541 24.3 memory map/register definition................................................................................................................................. 541 24.3.1 mcg control 1 register (mcg_c1)........................................................................................................... 542 24.3.2 mcg control 2 register (mcg_c2)........................................................................................................... 543 24.3.3 mcg control 3 register (mcg_c3)........................................................................................................... 544 24.3.4 mcg control 4 register (mcg_c4)........................................................................................................... 545 24.3.5 mcg control 5 register (mcg_c5)........................................................................................................... 546 24.3.6 mcg control 6 register (mcg_c6)........................................................................................................... 548 24.3.7 mcg status register (mcg_s) .................................................................................................................. 549 24.3.8 mcg auto trim control register (mcg_atc) ........................................................................................ 551 24.3.9 mcg auto trim compare value high register (mcg_atcvh) ............................................................ 551 24.3.10 mcg auto trim compare value low register (mcg_atcvl).............................................................. 552 24.4 functional description .................................................................................................................................................. 552 24.4.1 mcg mode state diagram .......................................................................................................................... 552 24.4.2 low power bit usage .................................................................................................................................. 557 k60 sub-family reference manual, rev. 6, nov 2011 20 freescale semiconductor, inc. section number title page 24.4.3 mcg internal reference clocks .................................................................................................................. 557 24.4.4 external reference clock ............................................................................................................................ 558 24.4.5 mcg fixed frequency clock ..................................................................................................................... 558 24.4.6 mcg pll clock ......................................................................................................................................... 559 24.4.7 mcg auto trim (atm) ............................................................................................................................ 559 24.5 initialization / application information ........................................................................................................................ 560 24.5.1 mcg module initialization sequence ......................................................................................................... 560 24.5.2 using a 32.768 khz reference .................................................................................................................... 562 24.5.3 mcg mode switching ................................................................................................................................. 563 chapter 25 oscillator (osc) 25.1 introduction ................................................................................................................................................................... 573 25.2 features and modes ...................................................................................................................................................... 573 25.3 block diagram .............................................................................................................................................................. 574 25.4 osc signal descriptions .............................................................................................................................................. 574 25.5 external crystal / resonator connections .................................................................................................................... 575 25.6 external clock connections ......................................................................................................................................... 576 25.7 memory map/register definitions ............................................................................................................................... 577 25.7.1 osc memory map/register definition ....................................................................................................... 577 25.8 functional description .................................................................................................................................................. 578 25.8.1 osc module states ...................................................................................................................................... 578 25.8.2 osc module modes..................................................................................................................................... 580 25.8.3 counter ......................................................................................................................................................... 582 25.8.4 reference clock pin requirements ............................................................................................................. 582 25.9 reset.............................................................................................................................................................................. 582 25.10 low power modes operation ....................................................................................................................................... 583 25.11 interrupts ....................................................................................................................................................................... 583 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 21 section number title page chapter 26 rtc oscillator 26.1 introduction ................................................................................................................................................................... 585 26.1.1 features and modes ..................................................................................................................................... 585 26.1.2 block diagram ............................................................................................................................................. 585 26.2 rtc signal descriptions .............................................................................................................................................. 586 26.2.1 extal32 oscillator input ..................................................................................................................... 586 26.2.2 xtal32 oscillator output ..................................................................................................................... 586 26.3 external crystal connections ....................................................................................................................................... 587 26.4 memory map/register descriptions ............................................................................................................................. 587 26.5 functional description .................................................................................................................................................. 587 26.6 reset overview ............................................................................................................................................................. 588 26.7 interrupts ....................................................................................................................................................................... 588 chapter 27 flash memory controller (fmc) 27.1 introduction ................................................................................................................................................................... 589 27.1.1 overview ...................................................................................................................................................... 589 27.1.2 features ........................................................................................................................................................ 590 27.2 modes of operation ....................................................................................................................................................... 590 27.3 external signal description............................................................................................................................................ 590 27.4 memory map and register descriptions ......................................................................................................................... 591 27.4.1 flash access protection register (fmc_pfapr)....................................................................................... 597 27.4.2 flash bank 0 control register (fmc_pfb0cr) ........................................................................................ 600 27.4.3 flash bank 1 control register (fmc_pfb1cr) ........................................................................................ 603 27.4.4 cache tag storage (fmc_tagvdw0s n ) ................................................................................................. 605 27.4.5 cache tag storage (fmc_tagvdw1s n ) ................................................................................................. 606 27.4.6 cache tag storage (fmc_tagvdw2s n ) ................................................................................................. 607 27.4.7 cache tag storage (fmc_tagvdw3s n ) ................................................................................................. 608 27.4.8 cache data storage (upper word) (fmc_dataw0s n u) .......................................................................... 609 k60 sub-family reference manual, rev. 6, nov 2011 22 freescale semiconductor, inc. section number title page 27.4.9 cache data storage (lower word) (fmc_dataw0s n l) .......................................................................... 610 27.4.10 cache data storage (upper word) (fmc_dataw1s n u) .......................................................................... 611 27.4.11 cache data storage (lower word) (fmc_dataw1s n l) .......................................................................... 612 27.4.12 cache data storage (upper word) (fmc_dataw2s n u) .......................................................................... 613 27.4.13 cache data storage (lower word) (fmc_dataw2s n l) .......................................................................... 614 27.4.14 cache data storage (upper word) (fmc_dataw3s n u) .......................................................................... 615 27.4.15 cache data storage (lower word) (fmc_dataw3s n l) .......................................................................... 616 27.5 functional description................................................................................................................................................... 616 chapter 28 flash memory module (ftfl) 28.1 introduction ................................................................................................................................................................... 619 28.1.1 features ........................................................................................................................................................ 620 28.1.2 block diagram ............................................................................................................................................. 622 28.1.3 glossary ....................................................................................................................................................... 623 28.2 external signal description .......................................................................................................................................... 625 28.3 memory map and registers .......................................................................................................................................... 625 28.3.1 flash configuration field description ......................................................................................................... 626 28.3.2 program flash ifr map ............................................................................................................................... 626 28.3.3 data flash ifr map ..................................................................................................................................... 627 28.3.4 register descriptions ................................................................................................................................... 629 28.4 functional description .................................................................................................................................................. 642 28.4.1 program flash memory swap...................................................................................................................... 642 28.4.2 flash protection............................................................................................................................................ 642 28.4.3 flexnvm description.................................................................................................................................. 644 28.4.4 interrupts ...................................................................................................................................................... 649 28.4.5 flash operation in low-power modes ........................................................................................................ 650 28.4.6 functional modes of operation ................................................................................................................... 650 28.4.7 flash reads and ignored writes .................................................................................................................. 650 28.4.8 read while write (rww) ........................................................................................................................... 651 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 23 section number title page 28.4.9 flash program and erase.............................................................................................................................. 651 28.4.10 ftfl command operations ........................................................................................................................ 651 28.4.11 margin read commands ............................................................................................................................. 660 28.4.12 ftfl command description ....................................................................................................................... 661 28.4.13 security ........................................................................................................................................................ 689 28.4.14 reset sequence ............................................................................................................................................ 691 chapter 29 external bus interface (flexbus) 29.1 introduction ................................................................................................................................................................... 693 29.1.1 overview ...................................................................................................................................................... 693 29.1.2 features ........................................................................................................................................................ 693 29.1.3 modes of operation ..................................................................................................................................... 694 29.2 signal descriptions ....................................................................................................................................................... 694 29.2.1 address and data buses (fb_an, fb_dn, fb_adn) ................................................................................. 695 29.2.2 chip selects (fb_cs[5 :0]) ......................................................................................................................... 695 29.2.3 byte enables (fb_be_31_24, fb_be_23_16, fb_be_15_8, fb_be_7_0) ............................................. 696 29.2.4 output enable (fb_oe)............................................................................................................................... 696 29.2.5 read/write (fb_r/w) ................................................................................................................................. 696 29.2.6 transfer start/address latch enable (fb_ts/fb_ale) ............................................................................ 696 29.2.7 transfer size (fb_tsiz[1:0]) ..................................................................................................................... 697 29.2.8 transfer burst (fb_tbst) .......................................................................................................................... 697 29.2.9 transfer acknowledge (fb_ta) ................................................................................................................. 698 29.3 memory map/register definition................................................................................................................................. 698 29.3.1 chip select address register (fb_csar n ) ................................................................................................... 700 29.3.2 chip select mask register (fb_csmr n ) ...................................................................................................... 701 29.3.3 chip select control register (fb_cscr n ) .................................................................................................... 702 29.3.4 chip select port multiplexing control register (fb_cspmcr) ................................................................... 705 k60 sub-family reference manual, rev. 6, nov 2011 24 freescale semiconductor, inc. section number title page 29.4 functional description .................................................................................................................................................. 706 29.4.1 chip-select operation .................................................................................................................................. 706 29.4.2 data transfer operation............................................................................................................................... 708 29.4.3 data byte alignment and physical connections ......................................................................................... 708 29.4.4 address/data bus multiplexing ................................................................................................................... 709 29.4.5 bus cycle execution .................................................................................................................................... 710 29.4.6 flexbus timing examples ........................................................................................................................... 712 29.4.7 burst cycles ................................................................................................................................................. 730 29.4.8 extended transfer start/address latch enable ........................................................................................... 739 29.4.9 bus errors .................................................................................................................................................... 739 29.5 initialization/application information .......................................................................................................................... 740 29.5.1 initializing a chip select .............................................................................................................................. 740 29.5.2 reconfiguring a chip select ........................................................................................................................ 740 chapter 30 ezport 30.1 overview ....................................................................................................................................................................... 741 30.1.1 introduction .................................................................................................................................................. 741 30.1.2 features ........................................................................................................................................................ 742 30.1.3 modes of operation ..................................................................................................................................... 742 30.2 external signal description .......................................................................................................................................... 743 30.2.1 ezport clock (ezp_ck) .............................................................................................................................. 743 30.2.2 ezport chip select (ezp_cs)...................................................................................................................... 743 30.2.3 ezport serial data in (ezp_d) .................................................................................................................... 744 30.2.4 ezport serial data out (ezp_q) ................................................................................................................. 744 30.3 command definition .................................................................................................................................................... 744 30.3.1 command descriptions ................................................................................................................................ 745 30.4 flash memory map for ezport access ......................................................................................................................... 751 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 25 section number title page chapter 31 cyclic redundancy check (crc) 31.1 introduction ................................................................................................................................................................... 753 31.1.1 features ........................................................................................................................................................ 753 31.1.2 block diagram .............................................................................................................................................. 753 31.1.3 modes of operation ...................................................................................................................................... 754 31.2 memory map and register descriptions ......................................................................................................................... 754 31.2.1 crc data register (crc_crc) ................................................................................................................. 755 31.2.2 crc polynomial register (crc_gpoly) ................................................................................................. 756 31.2.3 crc control register (crc_ctrl) .......................................................................................................... 757 31.3 functional description................................................................................................................................................... 758 31.3.1 crc initialization/re-initialization ............................................................................................................... 758 31.3.2 crc calculations.......................................................................................................................................... 758 31.3.3 transpose feature ......................................................................................................................................... 759 31.3.4 crc result complement ............................................................................................................................... 761 chapter 32 memory-mapped cryptographic acceleration unit (mmcau) 32.1 introduction ................................................................................................................................................................... 763 32.2 mmcau block diagram ............................................................................................................................................. 763 32.3 overview ....................................................................................................................................................................... 765 32.4 features ......................................................................................................................................................................... 766 32.5 memory map/register definition................................................................................................................................. 766 32.5.1 status register (cau_casr) ..................................................................................................................... 768 32.5.2 accumulator (cau_caa) .......................................................................................................................... 769 32.5.3 general purpose register (cau_ca n ) ....................................................................................................... 769 k60 sub-family reference manual, rev. 6, nov 2011 26 freescale semiconductor, inc. section number title page 32.6 functional description .................................................................................................................................................. 770 32.6.1 mmcau programming model .................................................................................................................... 770 32.6.2 mmcau integrity checks........................................................................................................................... 772 32.6.3 cau commands .......................................................................................................................................... 774 32.7 application/initialization information .......................................................................................................................... 781 32.7.1 code example .............................................................................................................................................. 781 32.7.2 assembler equate values ............................................................................................................................ 781 chapter 33 random number generator (rngb) 33.1 introduction ................................................................................................................................................................... 783 33.1.1 block diagram ............................................................................................................................................. 783 33.1.2 features ........................................................................................................................................................ 784 33.2 modes of operation ...................................................................................................................................................... 784 33.2.1 self test mode ............................................................................................................................................. 784 33.2.2 seed generation mode ................................................................................................................................. 785 33.2.3 random number generation mode ............................................................................................................. 785 33.3 memory map/register definition................................................................................................................................. 785 33.3.1 rngb version id register (rng_ver) ................................................................................................... 786 33.3.2 rngb command register (rng_cmd) ................................................................................................... 787 33.3.3 rngb control register (rng_cr)............................................................................................................ 788 33.3.4 rngb status register (rng_sr) .............................................................................................................. 790 33.3.5 rngb error status register (rng_esr)................................................................................................... 792 33.3.6 rngb output fifo (rng_out) .............................................................................................................. 793 33.4 functional description .................................................................................................................................................. 794 33.4.1 pseudorandom number generator (prng) ................................................................................................ 794 33.4.2 true random number generator (trng) .................................................................................................. 794 33.4.3 resets ........................................................................................................................................................... 794 33.4.4 rng interrupts ............................................................................................................................................. 795 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 27 section number title page 33.5 initialization/application information .......................................................................................................................... 796 33.5.1 manual seeding............................................................................................................................................ 796 33.5.2 automatic seeding ....................................................................................................................................... 797 chapter 34 analog-to-digital converter (adc) 34.1 introduction ................................................................................................................................................................... 799 34.1.1 features ........................................................................................................................................................ 799 34.1.2 block diagram .............................................................................................................................................. 800 34.2 adc signal descriptions.............................................................................................................................................. 801 34.2.1 analog power (vdda) ................................................................................................................................ 802 34.2.2 analog ground (vssa) ................................................................................................................................ 802 34.2.3 voltage reference select ............................................................................................................................... 802 34.2.4 analog channel inputs (adx) ...................................................................................................................... 803 34.2.5 differential analog channel inputs (dadx) ................................................................................................. 803 34.3 register definition ........................................................................................................................................................ 803 34.3.1 adc status and control registers 1 (adc x _sc1 n ) ...................................................................................... 806 34.3.2 adc configuration register 1 (adc x _cfg1) ............................................................................................. 809 34.3.3 configuration register 2 (adc x _cfg2)...................................................................................................... 811 34.3.4 adc data result register (adc x _r n ) .......................................................................................................... 812 34.3.5 compare value registers (adc x _cv n ) ....................................................................................................... 813 34.3.6 status and control register 2 (adc x _sc2) .................................................................................................. 814 34.3.7 status and control register 3 (adc x _sc3) .................................................................................................. 816 34.3.8 adc offset correction register (adc x _ofs) .............................................................................................. 817 34.3.9 adc plus-side gain register (adc x _pg) .................................................................................................... 818 34.3.10 adc minus-side gain register (adc x _mg) ............................................................................................... 818 34.3.11 adc plus-side general calibration value register (adc x _clpd) .............................................................. 819 34.3.12 adc plus-side general calibration value register (adc x _clps) ............................................................... 820 34.3.13 adc plus-side general calibration value register (adc x _clp4) ............................................................... 820 34.3.14 adc plus-side general calibration value register (adc x _clp3) ............................................................... 821 k60 sub-family reference manual, rev. 6, nov 2011 28 freescale semiconductor, inc. section number title page 34.3.15 adc plus-side general calibration value register (adc x _clp2) ............................................................... 821 34.3.16 adc plus-side general calibration value register (adc x _clp1) ............................................................... 822 34.3.17 adc plus-side general calibration value register (adc x _clp0) ............................................................... 822 34.3.18 adc pga register (adc x _pga) ............................................................................................................... 823 34.3.19 adc minus-side general calibration value register (adc x _clmd) .......................................................... 824 34.3.20 adc minus-side general calibration value register (adc x _clms) .......................................................... 825 34.3.21 adc minus-side general calibration value register (adc x _clm4)........................................................... 825 34.3.22 adc minus-side general calibration value register (adc x _clm3)........................................................... 826 34.3.23 adc minus-side general calibration value register (adc x _clm2)........................................................... 826 34.3.24 adc minus-side general calibration value register (adc x _clm1)........................................................... 827 34.3.25 adc minus-side general calibration value register (adc x _clm0)........................................................... 827 34.4 functional description................................................................................................................................................... 828 34.4.1 pga functional description .......................................................................................................................... 828 34.4.2 clock select and divide control .................................................................................................................... 829 34.4.3 voltage reference selection .......................................................................................................................... 829 34.4.4 hardware trigger and channel selects .......................................................................................................... 830 34.4.5 conversion control ....................................................................................................................................... 831 34.4.6 automatic compare function ........................................................................................................................ 838 34.4.7 calibration function ..................................................................................................................................... 839 34.4.8 user defined offset function ......................................................................................................................... 841 34.4.9 temperature sensor ...................................................................................................................................... 842 34.4.10 mcu wait mode operation ........................................................................................................................... 842 34.4.11 mcu normal stop mode operation ............................................................................................................. 843 34.4.12 mcu low power stop mode operation ....................................................................................................... 844 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 29 section number title page 34.5 initialization information .............................................................................................................................................. 844 34.5.1 adc module initialization example ............................................................................................................ 845 34.6 application information ................................................................................................................................................ 847 34.6.1 external pins and routing ............................................................................................................................. 847 34.6.2 sources of error ............................................................................................................................................ 849 chapter 35 comparator (cmp) 35.1 introduction ................................................................................................................................................................... 855 35.2 cmp features................................................................................................................................................................ 855 35.3 6-bit dac key features ............................................................................................................................................... 856 35.4 anmux key features ................................................................................................................................................. 857 35.5 cmp, dac, and anmux diagram ............................................................................................................................. 857 35.6 cmp block diagram..................................................................................................................................................... 858 35.7 memory map/register definitions ............................................................................................................................... 860 35.7.1 cmp control register 0 (cmp x _cr0) ....................................................................................................... 861 35.7.2 cmp control register 1 (cmp x _cr1) ....................................................................................................... 862 35.7.3 cmp filter period register (cmp x _fpr) ................................................................................................... 863 35.7.4 cmp status and control register (cmp x _scr) ......................................................................................... 864 35.7.5 dac control register (cmp x _daccr) .................................................................................................... 865 35.7.6 mux control register (cmp x _muxcr) .................................................................................................. 866 35.8 cmp functional description ........................................................................................................................................ 867 35.8.1 cmp functional modes ............................................................................................................................... 868 35.8.2 power modes................................................................................................................................................ 877 35.8.3 startup and operation .................................................................................................................................. 878 35.8.4 low pass filter............................................................................................................................................. 879 35.9 cmp interrupts.............................................................................................................................................................. 881 35.10 cmp dma support ...................................................................................................................................................... 881 35.11 digital to analog converter block diagram ................................................................................................................ 881 k60 sub-family reference manual, rev. 6, nov 2011 30 freescale semiconductor, inc. section number title page 35.12 dac functional description ........................................................................................................................................ 882 35.12.1 voltage reference source select ................................................................................................................. 882 35.13 dac resets................................................................................................................................................................... 882 35.14 dac clocks .................................................................................................................................................................. 882 35.15 dac interrupts.............................................................................................................................................................. 883 chapter 36 12-bit digital-to-analog converter (dac) 36.1 introduction ................................................................................................................................................................... 885 36.2 features ......................................................................................................................................................................... 885 36.3 block diagram .............................................................................................................................................................. 885 36.4 memory map/register definition................................................................................................................................. 886 36.4.1 dac data low register (dac x _dat n l) ................................................................................................. 888 36.4.2 dac data high register (dac x _dat n h) ................................................................................................ 889 36.4.3 dac status register (dac x _sr) ............................................................................................................... 889 36.4.4 dac control register (dac x _c0) ............................................................................................................. 890 36.4.5 dac control register 1 (dac x _c1) .......................................................................................................... 891 36.4.6 dac control register 2 (dac x _c2) .......................................................................................................... 892 36.5 functional description .................................................................................................................................................. 892 36.5.1 dac data buffer operation ........................................................................................................................ 893 36.5.2 dma operation ........................................................................................................................................... 894 36.5.3 resets ........................................................................................................................................................... 894 36.5.4 low power mode operation ........................................................................................................................ 894 chapter 37 voltage reference (vrefv1) 37.1 introduction ................................................................................................................................................................... 897 37.1.1 overview ...................................................................................................................................................... 898 37.1.2 features ........................................................................................................................................................ 898 37.1.3 modes of operation ..................................................................................................................................... 899 37.1.4 vref signal descriptions ........................................................................................................................... 899 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 31 section number title page 37.2 memory map and register definition .......................................................................................................................... 899 37.2.1 vref trim register (vref_trm)............................................................................................................ 900 37.2.2 vref status and control register (vref_sc).......................................................................................... 901 37.3 functional description .................................................................................................................................................. 902 37.3.1 voltage reference disabled, sc[vrefen] = 0 ......................................................................................... 902 37.3.2 voltage reference enabled, sc[vrefen] = 1 .......................................................................................... 902 37.4 initialization/application information .......................................................................................................................... 903 chapter 38 programmable delay block (pdb) 38.1 introduction ................................................................................................................................................................... 905 38.1.1 features ........................................................................................................................................................ 905 38.1.2 implementation ............................................................................................................................................ 906 38.1.3 back-to-back acknowledgement connections ............................................................................................ 907 38.1.4 dac external trigger input connections ................................................................................................... 907 38.1.5 block diagram ............................................................................................................................................. 907 38.1.6 modes of operation ..................................................................................................................................... 909 38.2 pdb signal descriptions .............................................................................................................................................. 909 38.3 memory map and register definition .......................................................................................................................... 909 38.3.1 status and control register (pdb x _sc) ..................................................................................................... 911 38.3.2 modulus register (pdb x _mod)................................................................................................................. 913 38.3.3 counter register (pdb x _cnt) ................................................................................................................... 914 38.3.4 interrupt delay register (pdb x _idly) ...................................................................................................... 914 38.3.5 channel n control register 1 (pdb x _ch n c1) ........................................................................................... 915 38.3.6 channel n status register (pdb x _ch n s) ................................................................................................... 916 38.3.7 channel n delay 0 register (pdb x _ch n dly0) ........................................................................................ 917 38.3.8 channel n delay 1 register (pdb x _ch n dly1) ........................................................................................ 917 38.3.9 dac interval trigger n control register (pdb x _dacintc n ) ................................................................. 918 38.3.10 dac interval n register (pdb x _dacint n ) .............................................................................................. 918 38.3.11 pulse-out n enable register (pdb x _po n en)............................................................................................. 919 k60 sub-family reference manual, rev. 6, nov 2011 32 freescale semiconductor, inc. section number title page 38.3.12 pulse-out n delay register (pdb x _po n dly) ........................................................................................... 919 38.4 functional description .................................................................................................................................................. 920 38.4.1 pdb pre-trigger and trigger outputs .......................................................................................................... 920 38.4.2 pdb trigger input source selection ........................................................................................................... 922 38.4.3 dac interval trigger outputs ..................................................................................................................... 922 38.4.4 pulse-out's ................................................................................................................................................... 923 38.4.5 updating the delay registers ...................................................................................................................... 923 38.4.6 interrupts ...................................................................................................................................................... 925 38.4.7 dma ............................................................................................................................................................ 925 38.5 application information................................................................................................................................................ 925 38.5.1 impact of using the prescaler and multiplication factor on timing resolution ........................................ 925 chapter 39 flextimer (ftm) 39.1 introduction ................................................................................................................................................................... 927 39.1.1 flextimer philosophy .................................................................................................................................. 927 39.1.2 features ........................................................................................................................................................ 928 39.1.3 modes of operation ..................................................................................................................................... 929 39.1.4 block diagram ............................................................................................................................................. 929 39.2 ftm signal descriptions .............................................................................................................................................. 932 39.2.1 extclk ftm external clock............................................................................................................... 932 39.2.2 chn ftm channel (n) i/o pin ............................................................................................................... 932 39.2.3 faultj ftm fault input ....................................................................................................................... 932 39.2.4 pha ftm quadrature decoder phase a input ...................................................................................... 933 39.2.5 phb ftm quadrature decoder phase b input ....................................................................................... 933 39.3 memory map and register definition .......................................................................................................................... 933 39.3.1 module memory map .................................................................................................................................. 933 39.3.2 register descriptions ................................................................................................................................... 933 39.3.3 status and control (ftm x _sc) ................................................................................................................... 940 39.3.4 counter (ftm x _cnt) ................................................................................................................................. 941 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 33 section number title page 39.3.5 modulo (ftm x _mod) ................................................................................................................................ 942 39.3.6 channel (n) status and control (ftm x _c n sc) ........................................................................................... 943 39.3.7 channel (n) value (ftm x _c n v) ................................................................................................................. 946 39.3.8 counter initial value (ftm x _cntin) ........................................................................................................ 947 39.3.9 capture and compare status (ftm x _status) ......................................................................................... 947 39.3.10 features mode selection (ftm x _mode) .................................................................................................. 950 39.3.11 synchronization (ftm x _sync) ................................................................................................................. 951 39.3.12 initial state for channels output (ftm x _outinit).................................................................................. 954 39.3.13 output mask (ftm x _outmask) ............................................................................................................. 955 39.3.14 function for linked channels (ftm x _combine) ................................................................................... 957 39.3.15 deadtime insertion control (ftm x _deadtime) ..................................................................................... 962 39.3.16 ftm external trigger (ftm x _exttrig) ................................................................................................. 963 39.3.17 channels polarity (ftm x _pol) .................................................................................................................. 965 39.3.18 fault mode status (ftm x _fms) ................................................................................................................. 967 39.3.19 input capture filter control (ftm x _filter) ........................................................................................... 969 39.3.20 fault control (ftm x _fltctrl) ............................................................................................................... 971 39.3.21 quadrature decoder control and status (ftm x _qdctrl) ....................................................................... 973 39.3.22 configuration (ftm x _conf) ..................................................................................................................... 975 39.3.23 ftm fault input polarity (ftm x _fltpol) ............................................................................................... 976 39.3.24 synchronization configuration (ftm x _synconf) .................................................................................. 978 39.3.25 ftm inverting control (ftm x _invctrl)................................................................................................ 980 39.3.26 ftm software output control (ftm x _swoctrl) .................................................................................. 981 39.3.27 ftm pwm load (ftm x _pwmload) ..................................................................................................... 983 39.4 functional description .................................................................................................................................................. 985 39.4.1 clock source ................................................................................................................................................ 985 39.4.2 prescaler ....................................................................................................................................................... 986 39.4.3 counter ......................................................................................................................................................... 986 39.4.4 input capture mode ..................................................................................................................................... 991 39.4.5 output compare mode................................................................................................................................. 994 k60 sub-family reference manual, rev. 6, nov 2011 34 freescale semiconductor, inc. section number title page 39.4.6 edge-aligned pwm (epwm) mode ........................................................................................................... 995 39.4.7 center-aligned pwm (cpwm) mode ........................................................................................................ 997 39.4.8 combine mode ............................................................................................................................................. 998 39.4.9 complementary mode.................................................................................................................................. 1006 39.4.10 registers updated from write buffers ........................................................................................................ 1007 39.4.11 pwm synchronization ................................................................................................................................. 1009 39.4.12 inverting ....................................................................................................................................................... 1025 39.4.13 software output control .............................................................................................................................. 1026 39.4.14 deadtime insertion ....................................................................................................................................... 1028 39.4.15 output mask ................................................................................................................................................. 1031 39.4.16 fault control ................................................................................................................................................ 1032 39.4.17 polarity control ............................................................................................................................................ 1035 39.4.18 initialization ................................................................................................................................................. 1036 39.4.19 features priority ........................................................................................................................................... 1036 39.4.20 channel trigger output ............................................................................................................................... 1037 39.4.21 initialization trigger .................................................................................................................................... 1038 39.4.22 capture test mode ....................................................................................................................................... 1040 39.4.23 dma ............................................................................................................................................................ 1041 39.4.24 dual edge capture mode ............................................................................................................................. 1042 39.4.25 quadrature decoder mode ........................................................................................................................... 1049 39.4.26 bdm mode .................................................................................................................................................. 1054 39.4.27 intermediate load ........................................................................................................................................ 1055 39.4.28 global time base (gtb) ............................................................................................................................. 1057 39.5 reset overview ............................................................................................................................................................. 1058 39.6 ftm interrupts .............................................................................................................................................................. 1060 39.6.1 timer overflow interrupt............................................................................................................................. 1060 39.6.2 channel (n) interrupt .................................................................................................................................... 1060 39.6.3 fault interrupt .............................................................................................................................................. 1060 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 35 section number title page chapter 40 periodic interrupt timer (pit) 40.1 introduction ................................................................................................................................................................... 1063 40.1.1 block diagram ............................................................................................................................................. 1063 40.1.2 features ........................................................................................................................................................ 1064 40.2 signal description......................................................................................................................................................... 1064 40.3 memory map/register description .............................................................................................................................. 1065 40.3.1 pit module control register (pit_mcr) .................................................................................................. 1066 40.3.2 timer load value register (pit_ldval n )............................................................................................... 1067 40.3.3 current timer value register (pit_cval n ) ............................................................................................. 1067 40.3.4 timer control register (pit_tctrl n ) ...................................................................................................... 1068 40.3.5 timer flag register (pit_tflg n ) .............................................................................................................. 1068 40.4 functional description .................................................................................................................................................. 1069 40.4.1 general ......................................................................................................................................................... 1069 40.4.2 interrupts ...................................................................................................................................................... 1070 40.5 initialization and application information ................................................................................................................... 1071 chapter 41 low power timer (lptmr) 41.1 introduction ................................................................................................................................................................... 1073 41.1.1 features ........................................................................................................................................................ 1073 41.1.2 modes of operation ...................................................................................................................................... 1073 41.2 lptmr signal descriptions .......................................................................................................................................... 1074 41.2.1 detailed signal descriptions ......................................................................................................................... 1074 41.3 memory map and register definition............................................................................................................................. 1075 41.3.1 low power timer control status register (lptmr x _csr) ...................................................................... 1076 41.3.2 low power timer prescale register (lptmr x _psr) ................................................................................ 1077 41.3.3 low power timer compare register (lptmr x _cmr) ............................................................................. 1079 41.3.4 low power timer counter register (lptmr x _cnr) ............................................................................... 1079 k60 sub-family reference manual, rev. 6, nov 2011 36 freescale semiconductor, inc. section number title page 41.4 functional description................................................................................................................................................... 1080 41.4.1 lptmr power and reset .............................................................................................................................. 1080 41.4.2 lptmr clocking.......................................................................................................................................... 1080 41.4.3 lptmr prescaler/glitch filter ...................................................................................................................... 1081 41.4.4 lptmr compare.......................................................................................................................................... 1082 41.4.5 lptmr counter ........................................................................................................................................... 1082 41.4.6 lptmr hardware trigger ............................................................................................................................. 1083 41.4.7 lptmr interrupt.......................................................................................................................................... 1083 chapter 42 carrier modulator transmitter (cmt) 42.1 introduction ................................................................................................................................................................... 1085 42.2 features ......................................................................................................................................................................... 1085 42.3 block diagram .............................................................................................................................................................. 1086 42.4 modes of operation ...................................................................................................................................................... 1087 42.4.1 wait mode operation................................................................................................................................... 1088 42.4.2 stop mode operation ................................................................................................................................... 1088 42.5 cmt external signal descriptions ............................................................................................................................... 1089 42.5.1 cmt_iro infrared output ..................................................................................................................... 1089 42.6 memory map/register definition................................................................................................................................. 1089 42.6.1 cmt carrier generator high data register 1 (cmt_cgh1) .................................................................... 1090 42.6.2 cmt carrier generator low data register 1 (cmt_cgl1) ..................................................................... 1091 42.6.3 cmt carrier generator high data register 2 (cmt_cgh2) .................................................................... 1092 42.6.4 cmt carrier generator low data register 2 (cmt_cgl2) ..................................................................... 1092 42.6.5 cmt output control register (cmt_oc) ................................................................................................. 1093 42.6.6 cmt modulator status and control register (cmt_msc) ....................................................................... 1094 42.6.7 cmt modulator data register mark high (cmt_cmd1) ........................................................................ 1095 42.6.8 cmt modulator data register mark low (cmt_cmd2) ......................................................................... 1096 42.6.9 cmt modulator data register space high (cmt_cmd3) ....................................................................... 1096 42.6.10 cmt modulator data register space low (cmt_cmd4) ........................................................................ 1097 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 37 section number title page 42.6.11 cmt primary prescaler register (cmt_pps) ............................................................................................ 1097 42.6.12 cmt direct memory access (cmt_dma) ............................................................................................... 1098 42.7 functional description .................................................................................................................................................. 1099 42.7.1 clock divider ............................................................................................................................................... 1099 42.7.2 carrier generator ......................................................................................................................................... 1099 42.7.3 modulator ..................................................................................................................................................... 1102 42.7.4 extended space operation ........................................................................................................................... 1106 42.8 cmt interrupts and dma ............................................................................................................................................ 1107 chapter 43 real time clock (rtc) 43.1 introduction ................................................................................................................................................................... 1109 43.1.1 features ........................................................................................................................................................ 1109 43.1.2 modes of operation ...................................................................................................................................... 1109 43.1.3 rtc signal descriptions ............................................................................................................................... 1110 43.2 register definition......................................................................................................................................................... 1110 43.2.1 rtc time seconds register (rtc_tsr) ................................................................................................... 1111 43.2.2 rtc time prescaler register (rtc_tpr) .................................................................................................. 1112 43.2.3 rtc time alarm register (rtc_tar) ..................................................................................................... 1112 43.2.4 rtc time compensation register (rtc_tcr) ......................................................................................... 1113 43.2.5 rtc control register (rtc_cr)................................................................................................................ 1114 43.2.6 rtc status register (rtc_sr) .................................................................................................................. 1116 43.2.7 rtc lock register (rtc_lr) .................................................................................................................... 1117 43.2.8 rtc interrupt enable register (rtc_ier)................................................................................................. 1118 43.2.9 rtc write access register (rtc_war) .................................................................................................. 1119 43.2.10 rtc read access register (rtc_rar) .................................................................................................... 1120 43.3 functional description................................................................................................................................................... 1121 43.3.1 power, clocking and reset ............................................................................................................................ 1121 43.3.2 time counter ................................................................................................................................................ 1122 43.3.3 compensation............................................................................................................................................... 1123 k60 sub-family reference manual, rev. 6, nov 2011 38 freescale semiconductor, inc. section number title page 43.3.4 time alarm ................................................................................................................................................... 1124 43.3.5 update mode ................................................................................................................................................ 1124 43.3.6 register lock ................................................................................................................................................ 1124 43.3.7 access control .............................................................................................................................................. 1125 43.3.8 interrupt ........................................................................................................................................................ 1125 chapter 44 10/100-mbps ethernet mac (enet) 44.1 introduction ................................................................................................................................................................... 1127 44.1.1 overview ...................................................................................................................................................... 1127 44.1.2 features ........................................................................................................................................................ 1128 44.1.3 block diagram ............................................................................................................................................. 1130 44.2 external signal description .......................................................................................................................................... 1131 44.3 memory map/register definition................................................................................................................................. 1133 44.3.1 interrupt event register (enet_eir) ......................................................................................................... 1136 44.3.2 interrupt mask register (enet_eimr)...................................................................................................... 1138 44.3.3 receive descriptor active register (enet_rdar) .................................................................................. 1141 44.3.4 transmit descriptor active register (enet_tdar)................................................................................. 1142 44.3.5 ethernet control register (enet_ecr) ..................................................................................................... 1143 44.3.6 mii management frame register (enet_mmfr) .................................................................................... 1144 44.3.7 mii speed control register (enet_mscr) .............................................................................................. 1145 44.3.8 mib control register (enet_mibc) ........................................................................................................ 1147 44.3.9 receive control register (enet_rcr) ..................................................................................................... 1148 44.3.10 transmit control register (enet_tcr) .................................................................................................... 1150 44.3.11 physical address lower register (enet_palr) ...................................................................................... 1152 44.3.12 physical address upper register (enet_paur) ...................................................................................... 1152 44.3.13 opcode/pause duration register (enet_opd) ......................................................................................... 1153 44.3.14 descriptor individual upper address register (enet_iaur) .................................................................. 1153 44.3.15 descriptor individual lower address register (enet_ialr) .................................................................. 1154 44.3.16 descriptor group upper address register (enet_gaur) ....................................................................... 1154 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 39 section number title page 44.3.17 descriptor group lower address register (enet_galr) ....................................................................... 1155 44.3.18 transmit fifo watermark register (enet_tfwr) ................................................................................. 1155 44.3.19 receive descriptor ring start register (enet_rdsr) ............................................................................. 1156 44.3.20 transmit buffer descriptor ring start register (enet_tdsr) ................................................................ 1157 44.3.21 maximum receive buffer size register (enet_mrbr) .......................................................................... 1157 44.3.22 receive fifo section full threshold (enet_rsfl) ................................................................................ 1158 44.3.23 receive fifo section empty threshold (enet_rsem) .......................................................................... 1158 44.3.24 receive fifo almost empty threshold (enet_raem) .......................................................................... 1159 44.3.25 receive fifo almost full threshold (enet_rafl)................................................................................ 1159 44.3.26 transmit fifo section empty threshold (enet_tsem) ......................................................................... 1160 44.3.27 transmit fifo almost empty threshold (enet_taem) ......................................................................... 1160 44.3.28 transmit fifo almost full threshold (enet_tafl) .............................................................................. 1161 44.3.29 transmit inter-packet gap (enet_tipg) .................................................................................................. 1161 44.3.30 frame truncation length (enet_ftrl) ................................................................................................... 1162 44.3.31 transmit accelerator function configuration (enet_tacc) .................................................................. 1162 44.3.32 receive accelerator function configuration (enet_racc) .................................................................... 1163 44.3.33 timer control register (enet_atcr) ...................................................................................................... 1165 44.3.34 timer value register (enet_atvr) ........................................................................................................ 1166 44.3.35 timer offset register (enet_atoff) ...................................................................................................... 1167 44.3.36 timer period register (enet_atper)...................................................................................................... 1167 44.3.37 timer correction register (enet_atcor) .............................................................................................. 1168 44.3.38 time-stamping clock period register (enet_atinc) ............................................................................ 1168 44.3.39 timestamp of last transmitted frame (enet_atstmp) ........................................................................ 1169 44.3.40 timer global status register (enet_tgsr) ............................................................................................. 1169 44.3.41 timer control status register (enet_tcsr n ) .......................................................................................... 1170 44.3.42 timer compare capture register (enet_tccr n ) .................................................................................... 1171 44.3.43 statistic event counters ............................................................................................................................... 1172 k60 sub-family reference manual, rev. 6, nov 2011 40 freescale semiconductor, inc. section number title page 44.4 functional description .................................................................................................................................................. 1175 44.4.1 ethernet mac frame formats ..................................................................................................................... 1175 44.4.2 ip and higher layers frame format............................................................................................................ 1178 44.4.3 ieee 1588 message formats ....................................................................................................................... 1182 44.4.4 mac receive ............................................................................................................................................... 1186 44.4.5 mac transmit ............................................................................................................................................. 1191 44.4.6 full duplex flow control operation ........................................................................................................... 1195 44.4.7 magic packet detection ............................................................................................................................... 1197 44.4.8 ip accelerator functions .............................................................................................................................. 1198 44.4.9 resets and stop controls ............................................................................................................................. 1203 44.4.10 ieee 1588 functions ................................................................................................................................... 1206 44.4.11 fifo thresholds .......................................................................................................................................... 1209 44.4.12 loopback options ........................................................................................................................................ 1212 44.4.13 legacy buffer descriptors ........................................................................................................................... 1213 44.4.14 enhanced buffer descriptors ....................................................................................................................... 1214 44.4.15 client fifo application interface ............................................................................................................... 1221 44.4.16 fifo protection............................................................................................................................................ 1224 44.4.17 phy management interface......................................................................................................................... 1226 44.4.18 ethernet interfaces ....................................................................................................................................... 1228 chapter 45 universal serial bus otg controller (usbotg) 45.1 introduction ................................................................................................................................................................... 1233 45.1.1 usb .............................................................................................................................................................. 1233 45.1.2 usb on-the-go .......................................................................................................................................... 1234 45.1.3 usb-fs features.......................................................................................................................................... 1235 45.2 functional description .................................................................................................................................................. 1235 45.2.1 data structures ............................................................................................................................................. 1235 45.3 programmers interface .................................................................................................................................................. 1236 45.3.1 buffer descriptor table ............................................................................................................................... 1236 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 41 section number title page 45.3.2 rx vs. tx as a usb target device or usb host ......................................................................................... 1237 45.3.3 addressing buffer descriptor table entries ................................................................................................ 1238 45.3.4 buffer descriptor formats ........................................................................................................................... 1238 45.3.5 usb transaction .......................................................................................................................................... 1241 45.4 memory map/register definitions ............................................................................................................................... 1243 45.4.1 peripheral id register (usb x _perid) ....................................................................................................... 1245 45.4.2 peripheral id complement register (usb x _idcomp) ............................................................................. 1246 45.4.3 peripheral revision register (usb x _rev) ................................................................................................ 1246 45.4.4 peripheral additional info register (usb x _addinfo) ............................................................................ 1247 45.4.5 otg interrupt status register (usb x _otgistat)................................................................................... 1247 45.4.6 otg interrupt control register (usb x _otgicr) ..................................................................................... 1248 45.4.7 otg status register (usb x _otgstat) ................................................................................................... 1249 45.4.8 otg control register (usb x _otgctl) ................................................................................................... 1250 45.4.9 interrupt status register (usb x _istat) .................................................................................................... 1251 45.4.10 interrupt enable register (usb x _inten) .................................................................................................. 1252 45.4.11 error interrupt status register (usb x _errstat) .................................................................................... 1253 45.4.12 error interrupt enable register (usb x _erren) ....................................................................................... 1254 45.4.13 status register (usb x _stat) .................................................................................................................... 1256 45.4.14 control register (usb x _ctl) .................................................................................................................... 1257 45.4.15 address register (usb x _addr) ................................................................................................................ 1258 45.4.16 bdt page register 1 (usb x _bdtpage1) ................................................................................................ 1259 45.4.17 frame number register low (usb x _frmnuml) ................................................................................... 1259 45.4.18 frame number register high (usb x _frmnumh) .................................................................................. 1260 45.4.19 token register (usb x _token) ................................................................................................................ 1260 45.4.20 sof threshold register (usb x _softhld).............................................................................................. 1261 45.4.21 bdt page register 2 (usb x _bdtpage2) ................................................................................................ 1262 45.4.22 bdt page register 3 (usb x _bdtpage3) ................................................................................................ 1262 45.4.23 endpoint control register (usb x _endpt n ) ............................................................................................. 1262 45.4.24 usb control register (usb x _usbctrl) ................................................................................................. 1264 k60 sub-family reference manual, rev. 6, nov 2011 42 freescale semiconductor, inc. section number title page 45.4.25 usb otg observe register (usb x _observe)....................................................................................... 1264 45.4.26 usb otg control register (usb x _control) ....................................................................................... 1265 45.4.27 usb transceiver control register 0 (usb x _usbtrc0) ........................................................................... 1266 45.5 otg and host mode operation.................................................................................................................................... 1267 45.6 host mode operation examples ................................................................................................................................... 1267 45.7 on-the-go operation ................................................................................................................................................... 1270 45.7.1 otg dual role a device operation ........................................................................................................... 1271 45.7.2 otg dual role b device operation ........................................................................................................... 1272 chapter 46 usb device charger detection module (usbdcd) 46.1 preface........................................................................................................................................................................... 1275 46.1.1 references .................................................................................................................................................... 1275 46.1.2 acronyms and abbreviations....................................................................................................................... 1275 46.1.3 glossary ....................................................................................................................................................... 1276 46.2 introduction ................................................................................................................................................................... 1276 46.2.1 block diagram ............................................................................................................................................. 1276 46.2.2 features ........................................................................................................................................................ 1277 46.2.3 modes of operation ..................................................................................................................................... 1277 46.3 module signal description ........................................................................................................................................... 1278 46.3.1 usb signal descriptions ............................................................................................................................. 1278 46.4 memory map/register definition................................................................................................................................. 1279 46.4.1 control register (usbdcd_control) .................................................................................................. 1280 46.4.2 clock register (usbdcd_clock) .......................................................................................................... 1281 46.4.3 status register (usbdcd_status)......................................................................................................... 1282 46.4.4 timer0 register (usbdcd_timer0)..................................................................................................... 1284 46.4.5 usbdcd_timer1 ..................................................................................................................................... 1285 46.4.6 usbdcd_timer2 ..................................................................................................................................... 1285 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 43 section number title page 46.5 functional description .................................................................................................................................................. 1286 46.5.1 the charger detection sequence ................................................................................................................. 1287 46.5.2 interrupts and events ................................................................................................................................... 1297 46.5.3 resets ........................................................................................................................................................... 1298 46.6 initialization information .............................................................................................................................................. 1299 46.7 application information................................................................................................................................................ 1299 46.7.1 external pullups ........................................................................................................................................... 1299 46.7.2 dead or weak battery .................................................................................................................................. 1299 46.7.3 handling unplug events .............................................................................................................................. 1300 chapter 47 usb voltage regulator 47.1 introduction ................................................................................................................................................................... 1301 47.1.1 overview ...................................................................................................................................................... 1301 47.1.2 features ........................................................................................................................................................ 1302 47.1.3 modes of operation ..................................................................................................................................... 1303 47.2 usb voltage regulator module signal descriptions .................................................................................................. 1303 chapter 48 can (flexcan) 48.1 introduction ................................................................................................................................................................... 1305 48.1.1 overview ...................................................................................................................................................... 1306 48.1.2 flexcan module features .......................................................................................................................... 1307 48.1.3 modes of operation ..................................................................................................................................... 1308 48.2 flexcan signal descriptions....................................................................................................................................... 1310 48.2.1 can rx ....................................................................................................................................................... 1310 48.2.2 can tx ....................................................................................................................................................... 1310 48.3 memory map/register definition................................................................................................................................. 1310 48.3.1 flexcan memory mapping ........................................................................................................................ 1310 48.3.2 module configuration register (can x _mcr) ........................................................................................... 1316 48.3.3 control 1 register (can x _ctrl1) ............................................................................................................ 1321 k60 sub-family reference manual, rev. 6, nov 2011 44 freescale semiconductor, inc. section number title page 48.3.4 free running timer (can x _timer) ......................................................................................................... 1324 48.3.5 rx mailboxes global mask register (can x _rxmgmask).................................................................... 1325 48.3.6 rx 14 mask register (can x _rx14mask) ............................................................................................... 1326 48.3.7 rx 15 mask register (can x _rx15mask) ............................................................................................... 1327 48.3.8 error counter (can x _ecr) ........................................................................................................................ 1328 48.3.9 error and status 1 register (can x _esr1) ................................................................................................. 1329 48.3.10 interrupt masks 2 register (can x _imask2) ............................................................................................ 1333 48.3.11 interrupt masks 1 register (can x _imask1) ............................................................................................ 1334 48.3.12 interrupt flags 2 register (can x _iflag2) ............................................................................................... 1334 48.3.13 interrupt flags 1 register (can x _iflag1) ............................................................................................... 1335 48.3.14 control 2 register (can x _ctrl2) ............................................................................................................ 1338 48.3.15 error and status 2 register (can x _esr2) ................................................................................................. 1341 48.3.16 crc register (can x _crcr) ..................................................................................................................... 1342 48.3.17 rx fifo global mask register (can x _rxfgmask) ............................................................................. 1343 48.3.18 rx fifo information register (can x _rxfir) ......................................................................................... 1344 48.3.19 rx individual mask registers (can x _rximr n ) ....................................................................................... 1345 48.3.56 message buffer structure............................................................................................................................. 1346 48.3.57 rx fifo structure ........................................................................................................................................ 1352 48.4 functional description .................................................................................................................................................. 1355 48.4.1 transmit process .......................................................................................................................................... 1355 48.4.2 arbitration process ....................................................................................................................................... 1356 48.4.3 receive process............................................................................................................................................ 1360 48.4.4 matching process ......................................................................................................................................... 1362 48.4.5 move process ............................................................................................................................................... 1366 48.4.6 data coherence ............................................................................................................................................ 1368 48.4.7 rx fifo ....................................................................................................................................................... 1372 48.4.8 can protocol related features ................................................................................................................... 1373 48.4.9 modes of operation details ......................................................................................................................... 1380 48.4.10 interrupts ...................................................................................................................................................... 1384 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 45 section number title page 48.4.11 bus interface ................................................................................................................................................ 1385 48.5 initialization/application information .......................................................................................................................... 1386 48.5.1 flexcan initialization sequence ................................................................................................................ 1386 chapter 49 spi (dspi) 49.1 introduction ................................................................................................................................................................... 1389 49.1.1 block diagram ............................................................................................................................................. 1389 49.1.2 features ........................................................................................................................................................ 1390 49.1.3 dspi configurations .................................................................................................................................... 1391 49.1.4 modes of operation ..................................................................................................................................... 1392 49.2 dspi signal descriptions ............................................................................................................................................. 1394 49.2.1 pcs0/ss peripheral chip select/slave select ........................................................................................ 1394 49.2.2 pcs1 - pcs3 peripheral chip selects 1 - 3 ............................................................................................ 1394 49.2.3 pcs4 peripheral chip select 4................................................................................................................ 1395 49.2.4 pcs5/pcss peripheral chip select 5/peripheral chip select strobe..................................................... 1395 49.2.5 sin serial input ...................................................................................................................................... 1395 49.2.6 sout serial output ................................................................................................................................ 1395 49.2.7 sck serial clock .................................................................................................................................... 1395 49.3 memory map/register definition................................................................................................................................. 1396 49.3.1 dspi module configuration register (spi x _mcr) .................................................................................... 1399 49.3.2 dspi transfer count register (spi x _tcr) ................................................................................................ 1402 49.3.3 dspi clock and transfer attributes register (in master mode) (spi x _ctar n ) ...................................... 1402 49.3.4 dspi clock and transfer attributes register (in slave mode) (spi x _ctar n _slave) .......................... 1407 49.3.5 dspi status register (spi x _sr) .................................................................................................................. 1408 49.3.6 dspi dma/interrupt request select and enable register (spi x _rser) .................................................. 1411 49.3.7 dspi push tx fifo register in master mode (spi x _pushr)............................................................... 1413 49.3.8 dspi push tx fifo register in slave mode (spi x _pushr_slave) .................................................. 1415 49.3.9 dspi pop rx fifo register (spi x _popr) ............................................................................................... 1415 49.3.10 dspi transmit fifo registers (spi x _txfr n )........................................................................................... 1416 k60 sub-family reference manual, rev. 6, nov 2011 46 freescale semiconductor, inc. section number title page 49.3.11 dspi receive fifo registers (spi x _rxfr n ) ............................................................................................ 1416 49.4 functional description .................................................................................................................................................. 1417 49.4.1 start and stop of dspi transfers ................................................................................................................. 1418 49.4.2 serial peripheral interface (spi) configuration ........................................................................................... 1418 49.4.3 dspi baud rate and clock delay generation............................................................................................. 1422 49.4.4 transfer formats .......................................................................................................................................... 1426 49.4.5 continuous serial communications clock .................................................................................................. 1431 49.4.6 slave mode operation constraints .............................................................................................................. 1432 49.4.7 interrupts/dma requests ............................................................................................................................ 1433 49.4.8 power saving features ................................................................................................................................. 1435 49.5 initialization/application information .......................................................................................................................... 1436 49.5.1 how to manage dspi queues ..................................................................................................................... 1436 49.5.2 switching master and slave mode .............................................................................................................. 1437 49.5.3 baud rate settings ....................................................................................................................................... 1438 49.5.4 delay settings .............................................................................................................................................. 1438 49.5.5 calculation of fifo pointer addresses ....................................................................................................... 1439 chapter 50 inter-integrated circuit (i2c) 50.1 introduction ................................................................................................................................................................... 1443 50.1.1 features ........................................................................................................................................................ 1443 50.1.2 modes of operation ..................................................................................................................................... 1444 50.1.3 block diagram ............................................................................................................................................. 1444 50.2 i2c signal descriptions ................................................................................................................................................ 1445 50.3 memory map and register descriptions ...................................................................................................................... 1445 50.3.1 i2c address register 1 (i2c x _a1) .............................................................................................................. 1447 50.3.2 i2c frequency divider register (i2c x _f) .................................................................................................... 1447 50.3.3 i2c control register 1 (i2c x _c1) ............................................................................................................... 1448 50.3.4 i2c status register (i2c x _s) ....................................................................................................................... 1450 50.3.5 i2c data i/o register (i2c x _d) ................................................................................................................... 1452 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 47 section number title page 50.3.6 i2c control register 2 (i2c x _c2) ............................................................................................................... 1453 50.3.7 i2c programmable input glitch filter register (i2c x _flt) ....................................................................... 1454 50.3.8 i2c range address register (i2c x _ra) ...................................................................................................... 1454 50.3.9 i2c smbus control and status register (i2c x _smb) ................................................................................. 1455 50.3.10 i2c address register 2 (i2c x _a2) .............................................................................................................. 1456 50.3.11 i2c scl low timeout register high (i2c x _slth) .................................................................................. 1457 50.3.12 i2c scl low timeout register low (i2c x _sltl) ................................................................................... 1457 50.4 functional description .................................................................................................................................................. 1458 50.4.1 i2c protocol ................................................................................................................................................. 1458 50.4.2 10-bit address .............................................................................................................................................. 1463 50.4.3 address matching ........................................................................................................................................ 1464 50.4.4 system management bus specification ....................................................................................................... 1465 50.4.5 resets ........................................................................................................................................................... 1468 50.4.6 interrupts ...................................................................................................................................................... 1468 50.4.7 programmable input glitch filter ................................................................................................................ 1470 50.4.8 address matching wakeup .......................................................................................................................... 1470 50.4.9 dma support ............................................................................................................................................... 1471 50.5 initialization/application information .......................................................................................................................... 1471 chapter 51 universal asynchronous receiver/transmitter (uart) 51.1 introduction ................................................................................................................................................................... 1475 51.1.1 features ........................................................................................................................................................ 1475 51.1.2 modes of operation ...................................................................................................................................... 1477 51.2 uart signal descriptions ............................................................................................................................................. 1478 51.2.1 detailed signal descriptions ......................................................................................................................... 1478 51.3 memory map and registers............................................................................................................................................ 1479 51.3.1 uart baud rate registers:high (uart x _bdh) ..................................................................................... 1487 51.3.2 uart baud rate registers: low (uart x _bdl) ..................................................................................... 1489 51.3.3 uart control register 1 (uart x _c1) ..................................................................................................... 1490 k60 sub-family reference manual, rev. 6, nov 2011 48 freescale semiconductor, inc. section number title page 51.3.4 uart control register 2 (uart x _c2) ..................................................................................................... 1491 51.3.5 uart status register 1 (uart x _s1) ........................................................................................................ 1493 51.3.6 uart status register 2 (uart x _s2) ........................................................................................................ 1496 51.3.7 uart control register 3 (uart x _c3) ..................................................................................................... 1498 51.3.8 uart data register (uart x _d) ............................................................................................................... 1500 51.3.9 uart match address registers 1 (uart x _ma1) .................................................................................... 1501 51.3.10 uart match address registers 2 (uart x _ma2) .................................................................................... 1502 51.3.11 uart control register 4 (uart x _c4) ..................................................................................................... 1502 51.3.12 uart control register 5 (uart x _c5) ..................................................................................................... 1503 51.3.13 uart extended data register (uart x _ed) ............................................................................................ 1504 51.3.14 uart modem register (uart x _modem) ............................................................................................. 1505 51.3.15 uart infrared register (uart x _ir) ........................................................................................................ 1507 51.3.16 uart fifo parameters (uart x _pfifo) ................................................................................................. 1508 51.3.17 uart fifo control register (uart x _cfifo) ........................................................................................ 1509 51.3.18 uart fifo status register (uart x _sfifo) ........................................................................................... 1510 51.3.19 uart fifo transmit watermark (uart x _twfifo) ............................................................................. 1512 51.3.20 uart fifo transmit count (uart x _tcfifo) ....................................................................................... 1512 51.3.21 uart fifo receive watermark (uart x _rwfifo) ............................................................................... 1513 51.3.22 uart fifo receive count (uart x _rcfifo) ........................................................................................ 1514 51.3.23 uart 7816 control register (uart x _c7816) ......................................................................................... 1514 51.3.24 uart 7816 interrupt enable register (uart x _ie7816) .......................................................................... 1516 51.3.25 uart 7816 interrupt status register (uart x _is7816) ............................................................................ 1517 51.3.26 uart 7816 wait parameter register (uart x _wp7816t0) ..................................................................... 1519 51.3.27 uart 7816 wait parameter register (uart x _wp7816t1) ..................................................................... 1520 51.3.28 uart 7816 wait n register (uart x _wn7816) ...................................................................................... 1521 51.3.29 uart 7816 wait fd register (uart x _wf7816) .................................................................................... 1521 51.3.30 uart 7816 error threshold register (uart x _et7816).......................................................................... 1522 51.3.31 uart 7816 transmit length register (uart x _tl7816) ........................................................................ 1523 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 49 section number title page 51.4 functional description................................................................................................................................................... 1523 51.4.1 transmitter ................................................................................................................................................... 1523 51.4.2 receiver ....................................................................................................................................................... 1529 51.4.3 baud rate generation .................................................................................................................................... 1543 51.4.4 data format (non iso-7816) ........................................................................................................................ 1545 51.4.5 single-wire operation ................................................................................................................................... 1548 51.4.6 loop operation ............................................................................................................................................. 1549 51.4.7 iso-7816 / smartcard support ...................................................................................................................... 1549 51.4.8 infrared interface .......................................................................................................................................... 1554 51.5 reset.............................................................................................................................................................................. 1555 51.6 system level interrupt sources ...................................................................................................................................... 1555 51.6.1 rxedgif description.................................................................................................................................. 1556 51.7 dma operation ............................................................................................................................................................. 1557 51.8 application information ................................................................................................................................................ 1557 51.8.1 transmit/receive data buffer operation ........................................................................................................ 1557 51.8.2 iso-7816 initialization sequence ................................................................................................................. 1558 51.8.3 initialization sequence (non iso-7816) ....................................................................................................... 1560 51.8.4 overrun (or) flag implications ................................................................................................................... 1561 51.8.5 overrun nack considerations .................................................................................................................... 1562 51.8.6 match address registers ................................................................................................................................ 1563 51.8.7 modem feature ............................................................................................................................................. 1563 51.8.8 irda minimum pulse width ......................................................................................................................... 1564 51.8.9 clearing 7816 wait timer (wt, bwt, cwt) interrupts.............................................................................. 1564 51.8.10 legacy and reverse compatibility considerations ........................................................................................ 1565 chapter 52 secured digital host controller (sdhc) 52.1 introduction ................................................................................................................................................................... 1567 52.2 overview ....................................................................................................................................................................... 1567 52.2.1 supported types of cards .............................................................................................................................. 1567 k60 sub-family reference manual, rev. 6, nov 2011 50 freescale semiconductor, inc. section number title page 52.2.2 sdhc block diagram ................................................................................................................................... 1568 52.2.3 features ........................................................................................................................................................ 1569 52.2.4 modes and operations .................................................................................................................................. 1570 52.3 sdhc signal descriptions ............................................................................................................................................. 1571 52.4 memory map and register definition............................................................................................................................. 1572 52.4.1 dma system address register (sdhc_dsaddr) .................................................................................. 1573 52.4.2 block attributes register (sdhc_blkattr) .......................................................................................... 1574 52.4.3 command argument register (sdhc_cmdarg).................................................................................... 1575 52.4.4 transfer type register (sdhc_xfertyp) .............................................................................................. 1576 52.4.5 command response 0 (sdhc_cmdrsp0) ............................................................................................... 1580 52.4.6 command response 1 (sdhc_cmdrsp1) ............................................................................................... 1581 52.4.7 command response 2 (sdhc_cmdrsp2) ............................................................................................... 1581 52.4.8 command response 3 (sdhc_cmdrsp3) ............................................................................................... 1581 52.4.9 buffer data port register (sdhc_datport) .......................................................................................... 1583 52.4.10 present state register (sdhc_prsstat) ................................................................................................. 1583 52.4.11 protocol control register (sdhc_proctl) ............................................................................................. 1588 52.4.12 system control register (sdhc_sysctl) ............................................................................................... 1592 52.4.13 interrupt status register (sdhc_irqstat) ............................................................................................. 1595 52.4.14 interrupt status enable register (sdhc_irqstaten) ............................................................................ 1601 52.4.15 interrupt signal enable register (sdhc_irqsigen) ............................................................................... 1604 52.4.16 auto cmd12 error status register (sdhc_ac12err) ........................................................................... 1606 52.4.17 host controller capabilities (sdhc_htcapblt).................................................................................... 1609 52.4.18 watermark level register (sdhc_wml) ................................................................................................. 1611 52.4.19 force event register (sdhc_fevt).......................................................................................................... 1611 52.4.20 adma error status register (sdhc_admaes) ...................................................................................... 1614 52.4.21 adma system address register (sdhc_adsaddr)............................................................................. 1616 52.4.22 vendor specific register (sdhc_vendor) ............................................................................................ 1616 52.4.23 mmc boot register (sdhc_mmcboot) ................................................................................................ 1618 52.4.24 host controller version (sdhc_hostver) ............................................................................................ 1619 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 51 section number title page 52.5 functional description................................................................................................................................................... 1620 52.5.1 data buffer ................................................................................................................................................... 1620 52.5.2 dma crossbar switch interface.................................................................................................................... 1626 52.5.3 sd protocol unit ........................................................................................................................................... 1632 52.5.4 clock & reset manager ................................................................................................................................. 1634 52.5.5 clock generator ............................................................................................................................................ 1635 52.5.6 sdio card interrupt ...................................................................................................................................... 1635 52.5.7 card insertion and removal detection .......................................................................................................... 1637 52.5.8 power management and wakeup events....................................................................................................... 1638 52.5.9 mmc fast boot ............................................................................................................................................. 1639 52.6 initialization/application of sdhc ............................................................................................................................... 1641 52.6.1 command send and response receive basic operation ................................................................................. 1641 52.6.2 card identification mode .............................................................................................................................. 1642 52.6.3 card access ................................................................................................................................................... 1647 52.6.4 switch function ............................................................................................................................................ 1658 52.6.5 adma operation ......................................................................................................................................... 1660 52.6.6 fast boot operation ....................................................................................................................................... 1661 52.6.7 commands for mmc/sd/sdio/ce-ata................................................................................................... 1665 52.7 software restrictions ..................................................................................................................................................... 1671 52.7.1 initialization active ....................................................................................................................................... 1671 52.7.2 software polling procedure .......................................................................................................................... 1672 52.7.3 suspend operation ........................................................................................................................................ 1672 52.7.4 data length setting ....................................................................................................................................... 1672 52.7.5 (a)dma address setting .............................................................................................................................. 1672 52.7.6 data port access ........................................................................................................................................... 1673 52.7.7 change clock frequency ............................................................................................................................... 1673 52.7.8 multi-block read ........................................................................................................................................... 1673 k60 sub-family reference manual, rev. 6, nov 2011 52 freescale semiconductor, inc. section number title page chapter 53 integrated interchip sound (i2s) 53.1 introduction ................................................................................................................................................................... 1675 53.1.1 block diagram .............................................................................................................................................. 1675 53.1.2 features ........................................................................................................................................................ 1676 53.1.3 modes of operation ...................................................................................................................................... 1677 53.2 i2s signal descriptions .................................................................................................................................................. 1679 53.3 memory map/register definition ................................................................................................................................... 1683 53.3.1 i 2 s transmit data registers 0 (i2s x _tx0) ................................................................................................. 1685 53.3.2 i 2 s transmit data registers 1 (i2s x _tx1) ................................................................................................. 1685 53.3.3 i 2 s receive data registers 0 (i2s x _rx0) ................................................................................................... 1686 53.3.4 i 2 s receive data registers 1 (i2s x _rx1) ................................................................................................... 1686 53.3.5 i 2 s control register (i2s x _cr) ................................................................................................................... 1687 53.3.6 i 2 s interrupt status register (i2s x _isr) ..................................................................................................... 1690 53.3.7 i 2 s interrupt enable register (i2s x _ier) .................................................................................................... 1695 53.3.8 i 2 s transmit configuration register (i2s x _tcr) ....................................................................................... 1699 53.3.9 i 2 s receive configuration register (i2s x _rcr) ........................................................................................ 1701 53.3.10 i 2 s transmit clock control registers (i2s x _tccr) .................................................................................. 1703 53.3.11 i 2 s receive clock control registers (i2s x _rccr) ................................................................................... 1705 53.3.12 i 2 s fifo control/status register (i2s x _fcsr) .......................................................................................... 1706 53.3.13 i 2 s ac97 control register (i2s x _acnt) ................................................................................................... 1712 53.3.14 i 2 s ac97 command address register (i2s x _acadd) ............................................................................. 1713 53.3.15 i 2 s ac97 command data register (i2s x _acdat) ................................................................................... 1714 53.3.16 i 2 s ac97 tag register (i2s x _atag) ........................................................................................................ 1714 53.3.17 i 2 s transmit time slot mask register (i2s x _tmsk) ................................................................................ 1715 53.3.18 i 2 s receive time slot mask register (i2s x _rmsk) ................................................................................. 1715 53.3.19 i 2 s ac97 channel status register (i2s x _accst) ..................................................................................... 1716 53.3.20 i 2 s ac97 channel enable register (i2s x _accen) ................................................................................... 1716 53.3.21 i 2 s ac97 channel disable register (i2s x _accdis)................................................................................. 1717 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 53 section number title page 53.4 functional description................................................................................................................................................... 1717 53.4.1 detailed operating mode descriptions .......................................................................................................... 1717 53.4.2 i2s clocking ................................................................................................................................................. 1733 53.4.3 external frame and clock operation ............................................................................................................. 1738 53.4.4 receive interrupt enable bit description....................................................................................................... 1740 53.4.5 transmit interrupt enable bit description ..................................................................................................... 1741 53.4.6 internal frame and clock shutdown .............................................................................................................. 1742 53.4.7 reset ............................................................................................................................................................. 1743 53.5 initialization/application information ........................................................................................................................... 1743 chapter 54 general purpose input/output (gpio) 54.1 introduction ................................................................................................................................................................... 1747 54.1.1 features ........................................................................................................................................................ 1747 54.1.2 modes of operation ...................................................................................................................................... 1747 54.1.3 gpio signal descriptions ............................................................................................................................. 1748 54.2 memory map and register definition............................................................................................................................. 1749 54.2.1 port data output register (gpio x _pdor)................................................................................................. 1752 54.2.2 port set output register (gpio x _psor) .................................................................................................... 1752 54.2.3 port clear output register (gpio x _pcor) ................................................................................................ 1753 54.2.4 port toggle output register (gpio x _ptor) ............................................................................................. 1753 54.2.5 port data input register (gpio x _pdir) ..................................................................................................... 1754 54.2.6 port data direction register (gpio x _pddr)............................................................................................. 1754 54.3 functional description................................................................................................................................................... 1755 54.3.1 general purpose input .................................................................................................................................. 1755 54.3.2 general purpose output ................................................................................................................................ 1755 chapter 55 touch sense input (tsi) 55.1 introduction ................................................................................................................................................................... 1757 55.2 features ......................................................................................................................................................................... 1757 k60 sub-family reference manual, rev. 6, nov 2011 54 freescale semiconductor, inc. section number title page 55.3 overview ....................................................................................................................................................................... 1758 55.3.1 electrode capacitance measurement unit ..................................................................................................... 1758 55.3.2 electrode scan unit ....................................................................................................................................... 1759 55.3.3 touch detection unit..................................................................................................................................... 1760 55.4 modes of operation ....................................................................................................................................................... 1760 55.4.1 tsi disabled mode ....................................................................................................................................... 1760 55.4.2 tsi active mode ........................................................................................................................................... 1760 55.4.3 tsi low power mode .................................................................................................................................... 1761 55.4.4 block diagram .............................................................................................................................................. 1761 55.5 tsi signal descriptions.................................................................................................................................................. 1762 55.5.1 tsi_in[15:0] ................................................................................................................................................ 1762 55.6 memory map and register definition............................................................................................................................. 1762 55.6.1 general control and status register (tsi x _gencs) ................................................................................. 1764 55.6.2 scan control register (tsi x _scanc) ....................................................................................................... 1767 55.6.3 pin enable register (tsi x _pen) ................................................................................................................... 1770 55.6.4 status register (tsi x _status) ................................................................................................................. 1773 55.6.5 counter register (tsi x _cntr n ) ................................................................................................................ 1776 55.6.6 channel n threshold register (tsi x _threshld n ) .................................................................................... 1777 55.7 functional descriptions ................................................................................................................................................. 1777 55.7.1 capacitance measurement ............................................................................................................................ 1777 55.7.2 tsi measurement result ............................................................................................................................... 1780 55.7.3 electrode scan unit ....................................................................................................................................... 1781 55.7.4 touch detection unit..................................................................................................................................... 1784 55.8 application information ................................................................................................................................................ 1785 55.8.1 tsi module sensitivity ................................................................................................................................. 1785 chapter 56 jtag controller (jtagc) 56.1 introduction ................................................................................................................................................................... 1787 56.1.1 block diagram .............................................................................................................................................. 1787 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 55 section number title page 56.1.2 features ........................................................................................................................................................ 1788 56.1.3 modes of operation ...................................................................................................................................... 1788 56.2 external signal description............................................................................................................................................ 1790 56.2.1 tcktest clock input ................................................................................................................................ 1790 56.2.2 tditest data input ................................................................................................................................... 1790 56.2.3 tdotest data output ................................................................................................................................ 1790 56.2.4 tmstest mode select............................................................................................................................... 1790 56.3 register description ...................................................................................................................................................... 1791 56.3.1 instruction register ....................................................................................................................................... 1791 56.3.2 bypass register ............................................................................................................................................. 1791 56.3.3 device identification register ....................................................................................................................... 1791 56.3.4 boundary scan register ................................................................................................................................. 1792 56.4 functional description................................................................................................................................................... 1793 56.4.1 jtagc reset configuration .......................................................................................................................... 1793 56.4.2 ieee 1149.1-2001 (jtag) test access port .............................................................................................. 1793 56.4.3 tap controller state machine ....................................................................................................................... 1793 56.4.4 jtagc block instructions ............................................................................................................................ 1795 56.4.5 boundary scan .............................................................................................................................................. 1798 56.5 initialization/application information .......................................................................................................................... 1798 k60 sub-family reference manual, rev. 6, nov 2011 56 freescale semiconductor, inc. chapter 1 about this document overview 1.1.1 purpose this document describes the features, architecture, and programming model of the freescale k60 microcontroller. 1.1.2 audience this document is primarily for system architects and software application developers who are using or considering using the k60 microcontroller in a system. conventions 1.2.1 numbering systems the following suffixes identify different numbering systems: this suffix identifies a b binary number. for example, the binary equivalent of the number 5 is written 101b. in some cases, binary numbers are shown with the prefix 0b . d decimal number. decimal numbers are followed by this suffix only when the possibility of confusion exists. in general, decimal numbers are shown without a suffix. h hexadecimal number. for example, the hexadecimal euivalent of the number 60 is written ch. in some cases, hexadecimal numbers are shown with the prefix 0x . 1.1 1.2 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 7 1.2.2 typographic notation the following typographic notation is used throughout this document: example description placeholder , x items in italics are placeholders for information that you provide. italicized text is also used for the titles of publications and for emphasis. plain lowercase letters are also used as placeholders for single letters and numbers. code fixed-width type indicates text that must be typed exactly as shown. it is used for instruction mnemonics, directives, symbols, subcommands, parameters, and operators. fixed-width type is also used for example code. instruction mnemonics and directives in text and tables are shown in all caps; for example, bsr. sr[scm] a mnemonic in brackets represents a named field in a register. this example refers to the scaling mode (scm) field in the status register (sr). revno[6:4], xad[7:0] numbers in brackets and separated by a colon represent either: C a subset of a registers named field for example, revno[6:4] refers to bits 64 that are part of the corerev field that occupies bits 60 of the revno register. C a continuous range of individual signals of a bus for example, xad[7:0] refers to signals 70 of the xad bus. 1.2.3 special terms the following terms have special meanings: term meaning asserted refers to the state of a signal as follows: an active-high signal is asserted when high (1). an active-low signal is asserted when low (0). deasserted refers to the state of a signal as follows: an active-high signal is deasserted when low (0). an active-low signal is deasserted when high (1). in some cases, deasserted signals are described as negated . reserved refers to a memory space, register, or field that is either reserved for future use or for which, when written to, the module or chip behavior is unpredictable. conventions 60 sub-family reference manual, rev. 6, nov 2011 8 freescale semiconductor, inc. chapter 2 introduction 2.1 overview this chapter provides an overview of the kinetis portfolio and k60 family of products. it also presents high-level descriptions of the modules available on the devices covered by this document. 2.2 k60 family introduction the k60 mcu family includes ieee 1588 ethernet, full- and high-speed usb 2.0 on- the-go with device charger detect capability, hardware encryption and tamper detection capabilities. devices start from 256 kb of flash in 100lqfp packages extending up to 1 mb in a 256mapbga package with a rich suite of analog, communication, timing and control peripherals. high memory density k60 family devices include an optional single precision floating point unit, nand flash controller and dram controller. 2.3 module functional categories the modules on this device are grouped into functional categories. the following sections describe the modules assigned to each category in more detail. table 2-1. module functional categories module category description arm cortex-m4 core 32-bit mcu core from arms cortex-m class adding dsp instructions, 1.25 dmips/mhz, based on armv7 architecture table continues on the next page... 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. table 2-1. module functional categories (continued) module category description system ? system integration module ? power management and mode controllers ? multiple power modes available based on run, wait, stop, and power- down modes ? low-leakage wakeup unit ? miscellaneous control module ? crossbar switch ? memory protection unit ? peripheral bridge ? direct memory access (dma) controller with multiplexer to increase available dma requests ? external watchdog monitor ? watchdog memories ? internal memories include: ? program flash memory ? on devices with flexmemory: flexmemory ? flexnvm ? flexram ? on devices with program flash only: programming acceleration ram ? sram ? external memory or peripheral bus interface: flexbus ? serial programming interface: ezport clocks ? multiple clock generation options available from internally- and externally- generated clocks ? system oscillator to provide clock source for the mcu ? rtc oscillator to provide clock source for the rtc security ? cyclic redundancy check module for error detection ? hardware encryption, along with a random number generator analog ? high speed analog-to-digital converter with integrated programmable gain amplifier ? comparator ? digital-to-analog converter ? internal voltage reference timers ? programmable delay block ? flextimers ? periodic interrupt timer ? low power timer ? carrier modulator transmitter ? independent real time clock communications ? ethernet mac with ieee 1588 capability ? usb otg controller with built-in fs/ls transceiver ? usb device charger detect ? usb voltage regulator ? can ? serial peripheral interface ? inter-integrated circuit (i 2 c) ? uart ? secured digital host controller ? integrated interchip sound (i 2 s) human-machine interfaces (hmi) ? general purpose input/output controller ? capacitive touch sense input interface enabled in hardware module functional categories k60 sub-family reference manual, rev. 6, nov 2011 60 freescale semiconductor, inc. 2.3.1 arm cortex-m4 core modules the following core modules are available on this device. table 2-2. core modules module description arm cortex-m4 the arm cortex-m4 is the newest member of the cortex m series of processors targeting microcontroller cores focused on very cost sensitive, deterministic, interrupt driven environments. the cortex m4 processor is based on the armv7 architecture and thumbC-2 isa and is upward compatible with the cortex m3, cortex m1, and cortex m0 architectures. cortex m4 improvements include an armv7 thumb-2 dsp (ported from the armv7-a/r profile architectures) providing 32-bit instructions with simd (single instruction multiple data) dsp style multiply- accumulates and saturating arithmetic. nvic the armv7-m exception model and nested-vectored interrupt controller (nvic) implement a relocatable vector table supporting many external interrupts, a single non-maskable interrupt (nmi), and priority levels. the nvic replaces shadow registers with equivalent system and simplified programmability. the nvic contains the address of the function to execute for a particular handler. the address is fetched via the instruction port allowing parallel register stacking and look-up. the first sixteen entries are allocated to arm internal sources with the others mapping to mcu-defined interrupts. awic the primary function of the asynchronous wake-up interrupt controller (awic) is to detect asynchronous wake-up events in stop modes and signal to clock control logic to resume system clocking. after clock restart, the nvic observes the pending interrupt and performs the normal interrupt or event processing. debug interfaces most of this device's debug is based on the arm coresight architecture. four debug interfaces are supported: ieee 1149.1 jtag ieee 1149.7 jtag (cjtag) serial wire debug (swd) arm real-time trace interface 2.3.2 system modules the following system modules are available on this device. table 2-3. system modules module description system integration module (sim) the sim includes integration logic and several module configuration settings. mode controller the mc provides control and protection on entry and exit to each power mode, control for the power management controller (pmc), and reset entry and exit for the complete mcu. table continues on the next page... chapter 2 introduction 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 61 table 2-3. system modules (continued) module description power management controller (pmc) the pmc provides the user with multiple power options. ten different modes are supported that allow the user to optimize power consumption for the level of functionality needed. includes power-on-reset (por) and integrated low voltage detect (lvd) with reset (brownout) capability and selectable lvd trip points. low-leakage wakeup unit (llwu) the llwu module allows the device to wake from low leakage power modes (lls and vlls) through various internal peripheral and external pin sources. miscellaneous control module (mcm) the mcm includes integration logic and embedded trace buffer details. crossbar switch (xbs) the xbs connects bus masters and bus slaves, allowing all bus masters to access different bus slaves simultaneously and providing arbitration among the bus masters when they access the same slave. memory protection unit (mpu) the mpu provides memory protection and task isolation. it concurrently monitors all bus master transactions for the slave connections. peripheral bridges the peripheral bridge converts the crossbar switch interface to an interface to access a majority of peripherals on the device. dma multiplexer (dmamux) the dma multiplexer selects from many dma requests down to 16 for the dma controller. direct memory access (dma) controller the dma controller provides programmable channels with transfer control descriptors for data movement via dual-address transfers for 8-, 16-, 32- and 128- bit data values. external watchdog monitor (ewm) the ewm is a redundant mechanism to the software watchdog module that monitors both internal and external system operation for fail conditions. software watchdog (wdog) the wdog monitors internal system operation and forces a reset in case of failure. it can run from an independent 1 khz low power oscillator with a programmable refresh window to detect deviations in program flow or system frequency. 2.3.3 memories and memory interfaces the following memories and memory interfaces are available on this device. table 2-4. memories and memory interfaces module description flash memory program flash memory non-volatile flash memory that can execute program code flexmemory encompasses the following memory types: for devices with flexnvm: flexnvm non-volatile flash memory that can execute program code, store data, or backup eeprom data for devices with flexnvm: flexram ram memory that can be used as traditional ram or as high-endurance eeprom storage, and also accelerates flash programming for devices with only program flash memory: programming acceleration ram ram memory that accelerates flash programming flash memory controller manages the interface between the device and the on-chip flash memory. table continues on the next page... module functional categories 60 sub-family reference manual, rev. 6, nov 2011 62 freescale semiconductor, inc. table 2-4. memories and memory interfaces (continued) module description sram internal system ram. partial sram kept powered in vlls2 low leakage mode. sram controller manages simultaneous accesses to system ram by multiple master peripherals and core. system register file 32-byte register file that is accessible during all power modes and is powered by vdd. vbat register file 32-byte register file that is accessible during all power modes and is powered by vbat. serial programming interface (ezport) same serial interface as, and subset of, the command set used by industry- standard spi flash memories. provides the ability to read, erase, and program flash memory and reset command to boot the system after flash programming. flexbus external bus interface with multiple independent, user-programmable chip-select signals that can interface with external sram, prom, eprom, eeprom, flash, and other peripherals via 8-, 16- and 32-bit port sizes. configurations include multiplexed or non-multiplexed address and data buses using 8-bit, 16-bit, 32-bit, and 16-byte line-sized transfers. 2.3.4 clocks the following clock modules are available on this device. table 2-5. clock modules module description multi-clock generator (mcg) the mcg provides several clock sources for the mcu that include: phase-locked loop (pll) voltage-controlled oscillator (vco) frequency-locked loop (fll) digitally-controlled oscillator (dco) internal reference clocks can be used as a clock source for other on-chip peripherals system oscillator the system oscillator, in conjunction with an external crystal or resonator, generates a reference clock for the mcu. real-time clock oscillator the rtc oscillator has an independent power supply and supports a 32 khz crystal oscillator to feed the rtc clock. optionally, the rtc oscillator can replace the system oscillator as the main oscillator source. 2.3.5 security and integrity modules the following security and integrity modules are available on this device: chapter 2 introduction k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 63 table 2-6. security and integrity modules module description cryptographic acceleration unit (cau) supports des, 3des, aes, md5, sha-1, and sha-256 algorithms via simple c calls to optimized security functions provided by freescale. random number generator (rng) supports the key generation algorithm defined in the digital signature standard. cyclic redundancy check (crc) hardware crc generator circuit using 16/32-bit shift register. error detection for all single, double, odd, and most multi-bit errors, programmable initial seed value, and optional feature to transpose input data and crc result via transpose register. 2.3.6 analog modules the following analog modules are available on this device: table 2-7. analog modules module description 16-bit analog-to-digital converters (adc) and programmable-gain amplifiers (pga) 16-bit successive-approximation adc designed with integrated programmable gain amplifiers (pga) analog comparators compares two analog input voltages across the full range of the supply voltage. 6-bit digital-to-analog converters (dac) 64-tap resistor ladder network which provides a selectable voltage reference for applications where voltage reference is needed. 12-bit digital-to-analog converters (dac) low-power general-purpose dac, whose output can be placed on an external pin or set as one of the inputs to the analog comparator or adc. voltage reference (vref) supplies an accurate voltage output that is trimmable in 0.5 mv steps. the vref can be used in medical applications, such as glucose meters, to provide a reference voltage to biosensors or as a reference to analog peripherals, such as the adc, dac, or cmp. 2.3.7 timer modules the following timer modules are available on this device: module functional categories k60 sub-family reference manual, rev. 6, nov 2011 64 freescale semiconductor, inc. table 2-8. timer modules module description programmable delay block (pdb) ? 16-bit resolution ? 3-bit prescaler ? positive transition of trigger event signal initiates the counter ? supports two triggered delay output signals, each with an independently- controlled delay from the trigger event ? outputs can be ord together to schedule two conversions from one input trigger event and can schedule precise edge placement for a pulsed output. this feature is used to generate the control signal for the cmp windowing feature and output to a package pin if needed for applications, such as critical conductive mode power factor correction. ? continuous-pulse output or single-shot mode supported, each output is independently enabled, with possible trigger events ? supports bypass mode ? supports dma flexible timer modules (ftm) ? selectable ftm source clock, programmable prescaler ? 16-bit counter supporting free-running or initial/final value, and counting is up or up-down ? input capture, output compare, and edge-aligned and center-aligned pwm modes ? operation of ftm channels as pairs with equal outputs, pairs with complimentary outputs, or independent channels with independent outputs ? deadtime insertion is available for each complementary pair ? generation of hardware triggers ? software control of pwm outputs ? up to 4 fault inputs for global fault control ? configurable channel polarity ? programmable interrupt on input capture, reference compare, overflowed counter, or detected fault condition ? quadrature decoder with input filters, relative position counting, and interrupt on position count or capture of position count on external event ? dma support for ftm events periodic interrupt timers (pit) ? four general purpose interrupt timers ? interrupt timers for triggering adc conversions ? 32-bit counter resolution ? clocked by system clock frequency ? dma support low-power timer (lptimer) ? selectable clock for prescaler/glitch filter of 1 khz (internal lpo), 32.768 khz (external crystal), or internal reference clock ? configurable glitch filter or prescaler with 16-bit counter ? 16-bit time or pulse counter with compare ? interrupt generated on timer compare ? hardware trigger generated on timer compare carrier modulator timer (cmt) ? four cmt modes of operation: ? time with independent control of high and low times ? baseband ? frequency shift key (fsk) ? direct software control of cmt_iro pin ? extended space operation in time, baseband, and fsk modes ? selectable input clock divider ? interrupt on end of cycle with the ability to disable cmt_iro pin and use as timer interrupt ? dma support table continues on the next page... chapter 2 introduction 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 6 table 2-8. timer modules (continued) module description real-time clock (rtc) ? independent power supply, por, and 32 khz crystal oscillator ? 32-bit seconds counter with 32-bit alarm ? 16-bit prescaler with compensation that can correct errors between 0.12 ppm and 3906 ppm ieee 1588 timers ? the 10/100 ethernet module contains timers to provide ieee 1588 time stamping 2.3.8 communication interfaces the following communication interfaces are available on this device: table 2-9. communication modules module description ethernet mac with ieee 1588 capability (enet) 10/100 mb/s ethernet mac (mii and rmii) with hardware support for ieee 1588 usb otg (low-/full-speed) usb 2.0 compliant module with support for host, device, and on-the-go modes. includes an on-chip transceiver for full and low speeds. usb device charger detect (usbdcd) the usbdcd monitors the usb data lines to detect a smart charger meeting the usb battery charging specification rev1.1. this information allows the mcu to better manage the battery charging ic in a portable device. usb voltage regulator up to 5 v regulator input typically provided by usb vbus power with 3.3 v regulated output that powers on-chip usb subsystem, capable of sourcing 120 ma to external board components. controller area network (can) supports the full implementation of the can specification version 2.0, part b serial peripheral interface (spi) synchronous serial bus for communication to an external device inter-integrated circuit (i2c) allows communication between a number of devices. also supports the system management bus (smbus) specification, version 2. universal asynchronous receiver/ transmitters (uart) asynchronous serial bus communication interface with programmable 8- or 9-bit data format and support of iso 7816 smart card interface secure digital host controller (sdhc) interface between the host system and the sd, sdio, mmc, or ce-ata cards. the sdhc acts as a bridge, passing host bus transactions to the cards by sending commands and performing data accesses to/from the cards. it handles the sd, sdio, mmc, and ce-ata protocols at the transmission level. i2s the i 2 s is a full-duplex, serial port that allows the chip to communicate with a variety of serial devices, such as standard codecs, digital signal processors (dsps), microprocessors, peripherals, and audio codecs that implement the inter- ic sound bus (i 2 s) and the intel C ac97 standards 2.3.9 human-machine interfaces the following human-machine interfaces (hmi) are available on this device: module functional categories k60 sub-family reference manual, rev. 6, nov 2011 66 freescale semiconductor, inc. table 2-10. hmi modules module description general purpose input/output (gpio) all general purpose input or output (gpio) pins are capable of interrupt and dma request generation. all gpio pins have 5 v tolerance. capacitive touch sense input (tsi) contains up to 16 channel inputs for capacitive touch sensing applications. operation is available in low-power modes via interrupts. 2.4 orderable part numbers the following table summarizes the part numbers of the devices covered by this document. table 2-11. orderable part numbers summary freescale part number cpu frequenc y pin count package total flash memory program flash eeprom sram gpio mk60dn256zvll10 100 mhz 100 lqfp 256 kb 256 kb 64 kb 66 mk60dx256zvll10 100 mhz 100 lqfp 512 kb 256 kb 4 kb 64 kb 66 mk60dn512zvll10 100 mhz 100 lqfp 512 kb 512 kb 128 kb 66 chapter 2 introduction k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 67 orderable part numbers k60 sub-family reference manual, rev. 6, nov 2011 68 freescale semiconductor, inc. chapter 3 chip configuration 3.1 introduction this chapter provides details on the individual modules of the microcontroller. it includes: ? module block diagrams showing immediate connections within the device, ? specific module-to-module interactions not necessarily discussed in the individual module chapters, and ? links for more information. core modules 3.2.1 arm cortex-m4 core configuration this section summarizes how the module has been configured in the chip. full documentation for this module is provided by arm and can be found at http:// www.arm.com . 3.2 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 69 ppb modules ppb arm cortex-m4 core debug interrupts crossbar switch sram upper sram lower figure 3-1. core configuration table 3-1. reference links to related information topic related module reference full description arm cortex-m4 core, r0p0 http://www.arm.com system memory map system memory map clocking clock distribution power management power management system/instruction/data bus module crossbar switch crossbar switch system/instruction/data bus module sram sram debug ieee 1149.1 jtag ieee 1149.7 jtag (cjtag) serial wire debug (swd) arm real-time trace interface debug interrupts nested vectored interrupt controller (nvic) nvic private peripheral bus (ppb) module miscellaneous control module (mcm) mcm private peripheral bus (ppb) module memory-mapped cryptographic acceleration unit (mmcau) mmcau 3.2.1.1 buses, interconnects, and interfaces the arm cortex-m4 core has four buses as described in the following table. core modules k60 sub-family reference manual, rev. 6, nov 2011 70 freescale semiconductor, inc. bus name description instruction code (icode) bus the icode and dcode buses are muxed. this muxed bus is called the code bus and is connected to the crossbar switch via a single master port. in addition, the code bus is also tightly coupled to the lower half of the system ram (sram_l). data code (dcode) bus system bus the system bus is connected to a separate master port on the crossbar. in addition, the system bus is tightly coupled to the upper half system ram (sram_u). private peripheral (ppb) bus the ppb provides access to these modules: ? arm modules such as the nvic, etm, itm, dwt, fbp, and rom table ? freescale miscellaneous control module (mcm) ? memory-mapped cryptographic acceleration unit (mmcau) 3.2.1.2 system tick timer the system tick timer's clock source is always the core clock, fclk. this results in the following: ? the clksource bit in systick control and status register is always set to select the core clock. ? because the timing reference (fclk) is a variable frequency, the tenms bit in the systick calibration value register is always zero. ? the noref bit in systick calibration value register is always set, implying that fclk is the only available source of reference timing. 3.2.1.3 debug facilities this device has extensive debug capabilities including run control and tracing capabilities. the standard arm debug port that supports jtag and swd interfaces. also the cjtag interface is supported on this device. 3.2.1.4 core privilege levels the arm documentation uses different terms than this document to distinguish between privilege levels. if you see this term... it also means this term... privileged supervisor unprivileged or user user chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 71 3.2.2 nested vectored interrupt controller (nvic) configuration this section summarizes how the module has been configured in the chip. full documentation for this module is provided by arm and can be found at http:// www.arm.com . nested vectored interrupt controller (nvic) arm cortex-m4 core interrupts module module module ppb figure 3-2. nvic configuration table 3-2. reference links to related information topic related module reference full description nested vectored interrupt controller (nvic) http://www.arm.com system memory map system memory map clocking clock distribution power management power management private peripheral bus (ppb) arm cortex-m4 core arm cortex-m4 core 3.2.2.1 interrupt priority levels this device supports 16 priority levels for interrupts. therefore, in the nvic each source in the ipr registers contains 4 bits. for example, ipr0 is shown below: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r irq3 0 0 0 0 irq2 0 0 0 0 irq1 0 0 0 0 irq0 0 0 0 0 w 3.2.2.2 non-maskable interrupt the non-maskable interrupt request to the nvic is controlled by the external nmi signal. the pin the nmi signal is multiplexed on, must be configured for the nmi function to generate the non-maskable interrupt request. core modules k60 sub-family reference manual, rev. 6, nov 2011 72 freescale semiconductor, inc. 3.2.2.3 interrupt channel assignments the interrupt source assignments are defined in the following table. ? vector number the value stored on the stack when an interrupt is serviced. ? irq number non-core interrupt source count, which is the vector number minus 16. the irq number is used within arm's nvic documentation. table 3-4. interrupt vector assignments address vector irq 1 nvic non-ipr register number 2 nvic ipr register number 3 source module source description arm core system handler vectors 0x0000_0000 0 ? ? ? arm core initial stack pointer 0x0000_0004 1 ? ? ? arm core initial program counter 0x0000_0008 2 ? ? ? arm core non-maskable interrupt (nmi) 0x0000_000c 3 ? ? ? arm core hard fault 0x0000_0010 4 ? ? ? arm core memmanage fault 0x0000_0014 5 ? ? ? arm core bus fault 0x0000_0018 6 ? ? ? arm core usage fault 0x0000_001c 7 ? ? ? 0x0000_0020 8 ? ? ? 0x0000_0024 9 ? ? ? 0x0000_0028 10 ? ? ? 0x0000_002c 11 ? ? ? arm core supervisor call (svcall) 0x0000_0030 12 ? ? ? arm core debug monitor 0x0000_0034 13 ? ? ? 0x0000_0038 14 ? ? ? arm core pendable request for system service (pendablesrvreq) 0x0000_003c 15 ? ? ? arm core system tick timer (systick) non-core vectors 0x0000_0040 16 0 0 0 dma dma channel 0 transfer complete 0x0000_0044 17 1 0 0 dma dma channel 1 transfer complete 0x0000_0048 18 2 0 0 dma dma channel 2 transfer complete 0x0000_004c 19 3 0 0 dma dma channel 3 transfer complete 0x0000_0050 20 4 0 1 dma dma channel 4 transfer complete table continues on the next page... chapter chip configuration 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 7 table 3-4. interrupt vector assignments (continued) address vector irq 1 nvic non-ipr register number 2 nvic ipr register number 3 source module source description 0x0000_0054 21 5 0 1 dma dma channel 5 transfer complete 0x0000_0058 22 6 0 1 dma dma channel 6 transfer complete 0x0000_005c 23 7 0 1 dma dma channel 7 transfer complete 0x0000_0060 24 8 0 2 dma dma channel 8 transfer complete 0x0000_0064 25 9 0 2 dma dma channel 9 transfer complete . 0x0000_0068 26 10 0 2 dma dma channel 10 transfer complete 0x0000_006c 27 11 0 2 dma dma channel 11 transfer complete 0x0000_0070 28 12 0 3 dma dma channel 12 transfer complete 0x0000_0074 29 13 0 3 dma dma channel 13 transfer complete 0x0000_0078 30 14 0 3 dma dma channel 14 transfer complete 0x0000_007c 31 15 0 3 dma dma channel 15 transfer complete 0x0000_0080 32 16 0 4 dma dma error interrupt channels 0-15 0x0000_0084 33 17 0 4 mcm normal interrupt 0x0000_0088 34 18 0 4 flash memory command complete 0x0000_008c 35 19 0 4 flash memory read collision 0x0000_0090 36 20 0 5 mode controller low-voltage detect, low-voltage warning 0x0000_0094 37 21 0 5 llwu low leakage wakeup note: the llwu interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit stop mode on an lls recovery. 0x0000_0098 38 22 0 5 wdog watchdog interrupt 0x0000_009c 39 23 0 5 rng randon number generator 0x0000_00a0 40 24 0 6 i 2 c0 0x0000_00a4 41 25 0 6 i 2 c1 0x0000_00a8 42 26 0 6 spi0 single interrupt vector for all sources 0x0000_00ac 43 27 0 6 spi1 single interrupt vector for all sources 0x0000_00b0 44 28 0 7 spi2 single interrupt vector for all sources 0x0000_00b4 45 29 0 7 can0 ored message buffer (0-15) 0x0000_00b8 46 30 0 7 can0 bus off 0x0000_00bc 47 31 0 7 can0 error 0x0000_00c0 48 32 1 8 can0 transmit warning table continues on the next page... core modules 60 sub-family reference manual, rev. 6, nov 2011 74 freescale semiconductor, inc. table 3-4. interrupt vector assignments (continued) address vector irq 1 nvic non-ipr register number 2 nvic ipr register number 3 source module source description 0x0000_00c4 49 33 1 8 can0 receive warning 0x0000_00c8 50 34 1 8 can0 wake up 0x0000_00cc 51 35 1 8 0x0000_00d0 52 36 1 9 0x0000_00d4 53 37 1 9 can1 ored message buffer (0-15) 0x0000_00d8 54 38 1 9 can1 bus off 0x0000_00dc 55 39 1 9 can1 error 0x0000_00e0 56 40 1 10 can1 transmit warning 0x0000_00e4 57 41 1 10 can1 receive warning 0x0000_00e8 58 42 1 10 can1 wake up 0x0000_00ec 59 43 1 10 0x0000_00f0 60 44 1 11 0x0000_00f4 61 45 1 11 uart0 single interrupt vector for uart status sources 0x0000_00f8 62 46 1 11 uart0 single interrupt vector for uart error sources 0x0000_00fc 63 47 1 11 uart1 single interrupt vector for uart status sources 0x0000_0100 64 48 1 12 uart1 single interrupt vector for uart error sources 0x0000_0104 65 49 1 12 uart2 single interrupt vector for uart status sources 0x0000_0108 66 50 1 12 uart2 single interrupt vector for uart error sources 0x0000_010c 67 51 1 12 uart3 single interrupt vector for uart status sources 0x0000_0110 68 52 1 13 uart3 single interrupt vector for uart error sources 0x0000_0114 69 53 1 13 uart4 single interrupt vector for uart status sources 0x0000_0118 70 54 1 13 uart4 single interrupt vector for uart error sources 0x0000_011c 71 55 1 13 0x0000_0120 72 56 1 14 0x0000_0124 73 57 1 14 adc0 0x0000_0128 74 58 1 14 adc1 table continues on the next page... chapter chip configuration 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 7 table 3-4. interrupt vector assignments (continued) address vector irq 1 nvic non-ipr register number 2 nvic ipr register number 3 source module source description 0x0000_012c 75 59 1 14 cmp0 0x0000_0130 76 60 1 15 cmp1 0x0000_0134 77 61 1 15 cmp2 0x0000_0138 78 62 1 15 ftm0 single interrupt vector for all sources 0x0000_013c 79 63 1 15 ftm1 single interrupt vector for all sources 0x0000_0140 80 64 2 16 ftm2 single interrupt vector for all sources 0x0000_0144 81 65 2 16 cmt 0x0000_0148 82 66 2 16 rtc alarm interrupt 0x0000_014c 83 67 2 16 0x0000_0150 84 68 2 17 pit channel 0 0x0000_0154 85 69 2 17 pit channel 1 0x0000_0158 86 70 2 17 pit channel 2 0x0000_015c 87 71 2 17 pit channel 3 0x0000_0160 88 72 2 18 pdb 0x0000_0164 89 73 2 18 usb otg 0x0000_0168 90 74 2 18 usb charger detect 0x0000_016c 91 75 2 18 ethernet mac ieee 1588 timer interrupt 0x0000_0170 92 76 2 19 ethernet mac transmit interrupt 0x0000_0174 93 77 2 19 ethernet mac receive interrupt 0x0000_0178 94 78 2 19 ethernet mac error and miscellaneous interrupt 0x0000_017c 95 79 2 19 i 2 s0 0x0000_0180 96 80 2 20 sdhc 0x0000_0184 97 81 2 20 dac0 0x0000_0188 98 82 2 20 0x0000_018c 99 83 2 20 tsi single interrupt vector for all sources 0x0000_0190 100 84 2 21 mcg 0x0000_0194 101 85 2 21 low power timer 0x0000_0198 102 86 2 21 0x0000_019c 103 87 2 21 port control module pin detect (port a) 0x0000_01a0 104 88 2 22 port control module pin detect (port b) table continues on the next page... core modules 60 sub-family reference manual, rev. 6, nov 2011 76 freescale semiconductor, inc. table 3-4. interrupt vector assignments (continued) address vector irq 1 nvic non-ipr register number 2 nvic ipr register number 3 source module source description 0x0000_01a4 105 89 2 22 port control module pin detect (port c) 0x0000_01a8 106 90 2 22 port control module pin detect (port d) 0x0000_01ac 107 91 2 22 port control module pin detect (port e) 0x0000_01b0 108 92 2 23 0x0000_01b4 109 93 2 23 0x0000_01b8 110 94 2 23 software software interrupt 4 1. indicates the nvics interrupt source number. 2. indicates the nvics iser, icer, ispr, icpr, and iabr register number used for this irq. the equation to calculate this value is: irq div 32 3. indicates the nvics ipr register number used for this irq. the equation to calculate this value is: irq div 4 4. this interrupt can only be pended or cleared via the nvic registers. 3.2.2.3.1 determining the bitfield and register location for configuring a particular interrupt suppose you need to configure the low-power timer (lptmr) interrupt. the following table is an excerpt of the lptmr row from interrupt channel assignments . table 3-5. lptmr interrupt vector assignment address vector irq 1 nvic non-ipr register number 2 nvic ipr register number 3 source module source description 0x0000_0194 101 85 2 21 low power timer 1. indicates the nvic's interrupt source number. 2. indicates the nvic's iser, icer, ispr, icpr, and iabr register number used for this irq. the equation to calculate this value is: irq div 32 3. indicates the nvic's ipr register number used for this irq. the equation to calculate this value is: irq div 4 ? the nvic registers you would use to configure the interrupt are: ? nviciser2 ? nvicicer2 ? nvicispr2 ? nvicicpr2 chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 77 ? nviciabr2 ? nvicipr21 ? to determine the particular irq's bitfield location within these particular registers: ? nviciser2, nvicicer2, nvicispr2, nvicicpr2, nviciabr2 bit location = irq mod 32 = 21 ? nvicipr21 bitfield starting location = 8 * (irq mod 4) + 4 = 12 since the nvicipr bitfields are 4-bit wide ( 16 priority levels ), the nvicipr21 bitfield range is 12-15 therefore, the following bitfield locations are used to configure the lptmr interrupts: ? nviciser2[21] ? nvicicer2[21] ? nvicispr2[21] ? nvicicpr2[21] ? nviciabr2[21] ? nvicipr21[15:12] 3.2.3 asynchronous wake-up interrupt controller (awic) configuration this section summarizes how the module has been configured in the chip. full documentation for this module is provided by arm and can be found at http:// www.arm.com . asynchronous wake-up interrupt controller (awic) nested vectored interrupt controller (nvic) wake-up requests module module clock logic figure 3-3. asynchronous wake-up interrupt controller configuration table 3-6. reference links to related information topic related module reference system memory map system memory map clocking clock distribution table continues on the next page... core modules 60 sub-family reference manual, rev. 6, nov 2011 78 freescale semiconductor, inc. table 3-6. reference links to related information (continued) topic related module reference power management power management nested vectored interrupt controller (nvic) nvic wake-up requests awic wake-up sources 3.2.3.1 wake-up sources the device uses the following internal and external inputs to the awic module. table 3-7. awic stop and vlps wake-up sources wake-up source description available system resets reset pin and wdog when lpo is its clock source, and jtag low-voltage detect mode controller low-voltage warning mode controller pin interrupts port control module - any enabled pin interrupt is capable of waking the system adcx the adc is functional when using internal clock source cmpx since no system clocks are available, functionality is limited i 2 c address match wakeup uart active edge on rxd usb wakeup lptmr functional in stop/vlps modes rtc functional in stop/vlps modes ethernet magic packet wakeup sdhc wakeup i2s wakeup 1588 timer wakeup tsi can 3.2.4 jtag controller configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 79 signal multiplexing jtag controller cjtag figure 3-4. jtagc controller configuration table 3-8. reference links to related information topic related module reference full description jtagc jtagc signal multiplexing port control signal multiplexing system modules 3.3.1 sim configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. register access peripheral bridge system integration module (sim) figure 3-5. sim configuration table 3-9. reference links to related information topic related module reference full description sim sim system memory map system memory map clocking clock distribution power management power management 3.3 system modules k60 sub-family reference manual, rev. 6, nov 2011 80 freescale semiconductor, inc. 3.3.2 mode controller configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. power management controller (pmc) register access peripheral bridge mode controller resets figure 3-6. mode controller configuration table 3-10. reference links to related information topic related module reference full description mode controller mode controller system memory map system memory map power management power management power management controller (pmc) pmc 3.3.3 pmc configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 81 mode controller register access peripheral bridge power management controller (pmc) figure 3-7. pmc configuration table 3-11. reference links to related information topic related module reference full description pmc pmc system memory map system memory map power management power management full description mode controller mode controller low-leakage wakeup unit (llwu) llwu 3.3.4 low-leakage wake-up unit (llwu) configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. low-leakage wake-up unit (llwu) power management controller (pmc) peripheral bridge 0 register access wake-up requests module module figure 3-8. low-leakage wake-up unit configuration table 3-12. reference links to related information topic related module reference full description llwu llwu system memory map system memory map table continues on the next page... system modules 60 sub-family reference manual, rev. 6, nov 2011 82 freescale semiconductor, inc. table 3-12. reference links to related information (continued) topic related module reference clocking clock distribution power management power management chapter power management controller (pmc) power management controller (pmc) mode controller mode controller wake-up requests llwu wake-up sources 3.3.4.1 wake-up sources this chip uses the following internal peripheral and external pin inputs as wakeup sources to the llwu module: ? llwu_p0-15 are external pin inputs. see the chip's signal multiplexing table for the individual input signal options. ? llwu_m0if-m7if are connections to the internal peripheral interrupt flags. note reset is also a wakeup source, depending on the bit setting in the llwu_cs register. on devices where reset is not a dedicated pin, it must also be enabled in the explicit port mux control. table 3-13. wakeup sources for llwu inputs input wakeup source input wakeup source llwu_p0 pte1/llwu_p0 pin llwu_p12 ptd0/llwu_p12 pin llwu_p1 pte2/llwu_p1 pin llwu_p13 ptd2/llwu_p13 pin llwu_p2 pte4/llwu_p2 pin llwu_p14 ptd4/llw14_p0 pin llwu_p3 pta4/llwu_p3 pin 1 llwu_p15 ptd6/llwu_p15 pin llwu_p4 pta13/llwu_p4 pin llwu_m0if lptmr 2 llwu_p5 ptb0/llwu_p5 pin llwu_m1if cmp0 2 llwu_p6 ptc1/llwu_p6 pin llwu_m2if cmp1 2 llwu_p7 ptc3/llwu_p7 pin llwu_m3if cmp2 2 llwu_p8 ptc4/llwu_p8 pin llwu_m4if tsi 2 llwu_p9 ptc5/llwu_p9 pin llwu_m5if rtc alarm 2 llwu_p10 ptc6/llwu_p10 pin llwu_m6if reserved llwu_p11 ptc11/llwu_p11 pin llwu_m7if error detect - wake-up source unknown 1. a falling edge input that remains low on this pin when waking up the mcu from vllsx modes with the ezport enabled causes entry into ezport mode during the reset sequence. a falling edge input that remains low on this pin when waking chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 83 up the mcu from any non-vllsx mode with the nmi function selected in its port control register asserts an nmi exception on low power mode recovery. the same occurs when recovering from vllsx modes if ezport is disabled; otherwise, ezport mode is entered. see the "ezport configuration" section in this chapter for more information. 2. requires the peripheral and the peripheral interrupt to be enabled. the llwus wume bit enables the internal module flag as a wakeup input. after wakeup, the flags are cleared based on the peripheral clearing mechanism. 3.3.5 mcm configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. miscellaneous control module (mcm) transfers arm cortex-m4 core ppb figure 3-9. mcm configuration table 3-14. reference links to related information topic related module reference full description miscellaneous control module (mcm) mcm system memory map system memory map clocking clock distribution power management power management transfers private peripheral bus (ppb) arm cortex-m4 core arm cortex-m4 core 3.3.6 crossbar switch configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. system modules k60 sub-family reference manual, rev. 6, nov 2011 84 freescale semiconductor, inc. crossbar switch slave modules sdhc master modules m2 m5 m0 m1 s0 s3 arm core code bus arm core system bus dma ezport mux flash controller s1 sram backdoor s2 peripheral bridge 0 memory protection unit (mpu) mux peripheral bridge 1 gpio controller s4 flexbus mpu usb m4 ethernet m3 figure 3-10. crossbar switch configuration table 3-15. reference links to related information topic related module reference full description crossbar switch crossbar switch system memory map system memory map clocking clock distribution memory protection mpu mpu crossbar switch master arm cortex-m4 core arm cortex-m4 core crossbar switch master dma controller dma controller crossbar switch master ezport ezport crossbar switch master ethernet ethernet crossbar switch master usb fs/ls usb fs/ls crossbar switch master sdhc sdhc crossbar switch slave flash flash crossbar switch slave sram backdoor sram backdoor table continues on the next page... chapter chip configuration 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 8 table 3-15. reference links to related information (continued) topic related module reference crossbar switch slave peripheral bridges peripheral bridge crossbar switch slave gpio controller gpio controller crossbar switch slave flexbus flexbus 3.3.6.1 crossbar switch master assignments the masters connected to the crossbar switch are assigned as follows: master module master port number arm core code bus 0 arm core system bus 1 dma/ezport 2 ethernet 3 usb otg 4 sdhc 5 note the dma and ezport share a master port. since these modules never operate at the same time, no configuration or arbitration explanations are necessary. 3.3.6.2 crossbar switch slave assignments the slaves connected to the crossbar switch are assigned as follows: slave module slave port number protected by mpu? flash memory controller 0 yes sram backdoor 1 yes peripheral bridge 0 1 2 no. protection built into bridge. peripheral bridge 1/gpio 1 3 no. protection built into bridge. flexbus 4 yes 1. see system memory map for access restrictions. 3.3.6.3 prs register reset values the axbs_prs n registers reset to 0054_3210h. system modules k60 sub-family reference manual, rev. 6, nov 2011 86 freescale semiconductor, inc. 3.3.7 memory protection unit (mpu) configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. memory protection unit (mpu) transfers slave slave slave peripheral bridge 0 register access transfers logical master logical master logical master figure 3-11. memory protection unit configuration table 3-16. reference links to related information topic related module reference full description memory protection unit (mpu) mpu system memory map system memory map clocking clock distribution power management power management logical masters logical master assignments slave modules slave module assignments 3.3.7.1 mpu slave port assignments the memory-mapped resources protected by the mpu are: table 3-17. mpu slave port assignments source mpu slave port assignment destination crossbar slave port 0 mpu slave port 0 flash controller crossbar slave port 1 mpu slave port 1 sram backdoor code bus mpu slave port 2 sram_l frontdoor system bus mpu slave port 3 sram_u frontdoor crossbar slave port 4 mpu slave port 4 flexbus chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 87 3.3.7.2 mpu logical bus master assignments the logical bus master assignments for the mpu are: table 3-18. mpu logical bus master assignments mpu logical bus master number bus master 0 core 1 debugger 2 dma 3 enet 4 usb 5 sdhc 6 none 7 none 3.3.7.3 mpu access violation indications access violations detected by the mpu are signaled to the appropriate bus master as shown below: table 3-19. access violation indications bus master core indication core bus fault (interrupt vector #5) note: to enable bus faults set the core's system handler control and state register's busfaultena bit. if this bit is not set, mpu violations result in a hard fault (interrupt vector #3). debugger the stickyerror flag is set in the debug port control/status register. dma interrupt vector #32 ethernet interrupt vector #94 usb_otg interrupt vector #89 sdhc interrupt vector #96 3.3.7.4 reset values for rgd0 registers at reset, the mpu is enabled with a single region descriptor (rgd0) that maps the entire 4 gb address space with read, write and execute permissions given to the core, debugger and the dma bus masters. the following table shows the chip-specific reset values for rgd0 and rgdaac0. system modules k60 sub-family reference manual, rev. 6, nov 2011 88 freescale semiconductor, inc. table 3-20. reset values for rgd0 registers register reset value rgd0_word0 0000_0000h rgd0_word1 ffff_ffffh rgd0_word2 0061_f7dfh rgd0_word3 0000_0001h rgdaac0 0061_f7dfh 3.3.7.5 write access restrictions for rgd0 registers in addition to configuring the initial state of rgd0, the mpu implements further access control on writes to the rgd0 registers. specifically, the mpu assigns a priority scheme where the debugger is treated as the highest priority master followed by the core and then all the remaining masters. the mpu does not allow writes from the core to affect the rgd0 start or end addresses nor the permissions associated with the debugger; it can only write the permission fields associated with the other masters. these protections (summarized below) guarantee that the debugger always has access to the entire address space and those rights cannot be changed by the core or any other bus master. table 3-21. write access to rgd0 registers bus master write access? core partial. the core cannot write to the following registers or register fields: rgd0_word0, rgd0_word1, rgd0_word3 rgd0_word2[m1sm, m1um] rgdaac0[m1sm, m1um] note: changes to the rgd0_word2 alterable fields should be done via a write to rgdaac0. debugger yes all other masters no 3.3.8 peripheral bridge configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 89 peripherals transfers aips-lite peripheral bridge transfers crossbar switch figure 3-12. peripheral bridge configuration table 3-22. reference links to related information topic related module reference full description peripheral bridge (aips-lite) peripheral bridge (aips-lite) system memory map system memory map clocking clock distribution crossbar switch crossbar switch crossbar switch 3.3.8.1 number of peripheral bridges this device contains two identical peripheral bridges. 3.3.8.2 memory maps the peripheral bridges are used to access the registers of most of the modules on this device. see aips0 memory map and aips1 memory map for the memory slot assignment for each module. 3.3.8.3 mpra register each of the two peripheral bridges supports up to 8 crossbar switch masters, each assigned to a mprotx field in the mpra register. however, fewer are supported on this device. see crossbar switch for details of the master port assignments for this device. 3.3.8.4 aips_lite mpra register reset value ? aips x _mpra reset value is 0x7770_0000 therefore, masters 0, 1, and 2 are trusted bus masters after reset. system modules k60 sub-family reference manual, rev. 6, nov 2011 90 freescale semiconductor, inc. 3.3.8.5 pacr registers each of the two peripheral bridges support up to 128 peripherals each assigned to an pacrx field within the pacra-pacrp registers. however, fewer peripherals are supported on this device. see aips0 memory map and aips1 memory map for details of the peripheral slot assignments for this device. unused pacrx fields are reserved. 3.3.8.6 aips_lite pacre-p register reset values the aips x _pacre-p reset values depend on if the module is available on your particular device. for each populated slot in slots 32-127 in peripheral bridge 0 (aips- lite 0) memory map and peripheral bridge 1 (aips-lite 1) memory map , the corresponding module's pacr[32:127] field resets to 0x4. 3.3.9 dma request multiplexer configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. dma request multiplexer dma controller requests module module module peripheral bridge 0 register access channel request figure 3-13. dma request multiplexer configuration table 3-23. reference links to related information topic related module reference full description dma request multiplexer dma mux system memory map system memory map clocking clock distribution power management power management channel request dma controller dma controller requests dma request sources chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 91 3.3.9.1 dma mux request sources this device includes a dma request mux that allows up to 63 dma request signals to be mapped to any of the 16 dma channels. because of the mux there is not a hard correlation between any of the dma request sources and a specific dma channel. table 3-24. dma request sources - mux 0 source number source module source description 0 channel disabled 1 1 reserved not used 2 uart0 receive 3 uart0 transmit 4 uart1 receive 5 uart1 transmit 6 uart2 receive 7 uart2 transmit 8 uart3 receive 9 uart3 transmit 10 uart4 receive 11 uart4 transmit 12 reserved 13 reserved 14 i 2 s0 receive 15 i 2 s0 transmit 16 spi0 receive 17 spi0 transmit 18 spi1 receive 19 spi1 transmit 20 21 22 i 2 c0 23 i 2 c1 24 ftm0 channel 0 25 ftm0 channel 1 26 ftm0 channel 2 table continues on the next page... system modules 60 sub-family reference manual, rev. 6, nov 2011 2 freescale semiconductor, inc. table 3-24. dma request sources - mux 0 (continued) source number source module source description 27 ftm0 channel 3 28 ftm0 channel 4 29 ftm0 channel 5 30 ftm0 channel 6 31 ftm0 channel 7 32 ftm1 channel 0 33 ftm1 channel 1 34 ftm2 channel 0 35 ftm2 channel 1 36 ftm3 channel 0 37 ftm3 channel 1 38 ftm3 channel 2 39 ftm1 channel 3 40 adc0 41 adc1 42 cmp0 43 cmp1 44 cmp2 45 dac0 46 reserved 47 cmt 48 pdb 49 port control module port a 50 port control module port b 51 port control module port c 52 port control module port d 53 port control module port e 54 ftm3 channel 4 55 ftm3 channel 5 56 ftm3 channel 6 57 ftm3 channel 7 58 dma mux always enabled 59 dma mux always enabled 60 dma mux always enabled table continues on the next page... chapter chip configuration 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. table 3-24. dma request sources - mux 0 (continued) source number source module source description 61 dma mux always enabled 62 dma mux always enabled 63 dma mux always enabled 1. configuring a dma channel to select source 0 or any of the reserved sources disables that dma channel. 3.3.9.2 dma transfers via pit trigger the pit module can trigger a dma transfer on the first four dma channels. the assignments are detailed at pit/dma periodic trigger assignments . 3.3.10 dma controller configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. dma controller crossbar switch requests peripheral bridge 0 register access transfers dma multiplexer figure 3-14. dma controller configuration table 3-25. reference links to related information topic related module reference full description dma controller dma controller system memory map system memory map register access peripheral bridge (aips-lite 0) aips-lite 0 clocking clock distribution power management power management transfers crossbar switch crossbar switch system modules k60 sub-family reference manual, rev. 6, nov 2011 94 freescale semiconductor, inc. 3.3.11 external watchdog monitor (ewm) configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. external watchdog monitor (ewm) peripheral bridge 0 register access signal multiplexing module signals figure 3-15. external watchdog monitor configuration table 3-26. reference links to related information topic related module reference full description external watchdog monitor (ewm) ewm system memory map system memory map clocking clock distribution power management power management signal multiplexing port control module signal multiplexing 3.3.11.1 ewm clocks this table shows the ewm clocks and the corresponding chip clocks. table 3-27. ewm clock connections module clock chip clock low power clock 1 khz lpo clock 3.3.11.2 ewm low-power modes this table shows the ewm low-power modes and the corresponding chip low-power modes. chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 95 table 3-28. ewm low-power modes module mode chip mode wait wait, vlpw stop stop, vlps, lls power down vlls3, vlls2, vlls1 3.3.11.3 ewm_out pin state in low power modes during wait, stop and power down modes the ewm_out pin enters a high-impedance state. a user has the option to control the logic state of the pin using an external pull device or by configuring the internal pull device. when the cpu enters a run mode from wait or stop recovery, the pin resumes its previous state before entering wait or stop mode. when the cpu enters run mode from power down, the pin returns to its reset state. 3.3.12 watchdog configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. wdog mode controller peripheral bridge 0 register access figure 3-16. watchdog configuration table 3-29. reference links to related information topic related module reference full description watchdog watchdog system memory map system memory map clocking clock distribution power management power management mode controller (mc) mode controller system modules k60 sub-family reference manual, rev. 6, nov 2011 96 freescale semiconductor, inc. 3.3.12.1 wdog clocks this table shows the wdog module clocks and the corresponding chip clocks. table 3-30. wdog clock connections module clock chip clock lpo oscillator 1 khz lpo clock alt clock bus clock fast test clock bus clock system bus clock bus clock 3.3.12.2 wdog low-power modes this table shows the wdog low-power modes and the corresponding chip low-power modes. table 3-31. wdog low-power modes module mode chip mode wait wait, vlpw standby stop, vlps stop stop, vlps power down lls, vllsx note to enable the wdog module when the chip is in stop mode, write ones to both the stndbyen bit and the stopen bit of the watchdog status and control register high. clock modules 3.4.1 mcg configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. 3.4 chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 97 register access peripheral bridge multipurpose clock generator (mcg) rtc oscillator system oscillator system integration module (sim) figure 3-17. mcg configuration table 3-32. reference links to related information topic related module reference full description mcg mcg system memory map system memory map clocking clock distribution power management power management signal multiplexing port control signal multiplexing 3.4.2 osc configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. signal multiplexing register access peripheral bridge system oscillator mcg module signals figure 3-18. osc configuration table 3-33. reference links to related information topic related module reference full description osc osc system memory map system memory map clocking clock distribution table continues on the next page... cloc modules 60 sub-family reference manual, rev. 6, nov 2011 8 freescale semiconductor, inc. table 3-33. reference links to related information (continued) topic related module reference power management power management signal multiplexing port control signal multiplexing full description mcg mcg 3.4.2.1 osc modes of operation with mcg the mcg's c2 register bits configure the oscillator frequency range. see the osc and mcg chapters for more details. 3.4.3 rtc osc configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. signal multiplexing 32-khz rtc oscillator mcg module signals figure 3-19. rtc osc configuration table 3-34. reference links to related information topic related module reference full description rtc osc rtc osc signal multiplexing port control signal multiplexing full description mcg mcg memories and memory interfaces 3.5.1 flash memory configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. 3.5 chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 99 register access flash memory transfers flash memory controller peripheral bus controller 0 figure 3-20. flash memory configuration table 3-35. reference links to related information topic related module reference full description flash memory flash memory system memory map system memory map clocking clock distribution transfers flash memory controller flash memory controller register access peripheral bridge peripheral bridge 3.5.1.1 flash memory types this device contains the following types of flash memory: ? program flash memory non-volatile flash memory that can execute program code ? flexmemory encompasses the following memory types: ? for devices with flexnvm: flexnvm non-volatile flash memory that can execute program code, store data, or backup eeprom data ? for devices with flexnvm: flexram ram memory that can be used as traditional ram or as high-endurance eeprom storage, and also accelerates flash programming ? for devices with only program flash memory: programming acceleration ram ram memory that accelerates flash programming 3.5.1.2 flash memory sizes the devices covered in this document contain: ? for devices with program flash only: 2 blocks of program flash consisting of 2 kb sectors memories and memory interfaces k60 sub-family reference manual, rev. 6, nov 2011 100 freescale semiconductor, inc. ? for devices that contain flexnvm: 1 block of program flash consisting of 2 kb sectors ? for devices that contain flexnvm: 1 block of flexnvm consisting of 2 kb sectors ? for devices that contain flexnvm: 1 block of flexram the amounts of flash memory for the devices covered in this document are: device program flash (kb) block 0 (p- flash) address range 1 flexnvm (kb) block 1 (flexnvm/ p- flash) address range 1 flexram (kb) flexram address range mk60dn256zv ll10 256 0x0000_0000 ? 0x0001_ffff 0x0002_0000 ? 0x0003_ffff n/a mk60dx256zv ll10 256 0x0000_0000 ? 0x0003_ffff 256 0x1000_0000 ? 0x1003_ffff 4 0x1400_0000 ? 0x1400_0fff mk60dn512zv ll10 512 0x0000_0000 ? 0x0003_ffff 0x0004_0000 ? 0x0007_ffff n/a 1. for program flash only devices: the addresses shown assume program flash swap is disabled (default configuration). 3.5.1.3 flash memory size considerations since this document covers devices that contain program flash only and devices that contain program flash and flexnvm, there are some items to consider when reading the flash memory chapter. ? the flash memory chapter shows a mixture of information depending on the device you are using. ? for the program flash only devices: ? two program flash blocks are supported: program flash 1 and program flash 2. the two blocks are contiguous in the system memory map. ? the program flash blocks support a swap feature in which the starting address of the program flash blocks can be swapped. ? the flexram is not available as eeprom or traditional ram. its space is only used for programming acceleration through the program section command. ? for the devices containing program flash and flexnvm: ? since there is only one program flash block, the program flash swap feature is not available. chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 101 3.5.1.4 flash memory map the various flash memories and the flash registers are located at different base addresses as shown in the following figure. the base address for each is specified in system memory map . program flash flash configuration field program flash base address flash memory base address registers ram programming acceleration ram base address figure 3-21. flash memory map for devices containing only program flash program flash flash configuration field flexnvm base address program flash base address flash memory base address registers flexnvm flexram flexram base address figure 3-22. flash memory map for devices containing flexnvm 3.5.1.5 flash security how flash security is implemented on this device is described in chip security . 3.5.1.6 flash modes the flash memory operates in nvm normal and nvm special modes. the flash memory enters nvm special mode when the ezport is enabled ( ezp_cs asserted during reset), or the system is under debug mode. otherwise, flash memory operates in nvm normal mode. memories and memory interfaces k60 sub-family reference manual, rev. 6, nov 2011 102 freescale semiconductor, inc. 3.5.1.7 erase all flash contents in addition to software, the entire flash memory may be erased external to the flash memory in two ways: 1. via the ezport by issuing a bulk erase (be) command. see the ezport chapter for more details. 2. via the swj-dp debug port by setting dap_control[0]. dap_status[0] is set to indicate the mass erase command has been accepted. dap_status[0] is cleared when the mass erase completes. 3.5.1.8 ftfl_fopt register the flash memory's ftfl_fopt register allows the user to customize the operation of the mcu at boot time. see fopt boot options for details of its definition. 3.5.2 flash memory controller configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. register access flash memory controller transfers memory protection unit peripheral bus controller 0 transfers flash memory crossbar switch figure 3-23. flash memory controller configuration table 3-36. reference links to related information topic related module reference full description flash memory controller flash memory controller system memory map system memory map clocking clock distribution transfers flash memory flash memory table continues on the next page... chapter chip configuration 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 10 table 3-36. reference links to related information (continued) topic related module reference transfers mpu mpu transfers crossbar switch crossbar switch register access peripheral bridge peripheral bridge 3.5.2.1 number of masters the flash memory controller supports up to eight crossbar switch masters. however, this device has a different number of crossbar switch masters. see crossbar switch configuration for details on the master port assignments. 3.5.2.2 program flash swap on devices that contain program flash memory only, the program flash memory blocks may swap their base addresses. while not using swap: ? fmc_pfb0cr controls the lower code addresses (block 0) ? fmc_pfb1cr controls the upper code addresses (block 1) if swap is used, the opposite is true: ? fmc_pfb0cr controls the upper code addresses (now in block 0) ? fmc_pfb1cr controls the lower code addresses (now in block 1) 3.5.3 sram configuration this section summarizes how the module has been configured in the chip. memories and memory interfaces k60 sub-family reference manual, rev. 6, nov 2011 104 freescale semiconductor, inc. sram upper transfers sram controller cortex-m4 core mpu crossbar switch sram lower mpu figure 3-24. sram configuration table 3-37. reference links to related information topic related module reference full description sram sram system memory map system memory map clocking clock distribution transfers sram controller sram controller arm cortex-m4 core arm cortex-m4 core memory protection unit memory protection unit 3.5.3.1 sram sizes this device contains sram tightly coupled to the arm cortex-m4 core. the amount of sram for the devices covered in this document is shown in the following table. device sram (kb) mk60dn256zvll10 64 mk60dx256zvll10 64 mk60dn512zvll10 128 3.5.3.2 sram arrays the on-chip sram is split into two equally-sized logical arrays, sram_l and sram_u. the on-chip ram is implemented such that the sram_l and sram_u ranges form a contiguous block in the memory map. as such: ? sram_l is anchored to 0x1fff_ffff and occupies the space before this ending address. ? sram_u is anchored to 0x2000_0000 and occupies the space after this beginning address. chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 105 valid address ranges for sram_l and sram_u are then defined as: ? sram_l = [0x2000_0000C(sram_size/2)] to 0x1fff_ffff ? sram_u = 0x2000_0000 to [0x2000_0000+(sram_size/2)-1] this is illustrated in the following figure. sram_u 0x2000_0000 sram size / 2 sram_l 0x1fff_ffff sram size / 2 0x2000_0000 ? sram_size/2 0x2000_0000 + sram_size/2 - 1 figure 3-25. sram blocks memory map for example, for a device containing 64 kb of sram the ranges are: ? sram_l: 0x1fff_8000 C 0x1fff_ffff ? sram_u: 0x2000_0000 C 0x2000_7fff 3.5.3.3 sram retention in low power modes the sram is retained down to vlls3 mode. in vlls2 the 4 kb region of sram_u from 0x2000_0000 is powered. in vlls1 no sram is retained. however, the 32-byte register file is available in vlls1. 3.5.3.4 sram accesses the sram is split into two logical arrays that are 32-bits wide. ? sram_l accessible by the code bus of the cortex-m4 core and by the backdoor port. ? sram_u accessible by the system bus of the cortex-m4 core and by the backdoor port. memories and memory interfaces k60 sub-family reference manual, rev. 6, nov 2011 106 freescale semiconductor, inc. the backdoor port makes the sram accessible to the non-core bus masters (such as dma). the following figure illustrates the sram accesses within the device. cortex-m4 core code bus system bus sram controller backdoor sram_l sram_u crossbar switch non-core master non-core master non-core master frontdoor mpu mpu figure 3-26. sram access diagram the following simultaneous accesses can be made to different logical halves of the sram: ? core code and core system ? core code and non-core master ? core system and non-core master note two non-core masters cannot access sram simultaneously. the required arbitration and serialization is provided by the crossbar switch. the sram_{l,u} arbitration is controlled by the sram controller based on the configuration bits in the mcm module. note burst-access cannot occur across the 0x2000_0000 boundary that separates the two sram arrays. the two arrays should be treated as separate memory ranges for burst accesses. 3.5.3.5 sram arbitration and priority control the mcm's sramap register controls the arbitration and priority schemes for the two sram arrays. chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 107 3.5.4 sram controller configuration this section summarizes how the module has been configured in the chip. cortex-m4 core mpu crossbar switch sram controller transfers sram upper sram lower mpu figure 3-27. sram controller configuration table 3-38. reference links to related information topic related module reference system memory map system memory map power management power management power management controller (pmc) pmc transfers sram sram arm cortex-m4 core arm cortex-m4 core mpu memory protection unit configuration mcm mcm 3.5.5 system register file configuration this section summarizes how the module has been configured in the chip. memories and memory interfaces k60 sub-family reference manual, rev. 6, nov 2011 108 freescale semiconductor, inc. register file peripheral bridge 0 register access figure 3-28. system register file configuration table 3-39. reference links to related information topic related module reference full description register file register file system memory map system memory map clocking clock distribution power management power management 3.5.5.1 system register file this device includes a 32-byte register file that is powered in all power modes. also, it retains contents during low-voltage detect (lvd) events and is only reset during a power-on reset. 3.5.6 vbat register file configuration this section summarizes how the module has been configured in the chip. chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 109 vbat register file peripheral bridge register access figure 3-29. vbat register file configuration table 3-40. reference links to related information topic related module reference full description vbat register file vbat register file system memory map system memory map clocking clock distribution power management power management 3.5.6.1 vbat register file this device includes a 32-byte register file that is powered in all power modes and is powered by vbat. it is only reset during vbat power-on reset. 3.5.7 ezport configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. signal multiplexing module signals ezport transfers crossbar switch figure 3-30. ezport configuration table 3-41. reference links to related information topic related module reference full description ezport ezport table continues on the next page... memories and memory interfaces 60 sub-family reference manual, rev. 6, nov 2011 110 freescale semiconductor, inc. table 3-41. reference links to related information (continued) topic related module reference system memory map system memory map clocking clock distribution transfers crossbar switch crossbar switch signal multiplexing port control signal multiplexing 3.5.7.1 jtag instruction the system jtag controller implements an ezport instruction. when executing this instruction, the jtag controller resets the core logic and asserts the ezport chip select signal to force the processor into ezport mode. 3.5.7.2 flash option register (fopt) the fopt[ezport_dis] bit can be used to prevent entry into ezport mode during reset. if the fopt[ezport_dis] bit is cleared, then the state of the chip select signal ( ezp_cs) is ignored and the mcu always boots in normal mode. this option is useful for systems that use the ezp_cs/nmi signal configured for its nmi function. disabling ezport mode prevents possible unwanted entry into ezport mode if the external circuit that drives the nmi signal asserts it during reset. the fopt register is loaded from the flash option byte. if the flash option byte is modified the new value takes effect for any subsequent resets, until the value is changed again. 3.5.8 flexbus configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 111 signal multiplexing module signals register access flexbus transfers memory protection unit peripheral bridge 0 crossbar switch figure 3-31. flexbus configuration table 3-42. reference links to related information topic related module reference full description flexbus flexbus system memory map system memory map clocking clock distribution power management power management transfers memory protection unit (mpu) memory protection unit (mpu) signal multiplexing port control signal multiplexing 3.5.8.1 flexbus clocking the system provides a dedicated clock source to the flexbus module's external fb_clkout. its clock frequency is derived from a divider of the mcgoutclk. see clock distribution for more details. 3.5.8.2 flexbus signal multiplexing the multiplexing of the flexbus address and data signals is controlled by the port control module. however, the multiplexing of some of the flexbus control signals are controlled by the port control and flexbus modules. the port control module registers control whether the flexbus or another module signals are available on the external pin, while the flexbus's cspmcr register configures which flexbus signals are available from the module. the control signals are grouped as illustrated: memories and memory interfaces k60 sub-family reference manual, rev. 6, nov 2011 112 freescale semiconductor, inc. group3 group2 group1 group4 group5 cspmcr flexbus port control module to other modules to other modules to other modules to other modules to other modules external pins fb_ale reserved fb_tsiz0 reserved fb_tsiz1 reserved reserved reserved fb_cs1 fb_ts fb_cs4 fb_be_31_24 fb_be_23_16 fb_be_15_8 fb_be_7_0 fb_cs5 fb_tbst fb_cs2 fb_ta fb_cs3 figure 3-32. flexbus control signal multiplexing chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 113 therefore, use the cspmcr and port control registers to configure which control signal is available on the external pin. all control signals, except for fb_ta, are assigned to the alt5 function in the port control module. since, unlike the other control signals, fb_ta is an input signal, it is assigned to the alt6 function. 3.5.8.3 flexbus cscr0 reset value on this device the cscr0 resets to 0x003f_fc00. configure this register as needed before performing any flexbus access. 3.5.8.4 flexbus security when security is enabled on the device, flexbus accesses may be restricted by configuring the fbsel field in the sim's sopt2 register. see system integration module (sim) for details. 3.5.8.5 flexbus line transfers line transfers are not possible from the arm cortex-m4 core. ignore any references to line transfers in the flexbus chapter. security 3.6.1 crc configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. 3.6 security k60 sub-family reference manual, rev. 6, nov 2011 114 freescale semiconductor, inc. register access peripheral bridge crc figure 3-33. crc configuration table 3-43. reference links to related information topic related module reference full description crc crc system memory map system memory map power management power management 3.6.2 mmcau configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. mmcau transfers arm cortex m4 core ppb figure 3-34. mmcau configuration table 3-44. reference links to related information topic related module reference full description mmcau mmcau system memory map system memory map clocking clock distribution power management power management transfers private peripheral bus (ppb) arm cortex m4 core chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 115 3.6.3 rng configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. register access peripheral bridge random number generator figure 3-35. rng configuration table 3-45. reference links to related information topic related module reference full description rng rng system memory map system memory map clocking clock distribution power management power management analog 3.7.1 16-bit sar adc with pga configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. 3.7 analog k60 sub-family reference manual, rev. 6, nov 2011 116 freescale semiconductor, inc. signal multiplexing module signals register access 16-bit sar adc peripheral bus controller 0 other peripherals transfers figure 3-36. 16-bit sar adc with pga configuration table 3-46. reference links to related information topic related module reference full description 16-bit sar adc with pga 16-bit sar adc with pga system memory map system memory map clocking clock distribution power management power management signal multiplexing port control signal multiplexing 3.7.1.1 adc instantiation information this device contains two adcs. each adc contains a pga channel for a total of two separate pgas. 3.7.1.1.1 number of adc channels the number of adc channels present on the device is determined by the pinout of the specific device package. for details regarding the number of adc channel available on a particular package, refer to the signal multiplexing chapter of this mcu. 3.7.1.2 dma support on adc applications may require continuous sampling of the adc (4k samples/sec) that may have considerable load on the cpu. though using pdb to trigger adc may reduce some cpu load, the adc supports dma request functionality for higher performance when the adc is sampled at a very high rate or cases were pdb is bypassed. the adc can trigger the dma (via dma req) on conversion completion. chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 117 3.7.1.3 adc0 connections/channel assignment note as indicated by the following sections, each adcx_dpx input and certain adcx_dmx inputs may operate as single-ended adc channels in single-ended mode. 3.7.1.3.1 adc0 channel assignment for 100-pin package adc channel (sc1n[adch]) channel input signal (sc1n[diff]= 1) input signal (sc1n[diff]= 0) 00000 dad0 adc0_dp0 and adc0_dm0 1 adc0_dp0 2 00001 dad1 adc0_dp1 and adc0_dm1 adc0_dp1 00010 dad2 pga0_dp and pga0_dm pga0_dp 00011 dad3 adc0_dp3 and adc0_dm3 3 adc0_dp3 4 00100 5 ad4a reserved reserved 00101 5 ad5a reserved reserved 00110 5 ad6a reserved reserved 00111 5 ad7a reserved reserved 00100 5 ad4b reserved adc0_se4b 00101 5 ad5b reserved adc0_se5b 00110 5 ad6b reserved adc0_se6b 00111 5 ad7b reserved adc0_se7b 01000 ad8 reserved adc0_se8 6 01001 ad9 reserved adc0_se9 7 01010 ad10 reserved reserved 01011 ad11 reserved reserved 01100 ad12 reserved adc0_se12 01101 ad13 reserved adc0_se13 01110 ad14 reserved adc0_se14 01111 ad15 reserved adc0_se15 10000 ad16 reserved reserved 10001 ad17 reserved adc0_se17 10010 ad18 reserved adc0_se18 10011 ad19 reserved adc0_dm0 8 10100 ad20 reserved adc0_dm1 10101 ad21 reserved 10110 ad22 reserved 10111 ad23 reserved 12-bit dac0 output 11000 ad24 reserved reserved table continues on the next page... analog 60 sub-family reference manual, rev. 6, nov 2011 118 freescale semiconductor, inc. adc channel (sc1n[adch]) channel input signal (sc1n[diff]= 1) input signal (sc1n[diff]= 0) 11001 ad25 reserved reserved 11010 ad26 temperature sensor (diff) temperature sensor (s.e) 11011 ad27 bandgap (diff) 9 bandgap (s.e) 9 11100 ad28 reserved reserved 11101 ad29 -vrefh (diff) vrefh (s.e) 11110 ad30 reserved vrefl 11111 ad31 module disabled module disabled 1. interleaved with adc1_dp3 and adc1_dm3 2. interleaved with adc1_dp3 3. interleaved with adc1_dp0 and adc1_dm0 4. interleaved with adc1_dp0 5. adcx_cfg2[muxsel] bit selects between adcx_sen channels a and b. refer to muxsel description in adc chapter for details. 6. interleaved with adc1_se8 7. interleaved with adc1_se9 8. interleaved with adc1_dm3 9. this is the pmc bandgap 1v reference voltage not the vref module 1.2 v reference voltage. prior to reading from this adc channel, ensure that you enable the bandgap buffer by setting the pmc_regsc[bgbe] bit. refer to the device data sheet for the bandgap voltage (v bg ) specification. 3.7.1.4 adc1 connections/channel assignment note as indicated in the following tables, each adcx_dpx input and certain adcx_dmx inputs may operate as single-ended adc channels in single-ended mode. 3.7.1.4.1 adc1 channel assignment for 100-pin package adc channel (sc1n[adch]) channel input signal (sc1n[diff]= 1) input signal (sc1n[diff]= 0) 00000 dad0 adc1_dp0 and adc1_dm0 1 adc1_dp0 2 00001 dad1 adc1_dp1 and adc1_dm1 adc1_dp1 00010 dad2 pga1_dp and pga1_dm pga1_dp 00011 dad3 adc1_dp3 and adc1_dm3 3 adc1_dp3 4 00100 5 ad4a reserved adc1_se4a 00101 5 ad5a reserved adc1_se5a 00110 5 ad6a reserved adc1_se6a 00111 5 ad7a reserved adc1_se7a 00100 5 ad4b reserved adc1_se4b 00101 5 ad5b reserved adc1_se5b 00110 5 ad6b reserved adc1_se6b table continues on the next page... chapter chip configuration 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 11 adc channel (sc1n[adch]) channel input signal (sc1n[diff]= 1) input signal (sc1n[diff]= 0) 00111 5 ad7b reserved adc1_se7b 01000 ad8 reserved adc1_se8 6 01001 ad9 reserved adc1_se9 7 01010 ad10 reserved reserved 01011 ad11 reserved reserved 01100 ad12 reserved reserved 01101 ad13 reserved adc1_se13reserved 01110 ad14 reserved adc1_se14 01111 ad15 reserved adc1_se15 10000 ad16 reserved reserved 10001 ad17 reserved adc1_se17 10010 ad18 reserved vref output 10011 ad19 reserved adc1_dm0 8 10100 ad20 reserved adc1_dm1 10101 ad21 reserved reserved 10110 ad22 reserved 10111 ad23 reserved 11000 ad24 reserved reserved 11001 ad25 reserved reserved 11010 ad26 temperature sensor (diff) temperature sensor (s.e) 11011 ad27 bandgap (diff) 9 bandgap (s.e) 9 11100 ad28 reserved reserved 11101 ad29 -vrefh (diff) vrefh (s.e) 11110 ad30 reserved vrefl 11111 ad31 module disabled module disabled 1. interleaved with adc0_dp3 and adc0_dm3 2. interleaved with adc0_dp3 3. interleaved with adc0_dp0 and adc0_dm0 4. interleaved with adc0_dp0 5. adcx_cfg2[muxsel] bit selects between adcx_sen channels a and b. refer to muxsel description in adc chapter for details. 6. interleaved with adc0_se8 7. interleaved with adc0_se9 8. interleaved with adc0_dm3 9. this is the pmc bandgap 1v reference voltage not the vref module 1.2 v reference voltage. prior to reading from this adc channel, ensure that you enable the bandgap buffer by setting the pmc_regsc[bgbe] bit. refer to the device data sheet for the bandgap voltage (v bg ) specification. 3.7.1.5 adc channels mux selection the following figure shows the assignment of adcx_sen channels a and b through a mux selection to adc. to select between alternate set of channels, refer to adcx_cfg2[muxsel] bit settings for more details. analog k60 sub-family reference manual, rev. 6, nov 2011 120 freescale semiconductor, inc. ad5 [00101] ad4 [00100] ad6 [00110] ad7 [00111] the ad8 and ad9 channels on adcx are interleaved in hardware using the following configuration. adc0 ad8 ad9 adc1 ad8 ad9 adc0_se8/adc1_se8 adc0_se9/adc1_se9 figure 3-38. adc hardware interleaved channels integration 3.7.1.7 adc and pga reference options the adc supports the following references: chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 121 ? vrefh/vrefl - connected as the primary reference option ? 1.2 v vref_out - connected as the v alt reference option adcx_sc2[refsel] bit selects the voltage reference sources for adc. refer to refsel description in adc chapter for more details. the only reference option for the pga is the 1.2 v vref_out source. the vref_out signal can either be driven by an external voltage source via the vref_out pin or from the output of the vref module. ensure that the vref module is disabled when an external voltage source is used instead. for pga maximum differential input signal swing range, refer to the device data sheet for 16-bit adc with pga characteristics. 3.7.1.8 adc triggers the adc supports both software and hardware triggers. the primary hardware mechanism for triggering the adc is the pdb. the pdb itself can be triggered by other peripherals. for example: rtc (alarm, seconds) signal is connected to the pdb. the pdb trigger can receive the rtc (alarm/seconds) trigger input forcing adc conversions in run mode (where pdb is enabled). on the other hand, the adc can conduct conversions in low power modes, not triggered by pdb. this allows the adc to do conversions in low power mode and store the output in the result register. the adc generates interrupt when the data is ready in the result register that wakes the system from low power mode. the pdb can also be bypassed by using the adcxtrgsel bits in the sopt7 register. for operation of triggers in different modes, refer to power management chapter. 3.7.1.9 alternate clock for this device, the alternate clock is connected to oscerclk. note this clock option is only usable when oscerclk is in the mhz range. a system with oscerclk in the khz range has the optional clock source below minimum adc clock operating frequency. 3.7.1.10 adc low-power modes this table shows the adc low-power modes and the corresponding chip low-power modes. analog k60 sub-family reference manual, rev. 6, nov 2011 122 freescale semiconductor, inc. table 3-47. adc low-power modes module mode chip mode wait wait, vlpw normal stop stop, vlps low power stop lls, vlls3, vlls2, vlls1 3.7.1.11 pga integration ? no additional external pins are required for the pga as it is part of the adc and is selected as a separate channel ? each pga connects to the differential adc channels ? the pga outputs differential pairs that are connected to adc differential input ? when the pga is used, differential input from the pins is connected to differential input channel 2 on adcx chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 123 adc0 dad1 dad0 dad2 dad3 adc1 dad3 dad2 dad0 dad1 pga1 pga0 pga0_dp/adc0_dp0/adc1_dp3 pga0_dm/adc0_dm0/adc1_dm3 pga1_dp/adc1_dp0/adc0_dp3 pga1_dm/adc1_dm0/adc0_dm3 adc1_dp1 adc1_dm1 adc0_dp1 adc0_dm1 figure 3-39. pga integration 3.7.2 cmp configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. analog k60 sub-family reference manual, rev. 6, nov 2011 124 freescale semiconductor, inc. signal multiplexing module signals register access cmp peripheral bridge 0 other peripherals figure 3-40. cmp configuration table 3-48. reference links to related information topic related module reference full description comparator (cmp) comparator system memory map system memory map clocking clock distribution power management power management signal multiplexing port control signal multiplexing 3.7.2.1 cmp input connections the following table shows the fixed internal connections to the cmp. cmp inputs cmp0 cmp1 cmp2 in0 cmp0_in0 cmp1_in0 cmp2_in0 in1 cmp0_in1 cmp1_in1 cmp2_in1 in2 cmp0_in2 in3 cmp0_in3 12b dac0 reference/ cmp1_in3 cmp2_in3 in4 cmp0_in4 in5 vref output/cmp0_in5 vref output/cmp1_in5 cmp2_in5 in6 bandgap bandgap bandgap in7 6b dac0 reference 6b dac1 reference 3.7.2.2 cmp external references the 6-bit dac sub-block supports selection of two references. for this device, the references are connected as follows: ? vref_out - v in1 input ? vdd - v in2 input chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 125 3.7.2.3 external window/sample input pdb pulse-out controls the cmp sample/window timing. 3.7.3 12-bit dac configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. signal multiplexing module signals register access 12-bit dac peripheral bus controller 0 other peripherals transfers figure 3-41. 12-bit dac configuration table 3-49. reference links to related information topic related module reference full description 12-bit dac 12-bit dac system memory map system memory map clocking clock distribution power management power management signal multiplexing port control signal multiplexing 3.7.3.1 12-bit dac overview this device contains one 12-bit digital-to-analog converter (dac) with programmable reference generator output. the dac includes a fifo for dma support. 3.7.3.2 12-bit dac output the output of the dac can be placed on an external pin or set as one of the inputs to the analog comparator or adc. analog k60 sub-family reference manual, rev. 6, nov 2011 126 freescale semiconductor, inc. 3.7.3.3 12-bit dac reference for this device vref_out and vdda are selectable as the dac reference. vref_out is connected to the dacref_1 input and vdda is connected to the dacref_2 input. use dacx_c0[dacrfs] control bit to select between these two options. be aware that if the dac and adc use the vref_out reference simultaneously, some degradation of adc accuracy is to be expected due to dac switching. 3.7.4 vref configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. signal multiplexing module signals register access vref peripheral bus controller 0 other peripherals transfers figure 3-42. vref configuration table 3-50. reference links to related information topic related module reference full description vref vref system memory map system memory map clocking clock distribution power management power management signal multiplexing port control signal multiplexing 3.7.4.1 vref overview this device includes a voltage reference (vref) to supply an accurate 1.2 v voltage output. chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 127 the voltage reference can provide a reference voltage to external peripherals or a reference to analog peripherals, such as the adc, dac, or cmp. note for either an internal or external reference if the vref_out functionality is being used, vref_out signal must be connected to an output load capacitor. refer the device data sheet for more details. timers 3.8.1 pdb configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. signal multiplexing module signals register access pdb peripheral bus controller 0 other peripherals transfers figure 3-43. pdb configuration table 3-51. reference links to related information topic related module reference full description pdb pdb system memory map system memory map clocking clock distribution power management power management signal multiplexing port control signal multiplexing 3.8.1.1 pdb instantiation 3.8 timers k60 sub-family reference manual, rev. 6, nov 2011 128 freescale semiconductor, inc. 3.8.1.1.1 pdb output triggers table 3-52. pdb output triggers number of pdb channels for adc trigger 2 number of pre-triggers per pdb channel 2 number of dac triggers 1 number of pulseout 1 3.8.1.1.2 pdb input trigger connections table 3-53. pdb input trigger options pdb trigger pdb input 0000 external trigger 0001 cmp 0 0010 cmp 1 0011 cmp 2 0100 pit ch 0 output 0101 pit ch 1 output 0110 pit ch 2 output 0111 pit ch 3 output 1000 ftm0 init and ext trigger outputs 1001 ftm1 init and ext trigger outputs 1010 ftm2 init and ext trigger outputs 1011 reserved 1100 rtc alarm 1101 rtc seconds 1110 lptmr output 1111 software trigger 3.8.1.2 pdb module interconnections pdb trigger outputs connection channel 0 triggers adc0 trigger channel 1 triggers adc1 trigger and synchronous input 1 of ftm0 dac triggers dac0 trigger pulse-out pulse-out connected to each cmp modules sample/window input to control sample operation chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 129 3.8.1.3 back-to-back acknowledgement connections in this mcu, pdb back-to-back operation acknowledgment connections are implemented as follows: ? pdb channel 0 pre-trigger 0 acknowledgement input: adc1sc1b_coco ? pdb channel 0 pre-trigger 1 acknowledgement input: adc0sc1a_coco ? pdb channel 1 pre-trigger 0 acknowledgement input: adc0sc1b_coco ? pdb channel 1 pre-trigger 1 acknowledgement input: adc1sc1a_coco so, the back-to-back chain is connected as a ring: channel 0 pre-trigger 0 channel 1 pre-trigger 0 channel 0 pre-trigger 1 channel 1 pre-trigger 1 figure 3-44. pdb back-to-back chain the application code can set the pdb x _ch n c1[bb] bits to configure the pdb pre- triggers as a single chain or several chains. 3.8.1.4 pdb interval trigger connections to dac in this mcu, pdb interval trigger connections to dac are implemented as follows. ? pdb interval trigger 0 connects to dac0 hardware trigger input. 3.8.1.5 dac external trigger input connections in this mcu, two dac external trigger inputs are implemented. ? dac external trigger input 0: adc0sc1a_coco ? dac external trigger input 1: adc1sc1a_coco timers k60 sub-family reference manual, rev. 6, nov 2011 130 freescale semiconductor, inc. note application code can set the pdbx_dacintcn[ext] bit to allow dac external trigger input when the corresponding adc conversion complete flag, adcx_sc1n[coco], is set. 3.8.1.6 pulse-out connection the pulse-out of pdb is connected to all the cmp blocks and used as the sample window. 3.8.1.7 pulse-out enable register implementation the following table shows the comparison of pulse-out enable register at the module and chip level. table 3-54. pdb pulse-out enable register register module implementation chip implementation ponen 7:0 - poen 31:8 - reserved 0 - poen 31:1 - reserved 3.8.2 flextimer configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 131 signal multiplexing module signals register access flextimer peripheral bus controller 0 other peripherals transfers figure 3-45. flextimer configuration table 3-55. reference links to related information topic related module reference full description flextimer flextimer system memory map system memory map clocking clock distribution power management power management signal multiplexing port control signal multiplexing 3.8.2.1 instantiation information this device contains three flextimer modules. the following table shows how these modules are configured. table 3-56. ftm instantiations ftm instance number of channels features/usage ftm0 8 3-phase motor + 2 general purpose or stepper motor ftm1 2 quadrature decoder or general purpose ftm2 2 quadrature decoder or general purpose compared with the ftm0 configuration, the ftm1 and ftm2 configuration adds the quadrature decoder feature and reduces the number of channels. timers k60 sub-family reference manual, rev. 6, nov 2011 132 freescale semiconductor, inc. 3.8.2.2 external clock options by default each ftm is clocked by the internal bus clock (the ftm refers to it as system clock). each module contains a register setting that allows the module to be clocked from an external clock instead. there are two external ftm_clkinx pins that can be selected by any ftm module via the sopt4 register in the sim module. 3.8.2.3 fixed frequency clock the fixed frequency clock for each ftm is mcgffclk. 3.8.2.4 ftm interrupts the flextimer has multiple sources of interrupt. however, these sources are or'd together to generate a single interrupt request to the interrupt controller. when an ftm interrupt occurs, read the ftm status registers (fms, sc, and status) to determine the exact interrupt source. 3.8.2.5 ftm fault detection inputs the following fault detection input options for the ftm modules are selected via the sopt4 register in the sim module. the external pin option is selected by default. ? ftm0 fault0 = ftm0_flt0 pin or cmp0 output ? ftm0 fault1 = ftm0_flt1 pin or cmp1 output ? ftm0 fault2 = ftm0_flt2 pin or cmp2 output ? ftm0 fault3 = ftm0_flt3 pin ? ftm1 fault0 = ftm1_flt0 pin or cmp0 output ? ftm1 fault1 = cmp1 output ? ftm1 fault2 = cmp2 output ? ftm2 fault0 = ftm2_flt0 pin or cmp0 output ? ftm2 fault1 = cmp1 output ? ftm2 fault2 = cmp2 output 3.8.2.6 ftm hardware triggers the ftm synchronization hardware triggers are connected in the chip as follows: chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 133 ? ftm0 hardware trigger 0 = cmp0 output ? ftm0 hardware trigger 1 = pdb channel 1 trigger output ? ftm0 hardware trigger 2 = ftm0_flt0 pin ? ftm1 hardware trigger 0 = cmp0 output ? ftm1 hardware trigger 1 = cmp1 output ? ftm1 hardware trigger 2 = ftm1_flt0 pin ? ftm2 hardware trigger 0 = cmp0 output ? ftm2 hardware trigger 1 = cmp2 output ? ftm2 hardware trigger 2 = ftm2_flt0 pin 3.8.2.7 input capture options for ftm module instances the following channel 0 input capture source options are selected via the sopt4 register in the sim module. the external pin option is selected by default. ? ftm1 channel 0 input capture = ftm1_ch0 pin or cmp0 output or cmp1 output ? ftm2 channel 0 input capture = ftm2_ch0 pin or cmp0 output or cmp1 output 3.8.2.8 ftm output triggers for other modules ftm output triggers can be selected as input triggers for the pdb and adc modules. see pdb instantiation and adc triggers . 3.8.2.9 ftm global time base this chip provides the optional ftm global time base feature (see global time base (gtb) ). ftm0 provides the only source for the ftm global time base. the other ftm modules can share the time base as shown in the following figure: timers k60 sub-family reference manual, rev. 6, nov 2011 134 freescale semiconductor, inc. gtb_in ftm1 gtbeen = 1 ftm counter conf register gtbeout = 0 ftm0 gtbeen = 1 ftm counter conf register gtbeout = 1 gtb_out gtb_in gtb_in ftm2 gtbeen = 1 ftm counter conf register gtbeout = 0 figure 3-46. ftm global time base configuration 3.8.2.10 ftm bdm and debug halt mode in the ftm chapter, references to the chip being in "bdm" are the same as the chip being in debug halt mode". 3.8.3 pit configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. register access peripheral bridge periodic interrupt timer figure 3-47. pit configuration table 3-57. reference links to related information topic related module reference full description pit pit system memory map system memory map clocking clock distribution power management power management chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 135 3.8.3.1 pit/dma periodic trigger assignments the pit generates periodic trigger events to the dma mux as shown in the table below. table 3-58. pit channel assignments for periodic dma triggering dma channel number pit channel dma channel 0 pit channel 0 dma channel 1 pit channel 1 dma channel 2 pit channel 2 dma channel 3 pit channel 3 3.8.3.2 pit/adc triggers pit triggers are selected as adcx trigger sources using the sopt7[adcxtrgsel] bits in the sim module. for more details, refer to sim chapter. 3.8.4 low-power timer configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. signal multiplexing register access peripheral bridge module signals low-power timer figure 3-48. lpt configuration table 3-59. reference links to related information topic related module reference full description low-power timer low-power timer system memory map system memory map clocking clock distribution table continues on the next page... timers 60 sub-family reference manual, rev. 6, nov 2011 16 freescale semiconductor, inc. table 3-59. reference links to related information (continued) topic related module reference power management power management signal multiplexing port control signal multiplexing 3.8.4.1 lptmr prescaler/glitch filter clocking options the prescaler and glitch filter of the lptmr module can be clocked from one of four sources determined by the lptmr0_psr[pcs] bitfield. the following table shows the chip-specific clock assignments for this bitfield. note the chosen clock must remain enabled if the lptmr is to continue operating in all required low-power modes. lptmr0_psr[pcs] prescaler/glitch filter clock number chip clock 00 0 mcgirclk internal reference clock (not available in vlps/lls/vlls modes) 01 1 lpo 1 khz clock 10 2 erclk32k secondary external reference clock 11 3 oscerclk external reference clock see clock distribution for more details on these clocks. 3.8.4.2 lptmr pulse counter input options the lptmr_csr[tps] bitfield configures the input source used in pulse counter mode. the following table shows the chip-specific input assignments for this bitfield. lptmr_csr[tps] pulse counter input number chip input 00 0 cmp0 output 01 1 lptmr_alt1 pin 10 2 lptmr_alt2 pin 11 3 reserved chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 137 3.8.5 cmt configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. signal multiplexing module signals register access cmt peripheral bus controller 0 figure 3-49. cmt configuration table 3-60. reference links to related information topic related module reference full description carrier modulator transmitter (cmt) cmt system memory map system memory map clocking clock distribution power management power management signal multiplexing port control signal multiplexing 3.8.5.1 instantiation information this device contains one cmt module. 3.8.5.2 iro drive strength the iro pad requires higher current drive than can be obtained from a single pad. for this device, the pin associated with the cmt_iro signal is doubled bonded to two pads. the sopt2[cmtuartpad] field in sim module can be used to configure the pin associated with the cmt_iro signal as a higher current output port pin. timers k60 sub-family reference manual, rev. 6, nov 2011 138 freescale semiconductor, inc. 3.8.6 rtc configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. signal multiplexing register access peripheral bridge module signals real-time clock figure 3-50. rtc configuration table 3-61. reference links to related information topic related module reference full description rtc rtc system memory map system memory map clocking clock distribution power management power management 3.8.6.1 rtc_clkout signal when the rtc is enabled and the port control module selects the rtc_clkout function, the rtc_clkout signal is fixed to a 1 hz output. 3.8.6.2 rtc_wakeup signal the rtc_wakeup pin is not supported on this device. 3.8.6.3 rtc seconds interrupt the rtc seconds interrupt is not supported on this device. chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 139 communication interfaces 3.9.1 ethernet configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. signal multiplexing module signals register access ethernet peripheral bridge 1 crossbar switch transfers figure 3-51. ethernet configuration table 3-62. reference links to related information topic related module reference full description ethernet ethernet system memory map system memory map clocking clock distribution transfers crossbar switch crossbar switch signal multiplexing port control signal multiplexing 3.9.1.1 ethernet clocking options the ethernet module uses the following clocks: ? the device's system clock is connected to the module clock, as named in the ethernet chapter . the minimum system clock frequency for 100 mbps operation is 25 mhz. ? an externally-supplied 25 mhz mii clock or 50 mhz rmii clock. this clock is used as the timing reference for the external mii or rmii interface. ? a time-stamping clock for the ieee 1588 timers. for more details on the ethernet module clocking options, see ethernet clocking . 3.9 communication interfaces k60 sub-family reference manual, rev. 6, nov 2011 140 freescale semiconductor, inc. 3.9.1.2 rmii clocking on this device, rmii_ref_clk is internally tied to extal. see clock distribution for clocking requirements. 3.9.1.3 ieee 1588 timers the ethernet module includes a four channel timer module for ieee 1588 timestamping. the timer supports input capture (rising, falling, or both edges), output compare (toggle or pulse with programmable polarity). the timer matches on greater than or equal (the 1588 can skip numbers, so the counter might not ever exactly match the compare value). the counter is able to operate asynchronously to the ethernet bus by using one of four clock sources. see ethernet clocking for more details. 3.9.1.4 ethernet operation in low power modes the ethernet module is not fully operational in any low power modes. however, the module does support magic packet detection that can generate a wakeup in stop mode if enabled. during low power operation: ? the mac transmit logic is disabled ? the core fifo receive/transmit functions are disabled ? the mac receive logic is kept in normal mode, but it ignores all traffic from the line except magic packets. the recieve logic needed for magic packet detection is clocked using the externally- supplied mii or rmii clock. this allows for the wakeup functionality in stop mode. no ethernet operation, including magic packet wakeup, is supported in vlpx modes. 3.9.1.4.1 ieee 1588 timer operation in low power modes the 1588 counter and 1588 timer channels can continue operating in low power modes provided their clock is enabled in that mode. the 1588 timer channels can also generate an interrupt to exit the low power mode if the clock is enabled in that mode. chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 141 3.9.1.5 ethernet doze mode the doze mode for the ethernet module is the same as the wait and vlpw modes for the chip. 3.9.1.6 ethernet interrupts the ethernet has multiple sources of interrupt requests. however, some of these sources are or'd together to generate an interrupt request. see below for a summary: interrupt request interrupt source ieee 1588 timer interrupt time stamp available 1588 timer interrupt transmit interrupt transmit frame interrupt transmit buffer interrupt receive interrupt receive frame interrupt receive buffer interrupt error and miscellaneous interrupt wake-up payload receive error babbling receive error babbling transmit error graceful stop complete mii interrupt ? data transfer done ethernet bus error late collision collision retry limit 3.9.1.7 ethernet event signal the event signal output is not supported on this device. therefore, atcr[pinper] has no effect. 3.9.2 universal serial bus (usb) subsystem the usb subsystem includes these components: ? dual-role usb otg-capable (on-the-go) controller that supports a full-speed (fs) device or fs/ls host. the module complies with the usb 2.0 specification. ? usb transceiver that includes internal 15 k pulldowns on the d+ and d- lines for host mode functionality. ? a 3.3 v regulator. ? usb device charger detection module. ? vbus detect signal: to detect a valid vbus in device mode, use a gpio signal that can wake the chip in all power modes. communication interfaces k60 sub-family reference manual, rev. 6, nov 2011 142 freescale semiconductor, inc. usb controller fs/ls transceiver usb voltage regulator d+ d- vregin device charger detect vout33 figure 3-52. usb subsystem overview 3.9.2.1 usb wakeup when the usb detects that there is no activity on the usb bus for more than 3 ms, the int_stat[sleep] bit is set. this bit can cause an interrupt and software decides the appropriate action. waking from a low power mode (except in lls/vlls mode where usb is not powered) occurs through an asynchronous interrupt triggered by activity on the usb bus. setting the usbtrc0[usbresmen] bit enables this function. 3.9.2.2 usb power distribution this chip includes an internal 5 v to 3.3 v usb regulator that powers the usb transceiver or the mcu (depending on the application). 3.9.2.2.1 aa/aaa cells power supply the chip can be powered by two aa/aaa cells. in this case, the mcu is powered through vdd which is within the 1.8 to 3.0 v range. after usb cable insertion is detected, the usb regulator is enabled to power the usb transceiver. chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 143 usb regulator usb xcvr usb controller usb0_dp usb0_dm vdd vout33 vregin type a d+ d- vbus 2 aa cells cstab to pmc and pads chip figure 3-53. usb regulator aa cell usecase 3.9.2.2.2 li-ion battery power supply the chip can also be powered by a single li-ion battery. in this case, vout33 is connected to vdd. the usb regulator must be enabled by default to power the mcu. when connected to a usb host, the input source of this regulator is switched to the usb bus supply from the li-ion battery. to charge the battery, the mcu can configure the battery charger according to the charger detection information. communication interfaces k60 sub-family reference manual, rev. 6, nov 2011 144 freescale semiconductor, inc. usb regulator usb xcvr usb controller usb0_dm usb0_dp vdd vout33 vregin type a d+ d- vbus c stab to pmc and pads chip charger detect vbus sense vss charger li-ion si2301 figure 3-54. usb regulator li-ion usecase 3.9.2.2.3 usb bus power supply the chip can also be powered by the usb bus directly. in this case, vout33 is connected to vdd. the usb regulator must be enabled by default to power the mcu, then to power usb transceiver or external sensor. usb regulator usb xcvr usb controller usb0_dp usb0_dm vdd vout33 vregin type a d+ d- vbus cstab to pmc and pads chip figure 3-55. usb regulator bus supply chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 145 3.9.2.3 usb power management the regulator should be put into standby mode whenever the chip is in stop mode. this can be done by setting the sim_sopt1[usbstby] bit. 3.9.2.4 usb controller configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. signal multiplexing module signals register access usb controller peripheral bridge 0 crossbar switch transfers figure 3-56. usb controller configuration table 3-63. reference links to related information topic related module reference full description usb controller usb controller system memory map system memory map clocking clock distribution transfers crossbar switch crossbar switch signal multiplexing port control signal multiplexing note when usb is not used in the application, it is recommended that the usb regulator vregin and vout33 pins remain floating. 3.9.2.5 usb dcd configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. communication interfaces k60 sub-family reference manual, rev. 6, nov 2011 146 freescale semiconductor, inc. register access usb device charger detect peripheral bridge 0 usb otg figure 3-57. usb dcd configuration table 3-64. reference links to related information topic related module reference full description usb dcd usb dcd system memory map system memory map clocking clock distribution usb controller usb controller 3.9.2.6 usb voltage regulator configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. signal multiplexing module signals usb voltage regulator usb otg figure 3-58. usb voltage regulator configuration table 3-65. reference links to related information topic related module reference full description usb voltage regulator usb voltage regulator system memory map system memory map clocking clock distribution usb controller usb controller signal multiplexing port control signal multiplexing chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 147 note when usb is not used in the application, it is recommended that the usb regulator vregin and vout33 pins remain floating. 3.9.3 can configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. signal multiplexing register access flexcan peripheral bridge module signals figure 3-59. can configuration table 3-66. reference links to related information topic related module reference full description can can system memory map system memory map clocking clock distribution power management power management signal multiplexing port control signal multiplexing 3.9.3.1 number of flexcan modules this device contains 2 identical flexcan modules. 3.9.3.2 reset value of mdis bit the can_mcr[mdis] bit is set after reset. therefore, flexcan module is disabled following a reset. communication interfaces k60 sub-family reference manual, rev. 6, nov 2011 148 freescale semiconductor, inc. 3.9.3.3 number of message buffers each flexcan module contains 16 message buffers. each message buffer is 16 bytes. 3.9.3.4 flexcan clocking 3.9.3.4.1 clocking options the flexcan module has a register bit canctrl[clk_src] that selects between clocking the flexcan from the internal bus clock or the input clock (extal). 3.9.3.4.2 clock gating the clock to each can module can be gated on and off using the scgc n [can x ] bits. these bits are cleared after any reset, which disables the clock to the corresponding module. the appropriate clock enable bit should be set by software at the beginning of the flexcan initialization routine to enable the module clock before attempting to initialize any of the flexcan registers. 3.9.3.5 flexcan interrupts the flexcan has multiple sources of interrupt requests. however, some of these sources are or'd together to generate a single interrupt request. see below for the mapping of the individual interrupt sources to the interrupt request: request sources message buffer message buffers 0-15 bus off bus off error bit1 error bit0 error acknowledge error cyclic redundancy check (crc) error form error stuffing error transmit error warning receive error warning transmit warning transmit warning receive warning receive warning wake-up wake-up chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 149 3.9.3.6 flexcan operation in low power modes the flexcan module is operational in vlpr and vlpw modes. with the 2 mhz bus clock, the fastest supported flexcan transfer rate is 256 kbps. the bit timing parameters in the module must be adjusted for the new frequency, but full functionality is possible. the flexcan module can be configured to generate a wakeup interrupt in stop and vlps modes. when the flexcan is configured to generate a wakeup, a recessive to dominant transition on the can bus generates an interrupt. 3.9.3.7 flexcan doze mode the doze mode for the flexcan module is the same as the wait and vlpw modes for the chip. 3.9.4 spi configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. signal multiplexing register access spi peripheral bridge module signals figure 3-60. spi configuration table 3-67. reference links to related information topic related module reference full description spi spi system memory map system memory map clocking clock distribution signal multiplexing port control signal multiplexing communication interfaces k60 sub-family reference manual, rev. 6, nov 2011 150 freescale semiconductor, inc. 3.9.4.1 spi modules configuration this device contains three spi modules. 3.9.4.2 spi clocking the spi module is clocked by the internal bus clock (the dspi refers to it as system clock). the module has an internal divider, with a minimum divide is two. so, the spi can run at a maximum frequency of bus clock/2. 3.9.4.3 number of ctars spi ctar registers define different transfer attribute configurations. the spi module supports up to eight ctar registers. this device supports two ctars on all instances of the spi. in master mode, the ctar registers define combinations of transfer attributes, such as frame size, clock phase, clock polarity, data bit ordering, baud rate, and various delays. in slave mode only ctar0 is used, and a subset of its bitfields sets the slave transfer attributes. 3.9.4.4 tx fifo size table 3-68. spi transmit fifo size spi module transmit fifo size spi0 4 spi1 4 spi2 4 3.9.4.5 rx fifo size spi supports up to 16-bit frame size during reception. table 3-69. spi receive fifo size spi module receive fifo size spi0 4 spi1 4 spi2 4 chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 151 3.9.4.6 number of pcs signals the following table shows the number of peripheral chip select signals available per spi module. table 3-70. spi pcs signals spi module pcs signals spi0 spi_pcs[5:0] spi1 spi_pcs[3:0] spi2 spi_pcs[1:0] 3.9.4.7 spi operation in low power modes in vlpr and vlpw modes the spi is functional; however, the reduced system frequency also reduces the max frequency of operation for the spi. in vlpr and vlpw modes the max spi_clk frequency is 1mhz. in stop and vlps modes, the clocks to the spi module are disabled. the module is not functional, but it is powered so that it retains state. there is one way to wake from stop mode via the spi, which is explained in the following section. 3.9.4.7.1 using gpio interrupt to wake from stop mode here are the steps to use a gpio to create a wakeup upon reception of spi data in slave mode: 1. point the gpio interrupt vector to the desired interrupt handler. 2. enable the gpio input to generate an interrupt on either the rising or falling edge (depending on the polarity of the chip select signal). 3. enter stop or vlps mode and wait for the gpio interrupt. note it is likely that in using this approach the first word of data from the spi host might not be received correctly. this is dependent on the transfer rate used for the spi, the delay between chip select assertion and presentation of data, and the system interrupt latency. communication interfaces k60 sub-family reference manual, rev. 6, nov 2011 152 freescale semiconductor, inc. 3.9.4.8 spi doze mode the doze mode for the spi module is the same as the wait and vlpw modes for the chip. 3.9.4.9 spi interrupts the spi has multiple sources of interrupt requests. however, these sources are or'd together to generate a single interrupt request per spi module to the interrupt controller. when an spi interrupt occurs, read the spi_sr to determine the exact interrupt source. 3.9.4.10 spi clocks this table shows the spi module clocks and the corresponding chip clocks. table 3-71. spi clock connections module clock chip clock system clock bus clock 3.9.5 i2c configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 153 signal multiplexing register access peripheral bridge module signals 2 i c figure 3-61. i2c configuration table 3-72. reference links to related information topic related module reference full description i 2 c i 2 c system memory map system memory map clocking clock distribution power management power management signal multiplexing port control signal multiplexing 3.9.5.1 number of i2c modules this device has two i 2 c modules. 3.9.6 uart configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. communication interfaces k60 sub-family reference manual, rev. 6, nov 2011 154 freescale semiconductor, inc. signal multiplexing register access peripheral bridge module signals uart figure 3-62. uart configuration table 3-73. reference links to related information topic related module reference full description uart uart system memory map system memory map clocking clock distribution power management power management signal multiplexing port control signal multiplexing 3.9.6.1 uart configuration information this device contains five uart modules. this section describes how each module is configured on this device. 1. standard features of all uarts: ? rs-485 support ? hardware flow control (rts/cts) ? 9-bit uart to support address mark with parity ? msb/lsb configuration on data 2. uart0 and uart1 are clocked from the core clock, the remaining uarts are clocked on the bus clock. the maximum baud rate is 1/16 of related source clock frequency. 3. irda is available on all uarts 4. uart0 contains the standard features plus iso7816 5. amr support on all uarts. the pin control and interrupts (port) module supports open-drain for all i/o. 6. uart0 and uart1 contains 8-entry transmit and 8-entry receive fifos 7. all other uarts contain a 1-entry transmit and receive fifos chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 155 3.9.6.2 uart wakeup the uart can be configured to generate an interrupt/wakeup on the first active edge that it receives. 3.9.6.3 uart interrupts the uart has multiple sources of interrupt requests. however, some of these sources are or'd together to generate a single interrupt request. see below for the mapping of the individual interrupt sources to the interrupt request: the status interrupt combines the following interrupt sources: source uart 0 uart 1 uart 2 uart 3 uart 4 transmit data empty x x x x x transmit complete x x x x x idle line x x x x x receive data full x x x x x lin break detect x x x x x rxd pin active edge x x x x x initial character detect x the error interrupt combines the following interrupt sources: source uart 0 uart 1 uart 2 uart 3 uart 4 receiver overrun x x x x x noise flag x x x x x framing error x x x x x parity error x x x x x transmitter buffer overflow x x x x x receiver buffer underflow x x x x x transmit threshold (iso7816) x receiver threshold (iso7816) x wait timer (iso7816) x character wait timer (iso7816) x table continues on the next page... communication interfaces 60 sub-family reference manual, rev. 6, nov 2011 16 freescale semiconductor, inc. source uart 0 uart 1 uart 2 uart 3 uart 4 block wait timer (iso7816) x guard time violation (iso7816) x 3.9.7 sdhc configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. crossbar switch register access peripheral bridge module signals sdhc transfers signal multiplexing figure 3-63. sdhc configuration table 3-74. reference links to related information topic related module reference full description sdhc sdhc system memory map system memory map clocking clock distribution power management power management transfers crossbar switch crossbar switch signal multiplexing port control signal multiplexing 3.9.7.1 sdhc clocking in addition to the system clock, the sdhc needs a clock for the base for the external card clock. there are four possible clock sources for this clock, selected by the sims sopt2 register: ? core/system clock ? mcgpllclk or mcgfllclk ? extal ? bypass clock from off-chip (sdhc0_clkin) chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 157 3.9.7.2 sd bus pullup/pulldown constraints the sd standard requires the sd bus signals (except the sd clock) to be pulled up during data transfers. the sdhc also provides a feature of detecting card insertion/removal, by detecting voltage level changes on dat[3] of the sd bus. to support this dat[3] must be pulled down. to avoid a situation where the sdhc detects voltage changes due to normal data transfers on the sd bus as card insertion/removal, the interrupt relating to this event must be disabled after the card has been inserted and detected. it can be re- enabled after the card is removed. 3.9.8 i 2 s configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. signal multiplexing register access peripheral bridge module signals 2 i s figure 3-64. i 2 s configuration table 3-75. reference links to related information topic related module reference full description i 2 s i2s system memory map system memory map clocking clock distribution power management power management signal multiplexing port control signal multiplexing note the i2s master clock can be output on the i2s0_mclk pin or input on the i2s0_clkin pin. using the i2s0_rx_bclk pin to output the i2s master clock in synchronous mode is not supported on this device. communication interfaces k60 sub-family reference manual, rev. 6, nov 2011 158 freescale semiconductor, inc. 3.9.8.1 interrupts the interrupt outputs from the i 2 s module are or'd to create a single interrupt to the interrupt control logic. 3.9.8.2 dma requests the i 2 s module has two dma requests: ? transmit fifo ? receive fifo 3.9.8.3 i 2 s clock generation to generate the desired frequencies for the i 2 s module there are multiple clocking options as shown below: ? the core/system clock is routed to an 8-bit fractional divider to generate the i 2 s clock. ? the pll output is routed to an 8-bit fractional divider to generate the i 2 s clock. ? the extal pin directly drives the i 2 s clock. ? the i2s0_clkin pin directly drives the i 2 s clock. these options are controlled by the sim_sopt2[i2ssrc] field, and the 8-bit fractional divider is controlled by the sim_clkdiv2[i2sdiv, i2sfrac] fields. see the sim module for details. 3.9.8.4 i 2 s operation in low power modes the i 2 s module requires interaction with the rest of the system to move data in or out of the fifos. since the rest of the system is not active in stop, vlps, and lls modes, there is no use for the i 2 s in these modes. the i 2 s is powered so that it retains state in these modes, but it is not functional. in vlpr and vlpw modes, the i 2 s is functional. however, the i 2 s is limited to 400 khz maximum frequency. chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 159 human-machine interfaces (hmi) 3.10.1 gpio configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. signal multiplexing register access peripheral bridge module signals gpio controller crossbar switch transfers figure 3-65. gpio configuration table 3-76. reference links to related information topic related module reference full description gpio gpio system memory map system memory map clocking clock distribution power management power management transfers crossbar switch clock distribution signal multiplexing port control signal multiplexing 3.10.1.1 gpio access protection the gpio module does not have access protection because it is not connected to a peripheral bridge slot and is not protected by the mpu. 3.10.1.2 number of gpio signals the number of gpio signals available on the devices covered by this document are detailed in orderable part numbers . 3.10 human-machine interfaces (hmi) k60 sub-family reference manual, rev. 6, nov 2011 160 freescale semiconductor, inc. 3.10.2 tsi configuration this section summarizes how the module has been configured in the chip. for a comprehensive description of the module itself, see the modules dedicated chapter. signal multiplexing register access peripheral bridge module signals touch sense input module figure 3-66. tsi configuration table 3-77. reference links to related information topic related module reference full description tsi tsi system memory map system memory map clocking clock distribution power management power management signal multiplexing port control signal multiplexing 3.10.2.1 number of inputs this device includes one tsi module containing 16 inputs. in low-power modes, one selectable pin is active. 3.10.2.2 tsi module functionality in mcu operation modes table 3-78. tsi module functionality in mcu operation modes mcu operation mode tsi clock sources tsi operation mode when gencs[tsien] is 1 functional electrode pins required gencs[stpe] state run busclk, mcgirclk, oscerclk active mode all dont care wait busclk, mcgirclk, oscerclk active mode all dont care table continues on the next page... chapter chip configuration 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 161 table 3-78. tsi module functionality in mcu operation modes (continued) mcu operation mode tsi clock sources tsi operation mode when gencs[tsien] is 1 functional electrode pins required gencs[stpe] state stop mcgirclk, oscerclk active mode all 1 vlpr busclk, mcgirclk, oscerclk active mode all don?t care vlpw busclk, mcgirclk, oscerclk active mode all don?t care vlps oscerclk active mode all 1 lls lpoclk, vlposcclk low power mode determined by pen[lpsp] 1 vlls3 lpoclk, vlposcclk low power mode determined by pen[lpsp] 1 vlls2 lpoclk, vlposcclk low power mode determined by pen[lpsp] 1 vlls1 lpoclk, vlposcclk low power mode determined by pen[lpsp] 1 3.10.2.3 tsi clocks this table shows the tsi clocks and the corresponding chip clocks. table 3-79. tsi clock connections module clock chip clock busclk bus clock mcgirclk mcgirclk oscerclk oscerclk lpoclk 1 khz lpo clock vlposcclk erclk32k 3.10.2.4 tsi interrupts the tsi has multiple sources of interrupt requests. however, these sources are or'd together to generate a single interrupt request. when a tsi interrupt occurs, read the tsi status register to determine the exact interrupt source. human-machine interfaces (hmi) k60 sub-family reference manual, rev. 6, nov 2011 162 freescale semiconductor, inc. 3.10.2.5 shield drive signal the shield drive signal is not supported on this device. ignore this feature in the tsi chapter. chapter 3 chip configuration k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 163 human-machine interfaces (hmi) k60 sub-family reference manual, rev. 6, nov 2011 164 freescale semiconductor, inc. chapter 4 memory map 4.1 introduction this device contains various memories and memory-mapped peripherals which are located in one 32-bit contiguous memory space. this chapter describes the memory and peripheral locations within that memory space. 4.2 system memory map the following table shows the high-level device memory map. table 4-1. system memory map system 32-bit address range destination slave access 0x0000_0000?0x0fff_ffff program flash and read-only data (includes exception vectors in first 1024 bytes) all masters 0x1000_0000?0x13ff_ffff for mk60dn256zvll10: reserved for mk60dx256zvll10: flexnvm for mk60dn512zvll10: reserved all masters 0x1400_0000?0x17ff_ffff for devices with flexnvm: flexram for devices with program flash only: programming acceleration ram all masters 0x1800_0000?0x1fff_ffff sram_l: lower sram (icode/dcode) all masters 0x2000_0000?0x200f_ffff sram_u: upper sram bitband region all masters 0x2010_0000?0x21ff_ffff reserved ? 0x2200_0000?0x23ff_ffff aliased to sram_u bitband cortex-m4 core only 0x2400_0000?0x3fff_ffff reserved ? 0x4000_0000?0x4007_ffff bitband region for peripheral bridge 0 (aips-lite0) cortex-m4 core & dma/ezport table continues on the next page... 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 16 table 4-1. system memory map (continued) system 32-bit address range destination slave access 0x4008_00000x400f_efff bitband region for peripheral bridge 1 (aips-lite1) cortex-m4 core & dma/ezport 0x400f_f0000x400f_ffff bitband region for general purpose input/output (gpio) cortex-m4 core & dma/ezport 0x4010_00000x41ff_ffff reserved 0x4200_00000x43ff_ffff aliased to peripheral bridge (aips-lite) and general purpose input/output (gpio) bitband cortex-m4 core only 0x4400_00000x5fff_ffff reserved 0x6000_00000x7fff_ffff flexbus (external memory - write-back) all masters 0x8000_00000x9fff_ffff flexbus (external memory - write-through) all masters 0xa000_00000xdfff_ffff flexbus (external peripheral - not executable) all masters 0xe000_00000xe00f_ffff private peripherals cortex-m4 core only 0xe010_00000xffff_ffff reserved note 1. ezport master port is statically muxed with dma master port. access rights to aips-lite peripheral bridges and general purpose input/output (gpio) module address space is limited to the core, dma, and ezport. 2. arm cortex-m4 core access privileges also includes accesses via the debug interface. 4.2.1 aliased bit-band regions the sram_u, aips-lite, and general purpose input/output (gpio) module resources reside in the cortex-m4 processor bit-band regions. the processor also includes two 32 mb aliased bit-band regions associated with the two 1 mb bit-band spaces. each 32-bit location in the 32 mb space maps to an individual bit in the bit-band region. a 32-bit write in the alias region has the same effect as a read- modify-write operation on the targeted bit in the bit-band region. bit 0 of the value written to the alias region determines what value is written to the target bit: ? writing a value with bit 0 set writes a 1 to the target bit. ? writing a value with bit 0 clear writes a 0 to the target bit. a 32-bit read in the alias region returns either: system memory map k60 sub-family reference manual, rev. 6, nov 2011 166 freescale semiconductor, inc. ? a value of 0x0000_0000 to indicate the target bit is clear ? a value of 0x0000_0001 to indicate the target bit is set 31 0 0 31 bit-band region alias bit-band region 1 mbyte 32 mbyte figure 4-1. alias bit-band mapping note each bit in bit-band region has an equivalent bit that can be manipulated through bit 0 in a corresponding long word in the alias bit-band region. 4.3 flash memory map the various flash memories and the flash registers are located at different base addresses as shown in the following figure. the base address for each is specified in system memory map . chapter 4 memory map k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 167 program flash flash configuration field program flash base address flash memory base address registers ram programming acceleration ram base address figure 4-2. flash memory map for devices containing only program flash program flash flash configuration field flexnvm base address program flash base address flash memory base address registers flexnvm flexram flexram base address figure 4-3. flash memory map for devices containing flexnvm 4.3.1 alternate non-volatile irc user trim description the following non-volatile locations (4 bytes) are reserved for custom irc user trim supported by some development tools. an alternate irc trim to the factory loaded trim can be stored at this location. to override the factory trim, user software must load new values into the mcg trim registers. non-volatile byte address alternate irc trim value 0x0000_03fc reserved 0x0000_03fd reserved 0x0000_03fe (bit 0) scftrim 0x0000_03fe (bit 4:1) fctrim 0x0000_03ff sctrim flash memory map k60 sub-family reference manual, rev. 6, nov 2011 168 freescale semiconductor, inc. 4.4 sram memory map the on-chip ram is split evenly among sram_l and sram_u. the ram is also implemented such that the sram_l and sram_u ranges form a contiguous block in the memory map. see sram arrays for details. accesses to the sram_l and sram_u memory ranges outside the amount of ram on the device causes the bus cycle to be terminated with an error followed by the appropriate response in the requesting bus master. 4.5 peripheral bridge (aips-lite0 and aips-lite1) memory maps the peripheral memory map is accessible via two slave ports on the crossbar switch in the 0x4000_0000C0x400f_ffff region. the device implements two peripheral bridges (aips-lite 0 and 1): ? aips-lite0 covers 512 kb ? aips-lite1 covers 508 kb with 4 kb assigned to the general purpose input/output module (gpio) aips-lite0 is connected to crossbar switch slave port 2, and is accessible at locations 0x4000_0000C0x4007_ffff. aips-lite1 and the general purpose input/output module share the connection to crossbar switch slave port 3. the aips-lite1 is accessible at locations 0x4008_0000C 0x400f_efff. the general purpose input/output module is accessible in a 4-kbyte region at 0x400f_f000C0x400f_ffff. its direct connection to the crossbar switch provides master access without incurring wait states associated with accesses via the aips-lite controllers. modules that are disabled via their clock gate control bits in the sim registers disable the associated aips slots. access to any address within an unimplemented or disabled peripheral bridge slot results in a transfer error termination. for programming model accesses via the peripheral bridges, there is generally only a small range within the 4 kb slots that is implemented. accessing an address that is not implemented in the peripheral results in a transfer error termination. chapter 4 memory map k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 169 4.5.1 peripheral bridge 0 (aips-lite 0) memory map table 4-2. peripheral bridge 0 slot assignments system 32-bit base address slot number module 0x4000_0000 0 peripheral bridge 0 (aips-lite 0) 0x4000_1000 1 0x4000_2000 2 0x4000_3000 3 0x4000_4000 4 crossbar switch 0x4000_5000 5 0x4000_6000 6 0x4000_7000 7 0x4000_8000 8 dma controller 0x4000_9000 9 dma controller transfer control descriptors 0x4000_a000 10 0x4000_b000 11 0x4000_c000 12 flexbus 0x4000_d000 13 mpu 0x4000_e000 14 0x4000_f000 15 0x4001_0000 16 0x4001_1000 17 0x4001_2000 18 0x4001_3000 19 0x4001_4000 20 0x4001_5000 21 0x4001_6000 22 0x4001_7000 23 0x4001_8000 24 0x4001_9000 25 0x4001_a000 26 0x4001_b000 27 0x4001_c000 28 0x4001_d000 29 0x4001_e000 30 0x4001_f000 31 flash memory controller 0x4002_0000 32 flash memory table continues on the next page... peripheral bridge aips-ite0 and aips-ite1 memory maps 60 sub-family reference manual, rev. 6, nov 2011 170 freescale semiconductor, inc. table 4-2. peripheral bridge 0 slot assignments (continued) system 32-bit base address slot number module 0x4002_1000 33 dma channel mutiplexer 0 0x4002_2000 34 0x4002_3000 35 0x4002_4000 36 flexcan 0 0x4002_5000 37 0x4002_6000 38 0x4002_7000 39 0x4002_8000 40 0x4002_9000 41 0x4002_a000 42 0x4002_b000 43 0x4002_c000 44 spi 0 0x4002_d000 45 spi 1 0x4002_e000 46 0x4002_f000 47 i2s 0 0x4003_0000 48 0x4003_1000 49 0x4003_2000 50 crc 0x4003_3000 51 0x4003_4000 52 0x4003_5000 53 usb dcd 0x4003_6000 54 programmable delay block (pdb) 0x4003_7000 55 periodic interrupt timers (pit) 0x4003_8000 56 flextimer (ftm) 0 0x4003_9000 57 flextimer (ftm) 1 0x4003_a000 58 0x4003_b000 59 analog-to-digital converter (adc) 0 0x4003_c000 60 0x4003_d000 61 real-time clock (rtc) 0x4003_e000 62 vbat register file 0x4003_f000 63 0x4004_0000 64 low-power timer (lptmr) 0x4004_1000 65 system register file 0x4004_2000 66 table continues on the next page... chapter 4 memory map 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 171 table 4-2. peripheral bridge 0 slot assignments (continued) system 32-bit base address slot number module 0x4004_3000 67 0x4004_4000 68 0x4004_5000 69 touch sense interface (tsi) 0x4004_6000 70 0x4004_7000 71 sim low-power logic 0x4004_8000 72 system integration module (sim) 0x4004_9000 73 port a multiplexing control 0x4004_a000 74 port b multiplexing control 0x4004_b000 75 port c multiplexing control 0x4004_c000 76 port d multiplexing control 0x4004_d000 77 port e multiplexing control 0x4004_e000 78 0x4004_f000 79 0x4005_0000 80 0x4005_1000 81 0x4005_2000 82 software watchdog 0x4005_3000 83 0x4005_4000 84 0x4005_5000 85 0x4005_6000 86 0x4005_7000 87 0x4005_8000 88 0x4005_9000 89 0x4005_a000 90 0x4005_b000 91 0x4005_c000 92 0x4005_d000 93 0x4005_e000 94 0x4005_f000 95 0x4006_0000 96 0x4006_1000 97 external watchdog 0x4006_2000 98 carrier modulator timer (cmt) 0x4006_3000 99 0x4006_4000 100 multi-purpose clock generator (mcg) table continues on the next page... peripheral bridge aips-ite0 and aips-ite1 memory maps 60 sub-family reference manual, rev. 6, nov 2011 172 freescale semiconductor, inc. table 4-2. peripheral bridge 0 slot assignments (continued) system 32-bit base address slot number module 0x4006_5000 101 system oscillator (osc) 0x4006_6000 102 i 2 c 0 0x4006_7000 103 i 2 c 1 0x4006_8000 104 0x4006_9000 105 0x4006_a000 106 uart 0 0x4006_b000 107 uart 1 0x4006_c000 108 uart 2 0x4006_d000 109 uart 3 0x4006_e000 110 0x4006_f000 111 0x4007_0000 112 0x4007_1000 113 0x4007_2000 114 usb otg fs/ls 0x4007_3000 115 analog comparator (cmp) / 6-bit digital-to-analog converter (dac) 0x4007_4000 116 voltage reference (vref) 0x4007_5000 117 0x4007_6000 118 0x4007_7000 119 0x4007_8000 120 0x4007_9000 121 0x4007_a000 122 0x4007_b000 123 0x4007_c000 124 low-leakage wakeup unit (llwu) 0x4007_d000 125 power management controller (pmc) 0x4007_e000 126 system mode controller (smc) 0x4007_f000 127 4.5.2 peripheral bridge 1 (aips-lite 1) memory map table 4-3. peripheral bridge 1 slot assignments system 32-bit base address slot number module 0x4008_0000 0 peripheral bridge 1 (aips-lite 1) table continues on the next page... chapter 4 memory map 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 17 table 4-3. peripheral bridge 1 slot assignments (continued) system 32-bit base address slot number module 0x4008_1000 1 0x4008_2000 2 0x4008_3000 3 0x4008_4000 4 0x4008_5000 5 0x4008_6000 6 0x4008_7000 7 0x4008_8000 8 0x4008_9000 9 0x4008_a000 10 0x4008_b000 11 0x4008_c000 12 0x4008_d000 13 0x4008_e000 14 0x4008_f000 15 0x4009_0000 16 0x4009_1000 17 0x4009_2000 18 0x4009_3000 19 0x4009_4000 20 0x4009_5000 21 0x4009_6000 22 0x4009_7000 23 0x4009_8000 24 0x4009_9000 25 0x4009_a000 26 0x4009_b000 27 0x4009_c000 28 0x4009_d000 29 0x4009_e000 30 0x4009_f000 31 0x400a_0000 32 random number generator (rngb) 0x400a_1000 33 0x400a_2000 34 table continues on the next page... peripheral bridge aips-ite0 and aips-ite1 memory maps 60 sub-family reference manual, rev. 6, nov 2011 174 freescale semiconductor, inc. table 4-3. peripheral bridge 1 slot assignments (continued) system 32-bit base address slot number module 0x400a_3000 35 0x400a_4000 36 flexcan 1 0x400a_5000 37 0x400a_6000 38 0x400a_7000 39 0x400a_8000 40 0x400a_9000 41 0x400a_a000 42 0x400a_b000 43 0x400a_c000 44 spi 2 0x400a_d000 45 0x400a_e000 46 0x400a_f000 47 0x400b_0000 48 0x400b_1000 49 sdhc 0x400b_2000 50 0x400b_3000 51 0x400b_4000 52 0x400b_5000 53 0x400b_6000 54 0x400b_7000 55 0x400b_8000 56 flextimer (ftm) 2 0x400b_9000 57 0x400b_a000 58 0x400b_b000 59 analog-to-digital converter (adc) 1 0x400b_c000 60 0x400b_d000 61 0x400b_e000 62 0x400b_f000 63 0x400c_0000 64 ethernet mac and ieee 1588 timers 0x400c_1000 65 0x400c_2000 66 0x400c_3000 67 0x400c_4000 68 table continues on the next page... chapter 4 memory map 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 17 table 4-3. peripheral bridge 1 slot assignments (continued) system 32-bit base address slot number module 0x400c_5000 69 0x400c_6000 70 0x400c_7000 71 0x400c_8000 72 0x400c_9000 73 0x400c_a000 74 0x400c_b000 75 0x400c_c000 76 12-bit digital-to-analog converter (dac) 0 0x400c_d000 77 0x400c_e000 78 0x400c_f000 79 0x400d_0000 80 0x400d_1000 81 0x400d_2000 82 0x400d_3000 83 0x400d_4000 84 0x400d_5000 85 0x400d_6000 86 0x400d_7000 87 0x400d_8000 88 0x400d_9000 89 0x400d_a000 90 0x400d_b000 91 0x400d_c000 92 0x400d_d000 93 0x400d_e000 94 0x400d_f000 95 0x400e_0000 96 0x400e_1000 97 0x400e_2000 98 0x400e_3000 99 0x400e_4000 100 0x400e_5000 101 0x400e_6000 102 table continues on the next page... peripheral bridge aips-ite0 and aips-ite1 memory maps 60 sub-family reference manual, rev. 6, nov 2011 176 freescale semiconductor, inc. table 4-3. peripheral bridge 1 slot assignments (continued) system 32-bit base address slot number module 0x400e_7000 103 0x400e_8000 104 0x400e_9000 105 0x400e_a000 106 uart 4 0x400e_b000 107 0x400e_c000 108 0x400e_d000 109 0x400e_e000 110 0x400e_f000 111 0x400f_0000 112 0x400f_1000 113 0x400f_2000 114 0x400f_3000 115 0x400f_4000 116 0x400f_5000 117 0x400f_6000 118 0x400f_7000 119 0x400f_8000 120 0x400f_9000 121 0x400f_a000 122 0x400f_b000 123 0x400f_c000 124 0x400f_d000 125 0x400f_e000 126 0x400f_f000 not an aips-lite slot. the 32-bit general purpose input/output module that shares the crossbar switch slave port with the aips-lite is accessed at this address. chapter 4 memory map k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 177 4.6 private peripheral bus (ppb) memory map the ppb is part of the defined arm bus architecture and provides access to select processor-local modules. these resources are only accessible from the core; other system masters do not have access to them. table 4-4. ppb memory map system 32-bit address range resource 0xe000_0000?0xe000_0fff instrumentation trace macrocell (itm) 0xe000_1000?0xe000_1fff data watchpoint and trace (dwt) 0xe000_2000?0xe000_2fff flash patch and breakpoint (fpb) 0xe000_3000?0xe000_dfff reserved 0xe000_e000?0xe000_efff system control space (scs) (for nvic) 0xe000_f000?0xe003_ffff reserved 0xe004_0000?0xe004_0fff trace port interface unit (tpiu) 0xe004_1000?0xe004_1fff embedded trace macrocell (etm) 0xe004_2000?0xe004_2fff embedded trace buffer (etb) 0xe004_3000?0xe004_3fff embedded trace funnel 0xe004_4000?0xe007_ffff reserved 0xe008_0000?0xe008_0fff miscellaneous control module (mcm)(including etb almost full) 0xe008_1000?0xe008_1fff memory mapped cryptographic acceleration unit (mmcau) 0xe008_2000?0xe00f_efff reserved 0xe00f_f000?0xe00f_ffff rom table - allows auto-detection of debug components private peripheral bus (ppb) memory map k60 sub-family reference manual, rev. 6, nov 2011 178 freescale semiconductor, inc. chapter 5 clock distribution 5.1 introduction the mcg module controls which clock source is used to derive the system clocks. the clock generation logic divides the selected clock source into a variety of clock domains, including the clocks for the system bus masters, system bus slaves, and flash memory. the clock generation logic also implements module-specific clock gating to allow granular shutoff of modules. the primary clocks for the system are generated from the mcgoutclk clock. the clock generation circuitry provides several clock dividers that allow different portions of the device to be clocked at different frequencies. this allows for trade-offs between performance and power dissipation. various modules, such as the usb otg controller, have module-specific clocks that can be generated from the mcgpllclk or mcgfllclk clock. in addition, there are various other module-specific clocks that have other alternate sources. clock selection for most modules is controlled by the sopt registers in the sim module. 5.2 programming model the selection and multiplexing of system clock sources is controlled and programmed via the mcg module. the setting of clock dividers and module clock gating for the system are programmed via the sim module. reference those sections for detailed register and bit descriptions. 5.3 high-level device clocking diagram the following system oscillator , mcg , and sim module registers control the multiplexers, dividers, and clock gates shown in the below figure: k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 179 osc mcg sim muliplexers mcg_c x mc_c x sim_spt1, sim_spt2 dividers mc_c x sim_cdiv x cloc gates sc_cr mc_c1 sim_scc x 2 hz irc p f mcutc mcpc mc mcfc utdiv1 core system clocs 4 mhz irc utdiv4 flash cloc real-time cloc utdiv2 bus cloc rtc oscillator exta2 xta2 exta xta system oscillator sim frdiv mcirc erc2 sc2c xta_c 2 mcffc scerc sc logic sc logic cloc options for some peripherals see note cloc options for some peripherals see note mcfc mcpc note see subseuent sections for details on where these clocs are used. pmc logic pmc p scc c c c c c c cloc gate 2 utdiv flexbus cloc c figure -1. clocing diagram .4 cloc definitions the following table describes the clocks in the previous block diagram. clock name description core clock mcgoutclk divided by outdiv1 clocks the arm cortex- m4 core system clock mcgoutclk divided by outdiv1 clocks the crossbar switch and bus masters directly connected to the crossbar. in addition, this clock is used for uart0 and uart1. table continues on the next page... cloc definitions 60 sub-family reference manual, rev. 6, nov 2011 180 freescale semiconductor, inc. clock name description bus clock mcgoutclk divided by outdiv2 clocks the bus slaves and peripheral (excluding memories) flexbus clock mcgoutclk divided by outdiv3 clocks the external flexbus interface flash clock mcgoutclk divided by outdiv4 clocks the flash memory mcgirclk mcg output of the slow or fast internal reference clock mcgffclk mcg output of the slow internal reference clock or a divided mcg external reference clock. the mcgffclk is further divided by 2 before being made available to modules outside the mcg (as shown in the preceding figure). mcgoutclk mcg output of either irc, mcgfllclk, mcgpllclk, or mcgs external reference clock that sources the core, system, bus, flexbus, and flash clock. it is also an option for the debug trace clock. mcgfllclk mcg output of the fll. mcgfllclk or mcgpllclk may clock some modules. mcgpllclk mcg output of the pll. mcgfllclk or mcgpllclk may clock some modules. mcg external reference clock input clock to the mcg sourced by the system oscillator (oscclk) or rtc oscillator oscclk system oscillator output of the internal oscillator or sourced directly from extal oscerclk system oscillator output sourced from oscclkthat may clock some on-chip modules osc32kclk system oscillator 32khz output erclk32k clock source for some modules that is chosen as osc32kclk or the rtc clock rtc clock rtc oscillator output for the rtc module lpo pmc 1khz output 5.4.1 device clock summary the following table provides more information regarding the on-chip clocks. table 5-1. clock summary clock name run mode clock frequency vlpr mode clock frequency clock source clock is disabled when mcgoutclk up to 100 mhz up to 2 mhz mcg in all stop modes core clock up to 100 mhz up to 2 mhz mcgoutclk clock divider in all wait and stop modes system clock up to 100 mhz up to 2 mhz mcgoutclk clock divider in all stop modes bus clock up to 50 mhz up to 2 mhz mcgoutclk clock divider in all stop modes table continues on the next page... chapter cloc distribution 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 181 table 5-1. clock summary (continued) clock name run mode clock frequency vlpr mode clock frequency clock source clock is disabled when? flexbus clock (fb_clk) up to 50 mhz up to 2 mhz mcgoutclk clock divider in all stop modes or flexbus disabled flash clock up to 25 mhz up to 1 mhz mcgoutclk clock divider in all stop modes internal reference (mcgirclk) 30-40 khz or 2 mhz 2 mhz only mcg mcg_c1[irclken] cleared, stop mode and mcg_c1[irefsten] cleared, or vlps/lls/vlls mode external reference (oscerclk) up to 50 mhz (bypass), 30-40 khz, or 4-32 mhz (crystal) up to 4 mhz (bypass), 30-40 khz (low-range crystal) or up to 4 mhz (high- range crystal) system osc system oscs osc_cr[erclken] cleared, or stop mode and osc_cr[erefsten] cleared external reference 32khz (erclk32k) 30-40 khz 30-40 khz system osc or rtc osc depending on sim_sopt1[osc32k sel] system oscs osc_cr[erclken] cleared or rtcs rtc_cr[osce] cleared rtc_clkout 1 hz 1 hz rtc clock clock is disabled in lls and vllsx modes lpo 1 khz 1 khz pmc available in all power modes usb fs clock 48 mhz n/a mcgpllclk or mcgfllclk with fractional clock divider, or usb_clkin usb fs otg is disabled i2s master clock up to 50 mhz n/a system clock, mcgpllclk, or mcgfllclk with fractional clock divider, oscerclk, or i2s_clkin i 2 s is disabled sdhc clock up to 50 mhz n/a system clock, mcgpllclk/ mcgfllclk, or oscerclk sdhc is disabled ethernet rmii clock 50 mhz n/a oscerclk ethernet is disabled table continues on the next page... cloc definitions 60 sub-family reference manual, rev. 6, nov 2011 182 freescale semiconductor, inc. table 5-1. clock summary (continued) clock name run mode clock frequency vlpr mode clock frequency clock source clock is disabled when? ethernet ieee 1588 clock up to 100 mhz n/a system clock, oscerclk, mcgpllclk/ mcgfllclk, or enet_1588_clkin ethernet is disabled trace clock up to 100 mhz up to 2 mhz system clock or mcgoutclk trace is disabled 5.5 internal clocking requirements the clock dividers are programmed via the sim modules clkdiv registers. each divider is programmable from a divide-by-1 through divide-by-16 setting. the following requirements must be met when configuring the clocks for this device: 1. the core and system clock frequencies must be 100 mhz or slower. 2. the bus clock frequency must be programmed to 50 mhz or less and an integer divide of the core clock. 3. the flash clock frequency must be programmed to 25 mhz or less and an integer divide of the bus clock. 4. the flexbus clock frequency must be programmed to be less than or equal to the bus clock frequency. the following are a few of the more common clock configurations for this device: option 1: clock frequency core clock 50 mhz system clock 50 mhz bus clock 50 mhz flexbus clock 50 mhz flash clock 25 mhz option 2: clock frequency core clock 100 mhz table continues on the next page... chapter cloc distribution 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 18 clock frequency system clock 100 mhz bus clock 50 mhz flexbus clock 25 mhz flash clock 25 mhz option 3: clock frequency core clock 96 mhz system clock 96 mhz bus clock 48 mhz flexbus clock 48 mhz flash clock 24 mhz 5.5.1 clock divider values after reset each clock divider is programmed via the sim modules clkdiv n registers. the flash memory's ftfl_fopt[lpboot] bit controls the reset value of the core clock, system clock, bus clock, and flash clock dividers as shown below: ftfl_fopt [lpboot] core/system clock bus clock flexbus clock flash clock description 0 0x7 (divide by 8) 0x7 (divide by 8) 0xf (divide by 16) 0xf (divide by 16) low power boot 1 0x0 (divide by 1) 0x0 (divide by 1) 0x1 (divide by 2) 0x1 (divide by 2) fast clock boot this gives the user flexibility for a lower frequency, low-power boot option. the flash erased state defaults to fast clocking mode, since where the low power boot (ftfl_fopt[lpboot]) bit resides in flash is logic 1 in the flash erased state. to enable the low power boot option program ftfl_fopt[lpboot] to zero. during the reset sequence, if lpboot is cleared, the system is in a slow clock configuration. upon any system reset, the clock dividers return to this configurable reset state. 5.5.2 vlpr mode clocking the clock dividers cannot be changed while in vlpr mode. they must be programmed prior to entering vlpr mode to guarantee: ? the core/system, flexbus, and bus clocks are less than or equal to 2 mhz, and ? the flash memory clock is less than or equal to 1 mhz internal clocking requirements k60 sub-family reference manual, rev. 6, nov 2011 184 freescale semiconductor, inc. 5.6 clock gating the clock to each module can be individually gated on and off using the sim module's scgc x registers. these bits are cleared after any reset, which disables the clock to the corresponding module to conserve power. prior to initializing a module, set the corresponding bit in scgc x register to enable the clock. before turning off the clock, make sure to disable the module. any bus access to a peripheral that has its clock disabled generates an error termination. 5.7 module clocks the following table summarizes the clocks associated with each module. table 5-2. module clocks module bus interface clock internal clocks i/o interface clocks core modules arm cortex-m4 core system clock core clock nvic system clock dap system clock itm system clock etm system clock trace clock trace_clkout etb system clock cjtag, jtagc jtag_clk system modules dma system clock dma mux bus clock port control bus clock lpo crossbar switch system clock peripheral bridges system clock bus clock mpu system clock llwu, pmc, sim bus clock lpo mode controller bus clock mcm system clock ewm bus clock lpo watchdog timer bus clock lpo table continues on the next page... chapter cloc distribution 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 18 table 5-2. module clocks (continued) module bus interface clock internal clocks i/o interface clocks clocks mcg bus clock mcgoutclk, mcgpllclk, mcgfllclk, mcgirclk, oscerclk osc bus clock oscerclk memory and memory interfaces flash controller system clock flash clock flash memory flash clock flexbus system clock fb_clkout ezport system clock ezp_clk security crc bus clock mmcau system clock rngb bus clock analog adc bus clock oscerclk cmp bus clock dac bus clock vref bus clock timers pdb bus clock flextimers bus clock mcgffclk ftm_clkin x pit bus cloc ptmr bus cloc p, scerc, mcirc, erc2 cmt bus cloc rtc bus cloc exta2 communication interfaces ethernet system cloc, bus cloc rmii cloc, ieee 188 cloc mii_rxc, mii_txc usb fs t system cloc usb fs cloc usb dcd bus cloc flexcan bus cloc scerc dspi bus cloc dspi_sc i 2 c bus cloc i2c_sc uart0, uart1 system cloc uart2-4 bus cloc table continues on the next page... module clocs 60 sub-family reference manual, rev. 6, nov 2011 186 freescale semiconductor, inc. table 5-2. module clocks (continued) module bus interface clock internal clocks i/o interface clocks sdhc system clock sdhc clock sdhc_dclk i 2 s bus clock i 2 s master clock i2s_tx_bclk, i2s_rx_bclk human-machine interfaces gpio system clock tsi bus clock lpo, erclk32k, mcgirclk 5.7.1 pmc 1-khz lpo clock the power management controller (pmc) generates a 1-khz clock that is enabled in all modes of operation, including all low power modes. this 1-khz source is commonly referred to as lpo clock or 1-khz lpo clock. 5.7.2 wdog clocking the wdog may be clocked from two clock sources as shown in the following figure. wdog_stctrlh[clksrc] wdog clock bus clock lpo figure 5-2. wdog clock generation 5.7.3 debug trace clock the debug trace clock source can be clocked as shown in the following figure. chapter 5 clock distribution k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 187 sim_sopt2[traceclksel] traceclkin core / system clock mcgoutclk tpiu 2 trace_clkout figure 5-3. trace clock generation note the trace clock frequency observed at the trace_clkout pin will be half that of the selected clock source. 5.7.4 port digital filter clocking the digital filters in each of the port x modules can be clocked as shown in the following figure. note in stop mode, the digital input filters are bypassed unless they are configured to run from the 1 khz lpo clock source. portx_dfcr[cs] portx digital input filter clock bus clock lpo figure 5-4. port x iital inut ilter cloc eneration lr clocin the prescaler and glitch filters in each of the lptmr x modules can be clocked as shown in the following figure. module clocks k60 sub-family reference manual, rev. 6, nov 2011 188 freescale semiconductor, inc. note the chosen clock must remain enabled if the lptmr x is to continue operating in all required low-power modes. lptmrx_psr[pcs] lptmrx prescaler/glitch filter clock mcgirclk oscerclk erclk32k lpo figure 5-5. lptmr x rescalerlitch ilter cloc eneration thernet locin ? the rmii clock source is fixed to oscerclk and must be 50 mhz ? the mii clocks are supplied from pins and must be 25 mhz ? the ieee 1588 timestamp clock can run up to 100 mhz, if generated from internal clock sources. its period must be an integer number of nanoseconds (eg: 10ns = 100 mhz, 15ns = 66.67 mhz, 20ns = 50 mhz). its clock source is chosen as shown in the following figure. core / system clock oscerclk mcgpllclk or mcgfllclk enet_1588_clkin sim_sopt2[timesrc] ethernet ieee 1588 timestamp clock figure 5-6. ethernet ieee1588 timestamp clock generation chapter 5 clock distribution k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 189 5.7.7 usb fs otg controller clocking the usb fs otg controller is a bus master attached to the crossbar switch. as such, its clock is connected to the system clock. note for the usb fs otg controller to operate, the minimum system clock frequency is 20 mhz. the usb otg controller also requires a 48 mhz clock. the clock source options are shown below. usb 48mhz usb_clkin mcgpllclk or mcgfllclk sim_clkdiv2 [usbfrac, usbdiv] sim_sopt2[usbsrc] figure 5-7. usb 48 mhz clock source 5.7.8 flexcan clocking the clock for the flexcan's protocol engine can be selected as shown in the following figure. canx_ctrl1[clksrc] flexcan clock bus clock oscerclk figure 5-8. flexcan clock generation module clocks k60 sub-family reference manual, rev. 6, nov 2011 190 freescale semiconductor, inc. 5.7.9 uart clocking uart0 and uart1 modules operate from the core/system clock, which provides higher performance level for these modules. all other uart modules operate from the bus clock. 5.7.10 sdhc clocking the sdhc module has four possible clock sources for the external clock source, as shown in the following figure. sim_sopt2[sdhcsrc] sdhc clock mcgpllclk or mcgfllclk core / system clock oscerclk sdhc0_clkin figure 5-9. sdhc clock generation 5.7.11 i 2 s clocking in addition to the bus clock, the i 2 s has a clock source for master clock generation. the maximum frequency of this clock is 50 mhz. the master clock source can be derived from several sources, as shown in the following figure. sim_sopt2[i2ssrc] core/system clock mcgpllclk or mcgfllclk oscerclk s master clock i 2 i2s_clkin sim_clkdiv2 [i2sfrac,i2sdiv] figure 5-10. i 2 s baud clock generation chapter 5 clock distribution k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 191 5.7.12 tsi clocking in active mode, the tsi can be clocked as shown in the following figure. tsi_scanc[amclks] tsi clock in active mode bus clock mcgirclk oscerclk figure 5-11. tsi clock generation in low-power mode, the tsi can be clocked as shown in the following figure. note in the tsi chapter, these two clocks are referred to as lpoclk and vlposcclk. tsi_gencs[lpclks] tsi clock in low-power mode lpo erclk32k figure 5-12. tsi low-power clock generation module clocks k60 sub-family reference manual, rev. 6, nov 2011 192 freescale semiconductor, inc. chapter 6 reset and boot 6.1 introduction the following reset sources are supported in this mcu: table 6-1. reset sources reset sources description por reset power-on reset (por) system resets external pin reset (pin) low-voltage detect (lvd) computer operating properly (cop) watchdog reset low leakage wakeup (llwu) reset multipurpose clock generator loss of clock (loc) reset software reset (sw) lockup reset (lockup) ezport reset mdm dap system reset debug reset jtag reset ntrst reset each of the system reset sources, with the exception of the ezport and mdm-ap reset, has an associated bit in the system reset status registers (srsh and srsl). see the mode controller for more details. the mcu exits reset in functional mode that is controlled by ezp_cs pin to select between the single chip (default) or serial flash programming (ezport) modes. see boot options for more details. 6.2 reset this section discusses basic reset mechanisms and sources. some modules that cause resets can be configured to cause interrupts instead. consult the individual peripheral chapters for more information. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 193 6.2.1 power-on reset (por) when power is initially applied to the mcu or when the supply voltage drops below the power-on reset re-arm voltage level (v por ), the por circuit causes a por reset condition. as the supply voltage rises, the lvd circuit holds the mcu in reset until the supply has risen above the lvd low threshold (v lvdl ). the por and lvd bits in srsl register are set following a por. 6.2.2 system resets resetting the mcu provides a way to start processing from a known set of initial conditions. system reset begins with the on-chip regulator in full regulation and system clocking generation from an internal reference. when the processor exits reset, it performs the following: ? reads the start sp (sp_main) from vector-table offset 0 ? reads the start pc from vector-table offset 4 ? lr is set to 0xffff_ffff the on-chip peripheral modules are disabled and the non-analog i/o pins are initially configured as disabled. the pins with analog functions assigned to them default to their analog function after reset. during and following a reset, the jtag pins have their associated input pins configured as: ? tdi in pull-up (pu) ? tck in pull-down (pd) ? tms in pu and associated output pin configured as: ? tdo with no pull-down or pull-up note that the ntrst signal is initially configured as disabled, however once configured to its jtag functionality its associated input pin is configured as: ? ntrst in pu reset k60 sub-family reference manual, rev. 6, nov 2011 194 freescale semiconductor, inc. 6.2.2.1 external pin reset (pin) on this device, reset is a dedicated pin. this pin is open drain and has an internal pullup device. asserting reset wakes the device from any mode. during a pin reset, the srsl[pin] bit is set. 6.2.2.1.1 reset pin filter the reset pin supports digital filtering in all modes of operation. for lls and vllsx modes, the llwu provides an optional fixed digital filter running off the 1 khz lpo clock. see the llwu chapter for operation of this filter. during non-low leakage operation, there are two clock options for the reset pin filter C the 1khz lpo clock and the bus clock. this reset pin filter implemented in sim logic includes a separate filter for each clock source. in stop and vlps operation this logic either switches to bypass operation or has continued filtering operation depending on the filtering mode selected. there are several modes defined C see the sopt6 register description in module for more details. sopt6[rstflten[2:0]] and sopt6[rstfltsel[4:0]] fields control the desired functionality. both filters are reset on por, lvd, and wakeup from vlls. the reset value for each filter defaults to off (non-detect). the lpo filter is simple with a fixed filter value count of 3. there is also a synchronizer on the input signal that results in an associated latency (2 cycles). as such, it takes 5 cycles to complete a transition from low-to-high or high-to-low. the lpo filter initializes to off (logic 1) when the lpo filter is not enabled. the bus filter initializes to off (logic 1) when the bus filter not enabled. when the bus filter is enabled, the number of counts is controlled by sopt6[rstfltsel[4:0]]. 6.2.2.2 low-voltage detect (lvd) reset this device includes a system to protect against low voltage conditions to protect memory contents and control mcu system states during supply voltage variations. the system is comprised of a power-on reset (por) circuit and a low-voltage detect (lvd) circuit with a user-selectable trip voltage, either high (v lvdh ) or low (v lvdl ). the trip voltage is selected by the lvdsc1[lvdv] bits. the lvd system is always enabled in normal run, wait, and stop modes. the lvd system is disabled in vlpx, llsx, and vllsx modes. refer to power management controller (pmc) chapter for more details. chapter 6 reset and boot k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 195 the lvd can be configured to generate a reset upon detection of a low voltage condition by setting lvdsc1[lvdre]. after an lvd reset has occurred, the lvd system holds the mcu in reset until the supply voltage rises above the low voltage detection threshold. the srsl[lvd] bit is set following an lvd reset or por. 6.2.2.3 computer operating properly (cop) watchdog reset the watchdog timer monitors the operation of the system by expecting periodic communication from the software, generally known as servicing (or refreshing) the watchdog. if this periodic refreshing does not occur, the watchdog issues a system reset. the cop reset causes the srsl[cop] bit to set. 6.2.2.4 low leakage wakeup (llwu) reset the llwu allows up to 16 external pins, the reset pin, and up to seven internal peripherals to wake the mcu from lls and vllsx power modes. the llwu module is only functional in lls and vllsx power modes. in both these modes, lls mode exits via reset pin and any vlls mode exits via a wakeup or reset event, the srsl[wakeup] bit in mode controller module is set indicating the low leakage mode was active prior to the last system reset flow. using the reset pin to trigger an exit from lls or vlls results in the srsl[pin] bit being set as well. refer to the mode controller chapter for more details. after a system reset, the llwu retains the flags to indicate the source of the last wakeup until the user clears them. note pin wakeup and error condition flags are cleared in the llwu and module wakeup flags are required to be cleared in the peripheral module. refer to the individual peripheral specifications for more information. 6.2.2.5 multipurpose clock generator loss-of-clock (loc) reset the mcg includes a clock monitor. the clock monitor resets the device when the following conditions are met: ? the clock monitor is enabled (mcg_c6[cme] = 1) ? the mcg's external reference clock falls outside of the expected frequency range, depending on the mcg_c2[range] bit reset k60 sub-family reference manual, rev. 6, nov 2011 196 freescale semiconductor, inc. the mc_srsl[loc] bit is set to indicate the error. 6.2.2.6 software reset (sw) the sysresetreq bit in the nvic application interrupt and reset control register can be set to force a software reset on the device. (see arm's nvic documentation for the full description of the register fields, especially the vectkey field requirements.) setting sysresetreq generates a software reset request. this reset forces a system reset of all major components except for the debug module. a software reset causes srsh[sw] bit to set. 6.2.2.7 lockup reset (lockup) the lockup gives immediate indication of seriously errant kernel software. this is the result of the core being locked because of an unrecoverable exception following the activation of the processors built in system state protection hardware. the lockup condition causes a system reset and also causes srsh[lockup] bit to set. 6.2.2.8 ezport reset the ezport supports a system reset request via ezport signalling. the ezport generates a system reset request following execution of a reset chip (reset) command via the ezport interface. this method of reset allows the chip to boot from flash memory after it has been programmed by an external source. the ezport is enabled or disabled by the ezp_cs pin. 6.2.2.9 mdm-ap system reset request set the system reset request bit in the mdm-ap control register to initiate a system reset. this is the primary method for resets via the jtag interface. the system reset is held until this bit is cleared. set the core hold reset bit in the mdm-ap control register to hold the core in reset as the rest of the chip comes out of system reset. chapter 6 reset and boot k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 197 6.2.3 debug resets the following sections detail the debug resets available on the device. 6.2.3.1 jtag reset the jtag module generate a system reset when certain ir codes are selected. this functional reset is asserted when ezport, extest, highz and clamp instructions are active. the reset source from the jtag module is released when any other ir code is selected. a jtag reset causes the srsh[jtag] bit to set. 6.2.3.2 ntrst reset the ntrst pin causes a reset of the jtag logic when asserted. asserting the ntrst pin allows the debugger to gain control of the tap controller state machine (after exiting lls or vllsx) without resetting the state of the debug modules. the ntrst pin does not cause a system reset. 6.2.3.3 resetting the debug subsystem use the cdbgrstreq bit within the swj-dp ctrl/stat register to reset the debug modules. however, as explained below, using the cdbgrstreq bit does not reset all debug-related registers. cdbgrstreq resets the debug-related registers within the following modules: ? swj-dp ? ahb-ap ? etm ? atb replicators ? atb upsizers ? atb funnels ? etb ? tpiu ? mdm-ap (mdm control and status registers) ? mcm (etb almost full logic) cdbgrstreq does not reset the debug-related registers within the following modules: ? cm4 core (core debug registers: dhcsr, dcrsr, dcrdr, demcr) ? fpb reset k60 sub-family reference manual, rev. 6, nov 2011 198 freescale semiconductor, inc. ? dwt ? itm ? nvic ? crossbar bus switch 1 ? ahb-ap 1 ? private peripheral bus 1 6.3 boot this section describes the boot sequence, including sources and options. 6.3.1 boot sources this device only supports booting from internal flash. any secondary boot must go through an initialization sequence in flash. 6.3.2 boot options the device's functional mode is controlled by the state of the ezport chip select ( ezp_cs) pin during reset. the device can be in single chip (default) or serial flash programming mode (ezport). while in single chip mode the device can be in run or various low power modes mentioned in power mode transitions . table 6-2. mode select decoding ezport chip select ( ezp_cs) description 0 serial flash programming mode (ezport) 1 single chip (default) 6.3.3 fopt boot options the flash option register (fopt) in flash memory module (ftfl) allows the user to customize the operation of the mcu at boot time. the register contains read-only bits that are loaded from the nvm's option byte in the flash configuration field. the user can 1. cdbgrstreq does not affect ahb resources so that debug resources on the private peripheral bus are available during system reset. chapter 6 reset and boot k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 199 reprogram the option byte in flash to change the fopt values that are used for subsequent resets. for more details on programming the option byte, refer to the flash memory chapter. the mcu uses the ftfl_fopt register bits to configure the device at reset as shown in the following table. table 6-3. flash option register (ftfl_fopt) bit definitions bit num field value definition 7-2 reserved reserved for future expansion. 1 ezport_dis 0 ezport operation is disabled. the device always boots to normal cpu execution and the state of ezp_cs signal during reset is ignored. this option avoids inadvertent resets into ezport mode if the ezp_cs/nmi pin is used for its nmi function. 1 ezport operation is enabled. the state of ezp_cs pin during reset determines if device enters ezport mode. 0 lpboot 0 low-power boot: outdivx values in sim_clkdiv1 register are auto-configured at reset exit for higher divide values that produce lower power consumption at reset exit. core and system clock divider (outdiv1) and bus clock divider (outdiv2) are 0x7 (divide by 8) flash clock divider (outdiv4) and flexbus clock divider (outdiv3) are 0xf (divide by 16) 1 normal boot: outdivx values in sim_clkdiv1 register are auto-configured at reset exit for higher frequency values that produce faster operating frequencies at reset exit. core and system clock divider (outdiv1) and bus clock divider (outdiv2) are 0x0 (divide by 1) flash clock divider (outdiv4) and flexbus clock divider (outdiv3) are 0x1 (divide by 2) 6.3.4 boot sequence at power up, the on-chip regulator holds the system in a por state until the input supply is above the por threshold. the system continues to be held in this static state until the internally regulated supplies have reached a safe operating voltage as determined by the lvd. the mode controller reset logic then controls a sequence to exit reset. 1. a system reset is held on internal logic, the reset pin is driven out low, and the mcg is enabled in its default clocking mode. 2. required clocks are enabled (core clock, system clock, flash clock, and any bus clocks that do not have clock gate control). 3. the system reset on internal logic continues to be held, but the flash controller is released from reset and begins initialization operation while the mode control logic continues to drive the reset pin out low for a count of ~128 bus clock cycles. boot k60 sub-family reference manual, rev. 6, nov 2011 200 freescale semiconductor, inc. 4. the reset pin is released, but the system reset of internal logic continues to be held until the flash controller finishes initialization. ezport mode is selected instead of the normal cpu execution if ezp_cs is low when the internal reset is deasserted. ezport mode can be disabled by programming ftfl_fopt[ezport_dis]. note: if recovering from vlls1, 2, or 3 with the llwu_p3 wakeup pin (pta4/ ftm0_ch1/ nmi/ ezp_cs), use rising-edge wakeup in the llwu or disable ezport mode to ensure normal recovery. 5. when flash initialization completes, the reset pin is observed. if reset continues to be asserted (an indication of a slow rise time on the reset pin or external drive in low), the system continues to be held in reset. once the reset pin is detected high, the system is released from reset. 6. at release of system reset, clocking is switched to a slow clock if ftfl_fopt[lpboot] is configured for low power boot 7. when the system exits reset, the processor sets up the stack, program counter (pc), and link register (lr). the processor reads the start sp (sp_main) from vector-table offset 0. the core reads the start pc from vector-table offset 4. lr is set to 0xffff_ffff. the cpu begins execution at the pc location. ezport mode is entered instead of the normal cpu execution if ezport mode was latched during the sequence. 8. if flexnvm is enabled, the flash controller continues to restore the flexnvm data. this data is not available immediately out of reset and the system should not access this data until the flash controller completes this initialization step as indicated by the eeerdy flag. subsequent system resets follow this reset flow beginning with the step where system clocks are enabled. chapter 6 reset and boot k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 201 boot k60 sub-family reference manual, rev. 6, nov 2011 202 freescale semiconductor, inc. chapter 7 power management 7.1 introduction this chapter describes the various chip power modes and functionality of the individual modules in these modes. 7.2 power modes the power management controller (pmc) provides multiple power options to allow the user to optimize power consumption for the level of functionality needed. depending on the stop requirements of the user application, a variety of stop modes are available that provide state retention, partial power down or full power down of certain logic and/or memory. i/o states are held in all modes of operation. the following table compares the various power modes available. for each run mode there is a corresponding wait and stop mode. wait modes are similar to arm sleep modes. stop modes (vlps, stop) are similar to arm sleep deep mode. the very low power run (vlpr) operating mode can drastically reduce runtime power when the maximum bus frequency is not required to handle the application needs. the three primary modes of operation are run, wait and stop. the wfi instruction invokes both wait and stop modes for the chip. the primary modes are augmented in a number of ways to provide lower power based on application needs. table 7-1. chip power modes chip mode description core mode normal recovery method normal run allows maximum performance of chip. default mode out of reset; on- chip voltage regulator is on. run - table continues on the next page... 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 20 table 7-1. chip power modes (continued) chip mode description core mode normal recovery method normal wait - via wfi allows peripherals to function while the core is in sleep mode, reducing power. nvic remains sensitive to interrupts; peripherals continue to be clocked. sleep interrupt normal stop - via wfi places chip in static state. lowest power mode that retains all registers while maintaining lvd protection. nvic is disabled; awic is used to wake up from interrupt; peripheral clocks are stopped. sleep deep interrupt vlpr (very low power run) on-chip voltage regulator is in a low power mode that supplies only enough power to run the chip at a reduced frequency. reduced frequency flash access mode (1 mhz); lvd off; internal oscillator provides a low power 2 mhz source for the core, the bus and the peripheral clocks. run interrupt vlpw (very low power wait) -via wfi same as vlpr but with the core in sleep mode to further reduce power; nvic remains sensitive to interrupts (fclk = on). on-chip voltage regulator is in a low power mode that supplies only enough power to run the chip at a reduced frequency. sleep interrupt vlps (very low power stop)-via wfi places chip in static state with lvd operation off. lowest power mode with adc and pin interrupts functional. peripheral clocks are stopped, but lptimer, rtc, cmp, tsi, dac can be used. nvic is disabled (fclk = off); awic is used to wake up from interrupt. on-chip voltage regulator is in a low power mode that supplies only enough power to run the chip at a reduced frequency. all sram is operating (content retained and i/o states held). sleep deep interrupt lls (low leakage stop) state retention power mode. most peripherals are in state retention mode (with clocks stopped), but llwu, lptimer, rtc, cmp, tsi, dac can be used. nvic is disabled; llwu is used to wake up. note: the llwu interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit stop mode on an lls recovery. all sram is operating (content retained and i/o states held). sleep deep wakeup interrupt 1 vlls3 (very low leakage stop3) most peripherals are disabled (with clocks stopped), but llwu, lptimer, rtc, cmp, tsi, dac can be used. nvic is disabled; llwu is used to wake up. sram_u and sram_l remain powered on (content retained and i/o states held). sleep deep wakeup reset 2 vlls2 (very low leakage stop2) most peripherals are disabled (with clocks stopped), but llwu, lptimer, rtc, cmp, tsi, dac can be used. nvic is disabled; llwu is used to wake up. sram_l is powered off. a portion of sram_u remains powered on (content retained and i/o states held). sleep deep wakeup reset 2 vlls1 (very low leakage stop1) most peripherals are disabled (with clocks stopped), but llwu, lptimer, rtc, cmp, tsi, dac can be used. nvic is disabled; llwu is used to wake up. all of sram_u and sram_l are powered off. the 32-byte system register file and the 32-byte vbat register file remain powered for customer-critical data. sleep deep wakeup reset 2 table continues on the next page... power modes 60 sub-family reference manual, rev. 6, nov 2011 204 freescale semiconductor, inc. table 7-1. chip power modes (continued) chip mode description core mode normal recovery method bat (backup battery only) the chip is powered down except for the vbat supply. the rtc and the 32-byte vbat register file for customer-critical data remain powered. off power-up sequence 1. resumes normal run mode operation by executing the llwu interrupt service routine. 2. follows the reset flow with the llwu interrupt flag set for the nvic. 7.3 entering and exiting power modes the wfi instruction invokes wait and stop modes for the chip. the processor exits the low-power mode via an interrupt. the nested vectored interrupt controller (nvic) describes interrupt operation and what peripherals can cause interrupts. note the wfe instruction can have the side effect of entering a low- power mode, but that is not its intended usage. see arm documentation for more on the wfe instruction. recovery from vllsx is through the wake-up reset event. the chip wake-ups from vllsx by means of reset, an enabled pin or enabled module. see the table "llwu inputs" in the llwu configuration section for a list of the sources. the wake-up flow from vllsx is through reset. the wakeup bit in the srs registers in the mode controller is set indicating that the chip is recovering from a low power mode. code execution begins; however, the i/o pins are held in their pre low power mode entry states, and the system oscillator and mcg registers are reset (even if erefsten had been set before entering vllsx). software must clear this hold by writing a 1 to the ackiso bit in the control and status register in the llwu module. note to avoid unwanted transitions on the pins, software must re- initialize the i/o pins to their pre-low-power mode entry states before releasing the hold. if the oscillator was configured to continue running during vllsx modes, it must be re- configured before the ackiso bit is cleared. the oscillator configuration within the mcg is cleared after vllsx recovery and the oscillator will stop when ackiso is cleared unless the register is re-configured. chapter 7 power management k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 205 7.4 power mode transitions the following figure shows the power mode transitions. any reset always brings the chip back to the normal run state. in run, wait, and stop modes active power regulation is enabled. the vlpx modes are limited in frequency, but offer a lower power operating mode than normal modes. the lls and vllsx modes are the lowest power stop modes based on amount of logic or memory that is required to be retained by the application. wait stop run lls vlls 3, 2, 1 vlps vlpr vlpw any reset 4 6 7 3 1 2 8 10 11 9 5 figure 7-1. power mode state transition diagram power mode transitions k60 sub-family reference manual, rev. 6, nov 2011 206 freescale semiconductor, inc. 7.5 power modes shutdown sequencing when entering stop or other low-power modes, the clocks are shut off in an orderly sequence to safely place the chip in the targeted low-power state. all low-power entry sequences are initiated by the core executing an wfi instruction. the arm core's outputs, sleepdeep and sleeping, trigger entry to the various low-power modes: ? system level wait and vlpw modes equate to: sleeping & sleepdeep ? all other low power modes equate to: sleeping & sleepdeep when entering the non-wait modes, the chip performs the following sequence: ? shuts off core clock and system clock to the arm cortex-m4 core immediately. ? polls stop acknowledge indications from the non-core crossbar masters (dma, ethernet), supporting peripherals (spi, pit, rng) and the flash controller for indications that system clocks, bus clock and/or flash clock need to be left enabled to complete a previously initiated operation, effectively stalling entry to the targeted low power mode. when all acknowledges are detected, system clock, bus clock and flash clock are turned off at the same time. ? mcg and mode controller shut off clock sources and/or the internal supplies driven from the on-chip regulator as defined for the targeted low power mode. in wait modes, most of the system clocks are not affected by the low power mode entry. the core clock to the arm cortex-m4 core is shut off. some modules support stop-in- wait functionality and have their clocks disabled under these configurations. the debugger modules support a transition from stop, wait, vlps, and vlpw back to a halted state when the debugger is enabled. this transition is initiated by setting the debug request bit in mdm-ap control register. as part of this transition, system clocking is re- established and is equivalent to normal run/vlpr mode clocking configuration. 7.6 module operation in low power modes the following table illustrates the functionality of each module while the chip is in each of the low power modes. (debug modules are discussed separately; see debug in low power modes .) number ratings (such as 2 mhz and 1 mbps) represent the maximum frequencies or maximum data rates per mode. also, these terms are used: ? ff = full functionality. in vlpr and vlpw the system frequency is limited, but if a module does not have a limitation in its functionality, it is still listed as ff. ? static = module register states and associated memories are retained. chapter 7 power management k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 207 ? powered = memory is powered to retain contents. ? low power = flash has a low power state that retains configuration registers to support faster wakeup. ? off = modules are powered off; module is in reset state upon wakeup. ? wakeup = modules can serve as a wakeup source for the chip. table 7-2. module operation in low power modes modules stop vlpr vlpw vlps lls vllsx core modules nvic static ff ff static static off system modules mode controller ff ff ff ff ff ff llwu 1 static static static static ff ff regulator on low power low power low power low power low power lvd on disabled disabled disabled disabled disabled brown-out detection on on on on on on dma static ff ff static static off watchdog ff ff ff ff static off ewm static ff static static static off clocks 1khz lpo on on on on on on system oscillator (osc) oscerclk optional oscerclk max of 4mhz crystal oscerclk max of 4mhz crystal oscerclk max of 4mhz crystal limited to low range/low power limited to low range/low power mcg static - mcgirclk optional; pll optionally on but gated 2 mhz irc 2 mhz irc static - no clock output static - no clock output off core clock off 2 mhz max off off off off system clock off 2 mhz max 2 mhz max off off off bus clock off 2 mhz max 2 mhz max off off off memory and memory interfaces flash powered 1 mhz max access - no pgm low power low power off off portion of sram_u 2 low power low power low power low power low power low power in vlls3,2 remaining sram_u and all of sram_l low power low power low power low power low power low power in vlls3 table continues on the next page... module peration in ow power modes 60 sub-family reference manual, rev. 6, nov 2011 208 freescale semiconductor, inc. table 7-2. module operation in low power modes (continued) modules stop vlpr vlpw vlps lls vllsx flexmemory 3 low power low power 4 low power low power low power low power in vlls3, off in vlls2 and vlls1 register files 5 powered powered powered powered powered powered flexbus static ff ff static static off ezport disabled disabled disabled disabled disabled disabled communication interfaces usb fs/ls static static static static static off usb dcd static ff ff static static off usb voltage regulator optional optional optional optional optional optional ethernet wakeup static static static static off uart static, wakeup on edge 125 kbps 125 kbps static, wakeup on edge static off spi static 1 mbps 1 mbps static static off i 2 c static, address match wakeup 100 kbps 100 kbps static, address match wakeup static off can wakeup 256 kbps 256 kbps wakeup static off i 2 s ff with external clock 6 ff ff ff with external clock 6 static off sdhc wakeup ff ff wakeup static off security crc static ff ff static static off rng static ff static static static off timers ftm static ff ff static static off pit static ff ff static static off pdb static ff ff static static off lptmr ff ff ff ff ff ff rtc - 32khz osc 5 ff ff ff ff ff ff cmt static ff ff static static off analog 16-bit adc adc internal clock only ff ff adc internal clock only static off cmp 7 hs or ls compare ff ff hs or ls compare ls compare ls compare 6-bit dac static ff ff static static static table continues on the next page... chapter 7 power management 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 20 table 7-2. module operation in low power modes (continued) modules stop vlpr vlpw vlps lls vllsx vref ff ff ff ff static off 12-bit dac static ff ff static static static human-machine interfaces gpio wakeup ff ff wakeup static, pins latched off, pins latched tsi wakeup ff ff wakeup wakeup 8 wakeup 8 1. using the llwu module, the external pins available for this chip do not require the associated peripheral function to be enabled. it only requires the function controlling the pin (gpio or peripheral) to be configured as an input to allow a transition to occur to the llwu. 2. a 4kb portion of sram_u block is left powered on in low power mode vlls2. 3. flexram is always powered in vlls3. when the flexram is configured for traditional ram, optionally powered in vlls2 mode. when the flexram is configured for eeprom, off in vlls2 mode. 4. flexram enabled as eeprom is not writable in vlpr and writes are ignored. read accesses to flexram as eeprom while in vlpr are allowed. there are no access restrictions for flexram configured as traditional ram. 5. these components remain powered in bat power mode. 6. use an externally generated bit clock or an externally generated audio master clock (including extal). 7. cmp in stop or vlps supports high speed or low speed external pin to pin or external pin to dac compares. cmp in lls or vllsx only supports low speed external pin to pin or external pin to dac compares. windowed, sampled & filtered modes of operation are not available while in stop, vlps, lls, or vllsx modes. 8. tsi wakeup from lls and vllsx modes is limited to a single selectable pin. 7.7 clock gating to conserve power, the clocks to most modules can be turned off using the scgcx registers in the sim module. these bits are cleared after any reset, which disables the clock to the corresponding module. prior to initializing a module, set the corresponding bit in the scgcx register to enable the clock. before turning off the clock, make sure to disable the module. for more details, refer to the clock distribution and sim chapters. clock gating k60 sub-family reference manual, rev. 6, nov 2011 210 freescale semiconductor, inc. chapter 8 security 8.1 introduction this device implements security based on the mode selected from the flash module. the following sections provide an overview of flash security and details the effects of security on non-flash modules. 8.2 flash security the flash module provides security information to the mcu based on the state held by the fsec[sec] bits. the mcu, in turn, confirms the security request and limits access to flash resources. during reset, the flash module initializes the fsec register using data read from the security byte of the flash configuration field. note the security features apply only to external accesses: debug and ezport. cpu accesses to the flash are not affected by the status of fsec. in the unsecured state all flash commands are available to the programming interfaces (jtag and ezport), as well as user code execution of flash controller commands. when the flash is secured (fsec[sec] = 00, 01, or 11), programmer interfaces are only allowed to launch mass erase operations and have no access to memory locations. further information regarding the flash security options and enabling/disabling flash security is available in the flash memory module . k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 211 8.3 security interactions with other modules the flash security settings are used by the soc to determine what resources are available. the following sections describe the interactions between modules and the flash security settings or the impact that the flash security has on non-flash modules. 8.3.1 security interactions with flexbus when flash security is enabled, sim_sopt2[fbsl] enables/disables off-chip accesses through the flexbus interface. the fbsl bitfield also has an option to allow opcode and operand accesses or only operand accesses. 8.3.2 security interactions with ezport when flash security is active the mcu can still boot in ezport mode. the ezport holds the flash logic in nvm special mode and thus limits flash operation when flash security is active. while in ezport mode and security is active, flash bulk erase (be) can still be executed. the write fccob registers (wrfccob) command is limited to the mass erase (erase all blocks) and verify all 1s (read 1s all blocks) commands. read accesses to internal memories via the ezport are blocked when security is enabled. the mass erase can be used to disable flash security, but all of the flash contents are lost in the process. a mass erase via the ezport is allowed even when some memory locations are protected. when mass erase has been disabled, mass erase via the ezport is blocked and cannot be defeated. 8.3.3 security interactions with debug when flash security is active the jtag port cannot access the memory resources of the mcu. boundary scan chain operations work, but debugging capabilities are disabled so that the debug port cannot read flash contents. although most debug functions are disabled, the debugger can write to the flash mass erase in progress bit in the mdm-ap control register to trigger a mass erase (erase all blocks) command. a mass erase via the debugger is allowed even when some memory locations are protected. security interactions with other modules k60 sub-family reference manual, rev. 6, nov 2011 212 freescale semiconductor, inc. when mass erase is disabled, mass erase via the debugger is blocked. chapter 8 security k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 213 security interactions with other modules k60 sub-family reference manual, rev. 6, nov 2011 214 freescale semiconductor, inc. chapter 9 debug 9.1 introduction this device's debug is based on the arm coresight architecture and is configured in each device to provide the maximum flexibility as allowed by the restrictions of the pinout and other available resources. four debug interfaces are supported: ? ieee 1149.1 jtag ? ieee 1149.7 jtag (cjtag) ? serial wire debug (swd) ? arm real-time trace interface the basic cortex-m4 debug architecture is very flexible. the following diagram shows the topology of the core debug architecture and its components. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 215 private peripheral bus (internal) trigger itm tpiu core fpb ahb-ap nvic swj-dp bus matrix apb i/f trace port (serial wire or multi-pin) cortex-m4 sw/ jtag debug sleep interrupts intnmi sleeping sleepdeep intisr[239:0] awic dwt rom table etb etm instr. data mcm mmcau i-code bus d-code bus system bus code bus mdm-ap figure 9-1. cortex-m4 debug topology the following table presents a brief description of each one of the debug components. table 9-1. debug components description module description swj-dp+ cjtag modified debug port with support for swd, jtag, cjtag ahb-ap ahb master interface from jtag to debug module and soc system memory maps jtag-ap bridge to dft/bist resources. rom table identifies which debug ip is available. core debug singlestep, register access, run, core status coresight trace funnel (not shown in figure) the cstf combines multiple trace streams onto a single atb bus. coresight trace replicator (not shown in figure) the atb replicator enables two trace sinks to be wired together and operate from the same incoming trace stream. etm (embedded trace macrocell) etmv3.5 architecture coresight etb (embedded trace buffer) memory mapped buffer used to store trace data. itm s/w instrumentation messaging + simple data trace messaging + watchpoint messaging table continues on the next page... introduction 60 sub-family reference manual, rev. 6, nov 2011 216 freescale semiconductor, inc. table 9-1. debug components description (continued) module description dwt (data and address watchpoints) 4 data and address watchpoints (configurable for less, but 4 seems to be accepted) fpb (flash patch and breakpoints) the fpb implements hardware breakpoints and patches code and data from code space to system space. the fpb unit contains two literal comparators for matching against literal loads from code space, and remapping to a corresponding area in system space. the fbp also contains six instruction comparators for matching against instruction fetches from code space, and remapping to a corresponding area in system space. alternatively, the six instruction comparators can individually configure the comparators to return a breakpoint instruction (bkpt) to the processor core on a match, so providing hardware breakpoint capability. tpiu (trace port inteface unit) synchronous mode (5-pin) = trace_d[3:0] + trace_clkout synchronous mode (3-pin) = trace_d[1:0] + trace_clkout asynchronous mode (1-pin) = trace_swo (available on jtag_tdo) mcm (miscellaneous control module) the mcm provides miscellaneous control functions including control of the etb and trace path switching. 9.1.1 references for more information on arm debug components, see these documents: ? armv7-m architecture reference manual ? arm debug interface v5.1 ? arm coresight architecture specification ? arm etm architecture specification v3.5 9.2 the debug port the configuration of the cjtag module, jtag controller, and debug port is illustrated in the following figure: chapter 9 debug k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 217 cjtag dap bus tdo traceswo tdo tdi tck tdi nsys_trst nsys_tdo nsys_tdi nsys_tck nsys_tms ntrst tck tms_out tms_in tms_out_oe tms tdo tdi swclktck swditms swdo swdoen swd/ jtag select swclktck swditms jtagsel swdsel 4b1111 or 4b0000 tdi tdo pen jtagnsw jtagc tdo tdi ntrst tck tms jtag_updateinstr[3:0] 4b1111 or 4b1110 jtagir[3:0] ir==bypass or idcode ir==bypass or idcode a a (1b0 = 2-pin cjtag) (1b1 = 4-pin jtag) to test resources 1b1 mdm-ap ahb-ap figure 9-2. modified debug port the debug port comes out of reset in standard jtag mode and is switched into either cjtag or swd mode by the following sequences. once the mode has been changed, unused debug pins can be reassigned to any of their alternative muxed functions. 9.2.1 jtag-to-swd change sequence 1. send more than 50 tck cycles with tms (swdio) =1 2. send the 16-bit sequence on tms (swdio) = 0111_1001_1110_0111 (msb transmitted first) 3. send more than 50 tck cycles with tms (swdio) =1 note see the arm documentation for the coresight dap lite for restrictions. 9.2.2 jtag-to-cjtag change sequence 1. reset the debug port the debug port k60 sub-family reference manual, rev. 6, nov 2011 218 freescale semiconductor, inc. 2. set the control level to 2 via zero-bit scans 3. execute the store format (stfmt) command (00011) to set the scan format register to 1149.7 scan format 9.3 debug port pin descriptions the debug port pins default after por to their jtag functionality with the exception of jtag_trst_b and can be later reassigned to their alternate functionalities. in cjtag and swd modes jtag_tdi and jtag_trst_b can be configured to alternate gpio functions. table 9-2. debug port pins pin name jtag debug port cjtag debug port swd debug port internal pull- updown type description type description type description jtag_tms/ swd_dio i/o jtag test mode selection i/o cjtag data i/o serial wire data pull-up jtag_tclk/ swd_clk i jtag test clock i cjtag clock i serial wire clock pull-down jtag_tdi i jtag test data input - - - - pull-up jtag_tdo/ trace_sw o o jtag test data output o trace output over a single pin o trace output over a single pin n/c jtag_trst _b i jtag reset i cjtag reset - - pull-up 9.4 system tap connection the system jtag controller is connected in parallel to the arm tap controller. the system jtag controller ir codes overlay the arm jtag controller ir codes without conflict. refer to the ir codes table for a list of the available ir codes. the output of the taps (tdo) are muxed based on the ir code which is selected. this design is fully jtag compliant and appears to the jtag chain as a single tap. at power on reset, arm's idcode (ir=4'b1110) is selected. chapter 9 debug k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 219 9.4.1 ir codes table 9-3. jtag instructions instruction code[3:0] instruction summary idcode 0000 selects device identification register for shift sample/preload 0010 selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation sample 0011 selects boundary scan register for shifting and sampling without disturbing functional operation extest 0100 selects boundary scan register while applying preloaded values to output pins and asserting functional reset highz 1001 selects bypass register while three-stating all output pins and asserting functional reset clamp 1100 selects bypass register while applying preloaded values to output pins and asserting functional reset ezport 1101 enables the ezport function for the soc and asserts functional reset. arm_idcode 1110 arm jtag-dp instruction bypass 1111 selects bypass register for data operations factory debug reserved 0101, 0110, 0111 intended for factory debug only arm jtag-dp reserved 1000, 1010, 1011, 1110 these instructions will go the arm jtag-dp controller. please look at arm jtag-dp documentation for more information on these instructions. reserved 1 all other opcodes decoded to select bypass register 1. the manufacturer reserves the right to change the decoding of reserved instruction codes in the future 9.5 jtag status and control registers through the arm debug access port (dap), the debugger has access to the status and control elements, implemented as registers on the dap bus as shown in the following figure. these registers provide additional control and status for low power mode recovery and typical run-control scenarios. the status register bits also provide a means for the debugger to get updated status of the core without having to initiate a bus transaction across the crossbar switch, thus remaining less intrusive during a debug session. jtag status and control registers k60 sub-family reference manual, rev. 6, nov 2011 220 freescale semiconductor, inc. it is important to note that these dap control and status registers are not memory mapped within the system memory map and are only accessible via the debug access port (dap) using jtag, cjtag, or swd. the mdm-ap is accessible as debug access port 1 with the available registers shown in the table below. table 9-4. mdm-ap register summary address register description 0x0100_0000 status see mdm-ap status register 0x0100_0004 control see mdm-ap control register 0x0100_00fc id read-only identification register that always reads as 0x001c_0000 swj-dp select[31:24] (apsel) selects the ap select[7:4] (apbanksel) selects the bank a[3:2] from the apacc selects the register within the bank ahb access port (ahb - ap) mdm - ap status 0x00 control 0x01 idr 0x3f ahb-ap select[31:24] = 0x00 selects the ahb-ap see arm documentation for further details mdm-ap select[31:24] = 0x01 selects the mdm-ap select[7:4] = 0x0 selects the bank with status and ctrl a[3:2] = 2b00 selects the status register a[3:2] = 2b01 selects the control register select[7:4] = 0xf selects the bank with idr a[3:2] = 2b11 selects the idr register (idr register reads 0x001c_0000) bus matrix see control and status register descriptions debug port internal bus access port data[31:0] a[7:4] a[3:2] rnw apsel decode debug port id register (dpidr) control/status (ctrl/stat) ap select (select) read buffer (rebuff) dp registers 0x00 0x04 0x08 0x0c data[31:0] a[3:2] rnw dpacc data[31:0] a[3:2] rnw apacc debug port (dp) generic see the arm debug interface v5p1 supplement. figure 9-3. mdm ap addressing chapter 9 debug k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 221 9.5.1 mdm-ap control register table 9-5. mdm-ap control register assignments bit name secure 1 description 0 flash mass erase in progress y set to cause mass erase. cleared by hardware after mass erase operation completes. when mass erase is disabled (via meen and sec settings), the erase request does not occur and the flash mass erase in progress bit continues to assert until the next system reset. 1 debug disable n set to disable debug. clear to allow debug operation. when set it overrides the c_debugen bit within the dhcsr and force disables debug logic. 2 debug request n set to force the core to halt. if the core is in a stop or wait mode, this bit can be used to wakeup the core and transition to a halted state. 3 system reset request n set to force a system reset. the system remains held in reset until this bit is cleared. 4 core hold reset n configuration bit to control core operation at the end of system reset sequencing. 0 normal operation - release the core from reset along with the rest of the system at the end of system reset sequencing. 1 suspend operation - hold the core in reset at the end of reset sequencing. once the system enters this suspended state, clearing this control bit immediately releases the core from reset and cpu operation begins. 5 vllsx debug request (vlldbgreq) n set to configure the system to be held in reset after the next recovery from a vllsx mode. this bit drives directly to the mode controller to control this feature. this bit holds the core in reset when vllsx modes are exited to allow the debugger time to re-initialize debug ip before the debug session continues. the mode controller captures this bit logic on entry to vllsx modes. upon exit from vllsx modes, the mode controller holds the core in reset at the end of system reset sequencing. the mode controller will hold the core in reset until vlldbgack is asserted. the vlldbgreq bit clears automatically due to the por reset generated as part of the vllsx recovery. 6 vllsx debug acknowledge (vlldbgack) n set to release a core being held in reset following a vllsx recovery this bit is used by the debugger to release the system reset when it is being held on vllsx mode exit. the debugger re-initializes all debug ip and then assert this control bit to allow the mode controller to release the core from reset and allow cpu operation to begin. the vlldbgack bit is cleared by the debugger or can be left set because it clears automatically due to the por reset generated as part of the next vllsx recovery. table continues on the next page... ta status and control registers 60 sub-family reference manual, rev. 6, nov 2011 222 freescale semiconductor, inc. table 9-5. mdm-ap control register assignments (continued) bit name secure 1 description 7 lls, vllsx status acknowledge n set this bit to acknowledge the dap lls and vlls status bits have been read. this acknowledge automatically clears the status bits. this bit is used by the debugger to clear the sticky lls and vllsx mode entry status bits. this bit is asserted and cleared by the debugger. 8 31 reserved for future use n 1. command available in secure mode 9.5.2 mdm-ap status register table 9-6. mdm-ap status register assignments bit name description 0 flash mass erase acknowledge the flash mass erase acknowledge bit is cleared after any system reset. the bit is also cleared at launch of a mass erase command due to write of flash mass erase in progress bit in mdm ap control register. the flash mass erase acknowledge is set after flash control logic has started the mass erase operation. when mass erase is disabled (via meen and sec settings), an erase request due to seting of flash mass erase in progress bit is not acknowledged. 1 flash ready indicate flash has been initialized and debugger can be configured even if system is continuing to be held in reset via the debugger. 2 system security indicates the security state. when secure, the debugger does not have access to the system bus or any memory mapped peripherals. this bit indicates when the part is locked and no system bus access is possible. 3 system reset indicates the system reset state. 0 system is in reset 1 system is not in reset 4 reserved 5 mass erase enable indicates if the mcu can be mass erased or not 0 mass erase is disabled 1 mass erase is enabled 6 backdoor access key enable indicates if the mcu has the backdoor access key enabled. 0 disabled 1 enabled table continues on the next page... chapter debug 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 22 table 9-6. mdm-ap status register assignments (continued) bit name description 7 lp enabled decode of lpllsm control bits to indicate that vlps, lls, or vllsx are the selected power mode the next time the arm core enters deep sleep. 0 low power stop mode is not enabled 1 low power stop mode is enabled usage intended for debug operation in which run to vlps is attempted. per debug definition, the system actually enters the stop state. a debugger should interpret deep sleep indication (with sleepdeep and sleeping asserted), in conjuntion with this bit asserted as the debugger- vlps status indication. 8 very low power mode indicates current power mode is vlpx. this bit is not sticky? and should always represent whether vlpx is enabled or not. this bit is used to throttle jtag tck frequency up/down. 9 lls mode exit this bit indicates an exit from lls mode has occurred. the debugger will lose communication while the system is in lls (including access to this register). once communication is reestablished, this bit indicates that the system had been in lls. since the debug modules held their state during lls, they do not need to be reconfigured. this bit is set during the lls recovery sequence. the lls mode exit bit is held until the debugger has had a chance to recognize that lls was exited and is cleared by a write of 1 to the lls, vllsx status acknowledge bit in mdm ap control register. 10 vllsx modes exit this bit indicates an exit from vllsx mode has occurred. the debugger will lose communication while the system is in vllsx (including access to this register). once communication is reestablished, this bit indicates that the system had been in vllsx. since the debug modules lose their state during vllsx modes, they need to be reconfigured. this bit is set during the vllsx recovery sequence. the vllsx mode exit bit is held until the debugger has had a chance to recognize that a vlls mode was exited and is cleared by a write of 1 to the lls, vllsx status acknowledge bit in mdm ap control register. 11 15 reserved for future use always read 0. 16 core halted indicates the core has entered debug halt mode 17 core sleepdeep indicates the core has entered a low power mode sleeping==1 and sleepdeep==0 indicates wait or vlpw mode. sleeping==1 and sleepdeep==1 indicates stop or vlps mode. 18 core sleeping 19 31 reserved for future use always read 0. 9.6 debug resets the debug system receives the following sources of reset: ? jtag_trst_b from an external signal. this signal is optional and may not be available in all packages. debug resets k60 sub-family reference manual, rev. 6, nov 2011 224 freescale semiconductor, inc. ? debug reset (cdbgrstreq bit within the swj-dp ctrl/stat register) in the tclk domain that allows the debugger to reset the debug logic. ? trst asserted via the cjtag escape command. ? system por reset conversely the debug system is capable of generating system reset using the following mechanism: ? a system reset in the dap control register which allows the debugger to hold the system in reset. ? sysresetreq bit in the nvic application interrupt and reset control register ? a system reset in the dap control register which allows the debugger to hold the core in reset. 9.7 ahb-ap ahb-ap provides the debugger access to all memory and registers in the system, including processor registers through the nvic. system access is independent of the processor status. ahb-ap does not do back-to-back transactions on the bus, so all transactions are non-sequential. ahb-ap can perform unaligned and bit-band transactions. ahb-ap transactions bypass the fpb, so the fpb cannot remap ahb-ap transactions. swj/sw-dp-initiated transaction aborts drive an ahb-ap-supported sideband signal called habort. this signal is driven into the bus matrix, which resets the bus matrix state, so that ahb-ap can access the private peripheral bus for last ditch debugging such as read/stop/reset the core. ahb-ap transactions are little endian. the mpu includes default settings and protections for the region descriptor 0 (rgd0) such that the debugger always has access to the entire address space and those rights cannot be changed by the core or any other bus master. for a short period at the start of a system reset event the system security status is being determined and debugger access to all ahb-ap transactions is blocked. the mdm-ap status register is accessible and can be monitored to determine when this initial period is completed. after this initial period, if system reset is held via assertion of the reset pin, the debugger has access via the bus matrix to the private peripheral bus to configure the debug ip even while system reset is asserted. while in system reset, access to other memory and register resources, accessed over the crossbar switch, is blocked. chapter 9 debug k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 225 9.8 itm the itm is an application-driven trace source that supports printf style debugging to trace operating system (os) and application events, and emits diagnostic system information. the itm emits trace information as packets. there are four sources that can generate packets. if multiple sources generate packets at the same time, the itm arbitrates the order in which packets are output. the four sources in decreasing order of priority are: 1. software trace -- software can write directly to itm stimulus registers. this emits packets. 2. hardware trace -- the dwt generates these packets, and the itm emits them. 3. time stamping -- timestamps are emitted relative to packets. the itm contains a 21-bit counter to generate the timestamp. the cortex-m4 clock or the bitclock rate of the serial wire viewer (swv) output clocks the counter. 4. global system timestamping. timestamps can optionally be generated using a system-wide 48-bit count value. the same count value can be used to insert timestamps in the etm trace stream, allowing coarse-grain correlation. 9.9 core trace connectivity 9.10 embedded trace macrocell v3.5 (etm) the cortex-m4 embedded trace macrocell (etm-m4) is a debug component that enables a debugger to reconstruct program execution. the coresight etm-m4 supports only instruction trace. you can use it either with the cortex-m4 trace port interface unit (m4-tpiu), or with the coresight etb. the main features of an etm are: ? tracing of 16-bit and 32-bit thumb instructions ? four embeddedice watchpoint inputs ? a trace start/stop block with embeddedice inputs ? one reduced function counter ? two external inputs ? a 24-byte fifo queue ? global timestamping itm k60 sub-family reference manual, rev. 6, nov 2011 226 freescale semiconductor, inc. 9.11 coresight embedded trace buffer (etb) the etb provides on-chip storage of trace data using 32-bit ram. the etb accepts trace data from any coresight-compliant component trace source with an atb master port, such as a trace source or a trace funnel. it is included in this device to remove dependencies from the trace pin pad speed, and enable low cost trace solutions. the traceram size is 2 kb. apb i/f atb slave port atb i/f traceram control trace ram interface trigin register bank formatter apb (from etm trigger out) figure 9-4. etb block diagram the etb contains the following blocks: ? formatter -- inserts source id signals into the data packet stream so that trace data can be re-associated with its trace source after the data is read back out of the etb. ? control -- control registers for trace capture and flushing. ? apb interface -- read, write, and data pointers provide access to etb registers. in addition, the apb interface supports wait states through the use of a preadydbg signal output by the etb. the apb interface is synchronous to the atb domain. ? register bank -- contains the management, control, and status registers for triggers, flushing behavior, and external control. ? trace ram interface -- controls reads and writes to the trace ram. 9.11.1 performance profiling with the etb to create a performance profile (e.g. gprof) for the target application, a means to collect trace over a long period of time is needed. the etb buffer is too small to capture a meaningful profile in just one take. what is needed is to collect and concatenate data from the etb buffer for multiple sequential runs. using the etb packet counter (described in miscellaneous control module (mcm) ), the trace analysis tool can capture chapter 9 debug k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 227 multiple sequential runs by executing code until the etb is almost full, and halting or executing an interrupt handler to allow the buffer to be emptied, and then continuing executing code. the target halts or executes an interrupt handler when the buffer is almost full to empty the data and then the debugger runs the target again. 9.11.2 etb counter control the etb packet counter is controlled by the etb counter control register, etb reload register, and etb counter value register implemented in the miscellaneous control module (mcm) accessible via the private peripheral bus. via the etb counter control register the etb control logic can be configured to cause an mcm alert interrupt, an nmi interrupt, or cause a debug halt when the down counter reaches 0. other features of the etb control logic include: ? down counter to count as many as 512 x 32-bit packets. ? reload request transfers reload value to counter. ? atb valid and ready signals used to form counter decrement. ? the counter disarms itself when the count reaches 0. 9.12 tpiu the tpiu acts as a bridge between the on-chip trace data from the embedded trace macrocell (etm) and the instrumentation trace macrocell (itm), with separate ids, to a data stream, encapsulating ids where required, that is then captured by a trace port analyzer (tpa). the tpiu is specially designed for low-cost debug. 9.13 dwt the dwt is a unit that performs the following debug functionality: ? it contains four comparators that you can configure as a hardware watchpoint, an etm trigger, a pc sampler event trigger, or a data address sampler event trigger. the first comparator, dwt_comp0, can also compare against the clock cycle counter, cyccnt. the second comparator, dwt_comp1, can also be used as a data comparator. ? the dwt contains counters for: ? clock cycles (cyccnt) ? folded instructions ? load store unit (lsu) operations tpiu k60 sub-family reference manual, rev. 6, nov 2011 228 freescale semiconductor, inc. ? sleep cycles ? cpi (all instruction cycles except for the first cycle) ? interrupt overhead note an event is emitted each time a counter overflows. ? the dwt can be configured to emit pc samples at defined intervals, and to emit interrupt event information. 9.14 debug in low power modes in low power modes in which the debug modules are kept static or powered off, the debugger cannot gather any debug data for the duration of the low power mode. in the case that the debugger is held static, the debug port returns to full functionality as soon as the low power mode exits and the system returns to a state with active debug. in the case that the debugger logic is powered off, the debugger is reset on recovery and must be reconfigured once the low power mode is exited. power mode entry logic monitors debug power up and system power up signals from the debug port as indications that a debugger is active. these signals can be changed in run, vlpr, wait and vlpw. if the debug signal is active and the system attempts to enter stop or vlps, fclk continues to run to support core register access and trace. in these modes in which fclk is left active the debug modules have access to core registers but not to system memory resources accessed via the crossbar. with debug enabled, transitions from run directly to vlps are not allowed and result in the system entering stop mode instead. status bits within the mdm-ap status register can be evaluated to determine this pseudo-vlps state. note with the debug enabled, transitions from run--> vlpr --> vlps are still possible but also result in the system entering stop mode instead. in vlls mode all debug modules are powered off and reset at wakeup. in lls mode, the debug modules retain their state but no debug activity is possible. note when using cjtag and entering lls mode, the cjtag controller must be reset on exit from lls mode. going into a vllsx mode causes all the debug controls and settings to be reset. to give time to the debugger to sync up with the hw, the mdm-ap control register can be configured hold the system in reset on recovery so that the debugger can regain control and reconfigure debug logic prior to the system exiting reset and resuming operation. chapter 9 debug k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 229 9.14.1 debug module state in low power modes the following table shows the state of the debug modules in low power modes. these terms are used: ? ff = full functionality. in vlpr and vlpw the system frequency is limited, but if a module does not have a limitation in its functionality, it is still listed as ff. ? static = module register states and associated memories are retained. ? off = modules are powered off; module is in reset state upon wakeup. table 9-7. debug module state in low power modes module stop vlpr vlpw vlps lls vllsx debug port ff ff ff off static off ahb-ap ff ff ff off static off itm ff ff ff off static off etm ff ff ff off static off etb ff ff ff off static off tpiu ff ff ff off static off dwt ff ff ff off static off 9.15 debug & security when security is enabled (fsec[sec] != 10), the debug port capabilities are limited in order to prevent exploitation of secure data. in the secure state the debugger still has access to the mdm-ap status register and can determine the current security state of the device. in the case of a secure device, the debugger also has the capability of performing a mass erase operation via writes to the mdm-ap control register. in the case of a secure device that has mass erase disabled (fsec[meen] = 10), attempts to mass erase via the debug interface are blocked. debug & security k60 sub-family reference manual, rev. 6, nov 2011 230 freescale semiconductor, inc. chapter 10 signal multiplexing and signal descriptions 10.1 introduction to optimize functionality in small packages, pins have several functions available via signal multiplexing. this chapter illustrates which of this device's signals are multiplexed on which external pin. the port control block controls which signal is present on the external pin. reference that chapter to find which register controls the operation of a specific pin. 10.2 signal multiplexing integration this section summarizes how the module is integrated into the device. for a comprehensive description of the module itself, see the modules dedicated chapter. register access signal multiplexing/ port control transfers module peripheral bus controller 1 module module external pins transfers figure 10-1. signal multiplexing integration table 10-1. reference links to related information topic related module reference full description port control port control system memory map system memory map table continues on the next page... 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 21 table 10-1. reference links to related information (continued) topic related module reference clocking clock distribution register access peripheral bus controller peripheral bridge 10.2.1 port control and interrupt module features ? five 32-pin ports note not all pins are available on the device. see the following section for details. ? each 32-pin port is assigned one interrupt. ? the digital filter option has two clock source options: bus clock and 1-khz lpo. the 1-khz lpo option gives users this feature in low power modes. ? the digital filter is configurable from 1 to 32 clock cycles when enabled. 10.2.2 clock gating the clock to the port control module can be gated on and off using the scgc5[portx] bits in the sim module. these bits are cleared after any reset, which disables the clock to the corresponding module to conserve power. prior to initializing the corresponding module, set scgc5[portx] in the sim module to enable the clock. before turning off the clock, make sure to disable the module. for more details, refer to the clock distribution chapter. 10.2.3 signal multiplexing constraints 1. a given peripheral function must be assigned to a maximum of one package pin. do not program the same function to more than one pin. 2. to ensure the best signal timing for a given peripheral's interface, choose the pins in closest proximity to each other. 10.3 pinout pinout k60 sub-family reference manual, rev. 6, nov 2011 232 freescale semiconductor, inc. 10.3.1 k60 signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. the port control module is responsible for selecting which alt functionality is available on each pin. 100 lqf p pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 1 pte0 adc1_se4a adc1_se4a pte0 spi1_pcs1 uart1_tx sdhc0_d1 i2c1_sda 2 pte1/ llwu_p0 adc1_se5a adc1_se5a pte1/ llwu_p0 spi1_sout uart1_rx sdhc0_d0 i2c1_scl 3 pte2/ llwu_p1 adc1_se6a adc1_se6a pte2/ llwu_p1 spi1_sck uart1_cts _b sdhc0_dcl k 4 pte3 adc1_se7a adc1_se7a pte3 spi1_sin uart1_rts _b sdhc0_cm d 5 pte4/ llwu_p2 disabled pte4/ llwu_p2 spi1_pcs0 uart3_tx sdhc0_d3 6 pte5 disabled pte5 spi1_pcs2 uart3_rx sdhc0_d2 7 pte6 disabled pte6 spi1_pcs3 uart3_cts _b i2s0_mclk i2s0_clkin 8 vdd vdd vdd 9 vss vss vss 10 usb0_dp usb0_dp usb0_dp 11 usb0_dm usb0_dm usb0_dm 12 vout33 vout33 vout33 13 vregin vregin vregin 14 adc0_dp1 adc0_dp1 adc0_dp1 15 adc0_dm1 adc0_dm1 adc0_dm1 16 adc1_dp1 adc1_dp1 adc1_dp1 17 adc1_dm1 adc1_dm1 adc1_dm1 18 pga0_dp/ adc0_dp0/ adc1_dp3 pga0_dp/ adc0_dp0/ adc1_dp3 pga0_dp/ adc0_dp0/ adc1_dp3 19 pga0_dm/ adc0_dm0/ adc1_dm3 pga0_dm/ adc0_dm0/ adc1_dm3 pga0_dm/ adc0_dm0/ adc1_dm3 20 pga1_dp/ adc1_dp0/ adc0_dp3 pga1_dp/ adc1_dp0/ adc0_dp3 pga1_dp/ adc1_dp0/ adc0_dp3 21 pga1_dm/ adc1_dm0/ adc0_dm3 pga1_dm/ adc1_dm0/ adc0_dm3 pga1_dm/ adc1_dm0/ adc0_dm3 22 vdda vdda vdda 23 vrefh vrefh vrefh 24 vrefl vrefl vrefl chapter 10 signal multiplexing and signal descriptions k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 233 100 lqf p pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 25 vssa vssa vssa 26 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 27 dac0_out/ cmp1_in3/ adc0_se23 dac0_out/ cmp1_in3/ adc0_se23 dac0_out/ cmp1_in3/ adc0_se23 28 xtal32 xtal32 xtal32 29 extal32 extal32 extal32 30 vbat vbat vbat 31 pte24 adc0_se17 adc0_se17 pte24 can1_tx uart4_tx ewm_out_ b 32 pte25 adc0_se18 adc0_se18 pte25 can1_rx uart4_rx ewm_in 33 pte26 disabled pte26 uart4_cts _b enet_1588 _clkin rtc_clko ut usb_clkin 34 pta0 jtag_tclk/ swd_clk/ ezp_clk tsi0_ch1 pta0 uart0_cts _b ftm0_ch5 jtag_tclk/ swd_clk ezp_clk 35 pta1 jtag_tdi/ ezp_di tsi0_ch2 pta1 uart0_rx ftm0_ch6 jtag_tdi ezp_di 36 pta2 jtag_tdo/ trace_sw o/ezp_do tsi0_ch3 pta2 uart0_tx ftm0_ch7 jtag_tdo/ trace_sw o ezp_do 37 pta3 jtag_tms/ swd_dio tsi0_ch4 pta3 uart0_rts _b ftm0_ch0 jtag_tms/ swd_dio 38 pta4/ llwu_p3 nmi_b/ ezp_cs_b tsi0_ch5 pta4/ llwu_p3 ftm0_ch1 nmi_b ezp_cs_b 39 pta5 disabled pta5 ftm0_ch2 rmii0_rxe r/ mii0_rxer cmp2_out i2s0_rx_bc lk jtag_trst 40 vdd vdd vdd 41 vss vss vss 42 pta12 cmp2_in0 cmp2_in0 pta12 can0_tx ftm1_ch0 rmii0_rxd1 /mii0_rxd1 i2s0_txd ftm1_qd_p ha 43 pta13/ llwu_p4 cmp2_in1 cmp2_in1 pta13/ llwu_p4 can0_rx ftm1_ch1 rmii0_rxd0 /mii0_rxd0 i2s0_tx_fs ftm1_qd_p hb 44 pta14 disabled pta14 spi0_pcs0 uart0_tx rmii0_crs_ dv/ mii0_rxdv i2s0_tx_bc lk 45 pta15 disabled pta15 spi0_sck uart0_rx rmii0_txen /mii0_txen i2s0_rxd 46 pta16 disabled pta16 spi0_sout uart0_cts _b rmii0_txd0 /mii0_txd0 i2s0_rx_fs 47 pta17 adc1_se17 adc1_se17 pta17 spi0_sin uart0_rts _b rmii0_txd1 /mii0_txd1 i2s0_mclk i2s0_clkin 48 vdd vdd vdd pinout k60 sub-family reference manual, rev. 6, nov 2011 234 freescale semiconductor, inc. 100 lqf p pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 49 vss vss vss 50 pta18 extal extal pta18 ftm0_flt2 ftm_clkin 0 51 pta19 xtal xtal pta19 ftm1_flt0 ftm_clkin 1 lpt0_alt1 52 reset_b reset_b reset_b 53 ptb0/ llwu_p5 /adc0_se8/ adc1_se8/ tsi0_ch0 /adc0_se8/ adc1_se8/ tsi0_ch0 ptb0/ llwu_p5 i2c0_scl ftm1_ch0 rmii0_mdio /mii0_mdio ftm1_qd_p ha 54 ptb1 /adc0_se9/ adc1_se9/ tsi0_ch6 /adc0_se9/ adc1_se9/ tsi0_ch6 ptb1 i2c0_sda ftm1_ch1 rmii0_mdc/ mii0_mdc ftm1_qd_p hb 55 ptb2 / adc0_se12/ tsi0_ch7 / adc0_se12/ tsi0_ch7 ptb2 i2c0_scl uart0_rts _b enet0_158 8_tmr0 ftm0_flt3 56 ptb3 / adc0_se13/ tsi0_ch8 / adc0_se13/ tsi0_ch8 ptb3 i2c0_sda uart0_cts _b enet0_158 8_tmr1 ftm0_flt0 57 ptb9 ptb9 spi1_pcs1 uart3_cts _b fb_ad20 58 ptb10 /adc1_se14 /adc1_se14 ptb10 spi1_pcs0 uart3_rx fb_ad19 ftm0_flt1 59 ptb11 /adc1_se15 /adc1_se15 ptb11 spi1_sck uart3_tx fb_ad18 ftm0_flt2 60 vss vss vss 61 vdd vdd vdd 62 ptb16 /tsi0_ch9 /tsi0_ch9 ptb16 spi1_sout uart0_rx fb_ad17 ewm_in 63 ptb17 /tsi0_ch10 /tsi0_ch10 ptb17 spi1_sin uart0_tx fb_ad16 ewm_out_ b 64 ptb18 /tsi0_ch11 /tsi0_ch11 ptb18 can0_tx ftm2_ch0 i2s0_tx_bc lk fb_ad15 ftm2_qd_p ha 65 ptb19 /tsi0_ch12 /tsi0_ch12 ptb19 can0_rx ftm2_ch1 i2s0_tx_fs fb_oe_b ftm2_qd_p hb 66 ptb20 ptb20 spi2_pcs0 fb_ad31 cmp0_out 67 ptb21 ptb21 spi2_sck fb_ad30 cmp1_out 68 ptb22 ptb22 spi2_sout fb_ad29 cmp2_out 69 ptb23 ptb23 spi2_sin spi0_pcs5 fb_ad28 70 ptc0 / adc0_se14/ tsi0_ch13 / adc0_se14/ tsi0_ch13 ptc0 spi0_pcs4 pdb0_extr g i2s0_txd fb_ad14 71 ptc1/ llwu_p6 / adc0_se15/ tsi0_ch14 / adc0_se15/ tsi0_ch14 ptc1/ llwu_p6 spi0_pcs3 uart1_rts _b ftm0_ch0 fb_ad13 72 ptc2 / adc0_se4b/ cmp1_in0/ tsi0_ch15 / adc0_se4b/ cmp1_in0/ tsi0_ch15 ptc2 spi0_pcs2 uart1_cts _b ftm0_ch1 fb_ad12 73 ptc3/ llwu_p7 /cmp1_in1 /cmp1_in1 ptc3/ llwu_p7 spi0_pcs1 uart1_rx ftm0_ch2 fb_clkout chapter 10 signal multiplexing and signal descriptions k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 235 100 lqf p pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 74 vss vss vss 75 vdd vdd vdd 76 ptc4/ llwu_p8 ptc4/ llwu_p8 spi0_pcs0 uart1_tx ftm0_ch3 fb_ad11 cmp1_out 77 ptc5/ llwu_p9 ptc5/ llwu_p9 spi0_sck lpt0_alt2 fb_ad10 cmp0_out 78 ptc6/ llwu_p10 /cmp0_in0 /cmp0_in0 ptc6/ llwu_p10 spi0_sout pdb0_extr g fb_ad9 79 ptc7 /cmp0_in1 /cmp0_in1 ptc7 spi0_sin fb_ad8 80 ptc8 / adc1_se4b/ cmp0_in2 / adc1_se4b/ cmp0_in2 ptc8 i2s0_mclk i2s0_clkin fb_ad7 81 ptc9 / adc1_se5b/ cmp0_in3 / adc1_se5b/ cmp0_in3 ptc9 i2s0_rx_bc lk fb_ad6 ftm2_flt0 82 ptc10 / adc1_se6b/ cmp0_in4 / adc1_se6b/ cmp0_in4 ptc10 i2c1_scl i2s0_rx_fs fb_ad5 83 ptc11/ llwu_p11 /adc1_se7b /adc1_se7b ptc11/ llwu_p11 i2c1_sda i2s0_rxd fb_rw_b 84 ptc12 ptc12 uart4_rts _b fb_ad27 85 ptc13 ptc13 uart4_cts _b fb_ad26 86 ptc14 ptc14 uart4_rx fb_ad25 87 ptc15 ptc15 uart4_tx fb_ad24 88 vss vss vss 89 vdd vdd vdd 90 ptc16 ptc16 can1_rx uart3_rx enet0_158 8_tmr0 fb_cs5_b/ fb_tsiz1/ fb_be23_16 _bls15_8_b 91 ptc17 ptc17 can1_tx uart3_tx enet0_158 8_tmr1 fb_cs4_b/ fb_tsiz0/ fb_be31_24 _bls7_0_b 92 ptc18 ptc18 uart3_rts _b enet0_158 8_tmr2 fb_tbst_b/ fb_cs2_b/ fb_be15_8_ bls23_16_b 93 ptd0/ llwu_p12 ptd0/ llwu_p12 spi0_pcs0 uart2_rts _b fb_ale/ fb_cs1_b/ fb_ts_b 94 ptd1 /adc0_se5b /adc0_se5b ptd1 spi0_sck uart2_cts _b fb_cs0_b 95 ptd2/ llwu_p13 ptd2/ llwu_p13 spi0_sout uart2_rx fb_ad4 96 ptd3 ptd3 spi0_sin uart2_tx fb_ad3 pinout k60 sub-family reference manual, rev. 6, nov 2011 236 freescale semiconductor, inc. 100 lqf p pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 97 ptd4/ llwu_p14 ptd4/ llwu_p14 spi0_pcs1 uart0_rts _b ftm0_ch4 fb_ad2 ewm_in 98 ptd5 /adc0_se6b /adc0_se6b ptd5 spi0_pcs2 uart0_cts _b ftm0_ch5 fb_ad1 ewm_out_ b 99 ptd6/ llwu_p15 /adc0_se7b /adc0_se7b ptd6/ llwu_p15 spi0_pcs3 uart0_rx ftm0_ch6 fb_ad0 ftm0_flt0 100 ptd7 ptd7 cmt_iro uart0_tx ftm0_ch7 ftm0_flt1 10.3.2 k60 pinouts the below figure shows the pinout diagram for the devices supported by this document. many signals may be multiplexed onto a single pin. to determine what signals can be used on which pin, see the previous section. chapter 10 signal multiplexing and signal descriptions k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 237 60 59 58 57 56 55 54 53 52 51 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 pga1_dp/adc1_dp0/adc0_dp3 pga0_dm/adc0_dm0/adc1_dm3 pga0_dp/adc0_dp0/adc1_dp3 adc1_dm1 adc1_dp1 adc0_dm1 adc0_dp1 vregin vout33 usb0_dm usb0_dp vss vdd pte6 pte5 pte4 pte3 pte2 pte1 pte0 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 vdd vss ptc3 ptc2 ptc1 ptc0 ptb23 ptb22 ptb21 ptb20 ptb19 ptb18 ptb17 ptb16 vdd vss ptb11 ptb10 ptb9 ptb3 ptb2 ptb1 ptb0 reset_b pta19 25 24 23 22 21 vssa vrefl vrefh vdda pga1_dm/adc1_dm0/adc0_dm3 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 99 79 78 77 76 ptd6 ptc7 ptc6 ptc5 ptc4 50 49 48 47 46 45 44 43 42 41 pta18 vss vdd pta17 pta16 pta15 pta14 pta13 pta12 vss vdd pta5 pta4 pta3 pta2 pta1 pta0 pte26 pte25 pte24 vbat extal32 xtal32 dac0_out/ cmp1_in3/adc0_se23 vref_out/cmp1_in5/ cmp0_in5/adc1_se18 98 ptd5 97 ptd4 96 ptd3 95 ptd2 94 ptd1 93 ptd0 92 ptc18 91 ptc17 90 ptc16 89 vdd 88 vss 80 ptc8 ptc9 ptc10 81 82 83 ptc11 84 ptc12 85 ptc13 86 ptc14 87 ptc15 100 ptd7 figure 10-2. k60 100 lqfp pinout diagram 10.4 module signal description tables the following sections correlate the chip-level signal name with the signal name used in the module's chapter. they also briefly describe the signal function and direction. module signal description tables k60 sub-family reference manual, rev. 6, nov 2011 238 freescale semiconductor, inc. 10.4.1 core modules table 10-2. jtag signal descriptions chip signal name module signal name description i/o jtag_tms jtag_tms/ swd_dio jtag test mode selection i/o jtag_tclk jtag_tclk/ swd_clk jtag test clock i jtag_tdi jtag_tdi jtag test data input i jtag_tdo jtag_tdo/ trace_swo jtag test data output o jtag_trst jtag_trst_b jtag reset i table 10-3. swd signal descriptions chip signal name module signal name description i/o swd_dio jtag_tms/ swd_dio serial wire data i/o swd_clk jtag_tclk/ swd_clk serial wire clock i table 10-4. tpiu signal descriptions chip signal name module signal name description i/o trace_clkout traceclk trace clock output from the arm coresight debug block o trace_d[3:2] tracedata trace output data from the arm coresight debug block used for 5- pin interface o trace_d[1:0] tracedata trace output data from the arm coresight debug block used for both 5-pin and 3-pin interfaces o trace_swo jtag_tdo/ trace_swo trace output data from the arm coresight debug block over a single pin o 10.4.2 system modules table 10-5. system signal descriptions chip signal name module signal name description i/o nmi non-maskable interrupt note: driving the nmi signal low forces a non-maskable interrupt, if the nmi function is selected on the corresponding pin. i table continues on the next page... chapter 10 signal multiplexing and signal descriptions 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 2 table 10-5. system signal descriptions (continued) chip signal name module signal name description i/o reset reset bi-directional signal i/o vdd mcu power i vss mcu ground i table 10-6. ewm signal descriptions chip signal name module signal name description i/o ewm_in ewm_in ewm input for safety status of external safety circuits. the polarity of ewm_in is programmable using the ctrl[assin] bit. the default polarity is active-low. i ewm_out ewm_out ewm reset out signal o 10.4.3 clock modules table 10-7. osc signal descriptions chip signal name module signal name description i/o extal0 extal external clock/oscillator input i xtal0 xtal oscillator output o table 10-8. rtc osc signal descriptions chip signal name module signal name description i/o extal32 extal32 32.768 khz oscillator input i xtal32 xtal32 32.768 khz oscillator output o 10.4.4 memories and memory interfaces table 10-9. ezport signal descriptions chip signal name module signal name description i/o ezp_clk ezp_ck ezport clock input ezp_cs ezp_cs ezport chip select input ezp_di ezp_d ezport serial data in input ezp_do ezp_q ezport serial data out output module signal description tables k60 sub-family reference manual, rev. 6, nov 2011 240 freescale semiconductor, inc. table 10-10. flexbus signal descriptions chip signal name module signal name description i/o fb_clkout fb_clk flexbus clock output o fb_ad[31:0] 1 fb_d[31:0]/ fb_ad[31:0] in a non-multiplexed configuration, this is the data bus. in a multiplexed configuration this bus is the address/data bus, fb_ad[31:0]. in non-multiplexed and multiplexed configurations, during the first cycle, this bus drives the upper address byte, addr[31:24]. i/o fb_cs[5:0] 2 fb_cs[5:0] general purpose chip-selects. the actual number of chip selects available depends upon the device and its pin configuration. o fb_be31_24_bls7 _0, fb_be23_16_bls1 5_8, fb_be15_8_bls23 _16, fb_be7_0_bls31_ 24 3 fb_be_31_24 fb_be_23_16 fb_be_15_8 fb_be_7_0 byte enables o fb_oe fb_oe output enable o fb_r w fb_r/ w read/write. 1 = read, 0 = write o fb_ts/ fb_ale fb_ts transfer start o fb_tsiz[1:0] fb_tsiz[1:0] transfer size o fb_ta 4 fb_ta transfer acknowledge i fb_tbst fb_tbst burst transfer indicator o 1. fb_ad[23:21] not available on 100-lqfp devices. 2. fb_cs3not available on 100-lqfp devices. 3. fb_be7_0_bls31_24not available on 100-lqfp devices. 4. fb_tanotavailable on 100-lqfp devices. 10.4.5 analog table 10-11. adc 0 signal descriptions chip signal name module signal name description i/o adc0_dp3, pga0_dp, adc0_dp[1:0] dadp[3:0] differential analog channel inputs i adc0_dm3, pga0_dm, adc0_dm[1:0] dadm[3:0] differential analog channel inputs i adc0_se[18,17,15: 12,9:418,17,15:12,9: 4] ad[23:4] single-ended analog channel inputs i table continues on the next page... chapter 10 signal multiplexing and signal descriptions 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 241 table 10-11. adc 0 signal descriptions (continued) chip signal name module signal name description i/o vrefh v refsh voltage reference select high i vrefl v refsl voltage reference select low i vdda v dda analog power supply i vssa v ssa analog ground i table 10-12. adc 1 signal descriptions chip signal name module signal name description i/o adc1_dp3, pga1_dp, adc1_dp[1:0] dadp[3:0] differential analog channel inputs i adc1_dm3, pga1_dm, adc1_dm[1:0] dadm[3:0] differential analog channel inputs i adc1_se[18:17,15: 13,9:4] ad[23:4] single-ended analog channel inputs i vrefh v refsh voltage reference select high i vrefl v refsl voltage reference select low i vdda v dda analog power supply i vssa v ssa analog ground i table 10-13. cmp 0 signal descriptions chip signal name module signal name description i/o cmp0_in[5:0] in[5:0] analog voltage inputs i cmp0_out cmpo comparator output o table 10-14. cmp 1 signal descriptions chip signal name module signal name description i/o cmp1_in[5:0] in[5:0] analog voltage inputs i cmp1_out cmpo comparator output o table 10-15. cmp 2 signal descriptions chip signal name module signal name description i/o cmp2_in[5:0] in[5:0] analog voltage inputs i cmp2_out cmpo comparator output o module signal description tables k60 sub-family reference manual, rev. 6, nov 2011 242 freescale semiconductor, inc. table 10-16. dac 0 signal descriptions chip signal name module signal name description i/o dac0_out dac output o table 10-17. triamp 1 signal descriptions chip signal name module signal name description i/o tri1_dp inp_3v amplifier positive input terminal i tri1_dm inn_3v amplifier negative input terminal i tri1_out out_3v amplifier output terminal o table 10-18. vref signal descriptions chip signal name module signal name description i/o vref_out vref_out internally-generated voltage reference output o 10.4.6 communication interfaces ethernet mii signal descriptions chip signal name module signal name description i/o mii0_col mii_col asserted upon detection of a collision and remains asserted while the collision persists. this signal is not defined for full-duplex mode. i mii0_crs mii_crs carrier sense. when asserted, indicates transmit or receive medium is not idle. in rmii mode, this signal is present on the rmii_crs_dv pin. i mii0_mdc mii_mdc output clock provides a timing reference to the phy for data transfers on the mdio signal. o mii0_mdio mii_mdio transfers control information between the external phy and the media-access controller. data is synchronous to mdc. this signal is an input after reset. i/o table continues on the next page... chapter 10 signal multiplexing and signal descriptions 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 24 chip signal name module signal name description i/o mii0_rxclk mii_rxclk in mii mode, provides a timing reference for rxdv, rxd[3:0], and rxer. i mii0_rxdv mii_rxdv asserting this input indicates the phy has valid nibbles present on the mii. rxdv must remain asserted from the first recovered nibble of the frame through to the last nibble. asserting rxdv must start no later than the sfd and exclude any eof. in rmii mode, this pin also generates the crs signal. i mii0_rxd[3:0] mii_rxd[3:0] contains the ethernet input data transferred from the phy to the media-access controller when rxdv is asserted. i mii0_rxer mii_rxer when asserted with rxdv, indicates the phy detects an error in the current frame. i mii0_txclk mii_txclk input clock which provides a timing reference for txen, txd[3:0], and txer. i mii0_txd[3:0] mii_txd[3:0] the serial output ethernet data and only valid during the assertion of txen. o mii0_txen mii_txen indicates when valid nibbles are present on the mii. this signal is asserted with the first nibble of a preamble and is negated before the first txclk following the final nibble of the frame. o mii0_txer mii_txer when asserted for one or more clock cycles while txen is also asserted, phy sends one or more illegal symbols. o ethernet rmii signal descriptions chip signal name module signal name description i/o rmii0_mdc rmii_mdc output clock provides a timing reference to the phy for data transfers on the mdio signal. o table continues on the next page... module signal description tables 60 sub-family reference manual, rev. 6, nov 2011 244 freescale semiconductor, inc. chip signal name module signal name description i/o rmii0_mdio rmii_mdio transfers control information between the external phy and the media-access controller. data is synchronous to mdc. this signal is an input after reset. i/o rmii0_crs_dv rmii_crs_dv asserting this input indicates the phy has valid nibbles present on the mii. rxdv must remain asserted from the first recovered nibble of the frame through to the last nibble. asserting rxdv must start no later than the sfd and exclude any eof. in rmii mode, this pin also generates the crs signal. i rmii0_rxd[1:0] rmii_rxd[1:0] contains the ethernet input data transferred from the phy to the media-access controller when rxdv is asserted. i rmii0_rxer rmii_rxer when asserted with rxdv, indicates the phy detects an error in the current frame. i rmii0_txd[1:0] rmii_txd[1:0] the serial output ethernet data and only valid during the assertion of txen. o rmii0_txen rmii_txen indicates when valid nibbles are present on the mii. this signal is asserted with the first nibble of a preamble and is negated before the first txclk following the final nibble of the frame. o internal oscerclk clock 1 rmii_ref_clk in rmii mode, this signal is the reference clock for receive, transmit, and the control interface. i table 10-19. usb fs otg signal descriptions chip signal name module signal name description i/o usb0_dm usb_dm usb d- analog data signal on the usb bus. i/o usb0_dp usb_dp usb d+ analog data signal on the usb bus. i/o usb_clkin alternate usb clock input i chapter 10 signal multiplexing and signal descriptions k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 245 table 10-20. usb vreg signal descriptions chip signal name module signal name description i/o vout33 reg33_out regulator output voltage o vregin reg33_in unregulated power supply i table 10-21. can 0 signal descriptions chip signal name module signal name description i/o can0_rx can rx can receive pin input can0_tx can tx can transmit pin output table 10-22. can 1 signal descriptions chip signal name module signal name description i/o can1_rx can rx can receive pin input can1_tx can tx can transmit pin output table 10-23. spi 0 signal descriptions chip signal name module signal name description i/o spi0_pcs0 pcs0/ ss master mode: peripheral chip select 0 output slave mode: slave select input i/o spi0_pcs[3:1] pcs[3:1] master mode: peripheral chip select 1 - 3 slave mode: unused o spi0_pcs4 pcs4 master mode: peripheral chip select 4 slave mode: unused o spi0_pcs5 pcs5/ pcss master mode: peripheral chip select 5 / peripheral chip select strobe slave mode: unused o spi0_sin sin serial data in i spi0_sout sout serial data out o spi0_sck sck master mode: serial clock (output) slave mode: serial clock (input) i/o table 10-24. i 2 c 0 signal descriptions chip signal name module signal name description i/o i2c0_scl scl bidirectional serial clock line of the i 2 c system. i/o i2c0_sda sda bidirectional serial data line of the i 2 c system. i/o module signal description tables k60 sub-family reference manual, rev. 6, nov 2011 246 freescale semiconductor, inc. table 10-25. i 2 c 1 signal descriptions chip signal name module signal name description i/o i2c1_scl scl bidirectional serial clock line of the i 2 c system. i/o i2c1_sda sda bidirectional serial data line of the i 2 c system. i/o table 10-26. uart 0 signal descriptions chip signal name module signal name description i/o uart0_cts cts clear to send i uart0_rts rts request to send o uart0_tx txd transmit data o uart0_rx rxd receive data i table 10-27. uart 1 signal descriptions chip signal name module signal name description i/o uart1_cts cts clear to send i uart1_rts rts request to send o uart1_tx txd transmit data o uart1_rx rxd receive data i table 10-28. uart 2 signal descriptions chip signal name module signal name description i/o uart2_cts cts clear to send i uart2_rts rts request to send o uart2_tx txd transmit data o uart2_rx rxd receive data i table 10-29. uart 3 signal descriptions chip signal name module signal name description i/o uart3_cts cts clear to send i uart3_rts rts request to send o uart3_tx txd transmit data o uart3_rx rxd receive data i chapter 10 signal multiplexing and signal descriptions k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 247 table 10-30. uart 4 signal descriptions chip signal name module signal name description i/o uart4_cts cts clear to send i uart4_rts rts request to send o uart4_tx txd transmit data o uart4_rx rxd receive data i table 10-31. sdhc signal descriptions chip signal name module signal name description i/o sdhc0_dclk sdhc_dclk generated clock used to drive the mmc, sd, sdio or ce-ata cards. o sdhc0_cmd sdhc_cmd send commands to and receive responses from the card. i/o sdhc0_d0 sdhc_d0 dat0 line or busy-state detect i/o sdhc0_d1 sdhc_d1 8-bit mode: dat1 line 4-bit mode: dat1 line or interrupt detect 1-bit mode: interrupt detect i/o sdhc0_d2 sdhc_d2 4-/8-bit mode: dat2 line or read wait 1-bit mode: read wait i/o sdhc0_d3 sdhc_d3 4-/8-bit mode: dat3 line or configured as card detection pin 1-bit mode: may be configured as card detection pin i/o table 10-32. i 2 s 0 signal descriptions chip signal name module signal name description i/o i2s0_mclk serial master clock output i/o i2s0_rx_bclk srck serial receive clock. srck can be used as an input or output. ? in asynchronous mode the receiver uses this clock signal and it is always continuous. ? in synchronous mode, the stck port is used instead for clocking in data. i/o i2s0_rx_fs srfs serial receive frame sync. the srfs port can be used as an input or output. the frame sync is used by the receiver to synchronize the transfer of data. the frame sync signal can be one bit or one word in length and can occur one bit before the transfer of data or right at the transfer of data. if srfs is configured as an input, the external device should drive srfs during the rising edge of stck or srck. i/o i2s0_rxd srxd serial receive data. the srxd port is an input and is used to bring serial data into the receive data shift register. i table continues on the next page... module signal description tables 60 sub-family reference manual, rev. 6, nov 2011 248 freescale semiconductor, inc. table 10-32. i 2 s 0 signal descriptions (continued) chip signal name module signal name description i/o i2s0_tx_bclk stck serial transmit clock. the stck port can be used as an input or output. this clock signal is used by the transmitter and can be continuous or gated. during gated clock mode, data on stck is valid only during the transmission of data. otherwise, it is pulled to the inactive state. in synchronous mode, this port is used by the transmit and receive sections. i/o i2s0_tx_fs stfs serial transmit frame sync. the stfs port can be used as an input or output. the frame sync is used by the transmitter to synchronize the transfer of data. the frame sync signal can be one bit or one word in length and can occur one bit before the transfer of data or right at the transfer of data. in synchronous mode, this port is used by both the transmit and receive sections. in gated clock mode, frame sync signals are not used. if stfs is configured as an input, the external device should drive stfs during the rising edge of stck if tsckp is positive-edge triggered. the external device should drive stfs during the falling edge of stck if tsckp is negative-edge triggered. i/o i2s0_txd stxd serial transmit data. the stxd port is an output and transmits data from the serial transmit shift register. the stxd port is an output port when data is being transmitted and is disabled between data word transmissions and on the trailing edge of the bit clock after the last bit of a word is transmitted. o 10.4.7 human-machine interfaces (hmi) table 10-33. gpio signal descriptions chip signal name module signal name description i/o pta[31:0] 1 porta[31:0] general purpose input/output i/o ptb[31:0] 1 portb[31:0] general purpose input/output i/o ptc[31:0] 1 portc[31:0] general purpose input/output i/o ptd[31:0] 1 portd[31:0] general purpose input/output i/o pte[31:0] 1 porte[31:0] general purpose input/output i/o 1. the available gpio pins depends on the specific package. see the signal multiplexing section for which exact gpio signals are available. table 10-34. tsi 0 signal descriptions chip signal name module signal name description i/o tsi0_ch[15:0] tsi_in[15:0] tsi pins. switchable driver that connects directly to the electrode pins tsi[15:0] can operate as gpio pins i/o chapter 10 signal multiplexing and signal descriptions k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 249 module signal description tables k60 sub-family reference manual, rev. 6, nov 2011 250 freescale semiconductor, inc. chapter 11 port control and interrupts (port) 11.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. 11.1.1 overview the port control and interrupt (port) module provides support for external interrupt, digital filtering and port control functions. most functions can be configured independently for each pin in the 32-bit port and affect the pin regardless of its pin muxing state. there is one instance of the port module for each port. not all pins within each port are implemented on a specific device. 11.1.2 features ? pin interrupt ? interrupt flag and enable registers for each pin ? supports edge sensitive (rising, falling, both) or level sensitive (low, high) configured per pin ? support for interrupt or dma request configured per pin ? asynchronous wakeup in low-power modes ? pin interrupt is functional in all digital pin muxing modes ? digital input filter ? digital input filter for each pin, usable by any digital peripheral muxed onto pin ? individual enable or bypass control bit per pin k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 251 ? selectable clock source for digital input filter with 5-bit resolution on filter size ? digital filter is functional in all digital pin muxing modes ? port control ? individual pull control registers with pullup, pulldown and pull-disable support ? individual drive strength register supporting high and low drive strength ? individual slew rate register supporting fast and slow slew rates ? individual input passive filter register supporting enabled and disabled ? individual open-drain register supporting enabled and disabled ? individual mux control register supporting analog (or pin disabled), gpio plus up to six chip specific digital functions ? pad configuration registers are functional in all digital pin muxing modes 11.1.3 modes of operation 11.1.3.1 run mode in run mode, the port operates normally. 11.1.3.2 wait mode in wait mode, the port continues to operate normally and may be configured to exit the low power mode if an enabled interrupt is detected. dma requests are still generated during wait mode, but do not cause an exit from the low power mode. 11.1.3.3 stop mode in stop mode, the digital input filters are bypassed unless they are configured to run from the 1 khz lpo clock source. the port can be configured to exit the low power mode via an asynchronous wakeup signal if an enabled interrupt (but not dma request) is detected. 11.1.3.4 debug mode in debug mode, the portx operates normally. introduction k60 sub-family reference manual, rev. 6, nov 2011 252 freescale semiconductor, inc. 11.2 external signal description table 11-1. signal properties name function i/o reset pull portx[31:0] external interrupt i/o 0 - note not all pins within each port are implemented on each device. 11.3 detailed signal descriptions table 11-2. portx interface-detailed signal descriptions signal i/o description portx[31:0] i/o external interrupt. state meaning asserted-pin is logic one. negated-pin is logic zero. timing assertion-may occur at any time and can assert asynchronously to the system clock. negation-may occur at any time and can assert asynchronously to the system clock. 11.4 memory map and register definition any read or write access to the port memory space that is outside the valid memory map results in a bus error. all register accesses complete with zero wait states. port memory map absolute address (hex) register name width (in bits) access reset value section/ page 4004_9000 pin control register n (porta_pcr0) 32 r/w 0000_0000h 11.4.1/260 4004_9004 pin control register n (porta_pcr1) 32 r/w 0000_0000h 11.4.1/260 4004_9008 pin control register n (porta_pcr2) 32 r/w 0000_0000h 11.4.1/260 table continues on the next page... chapter 11 port control and interrupts prt 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 2 port memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4004_900c pin control register n (porta_pcr3) 32 r/w 0000_0000h 11.4.1/260 4004_9010 pin control register n (porta_pcr4) 32 r/w 0000_0000h 11.4.1/260 4004_9014 pin control register n (porta_pcr5) 32 r/w 0000_0000h 11.4.1/260 4004_9018 pin control register n (porta_pcr6) 32 r/w 0000_0000h 11.4.1/260 4004_901c pin control register n (porta_pcr7) 32 r/w 0000_0000h 11.4.1/260 4004_9020 pin control register n (porta_pcr8) 32 r/w 0000_0000h 11.4.1/260 4004_9024 pin control register n (porta_pcr9) 32 r/w 0000_0000h 11.4.1/260 4004_9028 pin control register n (porta_pcr10) 32 r/w 0000_0000h 11.4.1/260 4004_902c pin control register n (porta_pcr11) 32 r/w 0000_0000h 11.4.1/260 4004_9030 pin control register n (porta_pcr12) 32 r/w 0000_0000h 11.4.1/260 4004_9034 pin control register n (porta_pcr13) 32 r/w 0000_0000h 11.4.1/260 4004_9038 pin control register n (porta_pcr14) 32 r/w 0000_0000h 11.4.1/260 4004_903c pin control register n (porta_pcr15) 32 r/w 0000_0000h 11.4.1/260 4004_9040 pin control register n (porta_pcr16) 32 r/w 0000_0000h 11.4.1/260 4004_9044 pin control register n (porta_pcr17) 32 r/w 0000_0000h 11.4.1/260 4004_9048 pin control register n (porta_pcr18) 32 r/w 0000_0000h 11.4.1/260 4004_904c pin control register n (porta_pcr19) 32 r/w 0000_0000h 11.4.1/260 4004_9050 pin control register n (porta_pcr20) 32 r/w 0000_0000h 11.4.1/260 4004_9054 pin control register n (porta_pcr21) 32 r/w 0000_0000h 11.4.1/260 4004_9058 pin control register n (porta_pcr22) 32 r/w 0000_0000h 11.4.1/260 4004_905c pin control register n (porta_pcr23) 32 r/w 0000_0000h 11.4.1/260 4004_9060 pin control register n (porta_pcr24) 32 r/w 0000_0000h 11.4.1/260 4004_9064 pin control register n (porta_pcr25) 32 r/w 0000_0000h 11.4.1/260 4004_9068 pin control register n (porta_pcr26) 32 r/w 0000_0000h 11.4.1/260 4004_906c pin control register n (porta_pcr27) 32 r/w 0000_0000h 11.4.1/260 4004_9070 pin control register n (porta_pcr28) 32 r/w 0000_0000h 11.4.1/260 4004_9074 pin control register n (porta_pcr29) 32 r/w 0000_0000h 11.4.1/260 4004_9078 pin control register n (porta_pcr30) 32 r/w 0000_0000h 11.4.1/260 4004_907c pin control register n (porta_pcr31) 32 r/w 0000_0000h 11.4.1/260 4004_9080 global pin control low register (porta_gpclr) 32 w (always reads zero) 0000_0000h 11.4.2/262 4004_9084 global pin control high register (porta_gpchr) 32 w (always 0000_0000h 11.4.3/263 table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 24 freescale semiconductor, inc. port memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page reads zero) 4004_90a0 interrupt status flag register (porta_isfr) 32 w1c 0000_0000h 11.4.4/263 4004_90c0 digital filter enable register (porta_dfer) 32 r/w 0000_0000h 11.4.5/264 4004_90c4 digital filter clock register (porta_dfcr) 32 r/w 0000_0000h 11.4.6/265 4004_90c8 digital filter width register (porta_dfwr) 32 r/w 0000_0000h 11.4.7/265 4004_a000 pin control register n (portb_pcr0) 32 r/w 0000_0000h 11.4.1/260 4004_a004 pin control register n (portb_pcr1) 32 r/w 0000_0000h 11.4.1/260 4004_a008 pin control register n (portb_pcr2) 32 r/w 0000_0000h 11.4.1/260 4004_a00c pin control register n (portb_pcr3) 32 r/w 0000_0000h 11.4.1/260 4004_a010 pin control register n (portb_pcr4) 32 r/w 0000_0000h 11.4.1/260 4004_a014 pin control register n (portb_pcr5) 32 r/w 0000_0000h 11.4.1/260 4004_a018 pin control register n (portb_pcr6) 32 r/w 0000_0000h 11.4.1/260 4004_a01c pin control register n (portb_pcr7) 32 r/w 0000_0000h 11.4.1/260 4004_a020 pin control register n (portb_pcr8) 32 r/w 0000_0000h 11.4.1/260 4004_a024 pin control register n (portb_pcr9) 32 r/w 0000_0000h 11.4.1/260 4004_a028 pin control register n (portb_pcr10) 32 r/w 0000_0000h 11.4.1/260 4004_a02c pin control register n (portb_pcr11) 32 r/w 0000_0000h 11.4.1/260 4004_a030 pin control register n (portb_pcr12) 32 r/w 0000_0000h 11.4.1/260 4004_a034 pin control register n (portb_pcr13) 32 r/w 0000_0000h 11.4.1/260 4004_a038 pin control register n (portb_pcr14) 32 r/w 0000_0000h 11.4.1/260 4004_a03c pin control register n (portb_pcr15) 32 r/w 0000_0000h 11.4.1/260 4004_a040 pin control register n (portb_pcr16) 32 r/w 0000_0000h 11.4.1/260 4004_a044 pin control register n (portb_pcr17) 32 r/w 0000_0000h 11.4.1/260 4004_a048 pin control register n (portb_pcr18) 32 r/w 0000_0000h 11.4.1/260 4004_a04c pin control register n (portb_pcr19) 32 r/w 0000_0000h 11.4.1/260 4004_a050 pin control register n (portb_pcr20) 32 r/w 0000_0000h 11.4.1/260 4004_a054 pin control register n (portb_pcr21) 32 r/w 0000_0000h 11.4.1/260 4004_a058 pin control register n (portb_pcr22) 32 r/w 0000_0000h 11.4.1/260 4004_a05c pin control register n (portb_pcr23) 32 r/w 0000_0000h 11.4.1/260 4004_a060 pin control register n (portb_pcr24) 32 r/w 0000_0000h 11.4.1/260 4004_a064 pin control register n (portb_pcr25) 32 r/w 0000_0000h 11.4.1/260 4004_a068 pin control register n (portb_pcr26) 32 r/w 0000_0000h 11.4.1/260 4004_a06c pin control register n (portb_pcr27) 32 r/w 0000_0000h 11.4.1/260 table continues on the next page... chapter 11 port control and interrupts prt 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 2 port memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4004_a070 pin control register n (portb_pcr28) 32 r/w 0000_0000h 11.4.1/260 4004_a074 pin control register n (portb_pcr29) 32 r/w 0000_0000h 11.4.1/260 4004_a078 pin control register n (portb_pcr30) 32 r/w 0000_0000h 11.4.1/260 4004_a07c pin control register n (portb_pcr31) 32 r/w 0000_0000h 11.4.1/260 4004_a080 global pin control low register (portb_gpclr) 32 w (always reads zero) 0000_0000h 11.4.2/262 4004_a084 global pin control high register (portb_gpchr) 32 w (always reads zero) 0000_0000h 11.4.3/263 4004_a0a0 interrupt status flag register (portb_isfr) 32 w1c 0000_0000h 11.4.4/263 4004_a0c0 digital filter enable register (portb_dfer) 32 r/w 0000_0000h 11.4.5/264 4004_a0c4 digital filter clock register (portb_dfcr) 32 r/w 0000_0000h 11.4.6/265 4004_a0c8 digital filter width register (portb_dfwr) 32 r/w 0000_0000h 11.4.7/265 4004_b000 pin control register n (portc_pcr0) 32 r/w 0000_0000h 11.4.1/260 4004_b004 pin control register n (portc_pcr1) 32 r/w 0000_0000h 11.4.1/260 4004_b008 pin control register n (portc_pcr2) 32 r/w 0000_0000h 11.4.1/260 4004_b00c pin control register n (portc_pcr3) 32 r/w 0000_0000h 11.4.1/260 4004_b010 pin control register n (portc_pcr4) 32 r/w 0000_0000h 11.4.1/260 4004_b014 pin control register n (portc_pcr5) 32 r/w 0000_0000h 11.4.1/260 4004_b018 pin control register n (portc_pcr6) 32 r/w 0000_0000h 11.4.1/260 4004_b01c pin control register n (portc_pcr7) 32 r/w 0000_0000h 11.4.1/260 4004_b020 pin control register n (portc_pcr8) 32 r/w 0000_0000h 11.4.1/260 4004_b024 pin control register n (portc_pcr9) 32 r/w 0000_0000h 11.4.1/260 4004_b028 pin control register n (portc_pcr10) 32 r/w 0000_0000h 11.4.1/260 4004_b02c pin control register n (portc_pcr11) 32 r/w 0000_0000h 11.4.1/260 4004_b030 pin control register n (portc_pcr12) 32 r/w 0000_0000h 11.4.1/260 4004_b034 pin control register n (portc_pcr13) 32 r/w 0000_0000h 11.4.1/260 4004_b038 pin control register n (portc_pcr14) 32 r/w 0000_0000h 11.4.1/260 4004_b03c pin control register n (portc_pcr15) 32 r/w 0000_0000h 11.4.1/260 4004_b040 pin control register n (portc_pcr16) 32 r/w 0000_0000h 11.4.1/260 4004_b044 pin control register n (portc_pcr17) 32 r/w 0000_0000h 11.4.1/260 4004_b048 pin control register n (portc_pcr18) 32 r/w 0000_0000h 11.4.1/260 4004_b04c pin control register n (portc_pcr19) 32 r/w 0000_0000h 11.4.1/260 table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 26 freescale semiconductor, inc. port memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4004_b050 pin control register n (portc_pcr20) 32 r/w 0000_0000h 11.4.1/260 4004_b054 pin control register n (portc_pcr21) 32 r/w 0000_0000h 11.4.1/260 4004_b058 pin control register n (portc_pcr22) 32 r/w 0000_0000h 11.4.1/260 4004_b05c pin control register n (portc_pcr23) 32 r/w 0000_0000h 11.4.1/260 4004_b060 pin control register n (portc_pcr24) 32 r/w 0000_0000h 11.4.1/260 4004_b064 pin control register n (portc_pcr25) 32 r/w 0000_0000h 11.4.1/260 4004_b068 pin control register n (portc_pcr26) 32 r/w 0000_0000h 11.4.1/260 4004_b06c pin control register n (portc_pcr27) 32 r/w 0000_0000h 11.4.1/260 4004_b070 pin control register n (portc_pcr28) 32 r/w 0000_0000h 11.4.1/260 4004_b074 pin control register n (portc_pcr29) 32 r/w 0000_0000h 11.4.1/260 4004_b078 pin control register n (portc_pcr30) 32 r/w 0000_0000h 11.4.1/260 4004_b07c pin control register n (portc_pcr31) 32 r/w 0000_0000h 11.4.1/260 4004_b080 global pin control low register (portc_gpclr) 32 w (always reads zero) 0000_0000h 11.4.2/262 4004_b084 global pin control high register (portc_gpchr) 32 w (always reads zero) 0000_0000h 11.4.3/263 4004_b0a0 interrupt status flag register (portc_isfr) 32 w1c 0000_0000h 11.4.4/263 4004_b0c0 digital filter enable register (portc_dfer) 32 r/w 0000_0000h 11.4.5/264 4004_b0c4 digital filter clock register (portc_dfcr) 32 r/w 0000_0000h 11.4.6/265 4004_b0c8 digital filter width register (portc_dfwr) 32 r/w 0000_0000h 11.4.7/265 4004_c000 pin control register n (portd_pcr0) 32 r/w 0000_0000h 11.4.1/260 4004_c004 pin control register n (portd_pcr1) 32 r/w 0000_0000h 11.4.1/260 4004_c008 pin control register n (portd_pcr2) 32 r/w 0000_0000h 11.4.1/260 4004_c00c pin control register n (portd_pcr3) 32 r/w 0000_0000h 11.4.1/260 4004_c010 pin control register n (portd_pcr4) 32 r/w 0000_0000h 11.4.1/260 4004_c014 pin control register n (portd_pcr5) 32 r/w 0000_0000h 11.4.1/260 4004_c018 pin control register n (portd_pcr6) 32 r/w 0000_0000h 11.4.1/260 4004_c01c pin control register n (portd_pcr7) 32 r/w 0000_0000h 11.4.1/260 4004_c020 pin control register n (portd_pcr8) 32 r/w 0000_0000h 11.4.1/260 4004_c024 pin control register n (portd_pcr9) 32 r/w 0000_0000h 11.4.1/260 4004_c028 pin control register n (portd_pcr10) 32 r/w 0000_0000h 11.4.1/260 4004_c02c pin control register n (portd_pcr11) 32 r/w 0000_0000h 11.4.1/260 table continues on the next page... chapter 11 port control and interrupts prt 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 27 port memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4004_c030 pin control register n (portd_pcr12) 32 r/w 0000_0000h 11.4.1/260 4004_c034 pin control register n (portd_pcr13) 32 r/w 0000_0000h 11.4.1/260 4004_c038 pin control register n (portd_pcr14) 32 r/w 0000_0000h 11.4.1/260 4004_c03c pin control register n (portd_pcr15) 32 r/w 0000_0000h 11.4.1/260 4004_c040 pin control register n (portd_pcr16) 32 r/w 0000_0000h 11.4.1/260 4004_c044 pin control register n (portd_pcr17) 32 r/w 0000_0000h 11.4.1/260 4004_c048 pin control register n (portd_pcr18) 32 r/w 0000_0000h 11.4.1/260 4004_c04c pin control register n (portd_pcr19) 32 r/w 0000_0000h 11.4.1/260 4004_c050 pin control register n (portd_pcr20) 32 r/w 0000_0000h 11.4.1/260 4004_c054 pin control register n (portd_pcr21) 32 r/w 0000_0000h 11.4.1/260 4004_c058 pin control register n (portd_pcr22) 32 r/w 0000_0000h 11.4.1/260 4004_c05c pin control register n (portd_pcr23) 32 r/w 0000_0000h 11.4.1/260 4004_c060 pin control register n (portd_pcr24) 32 r/w 0000_0000h 11.4.1/260 4004_c064 pin control register n (portd_pcr25) 32 r/w 0000_0000h 11.4.1/260 4004_c068 pin control register n (portd_pcr26) 32 r/w 0000_0000h 11.4.1/260 4004_c06c pin control register n (portd_pcr27) 32 r/w 0000_0000h 11.4.1/260 4004_c070 pin control register n (portd_pcr28) 32 r/w 0000_0000h 11.4.1/260 4004_c074 pin control register n (portd_pcr29) 32 r/w 0000_0000h 11.4.1/260 4004_c078 pin control register n (portd_pcr30) 32 r/w 0000_0000h 11.4.1/260 4004_c07c pin control register n (portd_pcr31) 32 r/w 0000_0000h 11.4.1/260 4004_c080 global pin control low register (portd_gpclr) 32 w (always reads zero) 0000_0000h 11.4.2/262 4004_c084 global pin control high register (portd_gpchr) 32 w (always reads zero) 0000_0000h 11.4.3/263 4004_c0a0 interrupt status flag register (portd_isfr) 32 w1c 0000_0000h 11.4.4/263 4004_c0c0 digital filter enable register (portd_dfer) 32 r/w 0000_0000h 11.4.5/264 4004_c0c4 digital filter clock register (portd_dfcr) 32 r/w 0000_0000h 11.4.6/265 4004_c0c8 digital filter width register (portd_dfwr) 32 r/w 0000_0000h 11.4.7/265 4004_d000 pin control register n (porte_pcr0) 32 r/w 0000_0000h 11.4.1/260 4004_d004 pin control register n (porte_pcr1) 32 r/w 0000_0000h 11.4.1/260 4004_d008 pin control register n (porte_pcr2) 32 r/w 0000_0000h 11.4.1/260 4004_d00c pin control register n (porte_pcr3) 32 r/w 0000_0000h 11.4.1/260 table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 28 freescale semiconductor, inc. port memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4004_d010 pin control register n (porte_pcr4) 32 r/w 0000_0000h 11.4.1/260 4004_d014 pin control register n (porte_pcr5) 32 r/w 0000_0000h 11.4.1/260 4004_d018 pin control register n (porte_pcr6) 32 r/w 0000_0000h 11.4.1/260 4004_d01c pin control register n (porte_pcr7) 32 r/w 0000_0000h 11.4.1/260 4004_d020 pin control register n (porte_pcr8) 32 r/w 0000_0000h 11.4.1/260 4004_d024 pin control register n (porte_pcr9) 32 r/w 0000_0000h 11.4.1/260 4004_d028 pin control register n (porte_pcr10) 32 r/w 0000_0000h 11.4.1/260 4004_d02c pin control register n (porte_pcr11) 32 r/w 0000_0000h 11.4.1/260 4004_d030 pin control register n (porte_pcr12) 32 r/w 0000_0000h 11.4.1/260 4004_d034 pin control register n (porte_pcr13) 32 r/w 0000_0000h 11.4.1/260 4004_d038 pin control register n (porte_pcr14) 32 r/w 0000_0000h 11.4.1/260 4004_d03c pin control register n (porte_pcr15) 32 r/w 0000_0000h 11.4.1/260 4004_d040 pin control register n (porte_pcr16) 32 r/w 0000_0000h 11.4.1/260 4004_d044 pin control register n (porte_pcr17) 32 r/w 0000_0000h 11.4.1/260 4004_d048 pin control register n (porte_pcr18) 32 r/w 0000_0000h 11.4.1/260 4004_d04c pin control register n (porte_pcr19) 32 r/w 0000_0000h 11.4.1/260 4004_d050 pin control register n (porte_pcr20) 32 r/w 0000_0000h 11.4.1/260 4004_d054 pin control register n (porte_pcr21) 32 r/w 0000_0000h 11.4.1/260 4004_d058 pin control register n (porte_pcr22) 32 r/w 0000_0000h 11.4.1/260 4004_d05c pin control register n (porte_pcr23) 32 r/w 0000_0000h 11.4.1/260 4004_d060 pin control register n (porte_pcr24) 32 r/w 0000_0000h 11.4.1/260 4004_d064 pin control register n (porte_pcr25) 32 r/w 0000_0000h 11.4.1/260 4004_d068 pin control register n (porte_pcr26) 32 r/w 0000_0000h 11.4.1/260 4004_d06c pin control register n (porte_pcr27) 32 r/w 0000_0000h 11.4.1/260 4004_d070 pin control register n (porte_pcr28) 32 r/w 0000_0000h 11.4.1/260 4004_d074 pin control register n (porte_pcr29) 32 r/w 0000_0000h 11.4.1/260 4004_d078 pin control register n (porte_pcr30) 32 r/w 0000_0000h 11.4.1/260 4004_d07c pin control register n (porte_pcr31) 32 r/w 0000_0000h 11.4.1/260 4004_d080 global pin control low register (porte_gpclr) 32 w (always reads zero) 0000_0000h 11.4.2/262 4004_d084 global pin control high register (porte_gpchr) 32 w (always reads zero) 0000_0000h 11.4.3/263 table continues on the next page... chapter 11 port control and interrupts prt 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 2 port memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4004_d0a0 interrupt status flag register (porte_isfr) 32 w1c 0000_0000h 11.4.4/263 4004_d0c0 digital filter enable register (porte_dfer) 32 r/w 0000_0000h 11.4.5/264 4004_d0c4 digital filter clock register (porte_dfcr) 32 r/w 0000_0000h 11.4.6/265 4004_d0c8 digital filter width register (porte_dfwr) 32 r/w 0000_0000h 11.4.7/265 11.4.1 pin control register n (port x r n for pcr1 to pcr5 of the port a, bit 0, 1, 6, 8, 9,10 reset to 1; for the pcr0 of the port a, bit 1, 6, 8, 9, 10 reset to 1; in other conditions, all bits reset to 0. addresses: 4004_9000h base + 0h offset + (4d n , where n 0d to 1d bit 1 0 2 28 27 26 2 24 2 22 21 20 1 18 17 16 1 14 1 12 11 10 8 7 6 4 2 1 0 r 0 isf 0 irc 0 mux 0 dse de pfe 0 sre pe ps w w1c reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 prt x r n iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero f nterrut tatus fla he in interrut coniuration is ali in all iital in uxin oes oniure interrut has not een etecte oniure interrut has een etecte in is coniure to enerate a request then the corresonin la will e cleare autoatically at the coletion o the requeste transer otherwise the la reains set until a loic one is written to that la coniure or a leel sensitie interrut that reains asserte then la will set aain ieiately resere his reaonly iel is resere an always has the alue ero r nterrut oniuration he in interrut coniuration is ali in all iital in uxin oes he corresonin in is coniure to enerate interrut request as ollows: nterrut request isale request on risin ee request on allin ee request on either ee resere nterrut when loic ero table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 260 freescale semiconductor, inc. port x r n iel escritions continue fiel escrition nterrut on risin ee nterrut on allin ee nterrut on either ee nterrut when loic one others resere l loc reister in ontrol reister its : are not loce in ontrol reister its : are loce an cannot e uate until the next yste reset resere his reaonly iel is resere an always has the alue ero u in ux ontrol he corresonin in is coniure as ollows: in isale nalo lternatie o lternatie chi seciic lternatie chi seciic lternatie chi seciic lternatie chi seciic lternatie chi seciic lternatie chi seciic resere his reaonly iel is resere an always has the alue ero rie trenth nale rie trenth coniuration is ali in all iital in uxin oes low rie strenth is coniure on the corresonin in i in is coniure as a iital outut hih rie strenth is coniure on the corresonin in i in is coniure as a iital outut o oen rain nale oen rain coniuration is ali in all iital in uxin oes oen rain outut is isale on the corresonin in oen rain outut is enale on the corresonin in roie in is coniure as a iital outut f assie filter nale assie filter coniuration is ali in all iital in uxin oes assie nut filter is isale on the corresonin in assie nut filter is enale on the corresonin in roie in is coniure as a iital inut low ass ilter h to h anwith is enale on the iital inut ath isale the assie nut filter when suortin hih see interaces h on the in resere his reaonly iel is resere an always has the alue ero table continues on the next page... chapter 11 port control and interrupts prt 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 261 port x r n iel escritions continue fiel escrition r lew rate nale lew rate coniuration is ali in all iital in uxin oes fast slew rate is coniure on the corresonin in i in is coniure as a iital outut low slew rate is coniure on the corresonin in i in is coniure as a iital outut ull nale ull coniuration is ali in all iital in uxin oes nternal ullu or ullown resistor is not enale on the corresonin in nternal ullu or ullown resistor is enale on the corresonin in roie in is coniure as a iital inut ull elect ull coniuration is ali in all iital in uxin oes nternal ullown resistor is enale on the corresonin in i the corresonin ort ull nale reister it is set nternal ullu resistor is enale on the corresonin in i the corresonin ort ull nale reister it is set loal in ontrol low reister or x lr resses: orlr is h ase h oset h orlr is h ase h oset h orlr is h ase h oset h orlr is h ase h oset h orlr is h ase h oset h it r reset or x lr iel escritions fiel escrition loal in rite nale hen set causes its : o the corresonin in ontrol reister throuh to uate with the alue in the loal in rite ata iel loal in rite ata alue to e written to its : o all in ontrol reisters that are enale y the loal in rite nale iel roie the corresonin reister has not een loce eory a an reister einition ufaily reerence anual re o freescale eiconuctor nc 11.4.3 global pin control high register (port x hr resses: orhr is h ase h oset h orhr is h ase h oset h orhr is h ase h oset h orhr is h ase h oset h orhr is h ase h oset h it r reset or x hr iel escritions fiel escrition loal in rite nale hen set causes its : o the corresonin in ontrol reister throuh to uate with the alue in the loal in rite ata iel loal in rite ata alue to e written to its : o all in ontrol reisters that are enale y the loal in rite nale iel roie the corresonin reister has not een loce nterrut tatus fla reister or x fr the pin interrupt configuration is valid in all digital pin muxing modes. the interrupt status flag for each pin is also visible in the corresponding pin control register, and each flag can be cleared in either location. addresses: porta_isfr is 4004_9000h base + a0h offset = 4004_90a0h portb_isfr is 4004_a000h base + a0h offset = 4004_a0a0h portc_isfr is 4004_b000h base + a0h offset = 4004_b0a0h portd_isfr is 4004_c000h base + a0h offset = 4004_c0a0h porte_isfr is 4004_d000h base + a0h offset = 4004_d0a0h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r isf w w1c reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 chapter 11 port control and interrupts (port) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 263 port x fr iel escritions fiel escrition f nterrut tatus fla ach it in the iel inicates the etection o the coniure interrut o the sae nuer as the it oniure interrut has not een etecte oniure interrut has een etecte in is coniure to enerate a request then the corresonin la will e cleare autoatically at the coletion o the requeste transer otherwise the la reains set until a loic one is written to the la coniure or a leel sensitie interrut an the in reains asserte then the la will set aain ieiately ater it is cleare iital filter nale reister or x fr resses: orfr is h ase h oset h orfr is h ase h oset h orfr is h ase h oset h orfr is h ase h oset h orfr is h ase h oset h it r f reset or x fr iel escritions fiel escrition f iital filter nale he iital ilter coniuration is ali in all iital in uxin oes he outut o each iital ilter is reset to ero at syste reset an wheneer the iital ilter is isale iital filter is isale on the corresonin in an outut o the iital ilter is reset to eroach it in the iel enales the iital ilter o the sae nuer as the it iital filter is enale on the corresonin in roie in is coniure as a iital inut eory a an reister einition ufaily reerence anual re o freescale eiconuctor nc 11.4.6 digital filter clock register (port x fr resses: orfr is h ase h oset h orfr is h ase h oset h orfr is h ase h oset h orfr is h ase h oset h orfr is h ase h oset h it r reset or x fr iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero loc ource he iital ilter coniuration is ali in all iital in uxin oes oniures the cloc source or the iital inut ilters hanin the ilter cloc source shoul only e one ater isalin all enale iital ilters iital filters are cloce y the us cloc iital filters are cloce y the h lo cloc iital filter ith reister or x fr the digital filter configuration is valid in all digital pin muxing modes. addresses: porta_dfwr is 4004_9000h base + c8h offset = 4004_90c8h portb_dfwr is 4004_a000h base + c8h offset = 4004_a0c8h portc_dfwr is 4004_b000h base + c8h offset = 4004_b0c8h portd_dfwr is 4004_c000h base + c8h offset = 4004_c0c8h porte_dfwr is 4004_d000h base + c8h offset = 4004_d0c8h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 filt w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 chapter 11 port control and interrupts (port) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 265 port x fr iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero fl filter lenth he iital ilter coniuration is ali in all iital in uxin oes oniures the axiu sie o the litches in cloc cycles the iital ilter asors or enale iital ilters litches that are loner than this reister settin in cloc cycles will ass throuh the iital ilter while litches that are equal to or less than this reister settin in cloc cycles will e iltere hanin the ilter lenth shoul only e one ater isalin all enale ilters functional escrition in control the lower half of the pin control register configures the following functions for each pin within the 32-bit port. these functions apply across all digital pin muxing modes and individual peripherals do not override the configuration in this register (for example, if an i 2 c function is enabled on a pin then that does not override the pullup or open drain configuration for that pin). when the pin muxing mode is configured for analog/disabled then the all digital functions on that pin are disabled. this includes the pullup and pulldown enables, digital output buffer enable, digital input buffer enable and passive filter enable. ? pullup or pulldown enable ? drive strength and slew rate configuration ? open drain enable ? passive input filter enable ? pin muxing mode a lock bit also exists that allows the configuration for each pin to be locked until the next system reset. once locked, writes to the lower half of that pin control register are ignored, although a bus error is not generated on an attempted write to a locked register. the configuration of each pin control register is retained when the port module is disabled. functional description k60 sub-family reference manual, rev. 6, nov 2011 266 freescale semiconductor, inc. 11.5.2 global pin control the two global pin control registers allow a single register write to update the lower half of the pin control register on up to sixteen pins, all with the same value. registers that are locked cannot be written using the global pin control registers. the global pin control registers are designed to enable software to quickly configure multiple pins within the one port for the same peripheral function. note however that interrupt functions are unable to be configured using the global pin control registers. the global pin control registers are write only registers, that always read as zero. 11.5.3 external interrupts the external interrupt capability of the port module are available in all digital pin muxing modes provided the port module is enabled. each pin can be individually configured for any of the following external interrupt modes: ? interrupt disabled (default out of reset) ? active high level sensitive interrupt ? active low level sensitive interrupt ? rising edge sensitive interrupt ? falling edge sensitive interrupt ? rising and falling edge sensitive interrupt ? rising edge sensitive dma request ? falling edge sensitive dma request ? rising and falling edge sensitive dma request the interrupt status flag is set when the configured edge or level is detected on the output of the digital filter (if enabled) or pin (if digital filter is bypassed). when not in stop mode, the input is first synchronized to the bus clock to detect the configured level or edge transition. the port module generates a single interrupt that asserts when the interrupt status flag is set for any enabled interrupt for that port. the interrupt negates once the interrupt status flags for all enabled interrupts have been cleared. the port module generates a single dma request that asserts when the interrupt status flag is set for any enabled dma request in that port. the dma request negates once the dma transfer has been completed, since that clears the interrupt status flags for all enabled dma requests. chapter 11 port control and interrupts (port) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 267 during stop mode, the interrupt status flag for any enabled interrupt (but not dma request) will asynchronously set if the required level or edge is detected. this also generates an asynchronous wakeup signal to exit the low power mode. 11.5.4 digital filter the digital filter capabilities of the port module are available in all digital pin muxing modes provided the port module is enabled. the clock used for all digital filters within the one port can be configured between the bus clock or the 1 khz lpo clock. this selection should be changed only when all digital filters for that port are disabled. if the digital filters for a port are configured to use the bus clock, then the digital filters are bypassed (and do not update) during stop mode. the filter width in clock size is the same for all enabled digital filters within the one port and should be changed only when all digital filters for that port are disabled. the output of each digital filter is logic zero after system reset and whenever a digital filter is disabled. once a digital filter is enabled, the input is synchronized to the filter clock (either the bus clock or the 1 khz lpo clock). if the synchronized input and the output of the digital filter remain different for a number of filter clock cycles equal to the filter width register configuration, then the output of the digital filter updates to equal the synchronized filter input. the minimum latency through a digital filter equals two or three filter clock cycles plus the filter width configuration register. functional description k60 sub-family reference manual, rev. 6, nov 2011 268 freescale semiconductor, inc. chapter 12 system integration module (sim) 12.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the system integration module (sim) provides system control and chip configuration registers. 12.1.1 features ? configuration for system clocking ? clock source selection for sdhc, i 2 s, ethernet timestamp, usb, and pll/fll source ? system clock divide values ? i 2 s and usb clock divide values ? architectural clock gating control ? flash configuration ? usb regulator configuration ? ram size configuration ? flextimer external clock and fault source selection ? uart0 and uart1 receive/transmit source selection/configuration ? reset pin filtering 12.1.2 modes of operation ? run mode ? sleep mode k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 269 ? deep sleep mode ? vlls mode 12.1.3 sim signal descriptions table 12-1. sim signal descriptions signa l description i/o ezp_ cs ezport mode select i 12.1.3.1 detailed signal description table 12-2. sim interface-detailed signal descriptions signal i/o description ezp_cs i ezport mode select state meaning assertion-0 - configure part for ezport mode negation- 1 - configure part for normal flash operation timing as a mode select, this signal is only recognized during reset although it can be asserted and negated at any time. assertion-may occur at any time; input may be asserted asynchronously to the system clock. negation-may occur at any time; input may be negated asynchronously to the system clock. 12.2 memory map and register definition the sim module contains many bitfields for selecting the clock source and dividers for various module clocks. see the clock distribution chapter for more information including block diagrams and clock definitions. note the sim_sopt1 register is located at a different base address than the other sim registers. memory map and register definition k60 sub-family reference manual, rev. 6, nov 2011 270 freescale semiconductor, inc. sim memory map absolute address (hex) register name width (in bits) access reset value section/ page 4004_7000 system options register 1 (sim_sopt1) 32 r/w undefined 12.2.1/272 4004_8004 system options register 2 (sim_sopt2) 32 r/w 0000_1000h 12.2.2/274 4004_800c system options register 4 (sim_sopt4) 32 r/w 0000_0000h 12.2.3/276 4004_8010 system options register 5 (sim_sopt5) 32 r/w 0000_0000h 12.2.4/279 4004_8014 system options register 6 (sim_sopt6) 32 r/w 0000_0000h 12.2.5/280 4004_8018 system options register 7 (sim_sopt7) 32 r/w 0000_0000h 12.2.6/281 4004_8024 system device identification register (sim_sdid) 32 r undefined 12.2.7/283 4004_8028 system clock gating control register 1 (sim_scgc1) 32 r/w 0000_0000h 12.2.8/284 4004_802c system clock gating control register 2 (sim_scgc2) 32 r/w 0000_0000h 12.2.9/285 4004_8030 system clock gating control register 3 (sim_scgc3) 32 r/w 0000_0000h 12.2.10/ 286 4004_8034 system clock gating control register 4 (sim_scgc4) 32 r/w 6010_0030h 12.2.11/ 287 4004_8038 system clock gating control register 5 (sim_scgc5) 32 r/w 0004_0180h 12.2.12/ 290 4004_803c system clock gating control register 6 (sim_scgc6) 32 r/w 4000_0001h 12.2.13/ 292 4004_8040 system clock gating control register 7 (sim_scgc7) 32 r/w 0000_0007h 12.2.14/ 294 4004_8044 system clock divider register 1 (sim_clkdiv1) 32 r/w undefined 12.2.15/ 295 4004_8048 system clock divider register 2 (sim_clkdiv2) 32 r/w 0000_0000h 12.2.16/ 298 4004_804c flash configuration register 1 (sim_fcfg1) 32 r undefined 12.2.17/ 299 4004_8050 flash configuration register 2 (sim_fcfg2) 32 r undefined 12.2.18/ 301 4004_8054 unique identification register high (sim_uidh) 32 r undefined 12.2.19/ 302 4004_8058 unique identification register mid-high (sim_uidmh) 32 r undefined 12.2.20/ 303 4004_805c unique identification register mid low (sim_uidml) 32 r undefined 12.2.21/ 303 4004_8060 unique identification register low (sim_uidl) 32 r undefined 12.2.22/ 304 chapter 12 system integration module (sim) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 271 12.2.1 system options register 1 (sim_sopt1) the reset value of the sopt1 register is as follows: exit from por and lvd: usbregen is set, usbstby is cleared, and osc32ksel is cleared. exit from vlls or other system reset: usbregen, usbstby and osc32ksel are unaffected address: sim_sopt1 is 4004_7000h base + 0h offset = 4004_7000h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r usbregen usbstby reserved 0 ms 0 osc32ksel 0 w reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r ramsize 0 w reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes: x = undefined at reset. sim_sopt1 field descriptions field description 31 usbregen usb voltage regulator enable controls whether the usb voltage regulator is enabled. 0 usb voltage regulator is disabled. 1 usb voltage regulator is enabled. 30 usbstby usb voltage regulator in standby mode controls whether the usb voltage regulator is placed in standby mode. 0 usb voltage regulator not in standby. 1 usb voltage regulator in standby. 29?27 reserved this field is reserved. 26?24 reserved this read-only field is reserved and always has the value zero. 23 ms ezport chip select pin state reflects the state of the ezport chip select ( ezp_cs) pin during the last reset. this bit is read-only. table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 272 freescale semiconductor, inc. sim_sopt1 field descriptions (continued) field description 2220 reserved this read-only field is reserved and always has the value zero. 19 osc32ksel 32k oscillator clock select selects the 32 khz clock source (erclk32k) for tsi and lptmr. this bit is reset only for por/lvd. 0 system oscillator (osc32kclk) 1 rtc oscillator 1816 reserved this read-only field is reserved and always has the value zero. 1512 ramsize ram size this field specifies the amount of system ram available on the device. 0000 undefined 0001 undefined 0010 undefined 0011 undefined 0100 undefined 0101 32 kbytes 0110 undefined 0111 64 kbytes 1000 96 kbytes 1001 128 kbytes 1010 undefined 1011 undefined 1100 undefined 1101 undefined 1110 undefined 1111 undefined 110 reserved this read-only field is reserved and always has the value zero. chapter 12 system integration module (sim) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 273 12.2.2 system options register 2 (sim_sopt2) sopt2 contains the controls for selecting many of the module clock source options on this device. see the clock distribution chapter for more information including clocking diagrams and definitions of device clocks. address: sim_sopt2 is 4004_7000h base + 1004h offset = 4004_8004h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 sdhcsrc 0 i2ssrc 0 timesrc 0 usbsrc 0 pllfllsel w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 traceclksel cmtuartpad 0 fbsl 0 mcgclksel w reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 sim_sopt2 field descriptions field description 31?30 reserved this read-only field is reserved and always has the value zero. 29?28 sdhcsrc sdhc clock source select selects the clock source for the sdhc clock. 00 core/system clock. 01 mcgpllclk/mcgfllclk clock 10 oscerclk clock 11 external bypass clock (sdhc0_clkin) 27?26 reserved this read-only field is reserved and always has the value zero. 25?24 i2ssrc i2s master clock source select selects the clock source for i 2 s master clock. 00 core/system clock divided by the i 2 s fractional clock divider. see the sim_clkdiv2[i2sfrac, i2sdiv] descriptions. 01 mcgpllclk/mcgfllclk clock divided by the i 2 s fractional clock divider. see the sim_clkdiv2[i2sfrac, i2sdiv] descriptions. table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 274 freescale semiconductor, inc. sim_sopt2 field descriptions (continued) field description 10 oscerclk clock 11 external bypass clock (i2s0_clkin) 2322 reserved this read-only field is reserved and always has the value zero. 2120 timesrc ieee 1588 timestamp clock source select selects the clock source for the ethernet timestamp clock. 00 core/system clock. 01 mcgpllclk/mcgfllclk clock 10 oscerclk clock 11 external bypass clock (enet_1588_clkin). 19 reserved this read-only field is reserved and always has the value zero. 18 usbsrc usb clock source select selects the clock source for the usb 48 mhz clock. 0 external bypass clock (usb_clkin). 1 mcgpllclk/mcgfllclk clock divided by the usb fractional divider. see the sim_clkdiv2[usbfrac, usbdiv] descriptions. 17 reserved this read-only field is reserved and always has the value zero. 16 pllfllsel pll/fll clock select selects the mcgpllclk or mcgfllclk clock for various peripheral clocking options. 0 mcgfllclk clock 1 mcgpllclk clock 1513 reserved this read-only field is reserved and always has the value zero. 12 traceclksel debug trace clock select selects the core/system clock or mcg output clock (mcgoutclk) as the trace clock source. 0 mcgoutclk 1 core/system clock 11 cmtuartpad cmt/uart pad drive strength controls the output drive strength of the cmt iro signal or uart0_txd signal on ptd7 pin by selecting either one or two pads to drive it. 0 single-pad drive strength for cmt iro or uart0_txd. 1 dual-pad drive strength for cmt iro or uart0_txd. 10 reserved this read-only field is reserved and always has the value zero. 98 fbsl flexbus security level table continues on the next page... chapter 12 system integration module sim 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 27 sim_sopt2 field descriptions (continued) field description if flash security is enabled, then this field affects what cpu operations can access off-chip via the flexbus interface. this field has no effect if flash security is not enabled. 00 all off-chip accesses (instruction and data) via the flexbus are disallowed. 01 all off-chip accesses (instruction and data) via the flexbus are disallowed. 10 off-chip instruction accesses are disallowed. data accesses are allowed. 11 off-chip instruction accesses and data accesses are allowed. 71 reserved this read-only field is reserved and always has the value zero. 0 mcgclksel mcg clock select selects the mcgs external reference clock. 0 system oscillator (oscclk) 1 32 khz rtc oscillator 12.2.3 system options register 4 (sim_sopt4) address: sim_sopt4 is 4004_7000h base + 100ch offset = 4004_800ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 ftm2clksel ftm1clksel ftm0clksel 0 ftm2ch0src ftm1ch0src 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 ftm2flt0 0 ftm1flt0 0 ftm0flt2 ftm0flt1 ftm0flt0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sim_sopt4 field descriptions field description 3127 reserved this read-only field is reserved and always has the value zero. 26 ftm2clksel flextimer 2 external clock pin select selects the external pin used to drive the clock to the ftm2 module. table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 276 freescale semiconductor, inc. sim_sopt4 field descriptions (continued) field description note: the selected pin must also be configured for the ftm2 module external clock function through the appropriate pin control register in the port control module. 0 ftm2 external clock driven by ftm_clk0 pin. 1 ftm2 external clock driven by ftm_clk1 pin. 25 ftm1clksel ftm1 external clock pin select selects the external pin used to drive the clock to the ftm1 module. note: the selected pin must also be configured for the ftm external clock function through the appropriate pin control register in the port control module. 0 ftm_clk0 pin 1 ftm_clk1 pin 24 ftm0clksel flextimer 0 external clock pin select selects the external pin used to drive the clock to the ftm0 module. note: the selected pin must also be configured for the ftm external clock function through the appropriate pin control register in the port control module. 0 ftm_clk0 pin 1 ftm_clk1 pin 2322 reserved this read-only field is reserved and always has the value zero. 2120 ftm2ch0src ftm2 channel 0 input capture source select selects the source for ftm2 channel 0 input capture. note: when the ftm is not in input capture mode, clear this field. 00 ftm2_ch0 signal 01 cmp0 output 10 cmp1 output 11 reserved 1918 ftm1ch0src ftm1 channel 0 input capture source select selects the source for ftm1 channel 0 input capture. note: when the ftm is not in input capture mode, clear this field. 00 ftm1_ch0 signal 01 cmp0 output 10 cmp1 output 11 reserved 179 reserved this read-only field is reserved and always has the value zero. 8 ftm2flt0 ftm2 fault 0 select selects the source of ftm2 fault 0. table continues on the next page... chapter 12 system integration module sim 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 277 sim_sopt4 field descriptions (continued) field description note: the pin source for fault 0 must be configured for the ftm module fault function through the appropriate portx pin control register. 0 ftm2_flt0 pin 1 cmp0 out 75 reserved this read-only field is reserved and always has the value zero. 4 ftm1flt0 ftm1 fault 0 select selects the source of ftm1 fault 0. note: the pin source for fault 0 must be configured for the ftm module fault function through the appropriate pin control register in the port control module. 0 ftm1_flt0 pin 1 cmp0 out 3 reserved this read-only field is reserved and always has the value zero. 2 ftm0flt2 ftm0 fault 2 select selects the source of ftm0 fault 2. note: the pin source for fault 2 must be configured for the ftm module fault function through the appropriate pin control register in the port control module. 0 ftm0_flt2 pin 1 cmp2 out 1 ftm0flt1 ftm0 fault 1 select selects the source of ftm0 fault 1. note: the pin source for fault 1 must be configured for the ftm module fault function through the appropriate pin control register in the port control module. 0 ftm0_flt1 pin 1 cmp1 out 0 ftm0flt0 ftm0 fault 0 select selects the source of ftm0 fault 0. note: the pin source for fault 0 must be configured for the ftm module fault function through the appropriate pin control register in the port control module. 0 ftm0_flt0 pin 1 cmp0 out memory map and register definition k60 sub-family reference manual, rev. 6, nov 2011 278 freescale semiconductor, inc. 12.2.4 system options register 5 (sim_sopt5) address: sim_sopt5 is 4004_7000h base + 1010h offset = 4004_8010h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 uart1rxsrc uarttxsrc uart0rxsrc uart0txsrc w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sim_sopt5 field descriptions field description 318 reserved this read-only field is reserved and always has the value zero. 76 uart1rxsrc uart 1 receive data source select selects the source for the uart 1 receive data. 00 uart1_rx pin 01 cmp0 10 cmp1 11 reserved 54 uarttxsrc uart 1 transmit data source select selects the source for the uart 1 transmit data. 00 uart1_tx pin 01 uart1_tx pin modulated with ftm1 channel 0 output 10 uart1_tx pin modulated with ftm2 channel 0 output 11 reserved 32 uart0rxsrc uart 0 receive data source select selects the source for the uart 0 receive data. 00 uart0_rx pin 01 cmp0 10 cmp1 11 reserved 10 uart0txsrc uart 0 transmit data source select selects the source for the uart 0 transmit data. 00 uart0_tx pin 01 uart0_tx pin modulated with ftm1 channel 0 output table continues on the next page... chapter 12 system integration module sim 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 27 sim_sopt5 field descriptions (continued) field description 10 uart0_tx pin modulated with ftm2 channel 0 output 11 reserved 12.2.5 system options register 6 (sim_sopt6) the reset values of the rstflten and rstfltsel bits are for power-on reset only. they are unaffected by other reset types. address: sim_sopt6 is 4004_7000h base + 1014h offset = 4004_8014h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r rstflten rstfltsel 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sim_sopt6 field descriptions field description 31?29 rstflten reset pin filter enable selects how the reset pin filter is enabled. see reset pin filter for more details. 000 all filtering disabled 001 bus clock filter enabled in normal operation. lpo clock filter enabled in stop mode. 010 lpo clock filter enabled 011 bus clock filter enabled in normal operation. all filtering disabled in stop mode. 100 lpo clock filter enabled in normal operation. all filtering disabled in stop mode. 101 reserved (all filtering disabled) 110 reserved (all filtering disabled) 111 reserved (all filtering disabled) 28?24 rstfltsel reset pin filter select selects the reset pin bus clock filter count value. the filter count value is the rstfl value + 1. 23?0 reserved this read-only field is reserved and always has the value zero. memory map and register definition k60 sub-family reference manual, rev. 6, nov 2011 280 freescale semiconductor, inc. 12.2.6 system options register 7 (sim_sopt7) address: sim_sopt7 is 4004_7000h base + 1018h offset = 4004_8018h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r adc1alttrgen 0 adc1pretrgsel adc1trgsel adc0alttrgen 0 adc0pretrgsel adc0trgsel w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sim_sopt7 field descriptions field description 3116 reserved this read-only field is reserved and always has the value zero. 15 adc1alttrgen adc1 alternate trigger enable enable alternative conversion triggers for adc1. 0 pdb trigger selected for adc1 1 alternate trigger selected for adc1 as defined by adc1trgsel. 1413 reserved this read-only field is reserved and always has the value zero. 12 adc1pretrgsel adc1 pre-trigger select selects the adc1 pre-trigger source when alternative triggers are enabled through adc1alttrgen. 0 pre-trigger a selected for adc1. 1 pre-trigger b selected for adc1. 118 adc1trgsel adc1 trigger select selects the adc1 trigger source when alternative triggers are functional. note: not all trigger sources are available in stop and vlps modes. 0000 pdb external trigger pin input (pdb0_extrg) table continues on the next page... chapter 12 system integration module sim 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 281 sim_sopt7 field descriptions (continued) field description 0001 high speed comparator 0 output 0010 high speed comparator 1 output 0011 high speed comparator 2 output 0100 pit trigger 0 0101 pit trigger 1 0110 pit trigger 2 0111 pit trigger 3 1000 ftm0 trigger 1001 ftm1 trigger 1010 ftm2 trigger 1011 unused 1100 rtc alarm 1101 rtc seconds 1110 low-power timer trigger 1011 unused 7 adc0alttrgen adc0 alternate trigger enable enable alternative conversion triggers for adc0. 0 pdb trigger selected for adc0. 1 alternate trigger selected for adc0. 65 reserved this read-only field is reserved and always has the value zero. 4 adc0pretrgsel adc0 pretrigger select selects the adc0 pre-trigger source when alternative triggers are enabled through adc0alttrgen. 0 pre-trigger a 1 pre-trigger b 30 adc0trgsel adc0 trigger select selects the adc0 trigger source when alternative triggers are functional. note: not all trigger sources are available in stop and vlps modes. . 0000 pdb external trigger pin input (pdb0_extrg) 0001 high speed comparator 0 output 0010 high speed comparator 1 output 0011 high speed comparator 2 output 0100 pit trigger 0 0101 pit trigger 1 0110 pit trigger 2 0111 pit trigger 3 1000 ftm0 trigger 1001 ftm1 trigger 1010 ftm2 trigger 1011 unused 1100 rtc alarm table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 282 freescale semiconductor, inc. sim_sopt7 field descriptions (continued) field description 1101 rtc seconds 1110 low-power timer trigger 1011 unused 12.2.7 system device identification register (sim_sdid) address: sim_sdid is 4004_7000h base + 1024h offset = 4004_8024h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 revid 0 0 1 0 famid pinid w reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes: x = undefined at reset. ? sim_sdid field descriptions field description 3116 reserved this read-only field is reserved and always has the value zero. 1512 revid device revision number specifies the silicon implementation number for the device. 1110 reserved this read-only field is reserved and always has the value zero. 9 reserved this read-only field is reserved and always has the value zero. 8 reserved this read-only field is reserved and always has the value one. 7 reserved this read-only field is reserved and always has the value zero. 64 famid kinetis family identification specifies the kinetis family of the device. 000 k10 001 k20 010 k30 011 k40 100 k60 101 k70 110 k50 and k52 111 k51 and k53 table continues on the next page... chapter 12 system integration module sim 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 28 sim_sdid field descriptions (continued) field description 30 pinid pincount identification specifies the pincount of the device. 0000 reserved 0001 reserved 0010 32-pin 0011 reserved 0100 48-pin 0101 64-pin 0110 80-pin 0111 81-pin 1000 100-pin 1001 121-pin 1010 144-pin 1011 reserved 1100 196-pin 1101 reserved 1110 256-pin 1111 reserved 12.2.8 system clock gating control register 1 (sim_scgc1) address: sim_scgc1 is 4004_7000h base + 1028h offset = 4004_8028h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 uart4 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sim_scgc1 field descriptions field description 3125 reserved this read-only field is reserved and always has the value zero. 24 reserved this read-only field is reserved and always has the value zero. 2322 reserved this read-only field is reserved and always has the value zero. 21 reserved this read-only field is reserved and always has the value zero. 2012 reserved this read-only field is reserved and always has the value zero. table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 284 freescale semiconductor, inc. sim_scgc1 field descriptions (continued) field description 11 reserved this read-only field is reserved and always has the value zero. 10 uart4 uart4 clock gate control this bit controls the clock gate to the uart4 module. 0 clock disabled 1 clock enabled 90 reserved this read-only field is reserved and always has the value zero. 12.2.9 system clock gating control register 2 (sim_scgc2) address: sim_scgc2 is 4004_7000h base + 102ch offset = 4004_802ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 dac0 0 enet w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sim_scgc2 field descriptions field description 3114 reserved this read-only field is reserved and always has the value zero. 13 reserved this read-only field is reserved and always has the value zero. 12 dac0 dac0 clock gate control this bit controls the clock gate to the dac0 module. 0 clock disabled 1 clock enabled 111 reserved this read-only field is reserved and always has the value zero. 0 enet enet clock gate control this bit controls the clock gate to the enet module. 0 clock disabled 1 clock enabled chapter 12 system integration module (sim) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 285 12.2.10 system clock gating control register 3 (sim_scgc3) address: sim_scgc3 is 4004_7000h base + 1030h offset = 4004_8030h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 adc1 0 ftm2 0 sdhc 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 spi2 0 flexcan1 0 rngb w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sim_scgc3 field descriptions field description 31 reserved this read-only field is reserved and always has the value zero. 30 reserved this read-only field is reserved and always has the value zero. 2928 reserved this read-only field is reserved and always has the value zero. 27 adc1 adc1 clock gate control this bit controls the clock gate to the adc1 module. 0 clock disabled 1 clock enabled 2625 reserved this read-only field is reserved and always has the value zero. 24 ftm2 ftm2 clock gate control this bit controls the clock gate to the ftm2 module. 0 clock disabled 1 clock enabled 2318 reserved this read-only field is reserved and always has the value zero. 17 sdhc sdhc clock gate control this bit controls the clock gate to the sdhc module. table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 286 freescale semiconductor, inc. sim_scgc3 field descriptions (continued) field description 0 clock disabled 1 clock enabled 1613 reserved this read-only field is reserved and always has the value zero. 12 spi2 spi2 clock gate control this bit controls the clock gate to the spi2 module. 0 clock disabled 1 clock enabled 115 reserved this read-only field is reserved and always has the value zero. 4 flexcan1 flexcan1 clock gate control this bit controls the clock gate to the flexcan1 module. 0 clock disabled 1 clock enabled 31 reserved this read-only field is reserved and always has the value zero. 0 rngb rngb clock gate control this bit controls the clock gate to the rngb module. 0 clock disabled 1 clock enabled 12.2.11 system clock gating control register 4 (sim_scgc4) address: sim_scgc4 is 4004_7000h base + 1034h offset = 4004_8034h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 1 llwu 0 vref cmp usbotg 0 w reset 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 uart3 uart2 uart1 uart0 0 i2c1 i2c0 1 0 cmt ewm 0 w reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 chapter 12 system integration module (sim) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 287 sim_scgc4 field descriptions field description 31 reserved this read-only field is reserved and always has the value zero. 3029 reserved this read-only field is reserved and always has the value one. 28 llwu llwu clock gate control this bit controls the clock gate to the llwu module. 0 clock disabled 1 clock enabled 2721 reserved this read-only field is reserved and always has the value zero. 20 vref vref clock gate control this bit controls the clock gate to the vref module. 0 clock disabled 1 clock enabled 19 cmp comparator clock gate control this bit controls the clock gate to the comparator module. 0 clock disabled 1 clock enabled 18 usbotg usb clock gate control this bit controls the clock gate to the usb module. 0 clock disabled 1 clock enabled 1714 reserved this read-only field is reserved and always has the value zero. 13 uart3 uart3 clock gate control this bit controls the clock gate to the uart3 module. 0 clock disabled 1 clock enabled 12 uart2 uart2 clock gate control this bit controls the clock gate to the uart2 module. 0 clock disabled 1 clock enabled 11 uart1 uart1 clock gate control this bit controls the clock gate to the uart1 module. table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 288 freescale semiconductor, inc. sim_scgc4 field descriptions (continued) field description 0 clock disabled 1 clock enabled 10 uart0 uart0 clock gate control this bit controls the clock gate to the uart0 module. 0 clock disabled 1 clock enabled 98 reserved this read-only field is reserved and always has the value zero. 7 i2c1 i2c1 clock gate control this bit controls the clock gate to the i 2 c1 module. 0 clock disabled 1 clock enabled 6 i2c0 i2c0 clock gate control this bit controls the clock gate to the i 2 c0 module. 0 clock disabled 1 clock enabled 54 reserved this read-only field is reserved and always has the value one. 3 reserved this read-only field is reserved and always has the value zero. 2 cmt cmt clock gate control this bit controls the clock gate to the cmt module. 0 clock disabled 1 clock enabled 1 ewm ewm clock gate control this bit controls the clock gate to the ewm module. 0 clock disabled 1 clock enabled 0 reserved this read-only field is reserved and always has the value zero. chapter 12 system integration module (sim) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 289 12.2.12 system clock gating control register 5 (sim_scgc5) address: sim_scgc5 is 4004_7000h base + 1038h offset = 4004_8038h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 1 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 porte portd portc portb porta 1 0 tsi 0 regfile lptimer w reset 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 sim_scgc5 field descriptions field description 3119 reserved this read-only field is reserved and always has the value zero. 18 reserved this read-only field is reserved and always has the value one. 1714 reserved this read-only field is reserved and always has the value zero. 13 porte port e clock gate control this bit controls the clock gate to the port e module. 0 clock disabled 1 clock enabled 12 portd port d clock gate control this bit controls the clock gate to the port d module. 0 clock disabled 1 clock enabled 11 portc port c clock gate control this bit controls the clock gate to the port c module. 0 clock disabled 1 clock enabled 10 portb port b clock gate control this bit controls the clock gate to the port b module. table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 20 freescale semiconductor, inc. sim_scgc5 field descriptions (continued) field description 0 clock disabled 1 clock enabled 9 porta port a clock gate control this bit controls the clock gate to the port a module. 0 clock disabled 1 clock enabled 87 reserved this read-only field is reserved and always has the value one. 6 reserved this read-only field is reserved and always has the value zero. 5 tsi tsi clock gate control this bit controls the clock gate to the tsi module. 0 clock disabled 1 clock enabled 42 reserved this read-only field is reserved and always has the value zero. 1 regfile register file clock gate control this bit controls the clock gate to the register file module. 0 clock disabled 1 clock enabled 0 lptimer low power timer clock gate control this bit controls the clock gate to the low power timer module. 0 clock disabled 1 clock enabled chapter 12 system integration module (sim) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 291 12.2.13 system clock gating control register 6 (sim_scgc6) address: sim_scgc6 is 4004_7000h base + 103ch offset = 4004_803ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 1 rtc 0 adc0 0 ftm1 ftm0 pit pdb usbdcd 0 crc 0 w reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r i2s 0 spi1 spi0 0 flexcan0 0 dmamux ftfl w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 sim_scgc6 field descriptions field description 31 reserved this read-only field is reserved and always has the value zero. 30 reserved this read-only field is reserved and always has the value one. 29 rtc rtc clock gate control this bit controls the clock gate to the rtc module. 0 clock disabled 1 clock enabled 28 reserved this read-only field is reserved and always has the value zero. 27 adc0 adc0 clock gate control this bit controls the clock gate to the adc0 module. 0 clock disabled 1 clock enabled 26 reserved this read-only field is reserved and always has the value zero. 25 ftm1 ftm1 clock gate control this bit controls the clock gate to the ftm1 module. 0 clock disabled 1 clock enabled table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 22 freescale semiconductor, inc. sim_scgc6 field descriptions (continued) field description 24 ftm0 ftm0 clock gate control this bit controls the clock gate to the ftm0 module. 0 clock disabled 1 clock enabled 23 pit pit clock gate control this bit controls the clock gate to the pit module. 0 clock disabled 1 clock enabled 22 pdb pdb clock gate control this bit controls the clock gate to the pdb module. 0 clock disabled 1 clock enabled 21 usbdcd usb dcd clock gate control this bit controls the clock gate to the usb dcd module. 0 clock disabled 1 clock enabled 2019 reserved this read-only field is reserved and always has the value zero. 18 crc crc clock gate control this bit controls the clock gate to the crc module. 0 clock disabled 1 clock enabled 1716 reserved this read-only field is reserved and always has the value zero. 15 i2s i2s clock gate control this bit controls the clock gate to the i 2 s module. 0 clock disabled 1 clock enabled 14 reserved this read-only field is reserved and always has the value zero. 13 spi1 spi1 clock gate control this bit controls the clock gate to the spi1 module. 0 clock disabled 1 clock enabled table continues on the next page... chapter 12 system integration module sim 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 2 sim_scgc6 field descriptions (continued) field description 12 spi0 spi0 clock gate control this bit controls the clock gate to the spi0 module. 0 clock disabled 1 clock enabled 115 reserved this read-only field is reserved and always has the value zero. 4 flexcan0 flexcan0 clock gate control this bit controls the clock gate to the flexcan0 module. 0 clock disabled 1 clock enabled 32 reserved this read-only field is reserved and always has the value zero. 1 dmamux dma mux clock gate control this bit controls the clock gate to the dma mux module. 0 clock disabled 1 clock enabled 0 ftfl flash memory clock gate control this bit controls the clock gate to the flash memory. 0 clock disabled 1 clock enabled 12.2.14 system clock gating control register 7 (sim_scgc7) address: sim_scgc7 is 4004_7000h base + 1040h offset = 4004_8040h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 mpu dma flexbus w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 memory map and register definition k60 sub-family reference manual, rev. 6, nov 2011 294 freescale semiconductor, inc. sim_scgc7 field descriptions field description 313 reserved this read-only field is reserved and always has the value zero. 2 mpu mpu clock gate control this bit controls the clock gate to the mpu module. 0 clock disabled 1 clock enabled 1 dma dma clock gate control this bit controls the clock gate to the dma module. 0 clock disabled 1 clock enabled 0 flexbus flexbus clock gate control this bit controls the clock gate to the flexbus module. 0 clock disabled 1 clock enabled 12.2.15 system clock divider register 1 (sim_clkdiv1) the clkdiv1 register cannot be written to when the device is in vlpr mode. address: sim_clkdiv1 is 4004_7000h base + 1044h offset = 4004_8044h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r outdiv1 outdiv2 outdiv3 outdiv4 0 w reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes: x = undefined at reset. sim_clkdiv1 field descriptions field description 31?28 outdiv1 clock 1 output divider value this field sets the divide value for the core/system clock. at the end of reset, it is loaded with either 0000 or 0111 depending on ftfl_fopt[lpboot]. 0000 divide-by-1. 0001 divide-by-2. 0010 divide-by-3. 0011 divide-by-4. table continues on the next page... chapter 12 system integration module sim 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 2 sim_clkdiv1 field descriptions (continued) field description 0100 divide-by-5. 0101 divide-by-6. 0110 divide-by-7. 0111 divide-by-8. 1000 divide-by-9. 1001 divide-by-10. 1010 divide-by-11. 1011 divide-by-12. 1100 divide-by-13. 1101 divide-by-14. 1110 divide-by-15. 1111 divide-by-16. 2724 outdiv2 clock 2 output divider value this field sets the divide value for the peripheral clock. at the end of reset, it is loaded with either 0000 or 0111 depending on ftfl_fopt[lpboot]. 0000 divide-by-1. 0001 divide-by-2. 0010 divide-by-3. 0011 divide-by-4. 0100 divide-by-5. 0101 divide-by-6. 0110 divide-by-7. 0111 divide-by-8. 1000 divide-by-9. 1001 divide-by-10. 1010 divide-by-11. 1011 divide-by-12. 1100 divide-by-13. 1101 divide-by-14. 1110 divide-by-15. 1111 divide-by-16. 2320 outdiv3 clock 3 output divider value this field sets the divide value for the flexbus clock driven to the external pin (fb_clk). at the end of reset, it is loaded with either 0001 or 1111 depending on ftfl_fopt[lpboot]. 0000 divide-by-1. 0001 divide-by-2. 0010 divide-by-3. 0011 divide-by-4. 0100 divide-by-5. 0101 divide-by-6. 0110 divide-by-7. 0111 divide-by-8. 1000 divide-by-9. 1001 divide-by-10. table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 26 freescale semiconductor, inc. sim_clkdiv1 field descriptions (continued) field description 1010 divide-by-11. 1011 divide-by-12. 1100 divide-by-13. 1101 divide-by-14. 1110 divide-by-15. 1111 divide-by-16. 1916 outdiv4 clock 4 output divider value this field sets the divide value for the flash clock. at the end of reset, it is loaded with either 0001 or 1111 depending on ftfl_fopt[lpboot]. 0000 divide-by-1. 0001 divide-by-2. 0010 divide-by-3. 0011 divide-by-4. 0100 divide-by-5. 0101 divide-by-6. 0110 divide-by-7. 0111 divide-by-8. 1000 divide-by-9. 1001 divide-by-10. 1010 divide-by-11. 1011 divide-by-12. 1100 divide-by-13. 1101 divide-by-14. 1110 divide-by-15. 1111 divide-by-16. 150 reserved this read-only field is reserved and always has the value zero. chapter 12 system integration module (sim) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 297 12.2.16 system clock divider register 2 (sim_clkdiv2) address: sim_clkdiv2 is 4004_7000h base + 1048h offset = 4004_8048h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r i2sdiv 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r i2sfrac 0 usbdiv usbfrac w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sim_clkdiv2 field descriptions field description 3120 i2sdiv i2s clock divider value this field sets the divide value for when the fractional clock divider is used as the source for the i 2 s master clock. the clock input to the fractional clock divider is set by the sopt2[i2ssrc] bit. divider output clock = divider input clock ? [(i2sfrac+1) / (i2sdiv+1) ] note: the i2s clock must be disabled (scgc6[i2s] = 0) before altering this bitfield. 1916 reserved this read-only field is reserved and always has the value zero. 158 i2sfrac i2s clock divider fraction this field sets the multiply value for when the fractional clock divider is used as a the source for i 2 s master clock. the clock input to the fractional clock divider is set by the sopt2[i2ssrc] bit. divider output clock = divider input clock ? [(i2sfrac+1) / (i2sdiv+1) ] note: the i2s clock must be disabled (scgc6[i2s] = 0) before altering this bitfield. 74 reserved this read-only field is reserved and always has the value zero. 31 usbdiv usb clock divider divisor this field sets the divide value for the fractional clock divider when the mcgfllclk/mcgpllclk clock is the usb clock source (sopt2[usbsrc] = 1). divider output clock = divider input clock ? [ (usbfrac+1) / (usbdiv+1) ] 0 usbfrac usb clock divider fraction this field sets the fraction multiply value for the fractional clock divider when the mcgfllclk/ mcgpllclk clock is the usb clock source (sopt2[usbsrc] = 1). divider output clock = divider input clock ? [ (usbfrac+1) / (usbdiv+1) ] memory map and register definition k60 sub-family reference manual, rev. 6, nov 2011 298 freescale semiconductor, inc. 12.2.17 flash configuration register 1 (sim_fcfg1) for devices with flexnvm: the reset value of eesize and depart are based on user programming in user ifr via the pgmpart flash command. for devices with program flash only: the eesize and depart filelds are not applicable. address: sim_fcfg1 is 4004_7000h base + 104ch offset = 4004_804ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r nvmsize pfsize 0 eesize 0 depart 0 w reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes: x = undefined at reset. sim_fcfg1 field descriptions field description 31?28 nvmsize flexnvm size this field specifies the amount of flexnvm memory available on the device. undefined values are reserved. 0000 0 kb of flexnvm 0111 128 kb of flexnvm, 16 kb protection region 1001 256 kb of flexnvm, 32 kb protection region 1111 256 kb of flexnvm, 32 kb protection region 27?24 pfsize program flash size this field specifies the amount of program flash memory available on the device. undefined values are reserved. 0111 128 kb of program flash memory, 4 kb protection region 1001 256 kb of program flash memory, 8 kb protection region 1011 512 kb of program flash memory, 16 kb protection region 1111 for devices with flexnvm (sim_fcfg2[pflsh]=0): 256 kb of program flash, 8 kb protection region. for devices without flexnvm (sim_fcfg2[pflsh]=1): 512 kb of program flash memory, 16 kb protection region 23?20 reserved this read-only field is reserved and always has the value zero. 19?16 eesize eeprom size eeprom data size. for devices with flexnvm: this value is only valid with eeprom partitioning. 0000 reserved table continues on the next page... chapter 12 system integration module sim 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 2 sim_fcfg1 field descriptions (continued) field description 0001 reserved 0010 4 kb 0011 2 kb 0100 1 kb 0101 512 bytes 0110 256 bytes 0111 128 bytes 1000 64 bytes 1001 32 bytes 1010-1110 reserved 1111 0 bytes for devices without flexnvm: reserved 1512 reserved this read-only field is reserved and always has the value zero. 118 depart flexnvm partition for devices with flexnvm: data flash / eeprom backup split. see depart bit description in ftfl chapter. for devices without flexnvm: reserved 70 reserved this read-only field is reserved and always has the value zero. memory map and register definition k60 sub-family reference manual, rev. 6, nov 2011 300 freescale semiconductor, inc. 12.2.18 flash configuration register 2 (sim_fcfg2) address: sim_fcfg2 is 4004_7000h base + 1050h offset = 4004_8050h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r swappflsh 0 maxaddr0 pflsh 0 maxaddr1 w reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 w reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes: x = undefined at reset. ? sim_fcfg2 field descriptions field description 31 swappflsh swap program flash for devices without flexnvm: indicates that swap is active. 0 swap is not active. 1 swap is active. 30 reserved this read-only field is reserved and always has the value zero. 2924 maxaddr0 max address block 0 this field concatenated with 13 zeros indicates the first invalid address of flash block 0 (program flash 0). for example, if maxaddr0 = 0x20 the first invalid address of flash block 0 is 0x0004_0000. this would be the maxaddr0 value for a device with 256 kb program flash in flash block 0. 23 pflsh program flash for devices with flexnvm: indicates whether block 1 is program flash or flexnvm. table continues on the next page... chapter 12 system integration module sim 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 01 sim_fcfg2 field descriptions (continued) field description for devices without flexnvm: this bit is always set. 0 for devices with flexnvm: physical flash block 1 is used as flexnvm for devices without flexnvm: reserved 1 physical flash block 1 is used as program flash 22 reserved this read-only field is reserved and always has the value zero. 2116 maxaddr1 max address block 1 for devices with flexnvm: this field concatenated with 13 zeros plus the flexnvm base address indicates the first invalid address of the flexnvm (flash block 1). for example, if maxaddr1 = 0x20 the first invalid address of flash block 1 is 0x4_0000 + 0x1000_0000 . this would be the maxaddr1 value for a device with 256 kb flexnvm. for devices with program flash only: this field concatenated with 13 zeros plus the value of the maxaddr1 field indicates the first invalid address of the second program flash block (flash block 1). for example, if maxaddr0 = maxaddr1 = 0x20 the first invalid address of flash block 1 is 0x4_0000 + 0x4_0000. this would be the maxaddr1 value for a device with 512 kb program flash memory and no flexnvm. 150 reserved this read-only field is reserved and always has the value zero. 12.2.19 unique identification register high (sim_uidh) address: sim_uidh is 4004_7000h base + 1054h offset = 4004_8054h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r uid w reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes: x = undefined at reset. ? sim_uidh field descriptions field description 310 uid unique identification unique identification for the device. memory map and register definition k60 sub-family reference manual, rev. 6, nov 2011 302 freescale semiconductor, inc. 12.2.20 unique identification register mid-high (sim_uidmh) address: sim_uidmh is 4004_7000h base + 1058h offset = 4004_8058h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r uid w reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes: x = undefined at reset. ? sim_uidmh field descriptions field description 310 uid unique identification unique identification for the device. 12.2.21 unique identification register mid low (sim_uidml) address: sim_uidml is 4004_7000h base + 105ch offset = 4004_805ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r uid w reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes: x = undefined at reset. ? sim_uidml field descriptions field description 310 uid unique identification unique identification for the device. chapter 12 system integration module (sim) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 303 12.2.22 unique identification register low (sim_uidl) address: sim_uidl is 4004_7000h base + 1060h offset = 4004_8060h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r uid w reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes: x = undefined at reset. ? sim_uidl field descriptions field description 310 uid unique identification unique identification for the device. 12.3 functional description see introduction section. functional description k60 sub-family reference manual, rev. 6, nov 2011 304 freescale semiconductor, inc. chapter 13 mode controller 13.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. this section discusses the mode controller (mc) which controls power management and reset mechanisms including the various sources of resets on the device. the mc provides: ? control and protection on entry and exit to each power mode ? control for the power management controller (pmc) ? reset entry and exit for the complete mcu the device's operating power modes are described in this chapter. entry into each mode, exit from each mode, and functionality while in each of the modes are described. this chapter also discusses basic information about all reset sources in one place for easy reference. modules that cause resets (such as the watchdog and the low leakage wake up (llwu) modules) discuss the reset operation in their own chapters. 13.1.1 features ? power mode entry/exit and protection ? reset control features include: ? multiple sources of reset for flexible system configuration and reliable operation ? system reset status (srsh and srsl) registers to indicate source of most recent reset k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 305 13.1.2 modes of operation the arm cpu has three primary modes of operation: run, sleep, and deep sleep. the wfi instruction is used to invoke sleep and deep sleep modes. for freescale microcontrollers, run, wait and stop are the common terminology used for the primary operating modes. the following table shows the translation between the arm cpu and the mcu power modes. arm cpu mode mcu mode sleep wait deep sleep stop accordingly, the arm cpu documentation refers to sleep and deep sleep, while the freescale mcu documentation normally uses wait and stop. this device augments stop, wait, and run in a number of ways. the power management controller (pmc) contains a run and a stop mode regulator. run regulation is used in normal run, wait and stop modes. stop mode regulation is used during all very low power and low leakage modes. during stop mode regulation the bus frequencies are limited for the very low power modes. the pmc provides the user with multiple power options. the low power operating modes can drastically reduce run time power when maximum bus frequency is not required to handle the application needs. from normal run mode, the run mode (runm) bit field can be modified to change the the mcu into the very lower power run (vlpr) mode when limited frequency is required during the application. for the low power run mode, a corresponding wait and stop mode can be entered. depending on the needs of the user application, a variety of stop modes are available that allow the state retention, partial power down or full power down of certain logic and/or memory. i/o states are held in all modes of operation. several registers are used to configure the various modes of operation for the device. the following table describes the power modes available for the device. table 13-1. power modes mode description run mcu can be run at full speed and the internal supply is fully regulated (run regulation mode). this mode is also referred to as normal run mode. wait in arm architectures, the core clock to the arm cortex-m4 core is shut off. the system clock continues to operate; bus clocks if enabled continue to operate; run regulation is maintained. stop in arm architectures, core clock and system clock to the arm cortex-m4 core shut off immediately.system clock to other masters and bus clocks are stopped after all stop acknowledge signals from supporting peripherals are valid. table continues on the next page... introduction 60 sub-family reference manual, rev. 6, nov 2011 06 freescale semiconductor, inc. table 13-1. power modes (continued) mode description vlpr the core clock, system clock and bus clocks maximum frequency is restricted to 2mhz max, flash clock is restricted to 1mhz. the slow irc within the mcg must not be enabled when vlpr is entered. vlpw in arm architectures, the core clock to the arm cortex-m4 core is shut off. the system clock continues to operate; bus clocks if enabled continue to operate; system and bus clock restricted to 2mhz max, flash clock is restricted to 1mhz vlps in arm architectures, core clock and system clock to the arm cortex-m4 core shut off immediately. system clock to other masters and bus clocks are stopped after all stop acknowledge signals from supporting peripherals are valid. lls in arm architectures, core clock and system clock to the arm cortex-m4 core shut off immediately. system clock and bus clocks are stopped after all stop acknowledge signals from supporting peripherals are valid. mcu is placed in a low leakage mode by reducing the voltage to internal logic. internal logic states are retained. vlls3 in arm architectures, core clock and system clock to the arm cortex-m4 core shut off immediately. system clock to other masters and bus clocks are stopped after all stop acknowledge signals from supporting peripherals are valid. mcu is placed in a low leakage mode by powering down the internal logic. system ram contents retained and i/o states held. internal logic states are not retained. vlls2 in arm architectures, core clock and system clock to the arm cortex-m4 core shut off immediately. system clock to other masters and bus clocks are stopped after all stop acknowledge signals from supporting peripherals are valid. mcu is placed in a low leakage mode by powering down the internal logic and part of system ram. the rest of the system ram contents are retained and i/o states held. flexram contents can optionally be retained. internal logic states are not retained. note: see the devices chip configuration details for the amount of sram retained in vlls2 mode. vlls1 in arm architectures, core clock and system clock to the arm cortex-m4 core shut off immediately. system clock to other masters and bus clocks are stopped after all stop acknowledge signals from supporting peripherals are valid. mcu is placed in a low leakage mode by powering down the internal logic and all system ram. a 32-byte register file (available in all modes) contents retained and i/o states held. internal logic states are not retained. 13.1.2.1 power mode transitions the following shows the power mode state transitions available on the device. chapter 13 mode controller k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 307 wait stop run lls vlls 3, 2, 1 vlps vlpr vlpw any reset 4 6 7 3 1 2 8 10 11 9 5 figure 13-1. power mode state diagram the following table defines triggers for the various state transitions shown in the previous figure. table 13-2. power mode transition triggers transition # from to trigger conditions 1 run wait sleep-now or sleep-on-exit modes entered with sleepdeep clear, controlled in system control register in arm core. wait run interrupt or reset 2 run stop sleep-now or sleep-on-exit modes entered with sleepdeep set, controlled in system control register in arm core stop run interrupt or reset table continues on the next page... introduction 60 sub-family reference manual, rev. 6, nov 2011 08 freescale semiconductor, inc. table 13-2. power mode transition triggers (continued) transition # from to trigger conditions 3 run vlpr reduce system, bus and core frequency to 2 mhz or less, flash access limited to 1mhz. avlp=1, set runm = 10. note: poll vlprs bit before transitioning out of vlpr mode. vlpr run set runm = 00 or interrupt with lpwui =1 or reset. note: poll regons bit before increasing frequency. 4 vlpr vlpw sleep-now or sleep-on-exit modes entered with sleepdeep clear, controlled in system control register in arm core vlpw vlpr interrupt with lpwui = 0 5 vlpw run interrupt with lpwui = 1 or reset 6 vlpr vlps lpllsm=000 or 010, sleep-now or sleep-on-exit modes entered with sleepdeep set, controlled in system control register in arm core vlps vlpr interrupt with lpwui = 0 7 run vlps avlp=1, lpllsm=010, sleep-now or sleep-on-exit modes entered with sleepdeep set, controlled in system control register in arm core note: hardware will set lpwui and will remain set until software clears. vlps run interrupt with lpwui =1 or reset 8 run lls lpllsm=011, sleep-now or sleep-on-exit modes entered with sleepdeep set, controlled in system control register in arm core lls run wakeup from enabled llwu input source or reset pin 9 vlpr lls lpllsm=011, sleep-now or sleep-on-exit modes entered with sleepdeep set, controlled in system control register in arm core 10 run vlls(3,2,1) lpllsm = (see pmctrl register description for vlls configuration), sleep-now or sleep-on-exit modes entered with sleepdeep set, controlled in system control register in arm core vlls(3,2,1) run wakeup from enabled llwu input source or reset pin table continues on the next page... chapter 1 mode controller 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 0 table 13-2. power mode transition triggers (continued) transition # from to trigger conditions 11 vlpr vlls(3,2,1) lpllsm = (see pmctrl register description for vlls configuration), sleep-now or sleep-on-exit modes entered with sleepdeep set, controlled in system control register in arm core 13.1.2.2 run modes the device contains two different run modes: ? run ? very low power run (vlpr) 13.1.2.2.1 run mode this is the normal operating mode for the device. this mode is selected after any reset. when the arm processor exits reset, it sets up the stack, program counter (pc), and link register (lr): ? the processor reads the start sp (sp_main) from vector-table offset 0x000 ? the processor reads the start pc from vector-table offset 0x004 ? lr is set to 0xffff_ffff. to reduce power in this mode, disable unused modules by clearing the peripherals corresponding clock gating control bit in the sim's registers. 13.1.2.2.2 very low power run (vlpr) mode in vlpr, the on-chip voltage regulator is put into a stop mode regulation state. in this state, the regulator is designed to supply enough current to the mcu over a reduced frequency. to further reduce power in this mode, disable the clocks to unused modules in the peripherals' corresponding clock gating control bits in the sim's registers. before entering this mode, the following conditions must be met: ? one of two clock sources selected: ? either blpe is the selected clock mode for the mcg or ? blpi with the 2mhz irc. ? the system, bus, and core frequency is 2 mhz or less. ? flash frequency is 1 mhz or less. ? mode protection must be set to allow vlp modes (avlp = 1). introduction k60 sub-family reference manual, rev. 6, nov 2011 310 freescale semiconductor, inc. ? runm set to 10b to enter vlpr. ? flash programming/erasing is not allowed. ? the slow irc must not be enabled. ? all clock monitors must be disabled before entering vlpr. while in vlpr, the regulator is slow responding and cannot handle fast load transitions. therefore, do not change the clock frequency. this includes a requirement to not modify the module clock enables in the sim or any clock divider registers. to re-enter normal run mode, simply clear runm. the regons and vlprs bits in the regsc register are read-only status bits that indicate if the regulator is in run regulation mode or not: ? when regons is set, the regulator is in run regulation mode and the mcu can run at full speed in any clock mode. if a higher execution frequency is desired, poll regons until it is set when returning from vlpr. ? when vlprs is set, the system is fully in vlpr mode. note ? do not enter vlps, lls, or vllsx until the transition to vlpr completes as indicated by the vlprs bit. ? do not attempt to transition out of run mode until the regons bit sets. vlpr also provides the option to return to run regulation if any interrupt occurs. this is done by setting the low power wake up on interrupt (lpwui) bit in the pmctrl register. in the interrupt service routine (isr) it is not be necessary to poll the regons before increasing the frequency. the vlpr frequency limits are such that the regulator is in run regulation and regons is set before the isr is entered. any reset exits vlpr, clears runm, regons is set, and the device is in normal run mode after the cpu exits its reset flow. 13.1.2.3 wait modes this device contains two different wait modes: ? wait ? very low power wait chapter 13 mode controller k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 311 13.1.2.3.1 wait mode wait mode is entered when the arm core enters the sleep-now or sleep-on-exit modes. the arm cpu enters a low-power state in which it is not clocked, but peripherals continue to be clocked provided they are enabled and clock gating to the peripheral is enabled via the sim. when an interrupt request occurs, the cpu exits wait mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. an asserted reset pin or lvd (if the lvd system is enabled) exits wait mode, returning the device to normal run mode. 13.1.2.3.2 very low power wait (vlpw) mode vlpw is entered by the entering the sleep-now" or "sleep-on-exit mode while the mcu is in the very low power run (vlpr) mode and configured appropriately. in vlpw, the on-chip voltage regulator remains in its stop regulation state. in this state, the regulator is designed to supply enough current to the mcu over a reduced frequency. to further reduce power in this mode, disable the clocks to unused modules by clearing the peripherals' corresponding clock gating control bits in the sim. vlpr mode restrictions also apply to vlpw. vlpw mode provides the option to return to full-regulated normal run mode if any enabled interrupt occurs. this is done by setting the low power wake up on interrupt (lpwui) bit in the pmctrl register. wait for regons status to set before increasing the frequency. if the lpwui bit is clear when the interrupt from vlpw occurs, the device returns to vlpr mode to execute the interrupt service routine. wait for vlprs status to set before transitioning to other power modes. an asserted reset pin or a watchdog timeout exits vlpw and clears the runm and waite bits. this returns the regulator to run regulation and the device to normal run mode. 13.1.2.4 stop modes this device contains a variety of stop modes to meet your application needs. the stop modes range from: stopped cpu where all states are saved and certain asynchronous mode peripherals are operating to only i/os are held, a small register file is retained, and introduction k60 sub-family reference manual, rev. 6, nov 2011 312 freescale semiconductor, inc. certain asynchronous mode peripherals are operating with the remainer of the mcu powered off. the tradeoffs depend upon the user's application, where power usage and state retention versus functional needs are weighed. the various stop modes are selected by setting the appropriate bits in the power mode protection (pmprot) and power mode control (pmctrl) registers. the selected stop mode mode is entered during the sleep-now or sleep-on-exit entry with with the sleepdeep bit set in the system control register in the arm core. the available stop modes are: ? stop ? very low power stop (vlps) ? low leakage stop (lls) ? very low leakage stop 1 (vlls1) ? very low leakage stop 2 (vlls2) ? very low leakage stop 3 (vlls3) 13.1.2.4.1 stop mode stop mode is entered via the sleep-now or sleep-on-exit with the sleepdeep bit set in the system control register in the arm core. the mcg module can be configured to leave the reference clocks running. a module capable of providing an asynchronous interrupt to the device (for example, an enabled pin interrupt, nmi, rtc, lvw, uart wakeup on edge, cmp, or adc) takes the device out of stop mode and returns the device to normal run mode. reference table 13-1 for peripheral, i/o, and memory operation in stop. when an interrupt request occurs, the cpu exits stop mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. an asserted reset pin, a watchdog timeout, or lvd with lvdre set exits stop mode. the device returns to normal run mode via a mcu reset. 13.1.2.4.2 very low power stop (vlps) mode vlps mode can be entered in one of two ways: ? entry into stop via the sleep-now or sleep-on-exit with the sleepdeep bit set in the system control register in the arm core while the mcu is in very low power run (vlpr) mode and configured as per table 13-2 . ? when the mcu is in normal run mode with lpllsm set to 010b, entry into stop via the sleep-now or sleep-on-exit with the sleepdeep bit set in the system control chapter 13 mode controller k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 313 register in the arm core forces the mcu into vlps and hardware sets the lpwui bit set. in vlps, the on-chip voltage regulator remains in its stop regulation state as in vlpr. on transitions from vlpr to vlps with lpllsm set to 000b, hardware forces lpllsm to value of 010b. a module capable of providing an asynchronous interrupt to the device (for example, an enabled pin interrupt, nmi, rtc, uart wakeup on edge, cmp or adc) takes the device out of vlps and returns the device to vlpr provided the lpwui bit is clear. if lpwui is set, the device returns to normal run mode upon an interrupt request. the regons bit must be set before allowing the system to return to a frequency higher than allowed in vlpr. an asserted reset pin or a watchdog timeout causes vlps exit. this returns the device to normal run mode. 13.1.2.4.3 low-leakage stop (lls) mode low leakage stop (lls) mode can be entered from normal run or vlpr modes. the mcu enters lls mode if: ? in sleep-now or sleep-on-exit mode, the sleepdeep bit is set in the system control register in the arm core, and ? the device is configured as per table 13-2 . in lls, the on-chip voltage regulator is in stop regulation. most of the peripherals are put in a state-retention mode that does not allow them to operate while in lls. in lls, configure the low leakage wake up (llwu) module to enable the desired wakeup sources. the available wakeup sources in lls are detailed in the chip configuration details for this device. after wakeup from lls, the device returns to normal run mode with a pending llwu module interrupt. in the llwu interrupt service routine (isr) poll the llwu module wakeup flags to determine the source of the wakeup. note the llwu interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit stop mode on an lls recovery. an asserted reset pin exits lls. this returns the device to normal run mode. when lls is exiting via the reset pin, the pin and wakeup bits are set in the srsl register. introduction k60 sub-family reference manual, rev. 6, nov 2011 314 freescale semiconductor, inc. 13.1.2.4.4 very low-leakage stop (vlls3,2,1) modes this device contains three very low leakage modes: vlls3, vlls2, and vlls1. when a reference applies to all three low leakage modes, vlls is used. all three of the vlls modes can be entered from normal run or vlpr. the mcu enters the configured vlls mode if: ? in sleep-now or sleep-on-exit mode, the sleepdeep bit is set in the system control register in the arm core, and ? the device is configured as per table 13-2 . in vlls, the on-chip voltage regulator is in its stop-regulation state. in vlls, configure the llwu module to enable the desired wakeup sources. the available wakeup sources in vlls are detailed llwu's chip configuration details for this device. when entering vlls, each i/o pin is latched as configured before executing vlls. since all digital logic in the mcu is powered off, all port and peripheral data is lost during vlls. this information must be restored before ackiso in the llwu is set. an asserted reset pin exits any vlls mode. this returns the device to normal run mode. when exiting vlls via the reset pin, the pin and wakeup bits are set in the srsl register. 13.1.2.5 arm debug in low power modes when the mcu is secure the device disables/limits debugger operation. when the mcu is unsecure, the arm debugger can assert two power-up request signals: ? system power up (syspwr bit in the debug port control/stat register) ? debug power up (cdbgpwrupreq bit in the debug port control/stat register) when asserted while in run, wait, vlpr, or vlpw, the mode controller drives a corresponding acknowledge for each signal (cdbgpwrupack, csyspwrupack). when both requests are asserted, the mode controller handles attempts to enter stop and vlps by entering an emulated stop state. in this emulated stop state: ? the regulator is in stop regulation, ? the mcg-generated clock source is enabled, ? all system clocks, except core clock, are disabled, ? the debug module has access to core registers, and ? access to the on-chip peripherals is blocked. chapter 13 mode controller k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 315 no debug is available while the mcu is in lls or vlls modes. lls is a state-retention mode and all debug operation can continue after waking from lls, even in cases where system wakeup is due to a system reset event. entering into a vlls mode causes all the debug controls and settings to be powered off. to give time to the debugger to sync with the mcu, the mdm ap control register includes a very low leakage debug request (vlldbgreq) bit that is set to configure the mode controller logic to hold the system in reset after the next recovery from a vlls mode. this bit allows the debugger time to re-initialize the debug module before the debug session continues. the vlldbgreq bit clears automatically due to the reset generated as part of the vlls recovery. the mdm ap control register also includes a very low leakage debug acknowledge (vlldbgack) bit that is set to release the arm core being held in reset following a vlls recovery. the debugger re-initializes all debug ip and then asserts the vlldbgack control bit to allow the mode controller to release the arm core from reset and allow cpu operation to begin. the vlldbgack bit is cleared by the debugger (or can be left set as is) or clears automatically due to the reset generated as part of the next vlls recovery. 13.1.3 mcu reset resetting the mcu provides a way to start processing from a known set of initial conditions. when the arm processor exits reset, it sets up the stack, program counter (pc), and link register (lr). ? the processor reads the start sp (sp_main) from vector-table offset 0x000 ? the processor reads the start pc from vector-table offset 0x004 ? lr is set to 0xffff_ffff the device resets can be generalized into three distinct groups: por, system resets, and debug resets. por reset: ? power-on reset (por) system resets: ? external pin reset (pin) introduction k60 sub-family reference manual, rev. 6, nov 2011 316 freescale semiconductor, inc. ? computer operating properly (cop) timer ? clock generator (mcg) loss of clock reset (loc) ? low-voltage detect (lvd) ? wakeup from very low leakage stop modes, vllsx ? software reset (sw) - by setting sysresetreq bit of the nvic's application interrupt and reset control register ? lockup - core in lockup state ? ezport ? mdm ap reset - by setting system reset request bit of the mdm ap control register debug reset: ? asserting jtag_trst pin each of the system reset sources, with the exception of the ezport and mdm ap reset, has an associated bit in the system reset status low (srsl) register. 13.1.3.1 power-on reset (por) when power is initially applied to the device, or when the supply voltage drops below the power-on-reset re-arm voltage level (v por ), the por circuit causes a reset condition. as the supply voltage rises, the lvd circuit holds the mcu in reset until the supply rises above the lvd low threshold (v lvdl ). the por and lvd bits in srsl are set following a por. 13.1.3.2 external reset pin reset is a dedicated pin. this pin is open drain and has an internal pullup device. asserting reset resets the device from any run, wait, stop, vlp, lls, or vlls mode. when the reset pin is the cause of reset, the srsl[pin] bit is set. 13.1.3.3 computer operating properly (cop) timer reset the watchdog timer monitors the operation of the system by expecting periodic communication from the software. generally, this is known as servicing, or refreshing, the watchdog. if this periodic refreshing does not occur, the watchdog issues a system reset. when the watchdog timer expiration causes a reset, the srsl[cop] bit is set. chapter 13 mode controller k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 317 13.1.3.4 multi-clock generator (mcg) loss-of-clock (loc) reset the mcg module supports an external reference clock. if the clock monitor is enabled (mcg_c6[cme] is set) and the external reference falls below a certain frequency (specified in the mcg_c2[range] field), the mcu resets. if a loss of clock causes a reset, the srsl[loc] bit is set. for more details on the clock generator, see multi-clock generator (mcg) . 13.1.3.5 low-voltage detect (lvd) reset if lvdre is set, the lvd generates a reset upon detection of a low voltage condition. after an lvd reset has occurred, the lvd system holds the mcu in reset until the supply voltage rises above the lvd threshold (specified by the lvdv bits). the srsl[lvd] bit is set following an lvd reset or por. 13.1.3.6 low leakage mode recovery the llwu provides the means for up to 16 external pins, the reset pin, and seven internal peripherals to wake the device from lls and vlls power modes. when in vlls mode, all enabled inputs to the llwu will generate a system reset flow when detected. when in lls mode, only a detected reset pin results in a recovery via a reset flow. for lls mode exits via reset pin and any vlls mode via a wakeup or reset event, the mc_srs[wakeup] is set indicating a low-leakage mode was active prior to the last system reset flow. using the reset pin to trigger an exit from lls or vlls results in the mc_srs[pin] being set as well. after the system reset, the llwu continues to retain the flags indicating the source of wakeup until the user clears them or the next lls or vlls entry occurs. note external pin flags are cleared by software via the llwu registers and internal peripheral module flags are required to be cleared in associated peripheral's registers. refer to the individual peripheral chapters for more information. introduction k60 sub-family reference manual, rev. 6, nov 2011 318 freescale semiconductor, inc. 13.1.3.7 software (sw) reset setting the sysresetreq bit in the nvic's application interrupt and reset control register forces a software reset on the device. a software reset resets of all major components except for debug. when the device is reset by a software reset, the srsh[sw] bit is set. 13.1.3.8 lock-up reset when the processors built-in system state protection hardware detects the core is locked up because of an unrecoverable exception, a lock-up reset occurs. when a lock-up condition causes a reset, the srsh[lockup] bit is set. 13.1.3.9 ezport reset the ezport generates a system reset request following execution of a reset command via the ezport interface. this method of reset allows the chip to boot from flash memory after it has been programmed by an external source. 13.1.3.10 mdm-ap system reset request a system reset is initiated by setting the system reset request bit in the mdm-ap control register. this is the primary method for resets via the debug interface. system reset is held until this bit is cleared. 13.1.3.11 jtag reset the jtag module generates a system reset when certain ir codes are selected. this functional reset is asserted when the ezport, extest, highz and clamp instructions are active. the reset source from the jtag module is released when any other ir code is selected. a jtag reset causes the srsh[jtag] bit to set. 13.2 mode control memory map/register definition the following table shows the registers related to the mode controller. chapter 13 mode controller k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 319 mc memory map absolute address (hex) register name width (in bits) access reset value section/ page 4007_e000 system reset status register high (mc_srsh) 8 r/w 00h 13.2.1/320 4007_e001 system reset status register low (mc_srsl) 8 r/w 82h 13.2.2/321 4007_e002 power mode protection register (mc_pmprot) 8 r/w 00h 13.2.3/322 4007_e003 power mode control register (mc_pmctrl) 8 r/w 00h 13.2.4/324 13.2.1 system reset status register high (mc_srsh) the srsh:srsl registers include read-only status flags to indicate the source of the most recent reset. the reset state of these bits depends on what caused the mcu to reset. throughout this document, srs refers to srsh:srsl. note the reset value of this register depends on the reset type: ? por 0x00 ? lvd 0x00 ? low-leakage wake-up (lls exit via reset pin or any exit from vlls) 0x00 ? other reset bits 2-0 are set if their corresponding reset source caused the reset address: mc_srsh is 4007_e000h base + 0h offset = 4007_e000h bit 7 6 5 4 3 2 1 0 read 0 sw lockup jtag write reset 0 0 0 0 0 0 0 0 mc_srsh field descriptions field description 7?3 reserved this read-only field is reserved and always has the value zero. 2 sw software indicates reset was caused by software setting of sysresetreq bit in application interrupt and reset control register in the arm core 0 reset not caused by software setting of sysresetreq bit 1 reset caused by software setting of sysresetreq bit 1 lockup core lock-up table continues on the next page... mode control memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 20 freescale semiconductor, inc. mc_srsh field descriptions (continued) field description indicates reset was caused by the arm core indication of a lockup event. 0 reset not caused by core lockup event 1 reset caused by core lockup event 0 jtag jtag generated reset indicates reset was caused by jtag selection of certain ir codes (ezport, extest, highz, and clamp). 0 reset not caused by jtag 1 reset caused by jtag 13.2.2 system reset status register low (mc_srsl) the srsh:srsl registers includes read-only status flags to indicate the source of the most recent reset. the reset state of these bits depends on what caused the mcu to reset. throughout this document, srs refers to srsh:srsl. note the reset value of this register depends on the reset type: ? por 0x82 ? lvd 0x02 ? low-leakage wake-up due to reset pin assertion 0x41 ? low-leakage wake-up due to other wake-up sources 0x01 ? other reset bits 6-5 and 2 are set if their corresponding reset source caused the reset address: mc_srsl is 4007_e000h base + 1h offset = 4007_e001h bit 7 6 5 4 3 2 1 0 read por pin cop 0 loc lvd wakeup write reset 1 0 0 0 0 0 1 0 mc_srsl field descriptions field description 7 por power-on reset indicates a reset was caused by the power-on detection logic. because the internal supply voltage was ramping up at the time, the low-voltage reset (lvd) status bit is also set to indicate that the reset occurred while the internal supply was below the lvd threshold. table continues on the next page... chapter 1 mode controller 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 21 mc_srsl field descriptions (continued) field description 0 reset not caused by por 1 reset caused by por 6 pin external reset pin indicates reset was caused by an active-low level on the external resetpin. 0 reset not caused by external reset pin 1 reset caused by external reset pin 5 cop computer operating properly (cop) watchdog reset was caused by the cop watchdog timer timing out. this reset source can be blocked by disabling the watchdog. for more information, see the watchdog chapter. 0 reset not caused by cop timeout 1 reset caused by cop timeout 43 reserved this read-only field is reserved and always has the value zero. 2 loc loss-of-clock reset indicates reset was caused by a loss of external clock. the mcg clock monitor must be enabled for a loss of clock to be detected. see the mcg chapter for information on enabling the clock monitor. 0 reset not caused by a loss of external clock. 1 reset caused by a loss of external clock. 1 lvd low-voltage detect reset if the lvdre bit is set and the supply drops below the lvd trip voltage, an lvd reset occurs. this bit is also set by por. 0 reset not caused by lvd trip or por 1 reset caused by lvd trip or por 0 wakeup low-leakage wakeup reset reset was caused by an enabled llwu module wakeup source while the device was in lls or vlls modes. wakeup sources in lls is limited to the reset pin. in vlls, any enabled wakeup source causes a reset. this bit is cleared by any reset except wakeup. 0 reset not caused by llwu module wakeup source 1 reset caused by llwu module wakeup source 13.2.3 power mode protection register (mc_pmprot) this write-once register allows low power or low leakage modes to be entered. the actual enabling of the low power or low leakage modes is done by configuring the power mode control register (pmctrl). mode control memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 322 freescale semiconductor, inc. if the mcu is configured for a disallowed power mode, the mcu remains in its current power mode. for example, if in normal run (runm = 00, avlp = 0) an attempt to enter vlpr using pmctrl[runm] is blocked and the runm bits remain 00b indicating mcu is still in normal run mode. pmprot is write once after any reset. this write to pmprot clears lpllsm, which provides protection after wakeup from low power or low leakage modes. the state of lpllsm prior to clearing due to update of pmprot indicates which power mode was exited and should be used by initialization software for proper power mode recovery. note the reset value of this register depends on the reset type: ? low-leakage wake-up (lls exit via reset pin or any exit from vlls) bits 4, 2-0 unaffected ? other reset 0x00 address: mc_pmprot is 4007_e000h base + 2h offset = 4007_e002h bit 7 6 5 4 3 2 1 0 read 0 avlp alls 0 avlls3 avlls2 avlls1 write reset 0 0 0 0 0 0 0 0 mc_pmprot field descriptions field description 7?6 reserved this read-only field is reserved and always has the value zero. 5 avlp allow very low power modes provided the appropriate control bits are set up in pmctrl, this write-once bit allows the mcu to enter the very low power modes: vlpr, vlpw, and vlps. 0 vlpr, vlpw, and vlps are not allowed 1 vlpr, vlpw, and vlps are allowed 4 alls allow low leakage stop mode this write once bit allows the mcu to enter low leakage stop mode (lls) provided the appropriate control bits are set up in pmctrl. 0 lls is not allowed 1 lls is allowed 3 reserved this read-only field is reserved and always has the value zero. 2 avlls3 allow very low leakage stop 3 mode this write once bit allows the mcu to enter very low leakage stop 3 mode (vlls3) provided the appropriate control bits are set up in pmctrl. table continues on the next page... chapter 1 mode controller 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 2 mc_pmprot field descriptions (continued) field description 0 vlls3 is not allowed 1 vlls3 is allowed 1 avlls2 allow very low leakage stop 2 mode this write once bit allows the mcu to enter very low leakage stop 2 mode (vlls2) provided the appropriate control bits are set up in pmctrl. 0 vlls2 is not allowed 1 vlls2 is allowed 0 avlls1 allow very low leakage stop 1 mode this write once bit allows the mcu to enter very low leakage stop 1 mode (vlls1) provided the appropriate control bits are set up in pmctrl. 0 vlls1 is not allowed 1 vlls1 is allowed 13.2.4 power mode control register (mc_pmctrl) the pmctrl register is used to enter the wait, low power, or low leakage modes provided the selected power mode is allowed via appropriate setting of the protection register (pmprot). if the mcu is configured for a disallowed power mode or to a reserved runm setting, the device remains in its current power mode. for example, if in normal run (runm = 00, avlp = 0) an attempt to enter vlpr using the pmctrl[runm] bits is blocked and runm bits remain 00 indicating the device is still in normal run mode. before configuring the lpllsm bits, the corresponding allow bit in pmprot must be set. writes to lpllsm that do not meet this criteria are ignored. a successful write to pmprot clears the lpllsm bits. the state of pmctrl[lpllsm] prior to clearing due to update of pmprot indicates which power mode was exited and should be used by initialization software for proper power mode recovery. note the reset value of this register depends on the reset type: ? low-leakage wake-up (lls exit via reset pin or any exit from vlls) bits 2-0 unaffected ? other reset 0x00 mode control memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 324 freescale semiconductor, inc. address: mc_pmctrl is 4007_e000h base + 3h offset = 4007_e003h bit 7 6 5 4 3 2 1 0 read lpwui runm 0 lpllsm write reset 0 0 0 0 0 0 0 0 mc_pmctrl field descriptions field description 7 lpwui low power wake up on interrupt controls if the voltage regulator exits stop regulation when any active mcu interrupt occurs, returning the mcu to normal run mode. 0 the voltage regulator remains in stop regulation on an interrupt 1 the voltage regulator exits stop regulation on an interrupt 65 runm run mode enable this field is used to enter very low power run. writes to this field are blocked if the protection level has not been enabled using pmprot register. this field is cleared by hardware on exit from lls or vlls modes. 00 normal run mode 01 reserved 10 very low power run mode 11 reserved 43 reserved this read-only field is reserved and always has the value zero. 20 lpllsm low power, low leakage stop mode select low power or low leakage stop modes provided the pmprot was set properly and stop mode entry via the sleep-now or sleep-on-exit. after any system reset, writes to reconfigure pmprot clears lpllsm. 000 normal stop 001 reserved 010 very low power stop (vlps) 011 low leakage stop (lls) 100 reserved 101 very low leakage stop 3 (vlls3) 110 very low leakage stop 2 (vlls2) 111 very low leakage stop 1 (vlls1) chapter 13 mode controller k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 325 mode control memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 326 freescale semiconductor, inc. chapter 14 power management controller 14.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the pmc contains the internal voltage regulator, power on reset (por), and low voltage detect system. the mode controller controls the pmc and its chapter contains description of all device resets, including por. 14.2 features power management control features include: ? internal voltage regulator ? active por providing brown-out detect ? low-voltage detect protection including: ? multiple programmable trip voltages ? warning and detect interrupt control ? drive a reset on low voltage detect 14.3 low-voltage detect (lvd) system this device includes a system to protect against low-voltage conditions to protect memory contents and control mcu system states during supply voltage variations. the system is comprised of a power-on reset (por) circuit and a lvd circuit with a user- k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 327 selectable trip voltage: high (v lvdh ) or low (v lvdl ). the trip voltage is selected by the lvdsc1[lvdv] bits. the lvd is disabled upon entering vlpx, lls, and vllsx modes. two flags are available to indicate the status of the low-voltage detect system: ? the low voltage detect flag (lvdf) operates in a level sensitive manner. the lvdf bit is set when the internal supply voltage falls below the selected internal monitor trip point (vlvd). the lvdf bit is cleared by writing one to the lvdack bit, but only if the internal supply has returned above the internal trip point; otherwise, the lvdf bit remains set. ? the low voltage warning flag (lvwf) operates in a level sensitive manner. the lvwf bit is set when the internal supply voltage falls below the selected internal monitor trip point (vlvw). the lvwf bit is cleared by writing one to the lvwack bit, but only if the internal supply has returned above the internal trip point; otherwise, the lvwf bit remains set. 14.3.1 lvd reset operation by setting the lvdre bit, the lvd generates a reset upon detection of a low voltage condition. the low voltage detection threshold is determined by the lvdv bits. after an lvd reset occurs, the lvd system holds the mcu in reset until the supply voltage rises above this threshold. the lvd bit in the srs register is set following an lvd or power- on reset. 14.3.2 lvd interrupt operation by configuring the lvd circuit for interrupt operation (lvdie set and lvdre clear), lvdsc1[lvdf] is set and an lvd interrupt request occurs upon detection of a low voltage condition. the lvdf bit is cleared by writing one to the lvdsc1[lvdack] bit. 14.3.3 low-voltage warning (lvw) interrupt operation the lvd system contains a low voltage warning flag (lvwf) to indicate that the supply voltage is approaching, but is above, the lvd voltage. the lvw also has an interrupt, which is enabled by setting the lvdsc2[lvwie] bit. if enabled, an lvw interrupt request occurs when the lvwf is set. lvwf is cleared by writing one to the lvdsc2[lvwack] bit. low-voltage detect (lvd) system k60 sub-family reference manual, rev. 6, nov 2011 328 freescale semiconductor, inc. the lvdsc2[lvwv] bits select one of four trip voltages: ? highest (v lvw4 ) ? two mid-levels (v lvw3 and v lvw2 ) ? lowest (v lvw1 ) 14.4 pmc memory map/register definition the following table shows the registers related to the pmc. see mode control memory map/register definition for the mode controller registers. pmc memory map absolute address (hex) register name width (in bits) access reset value section/ page 4007_d000 low voltage detect status and control 1 register (pmc_lvdsc1) 8 r/w 10h 14.4.1/329 4007_d001 low voltage detect status and control 2 register (pmc_lvdsc2) 8 r/w 00h 14.4.2/330 4007_d002 regulator status and control register (pmc_regsc) 8 r/w 04h 14.4.3/332 14.4.1 low voltage detect status and control 1 register (pmc_lvdsc1) this register contains status and control bits to support the low voltage detect function. this register should be written during the reset initialization program to set the desired controls even if the desired settings are the same as the reset settings. while the device is in the very low power or low leakage modes, the lvd system is disabled regardless of lvdsc1 settings. to protect systems that must have lvd always on, configure the power mode protection register (pmprot) to disallow any very low power or low leakage modes from being enabled. see the device's data sheet for the exact lvd trip voltages. note the reset value of this register depends on the reset type: ? por -- 0x10 ? other reset -- bit 4 is set, bits 1-0 are unaffected chapter 14 power management controller k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 329 address: pmc_lvdsc1 is 4007_d000h base + 0h offset = 4007_d000h bit 7 6 5 4 3 2 1 0 read lvdf 0 lvdie lvdre 0 lvdv write lvdack reset 0 0 0 1 0 0 0 0 pmc_lvdsc1 field descriptions field description 7 lvdf low-voltage detect flag this read-only status bit indicates a low-voltage detect event. 0 low-voltage event not detected 1 low-voltage event detected 6 lvdack low-voltage detect acknowledge this write-only bit is used to acknowledge low voltage detection errors (write 1 to clear lvdf). reads always return 0. 5 lvdie low-voltage detect interrupt enable enables hardware interrupt requests for lvdf. 0 hardware interrupt disabled (use polling) 1 request a hardware interrupt when lvdf = 1. 4 lvdre low-voltage detect reset enable this write-once bit enables lvdf events to generate a hardware reset. additional writes are ignored. 0 lvdf does not generate hardware resets 1 force an mcu reset when lvdf = 1 32 reserved this read-only field is reserved and always has the value zero. 10 lvdv low-voltage detect voltage select selects the lvd trip point voltage (v lvd ). 00 low trip point selected (v lvd = v lvdl ) 01 high trip point selected (v lvd = v lvdh ) 10 reserved 11 reserved 14.4.2 low voltage detect status and control 2 register (pmc_lvdsc2) this register contains status and control bits to support the low voltage warning function. while the device is in the very low power or low leakage modes, the lvd system is disabled regardless of lvdsc2 settings. pmc memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 330 freescale semiconductor, inc. see the device's data sheet for the exact lvd trip voltages. note the lvw trip voltages depend on lvwv and lvdv bits. note the reset value of this register depends on the reset type: ? por -- 0x00 ? other reset -- bits 1-0 are unaffected address: pmc_lvdsc2 is 4007_d000h base + 1h offset = 4007_d001h bit 7 6 5 4 3 2 1 0 read lvwf 0 lvwie 0 lvwv write lvwack reset 0 0 0 0 0 0 0 0 pmc_lvdsc2 field descriptions field description 7 lvwf low-voltage warning flag this read-only status bit indicates a low-voltage warning event. lvwf is set when v supply transitions below the trip point or after reset and v supply is already below v lvw . 0 low-voltage warning event not detected 1 low-voltage warning event detected 6 lvwack low-voltage warning acknowledge this write-only bit is used to acknowledge low voltage warning errors (write 1 to clear lvwf). reads always return 0. 5 lvwie low-voltage warning interrupt enable enables hardware interrupt requests for lvwf. 0 hardware interrupt disabled (use polling) 1 request a hardware interrupt when lvwf = 1. 4?2 reserved this read-only field is reserved and always has the value zero. 1?0 lvwv low-voltage warning voltage select selects the lvw trip point voltage (v lvw ). the actual voltage for the warning depends on lvdsc1[lvdv]. 00 low trip point selected (v lvw = v lvw1h/l ) 01 mid 1 trip point selected (v lvw = v lvw2h/l ) 10 mid 2 trip point selected (v lvw = v lvw3h/l ) 11 high trip point selected (v lvw = v lvw4h/l ) chapter 14 power management controller k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 331 14.4.3 regulator status and control register (pmc_regsc) the power management controller contains an internal voltage regulator. the voltage regulator design uses a bandgap reference, that is also available through a buffer as input to certain internal peripherals. the internal regulator provides a status bit (regons) indicating the regulator is in run regulation. this bit is used when the application moves from a low power or very low power mode where the frequency is limited to normal run mode. the frequency of the application can not be increased until the regulator is back in run regulation (regons=1). address: pmc_regsc is 4007_d000h base + 2h offset = 4007_d002h bit 7 6 5 4 3 2 1 0 read 0 trampo vlprs regons bgbe write 0 reset 0 0 0 0 0 1 0 0 pmc_regsc field descriptions field description 7?5 reserved this read-only field is reserved and always has the value zero. 4 trampo for devices with flexnvm: traditional ram power option for devices with program flash only: reserved for devices with flexnvm: when the flexram on the device is configured for traditional ram, this bit enables powering of this ram in vlls2 mode. 0 for devices with flexnvm: traditional ram not powered in vlls2 for devices with program flash only: no effect 1 for devices with flexnvm: traditional ram powered in vlls2 for devices with program flash only: no effect 3 vlprs very low power run status this read only bit indicates the current run mode is vlpr. 0 mcu is not in vlpr mode 1 mcu is in vlpr mode 2 regons regulator in run regulation status this read-only bit provides the current status of the internal voltage regulator. 0 regulator is in stop regulation or in transition to/from it 1 regulator is in run regulation 1 reserved this field is reserved. table continues on the next page... pmc memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 2 freescale semiconductor, inc. pmc_regsc field descriptions (continued) field description 0 bgbe bandgap buffer enable enables the bandgap buffer. 0 bandgap buffer not enabled 1 bandgap buffer enabled chapter 14 power management controller k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 333 pmc memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 334 freescale semiconductor, inc. chapter 15 low-leakage wake-up unit (llwu) 15.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the llwu module allows the user to select up to 16 external pin sources and up to 7 internal modules as a wakeup source from low-leakage power modes (lls and vlls). the input sources vary by device and are described in the specific device's chip configuration details. each of the available wakeup sources can be individually enabled. the reset pin is an additional source for triggering an exit from low-leakage power modes and causes the mcu to exit both lls and vlls through a reset flow. on mcus where the reset pin is shared with other functions, the explicit port mux control register must be set for reset pin before the reset pin can be used as a low-leakage reset source. when in lls mode, the i/o are released immediately on a wakeup or reset event. in the case of lls exit via a reset pin, the i/o default to their reset state. when in vlls modes, the i/o states are held on a wakeup event until the wakeup has been acknowledged via a write to the ackiso bit. in the case of vlls exit via a reset pin, the i/o are released and default to their reset state. in this case, no write to the ackiso is needed. in both lls mode exits via reset pin and any vlls mode via a wakeup or reset event, the mc_srs[wakeup] is set indicating the low-leakage mode was active prior to the last system reset flow. using the reset pin to trigger an exit from lls or vlls results in the mc_srs[pin] being set as well. the llwu module also includes two optional digital pin filters. one for the external wakeup pins combined and one for the reset pin. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 335 15.1.1 features the llwu module features include: ? supports up to 16 external input pins and up to 7 internal modules with individual enable bits ? input sources may be external pins or from internal peripherals capable of running in lls or vlls. see the chip configuration details for wakeup input sources for this device. ? each external pin wakeup input is programmable as falling edge, rising edge, or any change ? each internal module wakeup input source qualified with programmable enable ? wakeup inputs are activated if enabled once mcu enters low leakage stop (lls) or very low leakage stop (vlls) modes ? reset exit due to assertion of reset pin via reset flow. i/o states are reset on exit ? wakeup from lls mode is handled as an interrupt. i/o states are released on exit ? wakeup exit via reset flow when mcu is in vlls. i/o states remain in held state until wakeup has been acknowledged. ? an optional digital filter provided to qualify an external pin detect and reset pin detect. 15.1.2 modes of operation the llwu module is only functional in lls and vlls modes. 15.1.2.1 lls mode the llwu module provides up to 16 external wakeup inputs and up to seven internal module wakeup inputs. in addition, an lls reset event can be initiated via assertion of the reset pin. wakeup events due to external wakeup inputs and internal module wakeup inputs result in an interrupt flow when exiting lls. a reset event due to reset pin assertion results in a reset flow when exiting lls. note the llwu interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit stop mode on an lls recovery. introduction k60 sub-family reference manual, rev. 6, nov 2011 336 freescale semiconductor, inc. 15.1.2.2 vlls modes the llwu module provides up to 16 external wakeup inputs and up to seven internal module wakeup inputs. in addition, a vlls reset event can be initiated via assertion of the reset pin. all wakeup and reset events result in vlls exit via a reset flow. 15.1.2.3 non-low leakage modes the llwu is not active in all non- lls and vlls modes where detection and control logic are in a static state. the llwu registers are accessible in non-lls and vlls modes and are available for configuring and reading status when bus transactions are possible. when the reset pin filter is enabled, filter operation begins immediately so that if lls or vlls modes are entered while the the filter logic has seen an active edge on the reset pin and is currently sensing for minimum assertion duration, there is no restart of pin filtering as reset filtering transitions from a non-low leakage filter operation (implemented external to llwu) to the reset pin filter circuit implemented in the llwu. 15.1.2.4 debug mode in debug mode, when lls/vlls modes are entered, the chip enters fully functional vlls and lls modes and no debug logic is working; on exit from lls/vlls, the llwu becomes inactive and the debug logic becomes active again. 15.1.3 block diagram the following figure is the block diagram for the llwu module. chapter 15 low-leakage wake-up unit (llwu) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 337 module7 interrupt flag (llwu_m7if) module0 interrupt flag (llwu_m0if) wume7 wume0 llwu_mwuf7 occurred llwu_mwuf0 occurred internal module sources llwu controller external pin sources exit low leakge mode (lls or vlls) interrupt flow reset flow ackiso reset occurred fltr lpo reset llwu_p0 llwu_p15 wupe15 wupe0 2 2 lpo fltep llwu_p0-llwu_p15 wakeup occurred 16 pin filter interrupt module flag detect interrupt module flag detect reset filter edge detect edge detect lls/vlls entered module6 interrupt flag (llwu_m6if) wume6 llwu_mwuf6 occurred interrupt module flag detect (system error) figure 15-1. llwu block diagram 15.2 llwu signal descriptions the signal properties of llwu are shown in the following table. the external wakeup input pins can be enabled to detect either rising edge, falling edge, or on any change. table 15-1. llwu signal descriptions signal description i/o llwu_pn wakeup inputs (n = 0-15) i llwu signal descriptions k60 sub-family reference manual, rev. 6, nov 2011 338 freescale semiconductor, inc. 15.3 memory map/register definition the llwu includes the following registers: ? five 8-bit wakeup source enable registers ? enable external pin input sources ? enable internal peripheral sources ? three 8-bit wakeup flag registers ? indication of wakeup up source that caused exit from lls or vlls includes external pin or internal module interrupt ? one 8-bit status and control register ? digital filter enable for external pin detected and reset ? low leakage reset pin enable ? acknowledge bit to allow certain peripherals and pads to release their held low leakage state llwu memory map absolute address (hex) register name width (in bits) access reset value section/ page 4007_c000 llwu pin enable 1 register (llwu_pe1) 8 r/w 00h 15.3.1/339 4007_c001 llwu pin enable 2 register (llwu_pe2) 8 r/w 00h 15.3.2/340 4007_c002 llwu pin enable 3 register (llwu_pe3) 8 r/w 00h 15.3.3/342 4007_c003 llwu pin enable 4 register (llwu_pe4) 8 r/w 00h 15.3.4/343 4007_c004 llwu module enable register (llwu_me) 8 r/w 00h 15.3.5/344 4007_c005 llwu flag 1 register (llwu_f1) 8 r/w 00h 15.3.6/345 4007_c006 llwu flag 2 register (llwu_f2) 8 r/w 00h 15.3.7/347 4007_c007 llwu flag 3 register (llwu_f3) 8 r/w 00h 15.3.8/349 4007_c008 llwu control and status register (llwu_cs) 8 r/w 04h 15.3.9/350 15.3.1 llwu pin enable 1 register (llwu_pe1) llwu_pe1 contains the bit field to enable and select the edge detect type for the external wakeup input pins llwu_p3-llwu_p0. note this register is unaffected by wakeup from low leakage modes (exit from lls via reset or any exit from vlls). chapter 15 low-leakage wake-up unit (llwu) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 339 address: llwu_pe1 is 4007_c000h base + 0h offset = 4007_c000h bit 7 6 5 4 3 2 1 0 read wupe3 wupe2 wupe1 wupe0 write reset 0 0 0 0 0 0 0 0 llwu_pe1 field descriptions field description 76 wupe3 wakeup pin enable for llwu_p3 enables and configures the edge detection for the wakeup pin. 00 external input pin disabled as wakeup input 01 external input pin enabled with rising edge detection 10 external input pin enabled with falling edge detection 11 external input pin enabled with any change detection 54 wupe2 wakeup pin enable for llwu_p2 enables and configures the edge detection for the wakeup pin. 00 external input pin disabled as wakeup input 01 external input pin enabled with rising edge detection 10 external input pin enabled with falling edge detection 11 external input pin enabled with any change detection 32 wupe1 wakeup pin enable for llwu_p1 enables and configures the edge detection for the wakeup pin. 00 external input pin disabled as wakeup input 01 external input pin enabled with rising edge detection 10 external input pin enabled with falling edge detection 11 external input pin enabled with any change detection 10 wupe0 wakeup pin enable for llwu_p0 enables and configures the edge detection for the wakeup pin. 00 external input pin disabled as wakeup input 01 external input pin enabled with rising edge detection 10 external input pin enabled with falling edge detection 11 external input pin enabled with any change detection 15.3.2 llwu pin enable 2 register (llwu_pe2) llwu_pe2 contains the bit field to enable and select the edge detect type for the external wakeup input pins llwu_p7-llwu_p4. memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 340 freescale semiconductor, inc. note this register is unaffected by wakeup from low leakage modes (exit from lls via reset or any exit from vlls). address: llwu_pe2 is 4007_c000h base + 1h offset = 4007_c001h bit 7 6 5 4 3 2 1 0 read wupe7 wupe6 wupe5 wupe4 write reset 0 0 0 0 0 0 0 0 llwu_pe2 field descriptions field description 7?6 wupe7 wakeup pin enable for llwu_p7 enables and configures the edge detection for the wakeup pin. 00 external input pin disabled as wakeup input 01 external input pin enabled with rising edge detection 10 external input pin enabled with falling edge detection 11 external input pin enabled with any change detection 5?4 wupe6 wakeup pin enable for llwu_p6 enables and configures the edge detection for the wakeup pin. 00 external input pin disabled as wakeup input 01 external input pin enabled with rising edge detection 10 external input pin enabled with falling edge detection 11 external input pin enabled with any change detection 3?2 wupe5 wakeup pin enable for llwu_p5 enables and configures the edge detection for the wakeup pin. 00 external input pin disabled as wakeup input 01 external input pin enabled with rising edge detection 10 external input pin enabled with falling edge detection 11 external input pin enabled with any change detection 1?0 wupe4 wakeup pin enable for llwu_p4 enables and configures the edge detection for the wakeup pin. 00 external input pin disabled as wakeup input 01 external input pin enabled with rising edge detection 10 external input pin enabled with falling edge detection 11 external input pin enabled with any change detection chapter 15 low-leakage wake-up unit (llwu) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 341 15.3.3 llwu pin enable 3 register (llwu_pe3) llwu_pe3 contains the bit field to enable and select the edge detect type for the external wakeup input pins llwu_p11-llwu_p8. note this register is unaffected by wakeup from low leakage modes (exit from lls via reset or any exit from vlls). address: llwu_pe3 is 4007_c000h base + 2h offset = 4007_c002h bit 7 6 5 4 3 2 1 0 read wupe11 wupe10 wupe9 wupe8 write reset 0 0 0 0 0 0 0 0 llwu_pe3 field descriptions field description 7?6 wupe11 wakeup pin enable for llwu_p11 enables and configures the edge detection for the wakeup pin. 00 external input pin disabled as wakeup input 01 external input pin enabled with rising edge detection 10 external input pin enabled with falling edge detection 11 external input pin enabled with any change detection 5?4 wupe10 wakeup pin enable for llwu_p10 enables and configures the edge detection for the wakeup pin. 00 external input pin disabled as wakeup input 01 external input pin enabled with rising edge detection 10 external input pin enabled with falling edge detection 11 external input pin enabled with any change detection 3?2 wupe9 wakeup pin enable for llwu_p9 enables and configures the edge detection for the wakeup pin. 00 external input pin disabled as wakeup input 01 external input pin enabled with rising edge detection 10 external input pin enabled with falling edge detection 11 external input pin enabled with any change detection 1?0 wupe8 wakeup pin enable for llwu_p8 enables and configures the edge detection for the wakeup pin. 00 external input pin disabled as wakeup input 01 external input pin enabled with rising edge detection table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 42 freescale semiconductor, inc. llwu_pe3 field descriptions (continued) field description 10 external input pin enabled with falling edge detection 11 external input pin enabled with any change detection 15.3.4 llwu pin enable 4 register (llwu_pe4) llwu_pe4 contains the bit field to enable and select the edge detect type for the external wakeup input pins llwu_p15-llwu_p12. note this register is unaffected by wakeup from low leakage modes (exit from lls via reset or any exit from vlls). address: llwu_pe4 is 4007_c000h base + 3h offset = 4007_c003h bit 7 6 5 4 3 2 1 0 read wupe15 wupe14 wupe13 wupe12 write reset 0 0 0 0 0 0 0 0 llwu_pe4 field descriptions field description 7?6 wupe15 wakeup pin enable for llwu_p15 enables and configures the edge detection for the wakeup pin. 00 external input pin disabled as wakeup input 01 external input pin enabled with rising edge detection 10 external input pin enabled with falling edge detection 11 external input pin enabled with any change detection 5?4 wupe14 wakeup pin enable for llwu_p14 enables and configures the edge detection for the wakeup pin. 00 external input pin disabled as wakeup input 01 external input pin enabled with rising edge detection 10 external input pin enabled with falling edge detection 11 external input pin enabled with any change detection 3?2 wupe13 wakeup pin enable for llwu_p13 enables and configures the edge detection for the wakeup pin. 00 external input pin disabled as wakeup input 01 external input pin enabled with rising edge detection table continues on the next page... chapter 1 ow-leaage wae-up unit wu 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 4 llwu_pe4 field descriptions (continued) field description 10 external input pin enabled with falling edge detection 11 external input pin enabled with any change detection 10 wupe12 wakeup pin enable for llwu_p12 enables and configures the edge detection for the wakeup pin. 00 external input pin disabled as wakeup input 01 external input pin enabled with rising edge detection 10 external input pin enabled with falling edge detection 11 external input pin enabled with any change detection 15.3.5 llwu module enable register (llwu_me) llwu_me contains the bits to enable the internal module flag as a wakeup input source for inputs mwuf7-mwuf0. note this register is unaffected by wakeup from low leakage modes (exit from lls via reset or any exit from vlls). address: llwu_me is 4007_c000h base + 4h offset = 4007_c004h bit 7 6 5 4 3 2 1 0 read wume7 wume6 wume5 wume4 wume3 wume2 wume1 wume0 write reset 0 0 0 0 0 0 0 0 llwu_me field descriptions field description 7 wume7 wakeup module enable for module 7 enables an internal module as a wakeup source input. 0 internal module flag not used as wakeup source 1 internal module flag used as wakeup source 6 wume6 wakeup module enable for module 6 enables an internal module as a wakeup source input. 0 internal module flag not used as wakeup source 1 internal module flag used as wakeup source 5 wume5 wakeup module enable for module 5 enables an internal module as a wakeup source input. table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 44 freescale semiconductor, inc. llwu_me field descriptions (continued) field description 0 internal module flag not used as wakeup source 1 internal module flag used as wakeup source 4 wume4 wakeup module enable for module 4 enables an internal module as a wakeup source input. 0 internal module flag not used as wakeup source 1 internal module flag used as wakeup source 3 wume3 wakeup module enable for module 3 enables an internal module as a wakeup source input. 0 internal module flag not used as wakeup source 1 internal module flag used as wakeup source 2 wume2 wakeup module enable for module 2 enables an internal module as a wakeup source input. 0 internal module flag not used as wakeup source 1 internal module flag used as wakeup source 1 wume1 wakeup module enable for module 1 enables an internal module as a wakeup source input. 0 internal module flag not used as wakeup source 1 internal module flag used as wakeup source 0 wume0 wakeup module enable for module 0 enables an internal module as a wakeup source input. 0 internal module flag not used as wakeup source 1 internal module flag used as wakeup source 15.3.6 llwu flag 1 register (llwu_f1) llwu_f1 contains the wakeup flags indicating which wakeup source caused the mcu to exit lls or vlls mode. for lls, this will be the source causing the cpu interrupt flow. for vlls, this will be the source causing the mcu reset flow. the external wakeup flags are read only and clearing a flag is accomplished by a write of a one to the corresponding wufx bit. the wakeup flag (wufx) if set will remain set if the associated wupex bit is cleared. note this register is unaffected by wakeup from low leakage modes (exit from lls via reset or any exit from vlls). chapter 15 low-leakage wake-up unit (llwu) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 345 address: llwu_f1 is 4007_c000h base + 5h offset = 4007_c005h bit 7 6 5 4 3 2 1 0 read wuf7 wuf6 wuf5 wuf4 wuf3 wuf2 wuf1 wuf0 write w1c w1c w1c w1c w1c w1c w1c w1c reset 0 0 0 0 0 0 0 0 llwu_f1 field descriptions field description 7 wuf7 wakeup flag for llwu_p7 indicates that an enabled external wakeup pin was a source of exiting lls or vlls. to clear the flag write a one to wuf7. 0 llwu_p7 input was not a source of wakeup from lls or vlls mode 1 llwu_p7 input was a source of wakeup from lls or vlls mode 6 wuf6 wakeup flag for llwu_p6 indicates that an enabled external wakeup pin was a source of exiting lls or vlls. to clear the flag write a one to wuf6. 0 llwu_p6 input was not a source of wakeup from lls or vlls mode 1 llwu_p6 input was a source of wakeup from lls or vlls mode 5 wuf5 wakeup flag for llwu_p5 indicates that an enabled external wakeup pin was a source of exiting lls or vlls. to clear the flag write a one to wuf5. 0 llwu_p5 input was not a source of wakeup from lls or vlls mode 1 llwu_p5 input was a source of wakeup from lls or vlls mode 4 wuf4 wakeup flag for llwu_p4 indicates that an enabled external wakeup pin was a source of exiting lls or vlls. to clear the flag write a one to wuf4. 0 llwu_p4 input was not a source of wakeup from lls or vlls mode 1 llwu_p4 input was a source of wakeup from lls or vlls mode 3 wuf3 wakeup flag for llwu_p3 indicates that an enabled external wakeup pin was a source of exiting lls or vlls. to clear the flag write a one to wuf3. 0 llwu_p3 input was not a source of wakeup from lls or vlls mode 1 llwu_p3 input was a source of wakeup from lls or vlls mode 2 wuf2 wakeup flag for llwu_p2 indicates that an enabled external wakeup pin was a source of exiting lls or vlls. to clear the flag write a one to wuf2. 0 llwu_p2 input was not a source of wakeup from lls or vlls mode 1 llwu_p2 input was a source of wakeup from lls or vlls mode table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 46 freescale semiconductor, inc. llwu_f1 field descriptions (continued) field description 1 wuf1 wakeup flag for llwu_p1 indicates that an enabled external wakeup pin was a source of exiting lls or vlls. to clear the flag write a one to wuf1. 0 llwu_p1 input was not a source of wakeup from lls or vlls mode 1 llwu_p1 input was a source of wakeup from lls or vlls mode 0 wuf0 wakeup flag for llwu_p0 indicates that an enabled external wakeup pin was a source of exiting lls or vlls. to clear the flag write a one to wuf0. 0 llwu_p0 input was not a source of wakeup from lls or vlls mode 1 llwu_p0 input was a source of wakeup from lls or vlls mode 15.3.7 llwu flag 2 register (llwu_f2) llwu_f2 contains the wakeup flags indicating which wakeup source caused the mcu to exit lls or vlls mode. for lls, this will be the source causing the cpu interrupt flow. for vlls, this will be the source causing the mcu reset flow. the external wakeup flags are read only and clearing a flag is accomplished by a write of a one to the corresponding wufx bit. the wakeup flag (wufx) if set will remain set if the associated wupex bit is cleared. note this register is unaffected by wakeup from low leakage modes (exit from lls via reset or any exit from vlls). address: llwu_f2 is 4007_c000h base + 6h offset = 4007_c006h bit 7 6 5 4 3 2 1 0 read wuf15 wuf14 wuf13 wuf12 wuf11 wuf10 wuf9 wuf8 write w1c w1c w1c w1c w1c w1c w1c w1c reset 0 0 0 0 0 0 0 0 llwu_f2 field descriptions field description 7 wuf15 wakeup flag for llwu_p15 indicates that an enabled external wakeup pin was a source of exiting lls or vlls. to clear the flag write a one to wuf15. table continues on the next page... chapter 1 ow-leaage wae-up unit wu 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 47 llwu_f2 field descriptions (continued) field description 0 llwu_p15 input was not a source of wakeup from lls or vlls mode 1 llwu_p15 input was a source of wakeup from lls or vlls mode 6 wuf14 wakeup flag for llwu_p14 indicates that an enabled external wakeup pin was a source of exiting lls or vlls. to clear the flag write a one to wuf14. 0 llwu_p14 input was not a source of wakeup from lls or vlls mode 1 llwu_p14 input was a source of wakeup from lls or vlls mode 5 wuf13 wakeup flag for llwu_p13 indicates that an enabled external wakeup pin was a source of exiting lls or vlls. to clear the flag write a one to wuf13. 0 llwu_p13 input was not a source of wakeup from lls or vlls mode 1 llwu_p13 input was a source of wakeup from lls or vlls mode 4 wuf12 wakeup flag for llwu_p12 indicates that an enabled external wakeup pin was a source of exiting lls or vlls. to clear the flag write a one to wuf12. 0 llwu_p12 input was not a source of wakeup from lls or vlls mode 1 llwu_p12 input was a source of wakeup from lls or vlls mode 3 wuf11 wakeup flag for llwu_p11 indicates that an enabled external wakeup pin was a source of exiting lls or vlls. to clear the flag write a one to wuf11. 0 llwu_p11 input was not a source of wakeup from lls or vlls mode 1 llwu_p11 input was a source of wakeup from lls or vlls mode 2 wuf10 wakeup flag for llwu_p10 indicates that an enabled external wakeup pin was a source of exiting lls or vlls. to clear the flag write a one to wuf10. 0 llwu_p10 input was not a source of wakeup from lls or vlls mode 1 llwu_p10 input was a source of wakeup from lls or vlls mode 1 wuf9 wakeup flag for llwu_p9 indicates that an enabled external wakeup pin was a source of exiting lls or vlls. to clear the flag write a one to wuf9. 0 llwu_p9 input was not a source of wakeup from lls or vlls mode 1 llwu_p9 input was a source of wakeup from lls or vlls mode 0 wuf8 wakeup flag for llwu_p8 indicates that an enabled external wakeup pin was a source of exiting lls or vlls. to clear the flag write a one to wuf8. 0 llwu_p8 input was not a source of wakeup from lls or vlls mode 1 llwu_p8 input was a source of wakeup from lls or vlls mode memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 348 freescale semiconductor, inc. 15.3.8 llwu flag 3 register (llwu_f3) llwu_f3 contains the wakeup flags indicating which internal wakeup source caused the mcu to exit lls or vlls mode. for lls, this will be the source causing the cpu interrupt flow. for vlls, this will be the source causing the mcu reset flow. for internal peripherals that are capable of running in lls or vlls mode, such as rtc or cmp modules, the flag from the associated peripheral is accessible as the mwufx bit. clearing of the flag will need to be done in the peripheral instead of writing a one to the mwufx bit. note this register is unaffected by wakeup from low leakage modes (exit from lls via reset or any exit from vlls). address: llwu_f3 is 4007_c000h base + 7h offset = 4007_c007h bit 7 6 5 4 3 2 1 0 read mwuf7 mwuf6 mwuf5 mwuf4 mwuf3 mwuf2 mwuf1 mwuf0 write w1c reset 0 0 0 0 0 0 0 0 llwu_f3 field descriptions field description 7 mwuf7 wakeup flag for module 7 (error detect) indicates that an unexpected source of wakeup was active when lls or vlls was entered. an immediate wakeup event was triggered and the source of the wakeup event is not known. error handling routines should treat this source as an unknown wakeup. to clear the flag write a one to mwuf7. 0 module 7 (error detect) input was not a source of wakeup from lls or vlls mode 1 module 7 (error detect) input was a source of wakeup from lls or vlls mode 6 mwuf6 wakeup flag for module 6 indicates that an enabled internal peripheral was a source of exiting lls or vlls. to clear the flag follow the internal peripheral flag clearing mechanism. 0 module 6 input was not a source of wakeup from lls or vlls mode 1 module 6 input was a source of wakeup from lls or vlls mode 5 mwuf5 wakeup flag for module 5 indicates that an enabled internal peripheral was a source of exiting lls or vlls. to clear the flag follow the internal peripheral flag clearing mechanism. 0 module 5 input was not a source of wakeup from lls or vlls mode 1 module 5 input was a source of wakeup from lls or vlls mode table continues on the next page... chapter 1 ow-leaage wae-up unit wu 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 4 llwu_f3 field descriptions (continued) field description 4 mwuf4 wakeup flag for module 4 indicates that an enabled internal peripheral was a source of exiting lls or vlls. to clear the flag follow the internal peripheral flag clearing mechanism. 0 module 4 input was not a source of wakeup from lls or vlls mode 1 module 4 input was a source of wakeup from lls or vlls mode 3 mwuf3 wakeup flag for module 3 indicates that an enabled internal peripheral was a source of exiting lls or vlls. to clear the flag follow the internal peripheral flag clearing mechanism. 0 module 3 input was not a source of wakeup from lls or vlls mode 1 module 3 input was a source of wakeup from lls or vlls mode 2 mwuf2 wakeup flag for module 2 indicates that an enabled internal peripheral was a source of exiting lls or vlls. to clear the flag follow the internal peripheral flag clearing mechanism. 0 module 2 input was not a source of wakeup from lls or vlls mode 1 module 2 input was a source of wakeup from lls or vlls mode 1 mwuf1 wakeup flag for module 1 indicates that an enabled internal peripheral was a source of exiting lls or vlls. to clear the flag follow the internal peripheral flag clearing mechanism. 0 module 1 input was not a source of wakeup from lls or vlls mode 1 module 1 input was a source of wakeup from lls or vlls mode 0 mwuf0 wakeup flag for module 0 indicates that an enabled internal peripheral was a source of exiting lls or vlls. to clear the flag follow the internal peripheral flag clearing mechanism. 0 module 0 input was not a source of wakeup from lls or vlls mode 1 module 0 input was a source of wakeup from lls or vlls mode 15.3.9 llwu control and status register (llwu_cs) llwu_cs is a status and control register that is used to enable/disable the digital filter for the external pin detect and reset pin. note ackiso is set following wakeup from vlls modes. fltep and fltr are unaffected following wakeup from low leakage modes (exit from lls via reset or any exit from vlls). memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 350 freescale semiconductor, inc. address: llwu_cs is 4007_c000h base + 8h offset = 4007_c008h bit 7 6 5 4 3 2 1 0 read ackiso 0 fltep fltr write w1c 1 reset 0 0 0 0 0 1 0 0 llwu_cs field descriptions field description 7 ackiso acknowledge isolation reading this bit indicates whether certain peripherals and the i/o pads are in a latched state as a result of having been in a vlls mode. writing one to this bit when it is set releases the i/o pads and certain peripherals to their normal run mode state. 0 peripherals and i/o pads are in normal run state 1 certain peripherals and i/o pads are in an isolated and latched state 63 reserved this read-only field is reserved and always has the value zero. 2 reserved this field is reserved. 1 fltep digital filter on external pin enables the digital filter for the external pin detect. 0 filter not enabled 1 filter enabled 0 fltr digital filter on reset pin enables the digital filter for the reset pin during lls and vlls modes. 0 filter not enabled 1 filter enabled 15.4 functional description this on-chip peripheral module is called a low leakage wake up (llwu) module because it allows internal peripherals and external input pins to be sources of wakeup from low leakage modes. it is only operational in lls and vlls modes. the llwu module contains pin enables for each external pin and internal module. for each external pin, the user can disable or select the edge type for the wakeup. choices are falling, rising or either edge (any change). when an external pin is enabled as a wakeup source the pin must be configured as an input pin. chapter 15 low-leakage wake-up unit (llwu) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 351 the llwu implements an optional 3-cycle glitch filter, based on the lpo clock, such that a detected external pin is required to stay asserted until the enabled glitch filter times out. there is also 2 additional cycles of latency due to synchronization that results in a total of 5 cycles of delay before the detect circuit alerts the system to the wakeup or reset event when the filter function is enabled. the wakeup detect glitch filter is implemented on the "or" of external pin inputs of all enabled external pins. there is separate reset glitch filter implemented on the reset pin. there is no glitch filtering on the internal modules. note the wakeup glitch filter should not be enabled if any of the external pin detect edge types is set for either edge. enabling the wakeup glitch filter and selecting either edge detect on any pin results in unpredictable operation. for internal module wakeup operation, the wumex bit enables the respective module as a wakeup source. 15.4.1 lls mode while in lls, the mcu is in a state retention mode where all registers and memory retains its contents. the i/o pins are held in their input or output state. upon wakeup, the power management control (pmc) is re-enabled, goes through a power up sequence to full regulation and releases the logic from state retention mode. the i/o states are released. wakeup events triggered from either an external pin input or an internal module input result in a cpu interrupt flow to begin user code execution. an lls reset event due to reset pin assertion causes an exit via a system reset. state retention data is lost, the i/o states return to their reset state, and the ackiso bit is not set. the mc_srs[wakeup] and mc_srs[pin] bits are set and the system executes a reset flow before cpu operation begins with a reset vector fetch. 15.4.2 vlls modes while in vlls, much of the internal digital logic is powered down. the i/o pins are held in their input or output state. refer to the device's power management chapter for powered and un-powered modules in vllsx modes. after wakeup or reset, the pmc is re-enabled and performs a power-up sequence to full regulation. functional description k60 sub-family reference manual, rev. 6, nov 2011 352 freescale semiconductor, inc. in the case of a wakeup due to external pin or internal module wakeup, the i/o states are held until software clears the ackiso bit (by writing a 1 to it). recovery is always via a system reset flow and the mc_srs[wakeup] is set indicating the low leakage mode was active prior to the last system reset flow. an vlls reset event due to reset pin assertion causes an exit via a system reset. state retention data is lost, the i/o states return to their reset state, and the ackiso bit is not set. the mc_srs[wakeup] and mc_srs[pin] bits are set and the system executes a reset flow before cpu operation begins with a reset vector fetch. 15.4.3 initialization flags associated with external input pins (wufx) are cleared upon entry into lls or vlls modes. for an enabled peripheral wakeup input, the peripheral flag should be cleared by the user before entering lls or vlls to avoid an immediate exit from lls or vlls. 15.4.4 low power mode recovery recovery from vllsx is through the wake-up reset event. the chip wake-ups from vllsx by means of reset, an enabled pin or enabled module. see the table "llwu inputs" in the llwu configuration section for a list of the sources. the wake-up flow from vlls1,2 and 3 is through reset. the wakeup bit in the srs registers in the mode controller is set indicating that the chip is recovering from a low power mode. code execution begins; however, the i/o pins are held in their pre-low- power mode entry states, and the oscillator is disabled (even if erefsten had been set before entering vllsx). software must clear this hold by writing a 1 to the ackiso bit in the control and status register in the llwu module. note to avoid unwanted transitions on the pins, software must re- initialize the i/o pins to their pre-low-power mode entry states before releasing the hold. the oscillator cannot be re-enabled before the ackiso bit is cleared and must be reconfigured after the hold is released. chapter 15 low-leakage wake-up unit (llwu) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 353 functional description k60 sub-family reference manual, rev. 6, nov 2011 354 freescale semiconductor, inc. chapter 16 miscellaneous control module (mcm) 16.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the miscellaneous control module (mcm) provides a myriad of miscellaneous control functions. 16.1.1 features the mcm includes these distinctive features: ? program-visible information on the platform configuration and revision ? control and counting logic for etb almost full 16.2 memory map/register descriptions the memory map and register descriptions below describe the registers using byte addresses. mcm memory map absolute address (hex) register name width (in bits) access reset value section/ page e008_0008 crossbar switch (axbs) slave configuration (mcm_plasc) 16 r 001fh 16.2.1/356 table continues on the next page... 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. mcm memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page e008_000a crossbar switch (axbs) master configuration (mcm_plamc) 16 r 003fh 16.2.2/356 e008_000c sram arbitration and protection (mcm_sramap) 32 r/w 0000_0000h 16.2.3/357 e008_0010 interrupt status register (mcm_isr) 32 r 0000_0000h 16.2.4/358 e008_0014 etb counter control register (mcm_etbcc) 32 r/w 0000_0000h 16.2.5/359 e008_0018 etb reload register (mcm_etbrl) 32 r/w 0000_0000h 16.2.6/360 e008_001c etb counter value register (mcm_etbcnt) 32 r 0000_0000h 16.2.7/361 16.2.1 crossbar switch (axbs) slave configuration (mcm_plasc) the plasc is a 16-bit read-only register identifying the presence/absence of bus slave connections to the devices crossbar switch. address: mcm_plasc is e008_0000h base + 8h offset = e008_0008h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 asc write reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 mcm_plasc field descriptions field description 15?8 reserved this read-only field is reserved and always has the value zero. 7?0 asc each bit in the asc field indicates if there is a corresponding connection to the crossbar switch's slave input port. 0 a bus slave connection to axbs input port n is absent 1 a bus slave connection to axbs input port n is present 16.2.2 crossbar switch axbs master configuration mcm_pamc the plamc is a 16-bit read-only register identifying the presence/absence of bus master connections to the device's crossbar switch. address: mcm_plamc is e008_0000h base + ah offset = e008_000ah bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 amc write reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 memory map/register descriptions k60 sub-family reference manual, rev. 6, nov 2011 356 freescale semiconductor, inc. mcm_plamc field descriptions field description 158 reserved this read-only field is reserved and always has the value zero. 70 amc each bit in the amc field indicates if there is a corresponding connection to the axbs master input port. 0 a bus master connection to axbs input port n is absent 1 a bus master connection to axbs input port n is present 16.2. sram arbitration and protection mcm_sramap the sramap register defines the arbitration and protection schemes for the two sram arrays. note bits 23-0 are undefined after reset. address: mcm_sramap is e008_0000h base + ch offset = e008_000ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 sramlwp sramlap 0 sramuwp sramuap reserved w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r reserved reserved w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mcm_sramap field descriptions field description 31 reserved this read-only field is reserved and always has the value zero. 30 sramlwp sram_l write protect when this bit is set, writes to sram_l array generates a bus error. 29?28 sramlap sram_l arbitration priority defines the arbitration scheme and priority for the processor and sram backdoor accesses to the sram_l array. 00 round robin table continues on the next page... chapter 16 miscellaneous control module mcm 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 7 mcm_sramap field descriptions (continued) field description 01 special round robin (favors sram backoor accesses over the processor) 10 fixed priority. processor has highest, backdoor has lowest 11 fixed priority. backdoor has highest, processor has lowest 27 reserved this read-only field is reserved and always has the value zero. 26 sramuwp sram_u write protect when this bit is set, writes to sram_u array generates a bus error. 2524 sramuap sram_u arbitration priority defines the arbitration scheme and priority for the processor and sram backdoor accesses to the sram_u array. 00 round robin 01 special round robin (favors sram backoor accesses over the processor) 10 fixed priority. processor has highest, backdoor has lowest 11 fixed priority. backdoor has highest, processor has lowest 239 reserved this field is reserved. 80 reserved this field is reserved. 16.2.4 interrupt status register (mcm_isr) address: mcm_isr is e008_0000h base + 10h offset = e008_0010h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 nmi irq 0 w w1c w1c reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mcm_isr field descriptions field description 314 reserved this read-only field is reserved and always has the value zero. 3 reserved this read-only field is reserved and always has the value zero. table continues on the next page... memory mapregister descriptions 60 sub-family reference manual, rev. 6, nov 2011 8 freescale semiconductor, inc. mcm_isr field descriptions (continued) field description 2 nmi non-maskable interrupt pending if etbcc[rspt] is set to 10b, this bit is set when the etb counter expires. 0 no pending nmi 1 due to the etb counter expiring, an nmi is pending 1 irq normal interrupt pending if etbcc[rspt] is set to 01b, this bit is set when the etb counter expires. 0 no pending interrupt 1 due to the etb counter expiring, a normal interrupt is pending 0 reserved this read-only field is reserved and always has the value zero. 16.2.5 etb counter control register (mcm_etbcc) address: mcm_etbcc is e008_0000h base + 14h offset = e008_0014h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 itdis etdis rlrq rspt cnten w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mcm_etbcc field descriptions field description 316 reserved this read-only field is reserved and always has the value zero. 5 itdis itm-to-tpiu disable disables the trace path from itm to tpiu 0 itm-to-tpiu trace path enabled 1 itm-to-tpiu trace path disabled 4 etdis etm-to-tpiu disable disables the trace path from etm to tpiu 0 etm-to-tpiu trace path enabled 1 etm-to-tpiu trace path disabled 3 rlrq reload request reloads the etb packet counter with the mcm_etbrl reload value. if irq or nmi interrupts were enabled and an nmi or irq interrupt was generated on counter expiration, setting this bit clears the pending nmi or irq interrupt request. table continues on the next page... chapter 16 miscellaneous control module mcm 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. mcm_etbcc field descriptions (continued) field description if debug halt was enabled and a debug halt request was asserted on counter expiration, setting this bit clears the debug halt request. 0 no effect 1 clears pending debug halt, nmi, or irq interrupt requests 21 rspt response type 00 no response when the etb count expires 01 generate a normal interrupt when the etb count expires 10 generate an nmi when the etb count expires 11 generate a debug halt when the etb count expires 0 cnten counter enable enables the etb counter. 0 etb counter disabled 1 etb counter enabled 16.2.6 etb reload register (mcm_etbrl) address: mcm_etbrl is e008_0000h base + 18h offset = e008_0018h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 reload w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mcm_etbrl field descriptions field description 3111 reserved this read-only field is reserved and always has the value zero. 100 reload byte count reload value indicates the 0-mod-4 value the counter reloads to. writing a non-0-mod-4 value to this field results in an bus error memory map/register descriptions k60 sub-family reference manual, rev. 6, nov 2011 360 freescale semiconductor, inc. 16.2.7 etb counter value register (mcm_etbcnt) address: mcm_etbcnt is e008_0000h base + 1ch offset = e008_001ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 counter w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mcm_etbcnt field descriptions field description 3111 reserved this read-only field is reserved and always has the value zero. 100 counter byte count counter value indicates the current 0-mod-4 value of the counter. 16.3 functional description this section describes the functional description of mcm module. 16.3.1 interrupts the mcm generates two interrupt requests: ? non-maskable interrupt ? normal interrupt 16.3.1.1 non-maskable interrupt the mcm's non-maskable interrupt (nmi) is generated, if: ? mcm_iscr[etbn] is set, which is caused by ? the etb counter is enabled (mcm_etbcc[cnten] = 1), ? the etb count expires, and ? the response to counter expiration is an nmi (mcm_etbcc[rspt] = 10) chapter 16 miscellaneous control module (mcm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 361 16.3.1.2 normal interrupt the mcm's normal interrupt is generated if any of the following are true: ? mcm_iscr[etbi] is set, which is caused by ? the etb counter is enabled (mcm_etbcc[cnten] = 1), ? the etb count expires, and ? the response to counter expiration is a normal interrupt (mcm_etbcc[rspt] = 01) functional description k60 sub-family reference manual, rev. 6, nov 2011 362 freescale semiconductor, inc. chapter 17 crossbar switch (axbs) 17.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. this chapter provides information on the layout, configuration, and programming of the crossbar switch. the crossbar switch connects bus masters and bus slaves using a crossbar switch structure. this structure allows all bus masters to access different bus slaves simultaneously, while providing arbitration among the bus masters when they access the same slave. a variety of bus arbitration methods and attributes may be programmed on a slave by slave basis. 17.1.1 features the crossbar switch includes these distinctive features: ? symmetric crossbar bus switch implementation ? allows concurrent accesses from different masters to different slaves ? slave arbitration attributes configured on a slave by slave basis ? 32-bit width and support for byte, 2-byte, 4-byte, and 16-byte burst transfers ? operation at a 1-to-1 clock frequency with the bus masters ? low-power park mode support k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 363 17.2 memory map / register definition each slave port of the crossbar switch contains configuration registers. read- and write- transfers require two bus clock cycles. the registers can be read from and written to only in supervisor mode. additionally, these registers can be read from or written to only by 32-bit accesses. a bus error response is returned if an unimplemented location is accessed within the crossbar switch. the slave registers also feature a bit that, when set, prevents the registers from being written. the registers remain readable, but future write attempts have no effect on the registers and are terminated with a bus error response to the master initiating the write. the core, for example, takes a bus error interrupt. note this section shows the registers for all eight master and slave ports. if a master or slave is not used on this particular device, then unexpected results occur when writing to its registers. see the chip configuration details for the exact master/slave assignments for your device. axbs memory map absolute address (hex) register name width (in bits) access reset value section/ page 4000_4000 priority registers slave (axbs_prs0) 32 r/w 7654_3210h 17.2.1/365 4000_4010 control register (axbs_crs0) 32 r/w 0000_0000h 17.2.2/368 4000_4100 priority registers slave (axbs_prs1) 32 r/w 7654_3210h 17.2.1/365 4000_4110 control register (axbs_crs1) 32 r/w 0000_0000h 17.2.2/368 4000_4200 priority registers slave (axbs_prs2) 32 r/w 7654_3210h 17.2.1/365 4000_4210 control register (axbs_crs2) 32 r/w 0000_0000h 17.2.2/368 4000_4300 priority registers slave (axbs_prs3) 32 r/w 7654_3210h 17.2.1/365 4000_4310 control register (axbs_crs3) 32 r/w 0000_0000h 17.2.2/368 4000_4400 priority registers slave (axbs_prs4) 32 r/w 7654_3210h 17.2.1/365 4000_4410 control register (axbs_crs4) 32 r/w 0000_0000h 17.2.2/368 4000_4500 priority registers slave (axbs_prs5) 32 r/w 7654_3210h 17.2.1/365 4000_4510 control register (axbs_crs5) 32 r/w 0000_0000h 17.2.2/368 table continues on the next page... memory map register definition 60 sub-family reference manual, rev. 6, nov 2011 64 freescale semiconductor, inc. axbs memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4000_4600 priority registers slave (axbs_prs6) 32 r/w 7654_3210h 17.2.1/365 4000_4610 control register (axbs_crs6) 32 r/w 0000_0000h 17.2.2/368 4000_4700 priority registers slave (axbs_prs7) 32 r/w 7654_3210h 17.2.1/365 4000_4710 control register (axbs_crs7) 32 r/w 0000_0000h 17.2.2/368 4000_4800 master general purpose control register (axbs_mgpcr0) 32 r/w 0000_0000h 17.2.3/370 4000_4900 master general purpose control register (axbs_mgpcr1) 32 r/w 0000_0000h 17.2.3/370 4000_4a00 master general purpose control register (axbs_mgpcr2) 32 r/w 0000_0000h 17.2.3/370 4000_4b00 master general purpose control register (axbs_mgpcr3) 32 r/w 0000_0000h 17.2.3/370 4000_4c00 master general purpose control register (axbs_mgpcr4) 32 r/w 0000_0000h 17.2.3/370 4000_4d00 master general purpose control register (axbs_mgpcr5) 32 r/w 0000_0000h 17.2.3/370 4000_4e00 master general purpose control register (axbs_mgpcr6) 32 r/w 0000_0000h 17.2.3/370 4000_4f00 master general purpose control register (axbs_mgpcr7) 32 r/w 0000_0000h 17.2.3/370 17.2.1 priority registers slave (axbs_prs n the priority registers (prsn) set the priority of each master port on a per slave port basis and reside in each slave port. the priority register can be accessed only with 32-bit accesses. after the crsn[ro] bit is set, the prsn register can only be read; attempts to write to it have no effect on prsn and result in a bus-error response to the master initiating the write. no two available master ports may be programmed with the same priority level. attempts to program two or more masters with the same priority level result in a bus-error response and the prsn is not updated. note the possible values for the prsn fields depend on the number of masters available on the device. see the device's chip configuration details for the number of masters supported. chapter 17 crossbar switch (axbs) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 365 ? if the device contains less than five masters, values 000C 011 are valid and writing other values results in an error. ? if the device contains n masters where n 5, values 0 to n -1 are valid and writing other values results in an error. addresses: axbs_prs0 is 4000_4000h base + 0h offset = 4000_4000h axbs_prs1 is 4000_4000h base + 100h offset = 4000_4100h axbs_prs2 is 4000_4000h base + 200h offset = 4000_4200h axbs_prs3 is 4000_4000h base + 300h offset = 4000_4300h axbs_prs4 is 4000_4000h base + 400h offset = 4000_4400h axbs_prs5 is 4000_4000h base + 500h offset = 4000_4500h axbs_prs6 is 4000_4000h base + 600h offset = 4000_4600h axbs_prs7 is 4000_4000h base + 700h offset = 4000_4700h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 m7 0 m6 0 m5 0 m4 0 m3 0 m2 0 m1 0 m0 w reset 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 axbs_prs n iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero aster riority ets the aritration riority or this ort on the associate slae ort his aster has leel or hihest riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel or lowest riority when accessin the slae ort resere his reaonly iel is resere an always has the alue ero aster riority ets the aritration riority or this ort on the associate slae ort his aster has leel or hihest riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel or lowest riority when accessin the slae ort resere his reaonly iel is resere an always has the alue ero table continues on the next page... memory map register definition 60 sub-family reference manual, rev. 6, nov 2011 66 freescale semiconductor, inc. axbs_prs n iel escritions continue fiel escrition aster riority ets the aritration riority or this ort on the associate slae ort his aster has leel or hihest riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel or lowest riority when accessin the slae ort resere his reaonly iel is resere an always has the alue ero aster riority ets the aritration riority or this ort on the associate slae ort his aster has leel or hihest riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel or lowest riority when accessin the slae ort resere his reaonly iel is resere an always has the alue ero aster riority ets the aritration riority or this ort on the associate slae ort his aster has leel or hihest riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel or lowest riority when accessin the slae ort resere his reaonly iel is resere an always has the alue ero aster riority ets the aritration riority or this ort on the associate slae ort his aster has leel or hihest riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel or lowest riority when accessin the slae ort table continues on the next page... chapter 17 crossbar switch axbs 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 67 axbs_prs n iel escritions continue fiel escrition resere his reaonly iel is resere an always has the alue ero aster riority ets the aritration riority or this ort on the associate slae ort his aster has leel or hihest riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel or lowest riority when accessin the slae ort resere his reaonly iel is resere an always has the alue ero aster riority ets the aritration riority or this ort on the associate slae ort his aster has leel or hihest riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel riority when accessin the slae ort his aster has leel or lowest riority when accessin the slae ort ontrol reister r n these registers control several features of each slave port and must be accessed using 32- bit accesses. after crsn[ro] is set, the crsn can only be read; attempts to write to it have no effect and result in an error response. addresses: axbs_crs0 is 4000_4000h base + 10h offset = 4000_4010h axbs_crs1 is 4000_4000h base + 110h offset = 4000_4110h axbs_crs2 is 4000_4000h base + 210h offset = 4000_4210h axbs_crs3 is 4000_4000h base + 310h offset = 4000_4310h axbs_crs4 is 4000_4000h base + 410h offset = 4000_4410h axbs_crs5 is 4000_4000h base + 510h offset = 4000_4510h axbs_crs6 is 4000_4000h base + 610h offset = 4000_4610h axbs_crs7 is 4000_4000h base + 710h offset = 4000_4710h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r ro hlp 0 arb 0 pctl 0 park w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 memory map / register definition k60 sub-family reference manual, rev. 6, nov 2011 368 freescale semiconductor, inc. axbs_crs n iel escritions fiel escrition ro rea only forces the slae orts rn an rn reisters to e reaonly ter set only a harware reset clears it he slae orts reisters are writeale he slae orts reisters are reaonly an cannot e written ttete writes hae no eect on the reisters an result in a us error resonse hl halt low riority ets the initial aritration riority or low ower oe requests ettin this it will not eect the request or low ower oe ro attainin hihest riority once it has control o the slae orts he low ower oe request has the hihest riority or aritration on this slae ort he low ower oe request has the lowest initial riority or aritration on this slae ort resere his reaonly iel is resere an always has the alue ero r ritration oe elects the aritration olicy or the slae ort fixe riority rounroin or rotatin riority resere resere resere his reaonly iel is resere an always has the alue ero l arin control eterines the slae orts arin control he lowower ar eature results in an oerall ower sains i the slae ort is not saturate howeer this orces an extra latency cloc when any aster tries to access the slae ort while not in use ecause it is not are on any aster hen no aster aes a request the ariter ars the slae ort on the aster ort eine y the r it iel hen no aster aes a request the ariter ars the slae ort on the last aster to e in control o the slae ort hen no aster aes a request the slae ort is not are on a aster an the ariter ries all oututs to a constant sae state resere resere his reaonly iel is resere an always has the alue ero r ar eterines which aster ort the current slae ort ars on when no asters are actiely ain requests an the l its are cleare o: only select aster orts that are actually resent on the eice not uneine ehaior ay occur ar on aster ort table continues on the next page... chapter 17 crossbar switch axbs 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 6 axbs_crs n iel escritions continue fiel escrition ar on aster ort ar on aster ort ar on aster ort ar on aster ort ar on aster ort resere resere aster eneral urose ontrol reister r n the mgpcr controls only whether the masters undefined length burst accesses are allowed to complete uninterrupted or whether they can be broken by requests from higher priority masters. the mgpcr can only be accessed in supervisor mode with 32-bit accesses. addresses: axbs_mgpcr0 is 4000_4000h base + 800h offset = 4000_4800h axbs_mgpcr1 is 4000_4000h base + 900h offset = 4000_4900h axbs_mgpcr2 is 4000_4000h base + a00h offset = 4000_4a00h axbs_mgpcr3 is 4000_4000h base + b00h offset = 4000_4b00h axbs_mgpcr4 is 4000_4000h base + c00h offset = 4000_4c00h axbs_mgpcr5 is 4000_4000h base + d00h offset = 4000_4d00h axbs_mgpcr6 is 4000_4000h base + e00h offset = 4000_4e00h axbs_mgpcr7 is 4000_4000h base + f00h offset = 4000_4f00h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 aulb w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 axbs_mgpcr n iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero ul ritrates on uneine lenth ursts eterines whether an when the crossar switch aritrates away the slae ort the aster owns when the aster is erorin uneine lenth urst accesses o aritration is allowe urin an uneine lenth urst ritration is allowe at any tie urin an uneine lenth urst ritration is allowe ater our eats o an uneine lenth urst ritration is allowe ater eiht eats o an uneine lenth urst ritration is allowe ater eats o an uneine lenth urst table continues on the next page... memory map register definition 60 sub-family reference manual, rev. 6, nov 2011 70 freescale semiconductor, inc. axbs_mgpcr n iel escritions continue fiel escrition resere resere resere functional escrition eneral oeration when a master accesses the crossbar switch the access is immediately taken. if the targeted slave port of the access is available, then the access is immediately presented on the slave port. it is possible to make single-clock, or zero wait state, accesses through the crossbar. if the targeted slave port of the access is busy or parked on a different master port, the requesting master simply sees wait states inserted until the targeted slave port can service the master's request. the latency in servicing the request depends on each master's priority level and the responding peripheral's access time. because the crossbar switch appears to be just another slave to the master device, the master device has no knowledge of whether it actually owns the slave port it is targeting. while the master does not have control of the slave port it is targeting, it simply waits. a master is given control of the targeted slave port only after a previous access to a different slave port completes, regardless of its priority on the newly targeted slave port. this prevents deadlock from occurring when: ? a higher priority master has: ? an outstanding request to one slave port that has a long response time and ? a pending access to a different slave port, and ? a lower priority master is also making a request to the same slave port as the pending access of the higher priority master. after the master has control of the slave port it is targeting, the master remains in control of that slave port until it gives up the slave port by running an idle cycle or by leaving that slave port for its next access. the master could also lose control of the slave port if another higher priority master makes a request to the slave port; however, if the master is running a fixed-length burst transfer it retains control of the slave port until that transfer completes. based on mgpcr[aulb], the master either retains control of the slave port when doing undefined length incrementing burst transfers or loses the bus to a higher priority master. chapter 17 crossbar switch (axbs) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 371 the crossbar terminates all master idle transfers, as opposed to allowing the termination to come from one of the slave busses. additionally, when no master is requesting access to a slave port, the crossbar drives idle transfers onto the slave bus, even though a default master may be granted access to the slave port. when a slave bus is being idled by the crossbar, it can park the slave port on the master port indicated by crs n [park]. this is done to save the initial clock of arbitration delay that otherwise would be seen if the master had to arbitrate to gain control of the slave port. the slave port can also be put into low power park mode to save power, by using crs n [pctl]. 17.3.2 register coherency because the content of the registers has a real-time effect on the operation of the crossbar, it is important to understand that any register modifications take effect as soon as the register is written. the values of the registers do not track with slave-port-related master accesses, but instead track only with slave accesses. the mgpcrx[aulb] bits are the exception to this rule. the update of these bits is only recognized when the master on that master port runs an idle cycle, even though the slave bus cycle to write them will have already terminated successfully. if the mgpcrx[aulb] bits are written between two burst accesses, the new aulb encodings do not take effect until an idle cycle is initiated by the master on that master port. 17.3.3 arbitration the crossbar switch supports two arbitration schemes: ? a fixed-priority comparison algorithm ? a round-robin fairness algorithm the arbitration scheme is independently programmable for each slave port. 17.3.3.1 arbitration during undefined length bursts arbitration points during an undefined length burst are defined by the current master's mgpcr[aulb] field setting. when a defined length is imposed on the burst via the aulb bits, the undefined length burst is treated as a single or series of single back-to- back fixed-length burst accesses. the following figure illustrates an example: functional description k60 sub-family reference manual, rev. 6, nov 2011 372 freescale semiconductor, inc. lost control lost control master-to-slave transfer 1 2 3 4 5 6 7 8 9 10 11 12 1 beat 1 beat 12 beat burst no arbitration arbitration allowed no arbitration no arbitration mgpcr[aulb] figure 17-28. undefined length burst example in this example, a master runs an undefined length burst and the mgpcr[aulb] bits indicate arbitration occurs after the fourth beat of the burst. the master runs two sequential beats and then starts what will be a 12-beat undefined length burst access to a new address within the same slave port region as the previous access. the crossbar does not allow an arbitration point until the fourth overall access, or the second beat of the second burst. at that point, all remaining accesses are open for arbitration until the master loses control of the slave port. assume the master loses control of the slave port after the fifth beat of the second burst. after the master regains control of the slave port no arbitration point is available until after the master has run four more beats of its burst. after the fourth beat of the now continued burst, or the ninth beat of the second burst from the master's perspective, is taken, all beats of the burst are once again open for arbitration until the master loses control of the slave port. assume the master again loses control of the slave port on the fifth beat of the third now continued burst, or the 10th beat of the second burst from the master's perspective. after the master regains control of the slave port, it is allowed to complete its final two beats of its burst without facing arbitration. note fixed-length burst accesses are not affected by the aulb bits. all fixed-length burst accesses lock out arbitration until the last beat of the fixed-length burst. 17.3.3.2 fixed-priority operation when operating in fixed-priority mode, each master is assigned a unique priority level in the priority registers (prs n ) . if two masters request access to a slave port, the master with the highest priority in the selected priority register gains control over the slave port. chapter 17 crossbar switch (axbs) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 373 when a master makes a request to a slave port, the slave port checks if the new requesting master's priority level is higher than that of the master that currently has control over the slave port, unless the slave port is in a parked state. the slave port performs an arbitration check at every clock edge to ensure that the proper master, if any, has control of the slave port. the following table describes possible scenarios based on the requesting master port: table 17-29. how axbs grants control of a slave port to a master when then axbs grants control to the requesting master both of the following are true: the current master is not running a transfer. the new requesting master's priority level is higher than that of the current master. at the next clock edge both of the following are true: the current master is running a fixed length burst transfer or a locked transfer. the requesting master's priority level is higher than that of the current master. at the end of the burst transfer or locked transfer the master is running an undefined length burst transfer. at the next arbitration point note: arbitration points for an undefined length burst are defined in the mgpcr for each master. the requesting master's priority level is lower than the current master. at the conclusion of one of the following cycles: an idle cycle a non-idle cycle to a location other than the current slave port 17.3.3.3 round-robin priority operation when operating in round-robin mode, each master is assigned a relative priority based on the master port number. this relative priority is compared to the master port number (id) of the last master to perform a transfer on the slave bus. the highest priority requesting master becomes owner of the slave bus at the next transfer boundary, accounting for locked and fixed-length burst transfers. priority is based on how far ahead the id of the requesting master is to the id of the last master. after granted access to a slave port, a master may perform as many transfers as desired to that port until another master makes a request to the same slave port. the next master in line is granted access to the slave port at the next transfer boundary, or possibly on the next clock cycle if the current master has no pending access request. as an example of arbitration in round-robin mode, assume the crossbar is implemented with master ports 0, 1, 4, and 5. if the last master of the slave port was master 1, and master 0, 4 and 5 make simultaneous requests, they are serviced in the order 4, 5, and then 0. functional description k60 sub-family reference manual, rev. 6, nov 2011 374 freescale semiconductor, inc. parking may continue to be used in a round-robin mode, but does not affect the round- robin pointer unless the parked master actually performs a transfer. handoff occurs to the next master in line after one cycle of arbitration. if the slave port is put into low-power park mode, the round-robin pointer is reset to point at master port 0, giving it the highest priority. 17.3.3.4 priority assignment each master port needs to be assigned a unique 3-bit priority level. if an attempt is made to program multiple master ports with the same priority level within the priority registers (prs n ), the crossbar switch responds with a bus error and the registers are not updated. 17.4 initialization/application information no initialization is required by or for the crossbar switch. hardware reset ensures all the register bits used by the crossbar switch are properly initialized to a valid state. settings and priorities should be programmed to achieve maximum system performance. chapter 17 crossbar switch (axbs) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 375 initialization/application information k60 sub-family reference manual, rev. 6, nov 2011 376 freescale semiconductor, inc. chapter 18 memory protection unit (mpu) 18.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the memory protection unit (mpu) provides hardware access control for all memory references generated in the device. 18.2 overview the mpu concurrently monitors all system bus transactions and evaluates their appropriateness using pre-programmed region descriptors that define memory spaces and their access rights. memory references that have sufficient access control rights are allowed to complete, while references that are not mapped to any region descriptor or have insufficient rights are terminated with a protection error response. 18.2.1 block diagram a simplified block diagram of the mpu module is shown in the following figure. the hardware's two-dimensional connection matrix is clearly visible with the basic access evaluation macro shown as the replicated submodule block. the crossbar switch slave ports are shown on the left, the region descriptor registers in the middle, and the peripheral bus interface on the right side. the evaluation macro contains two magnitude comparators connected to the start and end address registers from each region descriptor as well as the combinational logic blocks to determine the region hit and the access protection error. for details of the access evaluation macro, see access evaluation macro . k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 377 slave port n nternal reion escritor reion escritor reion escritor x access evaluation macro access evaluation macro access evaluation macro mux address phase signals peripheral bus mpu_ear n mpu_edr n figure 18-1. mpu bloc diagram 18.2.2 features the mpu implements a two-dimensional hardware array of memory region descriptors and the crossbar slave ports to continuously monitor the legality of every memory reference generated by each bus master in the system. the feature set includes: ? 12 program-visible 128-bit region descriptors, accessible by four 32-bit words each ? each region descriptor defines a modulo-32 byte space, aligned anywhere in memory ? region sizes can vary from 32 bytes to 4 gbytes ? two access control permissions defined in a single descriptor word ? masters 0C3: read, write, and execute attributes for supervisor and user accesses ? masters 4C7: read and write attributes ? hardware-assisted maintenance of the descriptor valid bit minimizes coherency issues overview k60 sub-family reference manual, rev. 6, nov 2011 378 freescale semiconductor, inc. ? alternate programming model view of the access control permissions word ? priority given to granting permission over denying access for overlapping region descriptors ? detects access protection errors if a memory reference does not hit in any memory region, or if the reference is illegal in all hit memory regions. if an access error occurs, the reference is terminated with an error response, and the mpu inhibits the bus cycle being sent to the targeted slave device. ? error registers (per slave port) capture the last faulting address, attributes, and other information ? global mpu enable/disable control bit 18.3 memory map/register definition the programming model is partitioned into three groups: control/status registers, the data structure containing the region descriptors, and the alternate view of the region descriptor access control values. the programming model can only be referenced using 32-bit accesses. attempted references using different access sizes, to undefined (reserved) addresses, or with a non- supported access type (a write to a read-only register, or a read of a write-only register) generate an error termination. the programming model can be accessed only in supervisor mode. note see the chip configuration details for any chip-specific register information for this module. mpu memory map absolute address (hex) register name width (in bits) access reset value section/ page 4000_d000 control/error status register (mpu_cesr) 32 r/w 0081_5101h 18.3.1/382 4000_d010 error address register, slave port n (mpu_ear0) 32 r undefined 18.3.2/384 4000_d014 error detail register, slave port n (mpu_edr0) 32 r undefined 18.3.3/385 4000_d018 error address register, slave port n (mpu_ear1) 32 r undefined 18.3.2/384 4000_d01c error detail register, slave port n (mpu_edr1) 32 r undefined 18.3.3/385 table continues on the next page... chapter 18 memory protection unit mpu 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 7 mpu memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4000_d020 error address register, slave port n (mpu_ear2) 32 r undefined 18.3.2/384 4000_d024 error detail register, slave port n (mpu_edr2) 32 r undefined 18.3.3/385 4000_d028 error address register, slave port n (mpu_ear3) 32 r undefined 18.3.2/384 4000_d02c error detail register, slave port n (mpu_edr3) 32 r undefined 18.3.3/385 4000_d030 error address register, slave port n (mpu_ear4) 32 r undefined 18.3.2/384 4000_d034 error detail register, slave port n (mpu_edr4) 32 r undefined 18.3.3/385 4000_d400 region descriptor n, word 0 (mpu_rgd0_word0) 32 r/w 0000_0000h 18.3.4/386 4000_d404 region descriptor n, word 1 (mpu_rgd0_word1) 32 r/w 0000_001fh 18.3.5/387 4000_d408 region descriptor n, word 2 (mpu_rgd0_word2) 32 r/w 0000_0000h 18.3.6/387 4000_d40c region descriptor n, word 3 (mpu_rgd0_word3) 32 r/w 0000_0000h 18.3.7/390 4000_d410 region descriptor n, word 0 (mpu_rgd1_word0) 32 r/w 0000_0000h 18.3.4/386 4000_d414 region descriptor n, word 1 (mpu_rgd1_word1) 32 r/w 0000_001fh 18.3.5/387 4000_d418 region descriptor n, word 2 (mpu_rgd1_word2) 32 r/w 0000_0000h 18.3.6/387 4000_d41c region descriptor n, word 3 (mpu_rgd1_word3) 32 r/w 0000_0000h 18.3.7/390 4000_d420 region descriptor n, word 0 (mpu_rgd2_word0) 32 r/w 0000_0000h 18.3.4/386 4000_d424 region descriptor n, word 1 (mpu_rgd2_word1) 32 r/w 0000_001fh 18.3.5/387 4000_d428 region descriptor n, word 2 (mpu_rgd2_word2) 32 r/w 0000_0000h 18.3.6/387 4000_d42c region descriptor n, word 3 (mpu_rgd2_word3) 32 r/w 0000_0000h 18.3.7/390 4000_d430 region descriptor n, word 0 (mpu_rgd3_word0) 32 r/w 0000_0000h 18.3.4/386 4000_d434 region descriptor n, word 1 (mpu_rgd3_word1) 32 r/w 0000_001fh 18.3.5/387 4000_d438 region descriptor n, word 2 (mpu_rgd3_word2) 32 r/w 0000_0000h 18.3.6/387 4000_d43c region descriptor n, word 3 (mpu_rgd3_word3) 32 r/w 0000_0000h 18.3.7/390 4000_d440 region descriptor n, word 0 (mpu_rgd4_word0) 32 r/w 0000_0000h 18.3.4/386 4000_d444 region descriptor n, word 1 (mpu_rgd4_word1) 32 r/w 0000_001fh 18.3.5/387 4000_d448 region descriptor n, word 2 (mpu_rgd4_word2) 32 r/w 0000_0000h 18.3.6/387 4000_d44c region descriptor n, word 3 (mpu_rgd4_word3) 32 r/w 0000_0000h 18.3.7/390 4000_d450 region descriptor n, word 0 (mpu_rgd5_word0) 32 r/w 0000_0000h 18.3.4/386 4000_d454 region descriptor n, word 1 (mpu_rgd5_word1) 32 r/w 0000_001fh 18.3.5/387 4000_d458 region descriptor n, word 2 (mpu_rgd5_word2) 32 r/w 0000_0000h 18.3.6/387 4000_d45c region descriptor n, word 3 (mpu_rgd5_word3) 32 r/w 0000_0000h 18.3.7/390 4000_d460 region descriptor n, word 0 (mpu_rgd6_word0) 32 r/w 0000_0000h 18.3.4/386 4000_d464 region descriptor n, word 1 (mpu_rgd6_word1) 32 r/w 0000_001fh 18.3.5/387 4000_d468 region descriptor n, word 2 (mpu_rgd6_word2) 32 r/w 0000_0000h 18.3.6/387 table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 80 freescale semiconductor, inc. mpu memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4000_d46c region descriptor n, word 3 (mpu_rgd6_word3) 32 r/w 0000_0000h 18.3.7/390 4000_d470 region descriptor n, word 0 (mpu_rgd7_word0) 32 r/w 0000_0000h 18.3.4/386 4000_d474 region descriptor n, word 1 (mpu_rgd7_word1) 32 r/w 0000_001fh 18.3.5/387 4000_d478 region descriptor n, word 2 (mpu_rgd7_word2) 32 r/w 0000_0000h 18.3.6/387 4000_d47c region descriptor n, word 3 (mpu_rgd7_word3) 32 r/w 0000_0000h 18.3.7/390 4000_d480 region descriptor n, word 0 (mpu_rgd8_word0) 32 r/w 0000_0000h 18.3.4/386 4000_d484 region descriptor n, word 1 (mpu_rgd8_word1) 32 r/w 0000_001fh 18.3.5/387 4000_d488 region descriptor n, word 2 (mpu_rgd8_word2) 32 r/w 0000_0000h 18.3.6/387 4000_d48c region descriptor n, word 3 (mpu_rgd8_word3) 32 r/w 0000_0000h 18.3.7/390 4000_d490 region descriptor n, word 0 (mpu_rgd9_word0) 32 r/w 0000_0000h 18.3.4/386 4000_d494 region descriptor n, word 1 (mpu_rgd9_word1) 32 r/w 0000_001fh 18.3.5/387 4000_d498 region descriptor n, word 2 (mpu_rgd9_word2) 32 r/w 0000_0000h 18.3.6/387 4000_d49c region descriptor n, word 3 (mpu_rgd9_word3) 32 r/w 0000_0000h 18.3.7/390 4000_d4a0 region descriptor n, word 0 (mpu_rgd10_word0) 32 r/w 0000_0000h 18.3.4/386 4000_d4a4 region descriptor n, word 1 (mpu_rgd10_word1) 32 r/w 0000_001fh 18.3.5/387 4000_d4a8 region descriptor n, word 2 (mpu_rgd10_word2) 32 r/w 0000_0000h 18.3.6/387 4000_d4ac region descriptor n, word 3 (mpu_rgd10_word3) 32 r/w 0000_0000h 18.3.7/390 4000_d4b0 region descriptor n, word 0 (mpu_rgd11_word0) 32 r/w 0000_0000h 18.3.4/386 4000_d4b4 region descriptor n, word 1 (mpu_rgd11_word1) 32 r/w 0000_001fh 18.3.5/387 4000_d4b8 region descriptor n, word 2 (mpu_rgd11_word2) 32 r/w 0000_0000h 18.3.6/387 4000_d4bc region descriptor n, word 3 (mpu_rgd11_word3) 32 r/w 0000_0000h 18.3.7/390 4000_d800 region descriptor alternate access control n (mpu_rgdaac0) 32 r/w 0000_0000h 18.3.8/391 4000_d804 region descriptor alternate access control n (mpu_rgdaac1) 32 r/w 0000_0000h 18.3.8/391 4000_d808 region descriptor alternate access control n (mpu_rgdaac2) 32 r/w 0000_0000h 18.3.8/391 4000_d80c region descriptor alternate access control n (mpu_rgdaac3) 32 r/w 0000_0000h 18.3.8/391 4000_d810 region descriptor alternate access control n (mpu_rgdaac4) 32 r/w 0000_0000h 18.3.8/391 4000_d814 region descriptor alternate access control n (mpu_rgdaac5) 32 r/w 0000_0000h 18.3.8/391 4000_d818 region descriptor alternate access control n (mpu_rgdaac6) 32 r/w 0000_0000h 18.3.8/391 table continues on the next page... chapter 18 memory protection unit mpu 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 81 mpu memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4000_d81c region descriptor alternate access control n (mpu_rgdaac7) 32 r/w 0000_0000h 18.3.8/391 4000_d820 region descriptor alternate access control n (mpu_rgdaac8) 32 r/w 0000_0000h 18.3.8/391 4000_d824 region descriptor alternate access control n (mpu_rgdaac9) 32 r/w 0000_0000h 18.3.8/391 4000_d828 region descriptor alternate access control n (mpu_rgdaac10) 32 r/w 0000_0000h 18.3.8/391 4000_d82c region descriptor alternate access control n (mpu_rgdaac11) 32 r/w 0000_0000h 18.3.8/391 18.3.1 control/error status register (mpu_cesr) address: mpu_cesr is 4000_d000h base + 0h offset = 4000_d000h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r sperr 0 1 0 hrl nsp nrgd 0 vld w w1c reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 1 mpu_cesr field descriptions field description 3127 sperr slave port n error indicates a captured error in earn and edrn. this bit is set when the hardware detects an error and records the faulting address and attributes. it is cleared by writing one to it. if another error is captured at the exact same cycle as the write, the flag remains set. a find-first-one instruction (or equivalent) can detect the presence of a captured error. the following shows the correspondence between the bit number and slave port number: ? bit 31 corresponds to slave port 0. ? bit 30 corresponds to slave port 1. ? bit 29 corresponds to slave port 2. ? bit 28 corresponds to slave port 3. ? bit 27 corresponds to slave port 4. 0 no error has occurred for slave port n. 1 an error has occurred for slave port n. 2624 reserved this read-only field is reserved and always has the value zero. 23 reserved this read-only field is reserved and always has the value one. table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 82 freescale semiconductor, inc. mpu_cesr field descriptions (continued) field description 2220 reserved this read-only field is reserved and always has the value zero. 1916 hrl hardware revision level specifies the mpu?s hardware and definition revision level. it can be read by software to determine the functional definition of the module. 1512 nsp number of slave ports specifies the number of slave ports connected to the mpu. 118 nrgd number of region descriptors indicates the number of region descriptors implemented in the mpu. 0000 8 region descriptors 0001 12 region descriptors 0010 16 region descriptors 71 reserved this read-only field is reserved and always has the value zero. 0 vld valid (global enable/disable for the mpu) 0 mpu is disabled. all accesses from all bus masters are allowed. 1 mpu is enabled chapter 18 memory protection unit (mpu) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 383 18.3.2 error address register, slave port n (mpu_ear n when the mpu detects an access error on slave port n, the 32-bit reference address is captured in this read-only register and the corresponding bit in cesr[sperr] set. additional information about the faulting access is captured in the corresponding edrn at the same time. this register and the corresponding edrn contain the most recent access error; there are no hardware interlocks with cesr[sperr], as the error registers are always loaded upon the occurrence of each protection violation. addresses: mpu_ear0 is 4000_d000h base + 10h offset = 4000_d010h mpu_ear1 is 4000_d000h base + 18h offset = 4000_d018h mpu_ear2 is 4000_d000h base + 20h offset = 4000_d020h mpu_ear3 is 4000_d000h base + 28h offset = 4000_d028h mpu_ear4 is 4000_d000h base + 30h offset = 4000_d030h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r eaddr w reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes: x = undefined at reset. mpu_ear n iel escritions fiel escrition r rror aress nicates the reerence aress ro slae ort n that enerate the access error eory areister einition ufaily reerence anual re o freescale eiconuctor nc 18.3.3 error detail register, slave port n (mpu_edr n when the mpu detects an access error on slave port n, 32 bits of error detail are captured in this read-only register and the corresponding bit in cesr[sperr] is set. information on the faulting address is captured in the corresponding earn register at the same time. this register and the corresponding earn register contain the most recent access error; there are no hardware interlocks with cesr[sperr] as the error registers are always loaded upon the occurrence of each protection violation. addresses: mpu_edr0 is 4000_d000h base + 14h offset = 4000_d014h mpu_edr1 is 4000_d000h base + 1ch offset = 4000_d01ch mpu_edr2 is 4000_d000h base + 24h offset = 4000_d024h mpu_edr3 is 4000_d000h base + 2ch offset = 4000_d02ch mpu_edr4 is 4000_d000h base + 34h offset = 4000_d034h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r eacd w reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 emn eattr erw w reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes: x = undefined at reset. mpu_edr n iel escritions fiel escrition rror access control etail nicates the reion escritor with the access error rn contains a cature error an is cleare an access i not hit in any reion escritor only a sinle it is set the rotection error was cause y a sinle nonoerlain reion escritor two or ore its are set the rotection error was cause y an oerlain set o reion escritors resere his reaonly iel is resere an always has the alue ero rror aster nuer nicates the us aster that enerate the access error r rror attriutes nicates attriute inoration aout the aultin reerence table continues on the next page... chapter 18 memory protection unit mpu 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 8 mpu_edr n iel escritions continue fiel escrition o: ll other encoins are resere user oe instruction access user oe ata access uerisor oe instruction access uerisor oe ata access r rror reawrite nicates the access tye o the aultin reerence rea rite reion escritor n or uror the first word of the region descriptor defines the 0-modulo-32 byte start address of the memory region. writes to this register clear the region descriptors valid bit (rgdn_word3[vld]). addresses: 4000_d000h base + 400h offset + (16d n , where n 0d to 11d bit 1 0 2 28 27 26 2 24 2 22 21 20 1 18 17 16 1 14 1 12 11 10 8 7 6 4 2 1 0 r srtaddr 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mpu_rd n or iel escritions fiel escrition rr tart aress eines the ost siniicant its o the oulo yte start aress o the eory reion resere his reaonly iel is resere an always has the alue ero eory areister einition ufaily reerence anual re o freescale eiconuctor nc 18.3.5 region descriptor n, word 1 (mpu_rgd_word1) the second word of the region descriptor defines the 31-modulo-32 byte end address of the memory region. writes to this register clear the region descriptors valid bit (rgdn_word3[vld]). addresses: 4000_d000h base + 404h offset + (16d n , where n 0d to 11d bit 1 0 2 28 27 26 2 24 2 22 21 20 1 18 17 16 1 14 1 12 11 10 8 7 6 4 2 1 0 r endaddr reserved w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 mpu_rd n or iel escritions fiel escrition r n aress eines the ost siniicant its o the oulo yte en aress o the eory reion o: he u oes not eriy that r rr resere his iel is resere reion escritor n or uror the third word of the region descriptor defines the access control rights of the memory region. the access control privileges depend on two broad classifications of bus masters: ? bus masters 0C3 have a 5-bit field defining separate privilege rights for user and supervisor mode accesses. ? bus masters 4C7 are limited to separate read and write permissions. for the privilege rights of bus masters 0C3, there are three flags associated with this function: ? read (r) refers to accessing the referenced memory address using an operand (data) fetch ? write (w) refers to updating the referenced memory address using a store (data) instruction ? execute (x) refers to reading the referenced memory address using an instruction fetch chapter 18 memory protection unit (mpu) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 387 writes to rgdn_word2 clear the region descriptors valid bit (rgdn_word3[vld]). if only updating the access controls, write to rgdaacn instead because stores to these locations do not affect the descriptors valid bit. addresses: 4000_d000h base + 408h offset + (16d n , where n 0d to 11d bit 1 0 2 28 27 26 2 24 2 22 21 20 1 18 17 16 r m7re m7we m6re m6we mre mwe m4re m4we reserved msm mum reserved m2sm -141 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 1 14 1 12 11 10 8 7 6 4 2 1 0 r m2sm bit 0 m2um reserved m1sm m1um reserved m0sm m0um w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mpu_rd n or iel escritions fiel escrition r us aster rea enale us aster reas terinate with an access error an the rea is not erore us aster reas allowe us aster write enale us aster writes terinate with an access error an the write is not erore us aster writes allowe r us aster rea enale us aster reas terinate with an access error an the rea is not erore us aster reas allowe us aster write enale us aster writes terinate with an access error an the write is not erore us aster writes allowe r us aster rea enale us aster reas terinate with an access error an the rea is not erore us aster reas allowe us aster write enale us aster writes terinate with an access error an the write is not erore us aster writes allowe r us aster rea enale table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 88 freescale semiconductor, inc. mpu_rgd n or iel escritions continue fiel escrition us aster reas terinate with an access error an the rea is not erore us aster reas allowe us aster write enale us aster writes terinate with an access error an the write is not erore us aster writes allowe resere his iel is resere his it ust e written with a ero us aster suerisor oe access control eines the access controls or us aster in suerisor oe rwx rea write an execute allowe rx rea an execute allowe ut no write rw rea an write allowe ut no execute ae as user oe eine in u u us aster user oe access control eines the access controls or us aster in user oe u consists o three ineenent its enalin rea r write w an execute x erissions n attete access o that oe ay e terinate with an access error i not allowe y another escritor an the access not erore llows the ien access tye to occur resere his iel is resere his it ust e written with a ero us aster suerisor oe access control ee escrition u us aster user oe access control ee u escrition resere his iel is resere his it ust e written with a ero us aster suerisor oe access control ee escrition u us aster user oe access control ee u escrition resere his iel is resere his it ust e written with a ero us aster suerisor oe access control ee escrition u us aster user oe access control table continues on the next page... chapter 18 memory protection unit mpu 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 8 mpu_rgd n or iel escritions continue fiel escrition ee u escrition reion escritor n or uror the fourth word of the region descriptor contains the region descriptors valid bit. addresses: 4000_d000h base + 40ch offset + (16d n , where n 0d to 11d bit 1 0 2 28 27 26 2 24 2 22 21 20 1 18 17 16 1 14 1 12 11 10 8 7 6 4 2 1 0 r 0 vd w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mpu_rd n or iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero l ali inals the reion escritor is ali ny write to rnor clears this it reion escritor is inali reion escritor is ali eory areister einition ufaily reerence anual re o freescale eiconuctor nc 18.3.8 region descriptor alternate access control n (mpu_rgdaac n since software may adjust only the access controls within a region descriptor (rgdn_word2) as different tasks execute, an alternate programming view of this 32- bit entity is available. writing to this register does not affect the descriptors valid bit. addresses: 4000_d000h base + 800h offset + (4d n , where n 0d to 11d bit 1 0 2 28 27 26 2 24 2 22 21 20 1 18 17 16 r m7re m7we m6re m6we mre mwe m4re m4we reserved msm mum reserved m2sm -141 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 1 14 1 12 11 10 8 7 6 4 2 1 0 r m2sm bit 0 m2um reserved m1sm m1um reserved m0sm m0um w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mpu_rdaac n iel escritions fiel escrition r us aster rea enale us aster reas terinate with an access error an the rea is not erore us aster reas allowe us aster write enale us aster writes terinate with an access error an the write is not erore us aster writes allowe r us aster rea enale us aster reas terinate with an access error an the rea is not erore us aster reas allowe us aster write enale us aster writes terinate with an access error an the write is not erore us aster writes allowe r us aster rea enale us aster reas terinate with an access error an the rea is not erore us aster reas allowe us aster write enale table continues on the next page... chapter 18 memory protection unit mpu 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1 mpu_rgdaac n iel escritions continue fiel escrition us aster writes terinate with an access error an the write is not erore us aster writes allowe r us aster rea enale us aster reas terinate with an access error an the rea is not erore us aster reas allowe us aster write enale us aster writes terinate with an access error an the write is not erore us aster writes allowe resere his iel is resere his it ust e written with a ero us aster suerisor oe access control eines the access controls or us aster in suerisor oe rwx rea write an execute allowe rx rea an execute allowe ut no write rw rea an write allowe ut no execute ae as user oe eine in u u us aster user oe access control eines the access controls or us aster in user oe u consists o three ineenent its enalin rea r write w an execute x erissions n attete access o that oe ay e terinate with an access error i not allowe y another escritor an the access not erore llows the ien access tye to occur resere his iel is resere his it ust e written with a ero us aster suerisor oe access control ee escrition u us aster user oe access control ee u escrition resere his iel is resere his it ust e written with a ero us aster suerisor oe access control ee escrition u us aster user oe access control ee u escrition resere his iel is resere his it ust e written with a ero table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 2 freescale semiconductor, inc. mpu_rgdaac n iel escritions continue fiel escrition us aster suerisor oe access control ee escrition u us aster user oe access control ee u escrition functional escrition in this section, the functional operation of the mpu is detailed, including the operation of the access evaluation macro and the handling of error-terminated bus cycles. 18.4.1 access evaluation macro the basic operation of the mpu is performed in the access evaluation macro, a hardware structure replicated in the two-dimensional connection matrix. as shown in the following figure, the access evaluation macro inputs the crossbar bus address phase signals and the contents of a region descriptor (rgd n ) and performs two major functions: region hit determination and detection of an access protection violation. the following figure shows a functional block diagram. start end error n mpu_edr n access not allowed 18.4.1.1 hit determination to determine if the current reference hits in the given region, two magnitude comparators are used with the region's start and end addresses. the boolean equation for this portion of the hit determination is: region_hit = ((addr[31:5] >= rgd n _word0[srtaddr]) & (addr[31:5] <= rgd n _word1[endaddr])) & rgd n _word3[vld] where addr is the current reference address, rgd n _word0[srtaddr] and rgd n _word1[endaddr] are the start and end addresses, and rgd n _word3[vld] is the valid bit. note the mpu does not verify that endaddr srtaddr. 18.4.1.2 privilege violation determination while the access evaluation macro is determining region hit, the logic is also evaluating if the current access is allowed by the permissions defined in the region descriptor. using the master and supervisor/user mode signals, a set of effective permissions is generated from the appropriate fields in the region descriptor. the protection violation logic then evaluates the access against the effective permissions using the specification shown below. table 18-80. protection violation definition description m x u rotection iolation r w x nstruction etch rea es no execute erission o access is allowe ata rea es no rea erission o access is allowe ata write es no write erission o access is allowe uttin t ll oether an rror erinations for each slave port monitored, the mpu performs a reduction-and of all the individual terms from each access evaluation macro. this expression then terminates the bus cycle with an error and reports a protection error for three conditions: functional description k60 sub-family reference manual, rev. 6, nov 2011 394 freescale semiconductor, inc. 1. if the access does not hit in any region descriptor, a protection error is reported. 2. if the access hits in a single region descriptor and that region signals a protection violation, a protection error is reported. 3. if the access hits in multiple (overlapping) regions and all regions signal protection violations, a protection error is reported. as shown in the third condition, granting permission is a higher priority than denying access for overlapping regions. this approach is more flexible to system software in region descriptor assignments. for an example of the use of overlapping region descriptors, see application information . 18.4.3 power management disabling the mpu by clearing cesr[vld] minimizes power dissipation. to minimize the power dissipation of an enabled mpu, invalidate unused region descriptors by clearing the associated rgdn_word3[vld] bits. 18.5 initialization information at system startup, load the appropriate number of region descriptors, including setting rgd n _word3[vld]. setting cesr[vld] enables the module. if the system requires that all the loaded region descriptors be enabled simultaneously, first ensure that the entire mpu is disabled (cesr[vld]=0). note a region descriptor must be set to allow access to the mpu registers if further changes are needed. 18.6 application information in an operational system, interfacing with the mpu is generally classified into the following activities: chapter 18 memory protection unit (mpu) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 395 ? creating a new memory regionload the appropriate region descriptor into an available rgd n , using four sequential 32-bit writes. the hardware assists in the maintenance of the valid bit, so if this approach is followed, there are no coherency issues with the multi-cycle descriptor writes. (clearing rgd n _word3[vld] deletes/ removes an existing memory region.) ? altering only access privilegesto not affect the valid bit, write to the alternate version of the access control word (rgdaac n ), so there are no coherency issues involved with the update. when the write completes, the memory region's access rights switch instantaneously to the new value. ? changing a region's start and end addresseswrite a minimum of three words to the region descriptor (rgd n _word{0,1,3}). word 0 and 1 redefine the start and end addresses, respectively. word 3 re-enables the region descriptor valid bit. in most situations, all four words of the region descriptor are rewritten. ? accessing the mpuallocate a region descriptor to restrict mpu access to supervisor mode from a specific master. ? detecting an access errorthe current bus cycle is terminated with an error response and ear n and edr n capture information on the faulting reference. the error-terminated bus cycle typically initiates an error response in the originating bus master. for example, a processor core may respond with a bus error exception, while a data movement bus master may respond with an error interrupt. the processor can retrieve the captured error address and detail information simply by reading e{a,d}r n . cesr[sperr] signals which error registers contain captured fault data. ? overlapping region descriptorsapplying overlapping regions often reduces the number of descriptors required for a given set of access controls. in the overlapping memory space, the protection rights of the corresponding region descriptors are logically summed together (the boolean or operator). the following dual-core system example contains four bus masters: the two processors (cp0, cp1) and two dma engines (dma1, a traditional data movement engine transferring data between ram and peripherals and dma2, a second engine transferring data to/from the ram only). consider the following region descriptor assignments: table 18-81. overlapping region descriptor example region description rgdn cp0 cp1 dma1 dma2 cp0 code 0 rwx r-- flash cp1 code 1 r-- rwx table continues on the next page... application information 60 sub-family reference manual, rev. 6, nov 2011 6 freescale semiconductor, inc. table 18-81. overlapping region descriptor example (continued) region description rgdn cp0 cp1 dma1 dma2 cp0 data & stack 2 rw- ram cp0 in this example, there are eight descriptors used to span nine regions in the three main spaces of the system memory map (flash, ram, and peripheral space). each region indicates the specific permissions for each of the four bus masters and this definition provides an appropriate set of shared, private and executable memory spaces. of particular interest are the two overlapping spaces: region descriptors 2 & 3 and 3 & 4. the space defined by rgd2 with no overlap is a private data and stack area that provides read/write access to cp0 only. the overlapping space between rgd2 and rgd3 defines a shared data space for passing data from cp0 to cp1 and the access controls are defined by the logical or of the two region descriptors. thus, cp0 has (rw- | r--) = (rw-) permissions, while cp1 has (--- | r--) = (r--) permission in this space. both dma engines are excluded from this shared processor data region. the overlapping spaces between rgd3 and rgd4 defines another shared data space, this one for passing data from cp1 to cp0. for this overlapping space, cp0 has (r-- | ---) = (r--) permission, while cp1 has (rw- | r--) = (rw-) permission. the non-overlapped space of rgd4 defines a private data and stack area for cp1 only. the space defined by rgd5 is a shared data region, accessible by all four bus masters. finally, the slave peripheral space mapped onto the ips bus is partitioned into two regions: one containing the mpu's programming model accessible only to the two processor cores and the remaining peripheral region accessible to both processors and the traditional dma1 master. this simple example is intended to show one possible application of the capabilities of the mpu in a typical system. chapter 18 memory protection unit (mpu) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 397 application information k60 sub-family reference manual, rev. 6, nov 2011 398 freescale semiconductor, inc. chapter 19 peripheral bridge (aips-lite) 19.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the peripheral bridge (aips-lite) converts the crossbar switch interface to an interface to access a majority of peripherals on the device. the peripheral bridge supports up to 128 peripherals. the peripheral bridge occupies a 64 mb portion of the address space. the bridge includes separate clock enable inputs for each of the slots to accommodate slower peripherals. 19.1.1 features key features of the peripheral bridge are: ? supports up to 128 peripherals ? supports 8-, 16-, and 32-bit width peripheral slots ? each independently configurable peripheral includes a clock enable, which allows peripherals to operate at any speed less than the system clock rate. ? programming model provides memory protection functionality 19.1.2 general operation the peripherals connected to the peripheral bridge are modules that contain readable/ writable control and status registers. the system masters read and write these registers through the peripheral bridge. the peripheral bridge generates module enables, the k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 399 module address, transfer attributes, byte enables, and write data as inputs to the peripherals. the peripheral bridge captures read data from the peripheral interface and drives it to the crossbar switch. the register maps of the peripherals are located on 4 kb boundaries. each peripheral is allocated one 4 kb block of the memory map. the peripheral bridge (aips-lite) memory map is illustrated as follows. addresses description base + 0x000_0000 - 0x000_0fff module #0 base + 0x000_1000 - 0x000_1fff module #1 ... ... base + 0x007_f000 - 0x007_ffff module #127 19.2 memory map/register definition the peripheral bridge registers are 32-bit registers and can only be accessed in supervisor mode by trusted bus masters. additionally, these registers must only be read from or written to by a 32-bit aligned access. the peripheral bridge registers are mapped into the pacr0 address space. two system clocks are required for read accesses, and three system clocks are required for write accesses to the peripheral bridge registers. note the number of fields and registers available depends on the device-specific implementation of the peripheral bridge module. see the chip configuration chapter for more information. aips memory map absolute address (hex) register name width (in bits) access reset value section/ page 4000_0000 master privilege register a (aips0_mpra) 32 r/w undefined 19.2.1/401 4000_0020 peripheral access control register (aips0_pacra) 32 r/w 4444_4444h 19.2.2/405 4000_0024 peripheral access control register (aips0_pacrb) 32 r/w 4444_4444h 19.2.2/405 4000_0028 peripheral access control register (aips0_pacrc) 32 r/w 4444_4444h 19.2.2/405 4000_002c peripheral access control register (aips0_pacrd) 32 r/w 4444_4444h 19.2.2/405 table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 400 freescale semiconductor, inc. aips memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4000_0040 peripheral access control register (aips0_pacre) 32 r/w undefined 19.2.3/410 4000_0044 peripheral access control register (aips0_pacrf) 32 r/w undefined 19.2.3/410 4000_0048 peripheral access control register (aips0_pacrg) 32 r/w undefined 19.2.3/410 4000_004c peripheral access control register (aips0_pacrh) 32 r/w undefined 19.2.3/410 4000_0050 peripheral access control register (aips0_pacri) 32 r/w undefined 19.2.3/410 4000_0054 peripheral access control register (aips0_pacrj) 32 r/w undefined 19.2.3/410 4000_0058 peripheral access control register (aips0_pacrk) 32 r/w undefined 19.2.3/410 4000_005c peripheral access control register (aips0_pacrl) 32 r/w undefined 19.2.3/410 4000_0060 peripheral access control register (aips0_pacrm) 32 r/w undefined 19.2.3/410 4000_0064 peripheral access control register (aips0_pacrn) 32 r/w undefined 19.2.3/410 4000_0068 peripheral access control register (aips0_pacro) 32 r/w undefined 19.2.3/410 4000_006c peripheral access control register (aips0_pacrp) 32 r/w undefined 19.2.3/410 4008_0000 master privilege register a (aips1_mpra) 32 r/w undefined 19.2.1/401 4008_0020 peripheral access control register (aips1_pacra) 32 r/w 4444_4444h 19.2.2/405 4008_0024 peripheral access control register (aips1_pacrb) 32 r/w 4444_4444h 19.2.2/405 4008_0028 peripheral access control register (aips1_pacrc) 32 r/w 4444_4444h 19.2.2/405 4008_002c peripheral access control register (aips1_pacrd) 32 r/w 4444_4444h 19.2.2/405 4008_0040 peripheral access control register (aips1_pacre) 32 r/w undefined 19.2.3/410 4008_0044 peripheral access control register (aips1_pacrf) 32 r/w undefined 19.2.3/410 4008_0048 peripheral access control register (aips1_pacrg) 32 r/w undefined 19.2.3/410 4008_004c peripheral access control register (aips1_pacrh) 32 r/w undefined 19.2.3/410 4008_0050 peripheral access control register (aips1_pacri) 32 r/w undefined 19.2.3/410 4008_0054 peripheral access control register (aips1_pacrj) 32 r/w undefined 19.2.3/410 4008_0058 peripheral access control register (aips1_pacrk) 32 r/w undefined 19.2.3/410 4008_005c peripheral access control register (aips1_pacrl) 32 r/w undefined 19.2.3/410 4008_0060 peripheral access control register (aips1_pacrm) 32 r/w undefined 19.2.3/410 4008_0064 peripheral access control register (aips1_pacrn) 32 r/w undefined 19.2.3/410 4008_0068 peripheral access control register (aips1_pacro) 32 r/w undefined 19.2.3/410 4008_006c peripheral access control register (aips1_pacrp) 32 r/w undefined 19.2.3/410 19.2.1 master privilege register a (aips x r the mpra register specifies identical 4-bit fields defining the access-privilege level associated with a bus master in the device to the various peripherals. the register provides one field per bus master. chapter 19 peripheral bridge (aips-lite) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 401 note at reset, the default value loaded into the mprot[7-0] fields is device-specific. see the chip configuration details for the value on your particular device. accesses to registers or register fields which correspond to master or peripheral locations which are not implemented return zeros on reads, and are ignored on writes. each master is assigned depending on its connection to the crossbar switch master ports. see your device-specific chip configuration details for information about the master assignments to these registers. addresses: aips0_mpra is 4000_0000h base + 0h offset = 4000_0000h aips1_mpra is 4008_0000h base + 0h offset = 4008_0000h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 mtr0 mtw0 mpl0 0 mtr1 mtw1 mpl1 0 mtr2 mtw2 mpl2 0 mtr3 mtw3 mpl3 0 mtr4 mtw4 mpl4 0 mtr5 mtw5 mpl5 0 0 w reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes: x = undefined at reset. aips x r iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero r aster truste or rea eterines whether the aster is truste or rea accesses his aster is not truste or rea accesses his aster is truste or rea accesses aster truste or writes eterines whether the aster is truste or write accesses his aster is not truste or write accesses his aster is truste or write accesses l aster riilee leel eciies how the riilee leel o the aster is eterine ccesses ro this aster are orce to useroe ccesses ro this aster are not orce to useroe resere his reaonly iel is resere an always has the alue ero table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 402 freescale semiconductor, inc. aips x r iel escritions continue fiel escrition r aster truste or rea eterines whether the aster is truste or rea accesses his aster is not truste or rea accesses his aster is truste or rea accesses aster truste or writes eterines whether the aster is truste or write accesses his aster is not truste or write accesses his aster is truste or write accesses l aster riilee leel eciies how the riilee leel o the aster is eterine ccesses ro this aster are orce to useroe ccesses ro this aster are not orce to useroe resere his reaonly iel is resere an always has the alue ero r aster truste or rea eterines whether the aster is truste or rea accesses his aster is not truste or rea accesses his aster is truste or rea accesses aster truste or writes eterines whether the aster is truste or write accesses his aster is not truste or write accesses his aster is truste or write accesses l aster riilee leel eciies how the riilee leel o the aster is eterine ccesses ro this aster are orce to useroe ccesses ro this aster are not orce to useroe resere his reaonly iel is resere an always has the alue ero r aster truste or rea eterines whether the aster is truste or rea accesses his aster is not truste or rea accesses his aster is truste or rea accesses aster truste or writes eterines whether the aster is truste or write accesses table continues on the next page... chapter 1 peripheral bridge aips-ite 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 40 aips x r iel escritions continue fiel escrition his aster is not truste or write accesses his aster is truste or write accesses l aster riilee leel eciies how the riilee leel o the aster is eterine ccesses ro this aster are orce to useroe ccesses ro this aster are not orce to useroe resere his reaonly iel is resere an always has the alue ero r aster truste or rea eterines whether the aster is truste or rea accesses his aster is not truste or rea accesses his aster is truste or rea accesses aster truste or writes eterines whether the aster is truste or write accesses his aster is not truste or write accesses his aster is truste or write accesses l aster riilee leel eciies how the riilee leel o the aster is eterine ccesses ro this aster are orce to useroe ccesses ro this aster are not orce to useroe resere his reaonly iel is resere an always has the alue ero r aster truste or rea eterines whether the aster is truste or rea accesses his aster is not truste or rea accesses his aster is truste or rea accesses aster truste or writes eterines whether the aster is truste or write accesses his aster is not truste or write accesses his aster is truste or write accesses l aster riilee leel eciies how the riilee leel o the aster is eterine ccesses ro this aster are orce to useroe ccesses ro this aster are not orce to useroe resere his reaonly iel is resere an always has the alue ero table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 404 freescale semiconductor, inc. aips x r iel escritions continue fiel escrition resere his reaonly iel is resere an always has the alue ero eriheral ccess ontrol reister x r n each of the peripherals has a four-bit pacr[0:127] field which defines the access levels supported by the given module. eight pacr fields are grouped together to form a 32-bit pacr[a:p] register: ? pacra-p define the access levels for the 128 peripherals the peripheral assignments to each pacr register is defined by the memory map slot that the peripherals are assigned.see the device's memory map details for the assignments for your particular device. note the reset value of the pacra-d registers is 0x4444_4444. the following table shows the top-level structure of the pacr registers. offset register [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] 0x20 pacra pacr0 pacr1 pacr2 pacr3 pacr4 pacr5 pacr6 pacr7 0x24 pacrb pacr8 pacr9 pacr10 pacr11 pacr12 pacr13 pacr14 pacr15 0x28 pacrc pacr16 pacr17 pacr18 pacr19 pacr20 pacr21 pacr22 pacr23 0x2c pacrd pacr24 pacr25 pacr26 pacr27 pacr28 pacr29 pacr30 pacr31 0x30 reserved 0x34 reserved 0x38 reserved 0x3c reserved 0x40 pacre pacr32 pacr33 pacr34 pacr35 pacr36 pacr37 pacr38 pacr39 0x44 pacrf pacr40 pacr41 pacr42 pacr43 pacr44 pacr45 pacr46 pacr47 0x48 pacrg pacr48 pacr49 pacr50 pacr51 pacr52 pacr53 pacr54 pacr55 0x4c pacrh pacr56 pacr57 pacr58 pacr59 pacr60 pacr61 pacr62 pacr63 0x50 pacri pacr64 pacr65 pacr66 pacr67 pacr68 pacr69 pacr70 pacr71 0x54 pacrj pacr72 pacr73 pacr74 pacr75 pacr76 pacr77 pacr78 pacr79 0x58 pacrk pacr80 pacr81 pacr82 pacr83 pacr84 pacr85 pacr86 pacr87 0x5c pacrl pacr88 pacr89 pacr90 pacr91 pacr92 pacr93 pacr94 pacr95 table continues on the next page... chapter 1 peripheral bridge aips-ite 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 40 offset register [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] 0x60 pacrm pacr96 pacr97 pacr98 pacr99 pacr100 pacr101 pacr102 pacr103 0x64 pacrn pacr104 pacr105 pacr106 pacr107 pacr108 pacr109 pacr110 pacr111 0x68 pacro pacr112 pacr113 pacr114 pacr115 pacr116 pacr117 pacr118 pacr119 0x6c pacrp pacr120 pacr121 pacr122 pacr123 pacr124 pacr125 pacr126 pacr127 addresses: aips0_pacra is 4000_0000h base + 20h offset = 4000_0020h aips0_pacrb is 4000_0000h base + 24h offset = 4000_0024h aips0_pacrc is 4000_0000h base + 28h offset = 4000_0028h aips0_pacrd is 4000_0000h base + 2ch offset = 4000_002ch aips1_pacra is 4008_0000h base + 20h offset = 4008_0020h aips1_pacrb is 4008_0000h base + 24h offset = 4008_0024h aips1_pacrc is 4008_0000h base + 28h offset = 4008_0028h aips1_pacrd is 4008_0000h base + 2ch offset = 4008_002ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 sp0 wp0 tp0 0 sp1 wp1 tp1 0 sp2 wp2 tp2 0 sp3 wp3 tp3 0 sp4 wp4 tp4 0 sp5 wp5 tp5 0 sp6 wp6 tp6 0 sp7 wp7 tp7 w reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 aips x r n iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero uerisor rotect eterines whether the eriheral requires suerisor riilee leel or access hen this it is set the aster riilee leel ust inicate the suerisor access attriute an the ronl control it or the aster ust e set not access terinates with an error resonse an no eriheral access initiates his eriheral oes not require suerisor riilee leel or accesses his eriheral requires suerisor riilee leel or accesses rite rotect eterines whether the eriheral allows write accesss hen this it is set an a write access is attete access terinates with an error resonse an no eriheral access initiates his eriheral allows write accesses his eriheral is write rotecte ruste rotect eterines whether the eriheral allows accesses ro an untruste aster hen this it is set an an access is attete y an untruste aster the access terinates with an error resonse an no eriheral access initiates ccesses ro an untruste aster are allowe ccesses ro an untruste aster are not allowe table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 406 freescale semiconductor, inc. aips x r n iel escritions continue fiel escrition resere his reaonly iel is resere an always has the alue ero uerisor rotect eterines whether the eriheral requires suerisor riilee leel or access hen this it is set the aster riilee leel ust inicate the suerisor access attriute an the ronl control it or the aster ust e set not access terinates with an error resonse an no eriheral access initiates his eriheral oes not require suerisor riilee leel or accesses his eriheral requires suerisor riilee leel or accesses rite rotect eterines whether the eriheral allows write accesss hen this it is set an a write access is attete access terinates with an error resonse an no eriheral access initiates his eriheral allows write accesses his eriheral is write rotecte ruste rotect eterines whether the eriheral allows accesses ro an untruste aster hen this it is set an an access is attete y an untruste aster the access terinates with an error resonse an no eriheral access initiates ccesses ro an untruste aster are allowe ccesses ro an untruste aster are not allowe resere his reaonly iel is resere an always has the alue ero uerisor rotect eterines whether the eriheral requires suerisor riilee leel or access hen this it is set the aster riilee leel ust inicate the suerisor access attriute an the ronl control it or the aster ust e set not access terinates with an error resonse an no eriheral access initiates his eriheral oes not require suerisor riilee leel or accesses his eriheral requires suerisor riilee leel or accesses rite rotect eterines whether the eriheral allows write accesss hen this it is set an a write access is attete access terinates with an error resonse an no eriheral access initiates his eriheral allows write accesses his eriheral is write rotecte ruste rotect eterines whether the eriheral allows accesses ro an untruste aster hen this it is set an an access is attete y an untruste aster the access terinates with an error resonse an no eriheral access initiates table continues on the next page... chapter 1 peripheral bridge aips-ite 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 407 aips x r n iel escritions continue fiel escrition ccesses ro an untruste aster are allowe ccesses ro an untruste aster are not allowe resere his reaonly iel is resere an always has the alue ero uerisor rotect eterines whether the eriheral requires suerisor riilee leel or access hen this it is set the aster riilee leel ust inicate the suerisor access attriute an the ronl control it or the aster ust e set not access terinates with an error resonse an no eriheral access initiates his eriheral oes not require suerisor riilee leel or accesses his eriheral requires suerisor riilee leel or accesses rite rotect eterines whether the eriheral allows write accesss hen this it is set an a write access is attete access terinates with an error resonse an no eriheral access initiates his eriheral allows write accesses his eriheral is write rotecte ruste rotect eterines whether the eriheral allows accesses ro an untruste aster hen this it is set an an access is attete y an untruste aster the access terinates with an error resonse an no eriheral access initiates ccesses ro an untruste aster are allowe ccesses ro an untruste aster are not allowe resere his reaonly iel is resere an always has the alue ero uerisor rotect eterines whether the eriheral requires suerisor riilee leel or access hen this it is set the aster riilee leel ust inicate the suerisor access attriute an the ronl control it or the aster ust e set not access terinates with an error resonse an no eriheral access initiates his eriheral oes not require suerisor riilee leel or accesses his eriheral requires suerisor riilee leel or accesses rite rotect eterines whether the eriheral allows write accesss hen this it is set an a write access is attete access terinates with an error resonse an no eriheral access initiates his eriheral allows write accesses his eriheral is write rotecte ruste rotect table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 408 freescale semiconductor, inc. aips x r n iel escritions continue fiel escrition eterines whether the eriheral allows accesses ro an untruste aster hen this it is set an an access is attete y an untruste aster the access terinates with an error resonse an no eriheral access initiates ccesses ro an untruste aster are allowe ccesses ro an untruste aster are not allowe resere his reaonly iel is resere an always has the alue ero uerisor rotect eterines whether the eriheral requires suerisor riilee leel or access hen this it is set the aster riilee leel ust inicate the suerisor access attriute an the ronl control it or the aster ust e set not access terinates with an error resonse an no eriheral access initiates his eriheral oes not require suerisor riilee leel or accesses his eriheral requires suerisor riilee leel or accesses rite rotect eterines whether the eriheral allows write accesss hen this it is set an a write access is attete access terinates with an error resonse an no eriheral access initiates his eriheral allows write accesses his eriheral is write rotecte ruste rotect eterines whether the eriheral allows accesses ro an untruste aster hen this it is set an an access is attete y an untruste aster the access terinates with an error resonse an no eriheral access initiates ccesses ro an untruste aster are allowe ccesses ro an untruste aster are not allowe resere his reaonly iel is resere an always has the alue ero uerisor rotect eterines whether the eriheral requires suerisor riilee leel or access hen this it is set the aster riilee leel ust inicate the suerisor access attriute an the ronl control it or the aster ust e set not access terinates with an error resonse an no eriheral access initiates his eriheral oes not require suerisor riilee leel or accesses his eriheral requires suerisor riilee leel or accesses rite rotect eterines whether the eriheral allows write accesss hen this it is set an a write access is attete access terinates with an error resonse an no eriheral access initiates his eriheral allows write accesses his eriheral is write rotecte table continues on the next page... chapter 1 peripheral bridge aips-ite 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 40 aips x r n iel escritions continue fiel escrition ruste rotect eterines whether the eriheral allows accesses ro an untruste aster hen this it is set an an access is attete y an untruste aster the access terinates with an error resonse an no eriheral access initiates ccesses ro an untruste aster are allowe ccesses ro an untruste aster are not allowe resere his reaonly iel is resere an always has the alue ero uerisor rotect eterines whether the eriheral requires suerisor riilee leel or access hen this it is set the aster riilee leel ust inicate the suerisor access attriute an the ronl control it or the aster ust e set not access terinates with an error resonse an no eriheral access initiates his eriheral oes not require suerisor riilee leel or accesses his eriheral requires suerisor riilee leel or accesses rite rotect eterines whether the eriheral allows write accesss hen this it is set an a write access is attete access terinates with an error resonse an no eriheral access initiates his eriheral allows write accesses his eriheral is write rotecte ruste rotect eterines whether the eriheral allows accesses ro an untruste aster hen this it is set an an access is attete y an untruste aster the access terinates with an error resonse an no eriheral access initiates ccesses ro an untruste aster are allowe ccesses ro an untruste aster are not allowe eriheral ccess ontrol reister x r n each of the peripherals has a four-bit pacr[0:127] field which defines the access levels supported by the given module. eight pacr fields are grouped together to form a 32-bit pacr[a:p] register: ? pacra-p define the access levels for the 128 peripherals the peripheral assignments to each pacr register is defined by the memory map slot that the peripherals are assigned.see the device's memory map details for the assignments for your particular device. memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 410 freescale semiconductor, inc. note the reset value of the pacre-p depends on your device's configuration. addresses: 4000_0000h base + 40h offset + (4d n , where n 0d to 11d bit 1 0 2 28 27 26 2 24 2 22 21 20 1 18 17 16 1 14 1 12 11 10 8 7 6 4 2 1 0 r 0 sp0 wp0 tp0 0 sp1 wp1 tp1 0 sp2 wp2 tp2 0 sp wp tp 0 sp4 wp4 tp4 0 sp wp tp 0 sp6 wp6 tp6 0 sp7 wp7 tp7 w reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes x undefined at reset. aips x r n iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero uerisor rotect eterines whether the eriheral requires suerisor riilee leel or access hen this it is set the aster riilee leel ust inicate the suerisor access attriute an the ronl control it or the aster ust e set not access terinates with an error resonse an no eriheral access initiates his eriheral oes not require suerisor riilee leel or accesses his eriheral requires suerisor riilee leel or accesses rite rotect eterines whether the eriheral allows write accesss hen this it is set an a write access is attete access terinates with an error resonse an no eriheral access initiates his eriheral allows write accesses his eriheral is write rotecte ruste rotect eterines whether the eriheral allows accesses ro an untruste aster hen this it is set an an access is attete y an untruste aster the access terinates with an error resonse an no eriheral access initiates ccesses ro an untruste aster are allowe ccesses ro an untruste aster are not allowe resere his reaonly iel is resere an always has the alue ero uerisor rotect eterines whether the eriheral requires suerisor riilee leel or access hen this it is set the aster riilee leel ust inicate the suerisor access attriute an the ronl control it or the aster ust e set not access terinates with an error resonse an no eriheral access initiates table continues on the next page... chapter 1 peripheral bridge aips-ite 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 411 aips x r n iel escritions continue fiel escrition his eriheral oes not require suerisor riilee leel or accesses his eriheral requires suerisor riilee leel or accesses rite rotect eterines whether the eriheral allows write accesss hen this it is set an a write access is attete access terinates with an error resonse an no eriheral access initiates his eriheral allows write accesses his eriheral is write rotecte ruste rotect eterines whether the eriheral allows accesses ro an untruste aster hen this it is set an an access is attete y an untruste aster the access terinates with an error resonse an no eriheral access initiates ccesses ro an untruste aster are allowe ccesses ro an untruste aster are not allowe resere his reaonly iel is resere an always has the alue ero uerisor rotect eterines whether the eriheral requires suerisor riilee leel or access hen this it is set the aster riilee leel ust inicate the suerisor access attriute an the ronl control it or the aster ust e set not access terinates with an error resonse an no eriheral access initiates his eriheral oes not require suerisor riilee leel or accesses his eriheral requires suerisor riilee leel or accesses rite rotect eterines whether the eriheral allows write accesss hen this it is set an a write access is attete access terinates with an error resonse an no eriheral access initiates his eriheral allows write accesses his eriheral is write rotecte ruste rotect eterines whether the eriheral allows accesses ro an untruste aster hen this it is set an an access is attete y an untruste aster the access terinates with an error resonse an no eriheral access initiates ccesses ro an untruste aster are allowe ccesses ro an untruste aster are not allowe resere his reaonly iel is resere an always has the alue ero uerisor rotect eterines whether the eriheral requires suerisor riilee leel or access hen this it is set the aster riilee leel ust inicate the suerisor access attriute an the ronl control it or table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 412 freescale semiconductor, inc. aips x r n iel escritions continue fiel escrition the aster ust e set not access terinates with an error resonse an no eriheral access initiates his eriheral oes not require suerisor riilee leel or accesses his eriheral requires suerisor riilee leel or accesses rite rotect eterines whether the eriheral allows write accesss hen this it is set an a write access is attete access terinates with an error resonse an no eriheral access initiates his eriheral allows write accesses his eriheral is write rotecte ruste rotect eterines whether the eriheral allows accesses ro an untruste aster hen this it is set an an access is attete y an untruste aster the access terinates with an error resonse an no eriheral access initiates ccesses ro an untruste aster are allowe ccesses ro an untruste aster are not allowe resere his reaonly iel is resere an always has the alue ero uerisor rotect eterines whether the eriheral requires suerisor riilee leel or access hen this it is set the aster riilee leel ust inicate the suerisor access attriute an the ronl control it or the aster ust e set not access terinates with an error resonse an no eriheral access initiates his eriheral oes not require suerisor riilee leel or accesses his eriheral requires suerisor riilee leel or accesses rite rotect eterines whether the eriheral allows write accesss hen this it is set an a write access is attete access terinates with an error resonse an no eriheral access initiates his eriheral allows write accesses his eriheral is write rotecte ruste rotect eterines whether the eriheral allows accesses ro an untruste aster hen this it is set an an access is attete y an untruste aster the access terinates with an error resonse an no eriheral access initiates ccesses ro an untruste aster are allowe ccesses ro an untruste aster are not allowe resere his reaonly iel is resere an always has the alue ero uerisor rotect table continues on the next page... chapter 1 peripheral bridge aips-ite 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 41 aips x r n iel escritions continue fiel escrition eterines whether the eriheral requires suerisor riilee leel or access hen this it is set the aster riilee leel ust inicate the suerisor access attriute an the ronl control it or the aster ust e set not access terinates with an error resonse an no eriheral access initiates his eriheral oes not require suerisor riilee leel or accesses his eriheral requires suerisor riilee leel or accesses rite rotect eterines whether the eriheral allows write accesss hen this it is set an a write access is attete access terinates with an error resonse an no eriheral access initiates his eriheral allows write accesses his eriheral is write rotecte ruste rotect eterines whether the eriheral allows accesses ro an untruste aster hen this it is set an an access is attete y an untruste aster the access terinates with an error resonse an no eriheral access initiates ccesses ro an untruste aster are allowe ccesses ro an untruste aster are not allowe resere his reaonly iel is resere an always has the alue ero uerisor rotect eterines whether the eriheral requires suerisor riilee leel or access hen this it is set the aster riilee leel ust inicate the suerisor access attriute an the ronl control it or the aster ust e set not access terinates with an error resonse an no eriheral access initiates his eriheral oes not require suerisor riilee leel or accesses his eriheral requires suerisor riilee leel or accesses rite rotect eterines whether the eriheral allows write accesss hen this it is set an a write access is attete access terinates with an error resonse an no eriheral access initiates his eriheral allows write accesses his eriheral is write rotecte ruste rotect eterines whether the eriheral allows accesses ro an untruste aster hen this it is set an an access is attete y an untruste aster the access terinates with an error resonse an no eriheral access initiates ccesses ro an untruste aster are allowe ccesses ro an untruste aster are not allowe resere his reaonly iel is resere an always has the alue ero table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 414 freescale semiconductor, inc. aips x r n iel escritions continue fiel escrition uerisor rotect eterines whether the eriheral requires suerisor riilee leel or access hen this it is set the aster riilee leel ust inicate the suerisor access attriute an the ronl control it or the aster ust e set not access terinates with an error resonse an no eriheral access initiates his eriheral oes not require suerisor riilee leel or accesses his eriheral requires suerisor riilee leel or accesses rite rotect eterines whether the eriheral allows write accesss hen this it is set an a write access is attete access terinates with an error resonse an no eriheral access initiates his eriheral allows write accesses his eriheral is write rotecte ruste rotect eterines whether the eriheral allows accesses ro an untruste aster hen this it is set an an access is attete y an untruste aster the access terinates with an error resonse an no eriheral access initiates ccesses ro an untruste aster are allowe ccesses ro an untruste aster are not allowe functional escrition the peripheral bridge serves as an interface between the crossbar switch and the slave peripheral bus. it functions as a protocol translator. accesses which fall within the address space of the peripheral bridge are decoded to provide individual module selects for peripheral devices on the slave bus interface. 19.3.1 access support aligned and misaligned 32-bit and 16-bit accesses, as well as byte accesses are supported for 32-bit peripherals. misaligned accesses are supported to allow memory to be placed on the slave peripheral bus. peripheral registers must not be misaligned, although no explicit checking is performed by the peripheral bridge. all accesses are performed with a single transfer. all accesses to the peripheral slots must be sized less than or equal to the designated peripheral slot size. if an access is attempted which is larger (in size) than the targeted port, an error response is generated. chapter 19 peripheral bridge (aips-lite) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 415 functional description k60 sub-family reference manual, rev. 6, nov 2011 416 freescale semiconductor, inc. chapter 20 direct memory access multiplexer (dmamux) 20.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. 20.1.1 overview the dma mux routes up to 63 dma sources (called slots) to be mapped to any of the 16 dma channels. this is illustrated in the following figure. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 417 dma channel #0 source #1 source #2 source #3 always #1 dma channel # n always y source x trigger 1 trigger z dma channel 1 dmamux figure 20-1. dma mux bloc diagram 20.1.2 features the dma channel mux provides these features: ? 52 peripheral slots + 10 always-on slots can be routed to 16 channels. ? 16 independently selectable dma channel routers. ? the first 4 channels additionally provide a trigger functionality. ? each channel router can be assigned to one of the 52 possible peripheral dma slots or to one of the 10 always-on slots. 20.1.3 modes of operation the following operating modes are available: ? disabled mode introduction k60 sub-family reference manual, rev. 6, nov 2011 418 freescale semiconductor, inc. in this mode, the dma channel is disabled. since disabling and enabling of dma channels is done primarily via the dma configuration registers, this mode is used mainly as the reset state for a dma channel in the dma channel mux. it may also be used to temporarily suspend a dma channel while reconfiguration of the system takes place (e.g. changing the period of a dma trigger). ? normal mode in this mode, a dma source (such as dspi transmit or dspi receive) is routed directly to the specified dma channel. the operation of the dma mux in this mode is completely transparent to the system. ? periodic trigger mode in this mode, a dma source may only request a dma transfer (such as when a transmit buffer becomes empty or a receive buffer becomes full) periodically. configuration of the period is done in the registers of the periodic interrupt timer (pit). this mode is only available for channels 0-3. 20.2 external signal description the dma mux has no external pins. 20.3 memory map/register definition this section provides a detailed description of all memory-mapped registers in the dma mux. the following table shows the memory map for the dma mux. all registers are accessible via 8-bit, 16-bit or 32-bit accesses. however, 16-bit accesses must be aligned to 16-bit boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. as an example, chcfg0 through chcfg3 are accessible by a 32-bit read/ write to address 'base + 0x00', but performing a 32-bit access to address 'base + 0x01' is illegal. chapter 20 direct memory access multiplexer (dmamux) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 419 dmamux memory map absolute address (hex) register name width (in bits) access reset value section/ page 4002_1000 channel configuration register (dmamux_chcfg0) 8 r/w 00h 20.3.1/420 4002_1001 channel configuration register (dmamux_chcfg1) 8 r/w 00h 20.3.1/420 4002_1002 channel configuration register (dmamux_chcfg2) 8 r/w 00h 20.3.1/420 4002_1003 channel configuration register (dmamux_chcfg3) 8 r/w 00h 20.3.1/420 4002_1004 channel configuration register (dmamux_chcfg4) 8 r/w 00h 20.3.1/420 4002_1005 channel configuration register (dmamux_chcfg5) 8 r/w 00h 20.3.1/420 4002_1006 channel configuration register (dmamux_chcfg6) 8 r/w 00h 20.3.1/420 4002_1007 channel configuration register (dmamux_chcfg7) 8 r/w 00h 20.3.1/420 4002_1008 channel configuration register (dmamux_chcfg8) 8 r/w 00h 20.3.1/420 4002_1009 channel configuration register (dmamux_chcfg9) 8 r/w 00h 20.3.1/420 4002_100a channel configuration register (dmamux_chcfg10) 8 r/w 00h 20.3.1/420 4002_100b channel configuration register (dmamux_chcfg11) 8 r/w 00h 20.3.1/420 4002_100c channel configuration register (dmamux_chcfg12) 8 r/w 00h 20.3.1/420 4002_100d channel configuration register (dmamux_chcfg13) 8 r/w 00h 20.3.1/420 4002_100e channel configuration register (dmamux_chcfg14) 8 r/w 00h 20.3.1/420 4002_100f channel configuration register (dmamux_chcfg15) 8 r/w 00h 20.3.1/420 20.3.1 channel configuration register (dmamux_chcfg n each of the dma channels can be independently enabled/disabled and associated with one of the dma slots (peripheral slots or always-on slots) in the system. note setting multiple chcfg registers with the same source value will result in unpredictable behavior. note before changing the trigger or source settings a dma channel must be disabled via the chcfgn[enbl] bit. addresses: 4002_1000h base + 0h offset + (1d n , where n 0d to 1d bit 7 6 4 2 1 0 read enb tri surce write reset 0 0 0 0 0 0 0 0 memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 420 freescale semiconductor, inc. dmamux_chcfg n iel escritions fiel escrition l hannel nale nales the channel channel is isale his oe is riarily use urin coniuration o the ux he has searate channel enalesisales which shoul e use to isale or reconiure a channel channel is enale r hannel rier nale nales the erioic trier caaility or the triere channel rierin is isale trierin is isale an the l it is set the hannel will sily route the seciie source to the channel noral oe rierin is enale trierin is enale an the l it is set the u is in erioic trier oe our hannel ource slot eciies which source i any is route to a articular channel lease chec your eices hi oniuration etails or urther etails aout the eriherals an their slot nuers functional escrition this section provides the functional description of the dma mux. the primary purpose of the dma mux is to provide flexibility in the system's use of the available dma channels. as such, configuration of the dma mux is intended to be a static procedure done during execution of the system boot code. however, if the procedure outlined in enabling and configuring sources is followed, the configuration of the dma mux may be changed during the normal operation of the system. functionally, the dma mux channels may be divided into two classes: channels, which implement the normal routing functionality plus periodic triggering capability, and channels, which implement only the normal routing functionality. 20.4.1 dma channels with periodic triggering capability besides the normal routing functionality, the first four channels of the dma mux provide a special periodic triggering capability that can be used to provide an automatic mechanism to transmit bytes, frames or packets at fixed intervals without the need for processor intervention. the trigger is generated by the periodic interrupt timer (pit); as chapter 20 direct memory access multiplexer (dmamux) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 421 such, the configuration of the periodic triggering interval is done via configuration registers in the pit. please refer to periodic interrupt timer chapter for more information on this topic. note because of the dynamic nature of the system (i.e. dma channel priorities, bus arbitration, interrupt service routine lengths, etc.), the number of clock cycles between a trigger and the actual dma transfer cannot be guaranteed. dma channel #0 trigger #2 source #1 source #2 source #3 always #1 dma channel #3 always # y trigger 4 source x trigger 1 dma channel 1 figure 20-1. dma mux triggered channels the dma channel triggering capability allows the system to "schedule" regular dma transfers, usually on the transmit side of certain peripherals, without the intervention of the processor. this trigger works by gating the request from the peripheral to the dma until a trigger event has been seen. this is illustrated in the following figure. functional description k60 sub-family reference manual, rev. 6, nov 2011 422 freescale semiconductor, inc. dma request peripheral request trigger figure 20-20. dma mux channel triggering: normal operation once the dma request has been serviced, the peripheral will negate its request, effectively resetting the gating mechanism until the peripheral re-asserts its request and the next trigger event is seen. this means that if a trigger is seen, but the peripheral is not requesting a transfer, that triggered will be ignored. this situation is illustrated in the following figure. dma request peripheral request trigger figure 20-21. dma mux channel triggering: ignored trigger this triggering capability may be used with any peripheral that supports dma transfers, and is most useful for two types of situations: ? periodically polling external devices on a particular bus. as an example, the transmit side of an spi is assigned to a dma channel with a trigger, as described above. once setup, the spi will request dma transfers (presumably from memory) as long as its transmit buffer is empty. by using a trigger on this channel, the spi transfers can be automatically performed every 5 s (as an example). on the receive side of the spi, the spi and dma can be configured to transfer receive data into memory, effectively implementing a method to periodically read data from external devices and transfer the results into memory without processor intervention. ? using the gpio ports to drive or sample waveforms. by configuring the dma to transfer data to one or more gpio ports, it is possible to create complex waveforms using tabular data stored in on-chip memory. conversely, using the dma to periodically transfer data from one or more gpio ports, it is possible to sample complex waveforms and store the results in tabular form in on-chip memory. a more detailed description of the capability of each trigger (which includes resolution, range of values, etc.) may be found in the periodic interrupt timer chapter. chapter 20 direct memory access multiplexer (dmamux) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 423 20.4.2 dma channels with no triggering capability the other channels of the dma mux provide the normal routing functionality as described in modes of operation . 20.4.3 "always enabled" dma sources in addition to the peripherals that can be used as dma sources, there are 10 additional dma sources that are "always enabled". unlike the peripheral dma sources, where the peripheral controls the flow of data during dma transfers, the "always enabled" sources provide no such "throttling" of the data transfers. these sources are most useful in the following cases: ? doing dma transfers to/from gpiomoving data from/to one or more gpio pins, either un-throttled (that is as fast as possible), or periodically (using the dma triggering capability). ? doing dma transfers from memory to memorymoving data from memory to memory, typically as fast as possible, sometimes with software activation. ? doing dma transfers from memory to the external bus (or vice-versa)similar to memory to memory transfers, this is typically done as quickly as possible. ? any dma transfer that requires software activationany dma transfer that should be explicitly started by software. in cases where software should initiate the start of a dma transfer, an "always enabled" dma source can be used to provide maximum flexibility. when activating a dma channel via software, subsequent executions of the minor loop require a new "start" event be sent. this can either be a new software activation, or a transfer request from the dma channel mux. the options for doing this are: ? transfer all data in a single minor loop. by configuring the dma to transfer all of the data in a single minor loop (that is major loop counter = 1), no re-activation of the channel is necessary. the disadvantage to this option is the reduced granularity in determining the load that the dma transfer will incur on the system. for this option, the dma channel should be disabled in the dma channel mux. functional description k60 sub-family reference manual, rev. 6, nov 2011 424 freescale semiconductor, inc. ? use explicit software re-activation. in this option, the dma is configured to transfer the data using both minor and major loops, but the processor is required to re-activate the channel (by writing to the dma registers) after every minor loop . for this option, the dma channel should be disabled in the dma channel mux. ? use a "always enabled" dma source. in this option, the dma is configured to transfer the data using both minor and major loops, and the dma channel mux does the channel re-activation. for this option, the dma channel should be enabled and pointing to an "always enabled" source. note that the re-activation of the channel can be continuous (dma triggering is disabled) or can use the dma triggering capability. in this manner, it is possible to execute periodic transfers of packets of data from one source to another, without processor intervention. 20.5 initialization/application information this section provides instructions for initializing the dma channel mux. 20.5.1 reset the reset state of each individual bit is shown in memory map/register definition . in summary, after reset, all channels are disabled and must be explicitly enabled before use. 20.5.2 enabling and configuring sources enabling a source with periodic triggering 1. determine with which dma channel the source will be associated. note that only the first 4 dma channels have periodic triggering capability 2. clear the chcfg[enbl] and chcfg[trig] bits of the dma channel 3. ensure that the dma channel is properly configured in the dma. the dma channel may be enabled at this point 4. configure the corresponding timer 5. select the source to be routed to the dma channel. write to the corresponding chcfg register, ensuring that the chcfg[enbl] and chcfg[trig] bits are set configure source #5 transmit for use with dma channel 2, with periodic triggering capability 1. write 0x00 to chcfg2 (base address + 0x02) 2. configure channel 2 in the dma, including enabling the channel chapter 20 direct memory access multiplexer (dmamux) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 425 3. configure a timer for the desired trigger interval 4. write 0xc5 to chcfg2 (base address + 0x02) the following code example illustrates steps #1 and #4 above: in file registers.h: #define dmamux_base_addr 0xfc084000/* example only ! */ /* following example assumes char is 8-bits */ volatile unsigned char *chconfig0 = (volatile unsigned char *) (dmamux_base_addr+0x0000); volatile unsigned char *chconfig1 = (volatile unsigned char *) (dmamux_base_addr+0x0001); volatile unsigned char *chconfig2 = (volatile unsigned char *) (dmamux_base_addr+0x0002); volatile unsigned char *chconfig3 = (volatile unsigned char *) (dmamux_base_addr+0x0003); volatile unsigned char *chconfig4 = (volatile unsigned char *) (dmamux_base_addr+0x0004); volatile unsigned char *chconfig5 = (volatile unsigned char *) (dmamux_base_addr+0x0005); volatile unsigned char *chconfig6 = (volatile unsigned char *) (dmamux_base_addr+0x0006); volatile unsigned char *chconfig7 = (volatile unsigned char *) (dmamux_base_addr+0x0007); volatile unsigned char *chconfig8 = (volatile unsigned char *) (dmamux_base_addr+0x0008); volatile unsigned char *chconfig9 = (volatile unsigned char *) (dmamux_base_addr+0x0009); volatile unsigned char *chconfig10= (volatile unsigned char *) (dmamux_base_addr+0x000a); volatile unsigned char *chconfig11= (volatile unsigned char *) (dmamux_base_addr+0x000b); volatile unsigned char *chconfig12= (volatile unsigned char *) (dmamux_base_addr+0x000c); volatile unsigned char *chconfig13= (volatile unsigned char *) (dmamux_base_addr+0x000d); volatile unsigned char *chconfig14= (volatile unsigned char *) (dmamux_base_addr+0x000e); volatile unsigned char *chconfig15= (volatile unsigned char *) (dmamux_base_addr+0x000f); in file main.c: #include "registers.h" : : *chconfig2 = 0x00; *chconfig2 = 0xc5; enabling a source without periodic triggering 1. determine with which dma channel the source will be associated. note that only the first 4 dma channels have periodic triggering capability 2. clear the chcfg[enbl] and chcfg[trig] bits of the dma channel 3. ensure that the dma channel is properly configured in the dma. the dma channel may be enabled at this point 4. select the source to be routed to the dma channel. write to the corresponding chcfg register, ensuring that the chcfg[enbl] is set while the chcfg[trig] bit is cleared configure source #5 transmit for use with dma channel 2, with no periodic triggering capability. 1. write 0x00 to chcfg2 (base address + 0x02) 2. configure channel 2 in the dma, including enabling the channel 3. write 0x85 to chcfg2 (base address + 0x02) the following code example illustrates steps #1 and #3 above: in file registers.h: #define dmamux_base_addr 0xfc084000/* example only ! */ /* following example assumes char is 8-bits */ volatile unsigned char *chconfig0 = (volatile unsigned char *) (dmamux_base_addr+0x0000); volatile unsigned char *chconfig1 = (volatile unsigned char *) (dmamux_base_addr+0x0001); volatile unsigned char *chconfig2 = (volatile unsigned char *) (dmamux_base_addr+0x0002); initialization/application information k60 sub-family reference manual, rev. 6, nov 2011 426 freescale semiconductor, inc. volatile unsigned char *chconfig3 = (volatile unsigned char *) (dmamux_base_addr+0x0003); volatile unsigned char *chconfig4 = (volatile unsigned char *) (dmamux_base_addr+0x0004); volatile unsigned char *chconfig5 = (volatile unsigned char *) (dmamux_base_addr+0x0005); volatile unsigned char *chconfig6 = (volatile unsigned char *) (dmamux_base_addr+0x0006); volatile unsigned char *chconfig7 = (volatile unsigned char *) (dmamux_base_addr+0x0007); volatile unsigned char *chconfig8 = (volatile unsigned char *) (dmamux_base_addr+0x0008); volatile unsigned char *chconfig9 = (volatile unsigned char *) (dmamux_base_addr+0x0009); volatile unsigned char *chconfig10= (volatile unsigned char *) (dmamux_base_addr+0x000a); volatile unsigned char *chconfig11= (volatile unsigned char *) (dmamux_base_addr+0x000b); volatile unsigned char *chconfig12= (volatile unsigned char *) (dmamux_base_addr+0x000c); volatile unsigned char *chconfig13= (volatile unsigned char *) (dmamux_base_addr+0x000d); volatile unsigned char *chconfig14= (volatile unsigned char *) (dmamux_base_addr+0x000e); volatile unsigned char *chconfig15= (volatile unsigned char *) (dmamux_base_addr+0x000f); in file main.c: #include "registers.h" : : *chconfig2 = 0x00; *chconfig2 = 0x85; disabling a source a particular dma source may be disabled by not writing the corresponding source value into any of the chcfg registers. additionally, some module specific configuration may be necessary. please refer to the appropriate section for more details. switching the source of a dma channel 1. disable the dma channel in the dma and re-configure the channel for the new source 2. clear the chcfg[enbl] and chcfg[trig] bits of the dma channel 3. select the source to be routed to the dma channel. write to the corresponding chcfg register, ensuring that the chcfg[enbl] and chcfg[trig] bits are set switch dma channel 8 from source #5 transmit to source #7 transmit 1. in the dma configuration registers, disable dma channel 8 and re-configure it to handle the transfers to peripheral slot 7. this example assumes channel 8 doesn't have triggering capability 2. write 0x00 to chcfg8 (base address + 0x08) 3. write 0x87 to chcfg8 (base address + 0x08). (in this example, setting the chcfg[trig] bit would have no effect, due to the assumption that channels 8 does not support the periodic triggering functionality). the following code example illustrates steps #2 and #3 above: in file registers.h: #define dmamux_base_addr 0xfc084000/* example only ! */ /* following example assumes char is 8-bits */ volatile unsigned char *chconfig0 = (volatile unsigned char *) (dmamux_base_addr+0x0000); volatile unsigned char *chconfig1 = (volatile unsigned char *) (dmamux_base_addr+0x0001); volatile unsigned char *chconfig2 = (volatile unsigned char *) (dmamux_base_addr+0x0002); volatile unsigned char *chconfig3 = (volatile unsigned char *) (dmamux_base_addr+0x0003); volatile unsigned char *chconfig4 = (volatile unsigned char *) (dmamux_base_addr+0x0004); volatile unsigned char *chconfig5 = (volatile unsigned char *) (dmamux_base_addr+0x0005); volatile unsigned char *chconfig6 = (volatile unsigned char *) (dmamux_base_addr+0x0006); volatile unsigned char *chconfig7 = (volatile unsigned char *) (dmamux_base_addr+0x0007); chapter 20 direct memory access multiplexer (dmamux) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 427 volatile unsigned char *chconfig8 = (volatile unsigned char *) (dmamux_base_addr+0x0008); volatile unsigned char *chconfig9 = (volatile unsigned char *) (dmamux_base_addr+0x0009); volatile unsigned char *chconfig10= (volatile unsigned char *) (dmamux_base_addr+0x000a); volatile unsigned char *chconfig11= (volatile unsigned char *) (dmamux_base_addr+0x000b); volatile unsigned char *chconfig12= (volatile unsigned char *) (dmamux_base_addr+0x000c); volatile unsigned char *chconfig13= (volatile unsigned char *) (dmamux_base_addr+0x000d); volatile unsigned char *chconfig14= (volatile unsigned char *) (dmamux_base_addr+0x000e); volatile unsigned char *chconfig15= (volatile unsigned char *) (dmamux_base_addr+0x000f); in file main.c: #include "registers.h" : : *chconfig8 = 0x00; *chconfig8 = 0x87; initialization/application information k60 sub-family reference manual, rev. 6, nov 2011 428 freescale semiconductor, inc. chapter 21 direct memory access controller (edma) 21.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the enhanced direct memory access (edma) controller is a second-generation module capable of performing complex data transfers with minimal intervention from a host processor. the hardware microarchitecture includes: ? a dma engine that performs: ? source- and destination-address calculations ? data-movement operations ? local memory containing transfer control descriptors for each of the 16 channels 21.1.1 block diagram this diagram illustrates the edma module. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 429 1 transfer control descriptor (tcd ) edma engine data path edma 0 program model/ 64 control n-1 to/from crossbar switch 2 channel arbitration address path read data write data address read data write data write address internal peripheral bus edma peripheral request edma done figure 21-1. edma block diagram 21.1.2 block parts the edma module is partitioned into two major modules: the edma engine and the transfer-control descriptor local memory. the edma engine is further partitioned into four submodules: introduction k60 sub-family reference manual, rev. 6, nov 2011 430 freescale semiconductor, inc. table 21-1. edma engine submodules submodule function address path this block implements registered versions of two channel transfer control descriptors, channel x and channel y, and manages all master bus-address calculations. all the channels provide the same functionality. this structure allows data transfers associated with one channel to be preempted after the completion of a read/write sequence if a higher priority channel activation is asserted while the first channel is active. after a channel is activated, it runs until the minor loop is completed, unless preempted by a higher priority channel. this provides a mechanism (enabled by dchpri n ecp where a large data move operation can be preempted to minimize the time another channel is bloced from execution. when any channel is selected to execute, the contents of its tcd are read from local memory and loaded into the address path channel x registers for a normal start and into channel y registers for a preemption start. after the minor loop completes execution, the address path hardware writes the new values for the tcd n _saddr, daddr, citer bac to local memory. if the maor iteration count is exhausted, additional processing is performed, including the final address pointer updates, reloading the tcd n _citer field, and a possible fetch of the next tcd n from memory as part of a scattergather operation. data path this bloc implements the bus master readwrite datapath. it includes 16 bytes of register storage and the necessary multiplex logic to support any reuired data alignment. the internal read data bus is the primary input, and the internal write data bus is the primary output. the address and data path modules directly support the 2- stage pipelined internal bus. the address path module represents the 1st stage of the bus pipeline address phase, while the data path module implements the 2nd stage of the pipeline data phase. program modelchannel arbitration this bloc implements the first section of the edma programming model as well as the channel arbitration logic. the programming model registers are connected to the internal peripheral bus. the edma peripheral reuest inputs and interrupt reuest outputs are also connected to this bloc via control logic. control this bloc provides all the control functions for the edma engine. for data transfers where the source and destination sizes are eual, the edma engine performs a series of source readdestination write operations until the number of bytes specified in the minor loop byte count has moved. for descriptors where the sizes are not eual, multiple accesses of the smaller size data are reuired for each reference of the larger size. as an example, if the source size references 16- bit data and the destination is 2-bit data, two reads are performed, then one 2-bit write. the transfer-control descriptor local memory is further partitioned into: chapter 21 direct memory access controller (edma) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 431 table 21-2. transfer control descriptor memory submodule description memory controller this logic implements the required dual-ported controller, managing accesses from the edma engine as well as references from the internal peripheral bus. as noted earlier, in the event of simultaneous accesses, the edma engine is given priority and the peripheral transaction is stalled. memory array tcd storage is implemented using a single-port, synchronous ram array. 21.1.3 features the edma is a highly-programmable data-transfer engine optimized to minimize the required intervention from the host processor. it is intended for use in applications where the data size to be transferred is statically known and not defined within the data packet itself. the edma module features: ? all data movement via dual-address transfers: read from source, write to destination ? programmable source and destination addresses and transfer size ? support for enhanced addressing modes ? 16-channel implementation that performs complex data transfers with minimal intervention from a host processor ? internal data buffer, used as temporary storage to support 16-byte burst transfers ? connections to the crossbar switch for bus mastering the data movement ? transfer control descriptor (tcd) organized to support two-deep, nested transfer operations ? 32-byte tcd stored in local memory for each channel ? an inner data transfer loop defined by a minor byte transfer count ? an outer data transfer loop defined by a major iteration count ? channel activation via one of three methods: ? explicit software initiation ? initiation via a channel-to-channel linking mechanism for continuous transfers ? peripheral-paced hardware requests, one per channel ? fixed-priority and round-robin channel arbitration introduction k60 sub-family reference manual, rev. 6, nov 2011 432 freescale semiconductor, inc. ? channel completion reported via optional interrupt requests ? one interrupt per channel, optionally asserted at completion of major iteration count ? optional error terminations per channel and logically summed together to form one error interrupt to the interrupt controller ? optional support for scatter/gather dma processing ? support for complex data structures ? support to cancel transfers via software in the discussion of this module, n is used to reference the channel number. 21.2 modes of operation the edma operates in the following modes: table 21-3. modes of operation mode description normal in normal mode, the edma transfers data between a source and a destination. the source and destination can be a memory block or an i/o block capable of operation with the edma. a service request initiates a transfer of a specific number of bytes (nbytes) as specified in the transfer control descriptor (tcd). the minor loop is the sequence of read-write operations that transfers these nbytes per service request. each service request executes one iteration of the major loop, which transfers nbytes of data. debug dma operation is configurable in debug mode via the control register: if cr[edbg] is cleared, the dma continues to operate. if cr[edbg] is set, the edma stops transferring data. if debug mode is entered while a channel is active, the edma continues operation until the channel retires. wait before entering wait mode, the dma attempts to complete its current transfer. after the transfer completes, the device enters wait mode. 21.3 memory map/register definition the edma's programming model is partitioned into two regions: chapter 21 direct memory access controller (edma) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 433 ? the first region defines a number of registers providing control functions ? the second region corresponds to the local transfer control descriptor memory each channel requires a 32-byte transfer control descriptor for defining the desired data movement operation. the channel descriptors are stored in the local memory in sequential order: channel 0, channel 1,... channel 15 . each tcd n definition is presented as 11 registers of 16 or 32 bits. reading reserved bits in a register returns the value of zero. writes to reserved bits in a register are ignored. reading or writing a reserved memory location generates a bus error. dma memory map absolute address (hex) register name width (in bits) access reset value section/ page 4000_8000 control register (dma_cr) 32 r/w 0000_0000h 21.3.1/448 4000_8004 error status register (dma_es) 32 r 0000_0000h 21.3.2/450 4000_800c enable request register (dma_erq) 32 r/w 0000_0000h 21.3.3/452 4000_8014 enable error interrupt register (dma_eei) 32 r/w 0000_0000h 21.3.4/454 4000_8018 clear enable error interrupt register (dma_ceei) 8 w (always reads zero) 00h 21.3.5/456 4000_8019 set enable error interrupt register (dma_seei) 8 w (always reads zero) 00h 21.3.6/457 4000_801a clear enable request register (dma_cerq) 8 w (always reads zero) 00h 21.3.7/458 4000_801b set enable request register (dma_serq) 8 w (always reads zero) 00h 21.3.8/459 4000_801c clear done status bit register (dma_cdne) 8 w (always reads zero) 00h 21.3.9/460 4000_801d set start bit register (dma_ssrt) 8 w (always reads zero) 00h 21.3.10/ 461 table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 44 freescale semiconductor, inc. dma memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4000_801e clear error register (dma_cerr) 8 w (always reads zero) 00h 21.3.11/ 462 4000_801f clear interrupt request register (dma_cint) 8 w (always reads zero) 00h 21.3.12/ 463 4000_8024 interrupt request register (dma_int) 32 r/w 0000_0000h 21.3.13/ 463 4000_802c error register (dma_err) 32 r/w 0000_0000h 21.3.14/ 466 4000_8034 hardware request status register (dma_hrs) 32 r/w 0000_0000h 21.3.15/ 468 4000_8100 channel n priority register (dma_dchpri3) 8 r/w undefined 21.3.16/ 470 4000_8101 channel n priority register (dma_dchpri2) 8 r/w undefined 21.3.16/ 470 4000_8102 channel n priority register (dma_dchpri1) 8 r/w undefined 21.3.16/ 470 4000_8103 channel n priority register (dma_dchpri0) 8 r/w undefined 21.3.16/ 470 4000_8104 channel n priority register (dma_dchpri7) 8 r/w undefined 21.3.16/ 470 4000_8105 channel n priority register (dma_dchpri6) 8 r/w undefined 21.3.16/ 470 4000_8106 channel n priority register (dma_dchpri5) 8 r/w undefined 21.3.16/ 470 4000_8107 channel n priority register (dma_dchpri4) 8 r/w undefined 21.3.16/ 470 4000_8108 channel n priority register (dma_dchpri11) 8 r/w undefined 21.3.16/ 470 4000_8109 channel n priority register (dma_dchpri10) 8 r/w undefined 21.3.16/ 470 4000_810a channel n priority register (dma_dchpri9) 8 r/w undefined 21.3.16/ 470 4000_810b channel n priority register (dma_dchpri8) 8 r/w undefined 21.3.16/ 470 4000_810c channel n priority register (dma_dchpri15) 8 r/w undefined 21.3.16/ 470 4000_810d channel n priority register (dma_dchpri14) 8 r/w undefined 21.3.16/ 470 table continues on the next page... chapter 21 direct memory access controller edma 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 4 dma memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4000_810e channel n priority register (dma_dchpri13) 8 r/w undefined 21.3.16/ 470 4000_810f channel n priority register (dma_dchpri12) 8 r/w undefined 21.3.16/ 470 4000_9000 tcd source address (dma_tcd0_saddr) 32 r/w undefined 21.3.17/ 471 4000_9004 tcd signed source address offset (dma_tcd0_soff) 16 r/w undefined 21.3.18/ 472 4000_9006 tcd transfer attributes (dma_tcd0_attr) 16 r/w undefined 21.3.19/ 472 4000_9008 tcd minor byte count (minor loop disabled) (dma_tcd0_nbytes_mlno) 32 r/w undefined 21.3.20/ 473 4000_9008 tcd signed minor loop offset (minor loop enabled and offset disabled) (dma_tcd0_nbytes_mloffno) 32 r/w undefined 21.3.21/ 474 4000_9008 tcd signed minor loop offset (minor loop and offset enabled) (dma_tcd0_nbytes_mloffyes) 32 r/w undefined 21.3.22/ 475 4000_900c tcd last source address adjustment (dma_tcd0_slast) 32 r/w undefined 21.3.23/ 476 4000_9010 tcd destination address (dma_tcd0_daddr) 32 r/w undefined 21.3.24/ 476 4000_9014 tcd signed destination address offset (dma_tcd0_doff) 16 r/w undefined 21.3.25/ 477 4000_9016 tcd current minor loop link, major loop count (channel linking enabled) (dma_tcd0_citer_elinkyes) 16 r/w undefined 21.3.26/ 477 4000_9016 dma_tcd0_citer_elinkno 16 r/w undefined 21.3.27/ 478 4000_9018 tcd last destination address adjustment/scatter gather address (dma_tcd0_dlastsga) 32 r/w undefined 21.3.28/ 479 4000_901c tcd control and status (dma_tcd0_csr) 16 r/w undefined 21.3.29/ 480 4000_901e tcd beginning minor loop link, major loop count (channel linking enabled) (dma_tcd0_biter_elinkyes) 16 r/w undefined 21.3.30/ 482 4000_901e tcd beginning minor loop link, major loop count (channel linking disabled) (dma_tcd0_biter_elinkno) 16 r/w undefined 21.3.31/ 483 4000_9020 tcd source address (dma_tcd1_saddr) 32 r/w undefined 21.3.17/ 471 4000_9024 tcd signed source address offset (dma_tcd1_soff) 16 r/w undefined 21.3.18/ 472 4000_9026 tcd transfer attributes (dma_tcd1_attr) 16 r/w undefined 21.3.19/ 472 table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 46 freescale semiconductor, inc. dma memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4000_9028 tcd minor byte count (minor loop disabled) (dma_tcd1_nbytes_mlno) 32 r/w undefined 21.3.20/ 473 4000_9028 tcd signed minor loop offset (minor loop enabled and offset disabled) (dma_tcd1_nbytes_mloffno) 32 r/w undefined 21.3.21/ 474 4000_9028 tcd signed minor loop offset (minor loop and offset enabled) (dma_tcd1_nbytes_mloffyes) 32 r/w undefined 21.3.22/ 475 4000_902c tcd last source address adjustment (dma_tcd1_slast) 32 r/w undefined 21.3.23/ 476 4000_9030 tcd destination address (dma_tcd1_daddr) 32 r/w undefined 21.3.24/ 476 4000_9034 tcd signed destination address offset (dma_tcd1_doff) 16 r/w undefined 21.3.25/ 477 4000_9036 tcd current minor loop link, major loop count (channel linking enabled) (dma_tcd1_citer_elinkyes) 16 r/w undefined 21.3.26/ 477 4000_9036 dma_tcd1_citer_elinkno 16 r/w undefined 21.3.27/ 478 4000_9038 tcd last destination address adjustment/scatter gather address (dma_tcd1_dlastsga) 32 r/w undefined 21.3.28/ 479 4000_903c tcd control and status (dma_tcd1_csr) 16 r/w undefined 21.3.29/ 480 4000_903e tcd beginning minor loop link, major loop count (channel linking enabled) (dma_tcd1_biter_elinkyes) 16 r/w undefined 21.3.30/ 482 4000_903e tcd beginning minor loop link, major loop count (channel linking disabled) (dma_tcd1_biter_elinkno) 16 r/w undefined 21.3.31/ 483 4000_9040 tcd source address (dma_tcd2_saddr) 32 r/w undefined 21.3.17/ 471 4000_9044 tcd signed source address offset (dma_tcd2_soff) 16 r/w undefined 21.3.18/ 472 4000_9046 tcd transfer attributes (dma_tcd2_attr) 16 r/w undefined 21.3.19/ 472 4000_9048 tcd minor byte count (minor loop disabled) (dma_tcd2_nbytes_mlno) 32 r/w undefined 21.3.20/ 473 4000_9048 tcd signed minor loop offset (minor loop enabled and offset disabled) (dma_tcd2_nbytes_mloffno) 32 r/w undefined 21.3.21/ 474 4000_9048 tcd signed minor loop offset (minor loop and offset enabled) (dma_tcd2_nbytes_mloffyes) 32 r/w undefined 21.3.22/ 475 4000_904c tcd last source address adjustment (dma_tcd2_slast) 32 r/w undefined 21.3.23/ 476 4000_9050 tcd destination address (dma_tcd2_daddr) 32 r/w undefined 21.3.24/ 476 table continues on the next page... chapter 21 direct memory access controller edma 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 47 dma memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4000_9054 tcd signed destination address offset (dma_tcd2_doff) 16 r/w undefined 21.3.25/ 477 4000_9056 tcd current minor loop link, major loop count (channel linking enabled) (dma_tcd2_citer_elinkyes) 16 r/w undefined 21.3.26/ 477 4000_9056 dma_tcd2_citer_elinkno 16 r/w undefined 21.3.27/ 478 4000_9058 tcd last destination address adjustment/scatter gather address (dma_tcd2_dlastsga) 32 r/w undefined 21.3.28/ 479 4000_905c tcd control and status (dma_tcd2_csr) 16 r/w undefined 21.3.29/ 480 4000_905e tcd beginning minor loop link, major loop count (channel linking enabled) (dma_tcd2_biter_elinkyes) 16 r/w undefined 21.3.30/ 482 4000_905e tcd beginning minor loop link, major loop count (channel linking disabled) (dma_tcd2_biter_elinkno) 16 r/w undefined 21.3.31/ 483 4000_9060 tcd source address (dma_tcd3_saddr) 32 r/w undefined 21.3.17/ 471 4000_9064 tcd signed source address offset (dma_tcd3_soff) 16 r/w undefined 21.3.18/ 472 4000_9066 tcd transfer attributes (dma_tcd3_attr) 16 r/w undefined 21.3.19/ 472 4000_9068 tcd minor byte count (minor loop disabled) (dma_tcd3_nbytes_mlno) 32 r/w undefined 21.3.20/ 473 4000_9068 tcd signed minor loop offset (minor loop enabled and offset disabled) (dma_tcd3_nbytes_mloffno) 32 r/w undefined 21.3.21/ 474 4000_9068 tcd signed minor loop offset (minor loop and offset enabled) (dma_tcd3_nbytes_mloffyes) 32 r/w undefined 21.3.22/ 475 4000_906c tcd last source address adjustment (dma_tcd3_slast) 32 r/w undefined 21.3.23/ 476 4000_9070 tcd destination address (dma_tcd3_daddr) 32 r/w undefined 21.3.24/ 476 4000_9074 tcd signed destination address offset (dma_tcd3_doff) 16 r/w undefined 21.3.25/ 477 4000_9076 tcd current minor loop link, major loop count (channel linking enabled) (dma_tcd3_citer_elinkyes) 16 r/w undefined 21.3.26/ 477 4000_9076 dma_tcd3_citer_elinkno 16 r/w undefined 21.3.27/ 478 4000_9078 tcd last destination address adjustment/scatter gather address (dma_tcd3_dlastsga) 32 r/w undefined 21.3.28/ 479 4000_907c tcd control and status (dma_tcd3_csr) 16 r/w undefined 21.3.29/ 480 table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 48 freescale semiconductor, inc. dma memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4000_907e tcd beginning minor loop link, major loop count (channel linking enabled) (dma_tcd3_biter_elinkyes) 16 r/w undefined 21.3.30/ 482 4000_907e tcd beginning minor loop link, major loop count (channel linking disabled) (dma_tcd3_biter_elinkno) 16 r/w undefined 21.3.31/ 483 4000_9080 tcd source address (dma_tcd4_saddr) 32 r/w undefined 21.3.17/ 471 4000_9084 tcd signed source address offset (dma_tcd4_soff) 16 r/w undefined 21.3.18/ 472 4000_9086 tcd transfer attributes (dma_tcd4_attr) 16 r/w undefined 21.3.19/ 472 4000_9088 tcd minor byte count (minor loop disabled) (dma_tcd4_nbytes_mlno) 32 r/w undefined 21.3.20/ 473 4000_9088 tcd signed minor loop offset (minor loop enabled and offset disabled) (dma_tcd4_nbytes_mloffno) 32 r/w undefined 21.3.21/ 474 4000_9088 tcd signed minor loop offset (minor loop and offset enabled) (dma_tcd4_nbytes_mloffyes) 32 r/w undefined 21.3.22/ 475 4000_908c tcd last source address adjustment (dma_tcd4_slast) 32 r/w undefined 21.3.23/ 476 4000_9090 tcd destination address (dma_tcd4_daddr) 32 r/w undefined 21.3.24/ 476 4000_9094 tcd signed destination address offset (dma_tcd4_doff) 16 r/w undefined 21.3.25/ 477 4000_9096 tcd current minor loop link, major loop count (channel linking enabled) (dma_tcd4_citer_elinkyes) 16 r/w undefined 21.3.26/ 477 4000_9096 dma_tcd4_citer_elinkno 16 r/w undefined 21.3.27/ 478 4000_9098 tcd last destination address adjustment/scatter gather address (dma_tcd4_dlastsga) 32 r/w undefined 21.3.28/ 479 4000_909c tcd control and status (dma_tcd4_csr) 16 r/w undefined 21.3.29/ 480 4000_909e tcd beginning minor loop link, major loop count (channel linking enabled) (dma_tcd4_biter_elinkyes) 16 r/w undefined 21.3.30/ 482 4000_909e tcd beginning minor loop link, major loop count (channel linking disabled) (dma_tcd4_biter_elinkno) 16 r/w undefined 21.3.31/ 483 4000_90a0 tcd source address (dma_tcd5_saddr) 32 r/w undefined 21.3.17/ 471 4000_90a4 tcd signed source address offset (dma_tcd5_soff) 16 r/w undefined 21.3.18/ 472 table continues on the next page... chapter 21 direct memory access controller edma 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 4 dma memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4000_90a6 tcd transfer attributes (dma_tcd5_attr) 16 r/w undefined 21.3.19/ 472 4000_90a8 tcd minor byte count (minor loop disabled) (dma_tcd5_nbytes_mlno) 32 r/w undefined 21.3.20/ 473 4000_90a8 tcd signed minor loop offset (minor loop enabled and offset disabled) (dma_tcd5_nbytes_mloffno) 32 r/w undefined 21.3.21/ 474 4000_90a8 tcd signed minor loop offset (minor loop and offset enabled) (dma_tcd5_nbytes_mloffyes) 32 r/w undefined 21.3.22/ 475 4000_90ac tcd last source address adjustment (dma_tcd5_slast) 32 r/w undefined 21.3.23/ 476 4000_90b0 tcd destination address (dma_tcd5_daddr) 32 r/w undefined 21.3.24/ 476 4000_90b4 tcd signed destination address offset (dma_tcd5_doff) 16 r/w undefined 21.3.25/ 477 4000_90b6 tcd current minor loop link, major loop count (channel linking enabled) (dma_tcd5_citer_elinkyes) 16 r/w undefined 21.3.26/ 477 4000_90b6 dma_tcd5_citer_elinkno 16 r/w undefined 21.3.27/ 478 4000_90b8 tcd last destination address adjustment/scatter gather address (dma_tcd5_dlastsga) 32 r/w undefined 21.3.28/ 479 4000_90bc tcd control and status (dma_tcd5_csr) 16 r/w undefined 21.3.29/ 480 4000_90be tcd beginning minor loop link, major loop count (channel linking enabled) (dma_tcd5_biter_elinkyes) 16 r/w undefined 21.3.30/ 482 4000_90be tcd beginning minor loop link, major loop count (channel linking disabled) (dma_tcd5_biter_elinkno) 16 r/w undefined 21.3.31/ 483 4000_90c0 tcd source address (dma_tcd6_saddr) 32 r/w undefined 21.3.17/ 471 4000_90c4 tcd signed source address offset (dma_tcd6_soff) 16 r/w undefined 21.3.18/ 472 4000_90c6 tcd transfer attributes (dma_tcd6_attr) 16 r/w undefined 21.3.19/ 472 4000_90c8 tcd minor byte count (minor loop disabled) (dma_tcd6_nbytes_mlno) 32 r/w undefined 21.3.20/ 473 4000_90c8 tcd signed minor loop offset (minor loop enabled and offset disabled) (dma_tcd6_nbytes_mloffno) 32 r/w undefined 21.3.21/ 474 4000_90c8 tcd signed minor loop offset (minor loop and offset enabled) (dma_tcd6_nbytes_mloffyes) 32 r/w undefined 21.3.22/ 475 4000_90cc tcd last source address adjustment (dma_tcd6_slast) 32 r/w undefined 21.3.23/ 476 table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 440 freescale semiconductor, inc. dma memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4000_90d0 tcd destination address (dma_tcd6_daddr) 32 r/w undefined 21.3.24/ 476 4000_90d4 tcd signed destination address offset (dma_tcd6_doff) 16 r/w undefined 21.3.25/ 477 4000_90d6 tcd current minor loop link, major loop count (channel linking enabled) (dma_tcd6_citer_elinkyes) 16 r/w undefined 21.3.26/ 477 4000_90d6 dma_tcd6_citer_elinkno 16 r/w undefined 21.3.27/ 478 4000_90d8 tcd last destination address adjustment/scatter gather address (dma_tcd6_dlastsga) 32 r/w undefined 21.3.28/ 479 4000_90dc tcd control and status (dma_tcd6_csr) 16 r/w undefined 21.3.29/ 480 4000_90de tcd beginning minor loop link, major loop count (channel linking enabled) (dma_tcd6_biter_elinkyes) 16 r/w undefined 21.3.30/ 482 4000_90de tcd beginning minor loop link, major loop count (channel linking disabled) (dma_tcd6_biter_elinkno) 16 r/w undefined 21.3.31/ 483 4000_90e0 tcd source address (dma_tcd7_saddr) 32 r/w undefined 21.3.17/ 471 4000_90e4 tcd signed source address offset (dma_tcd7_soff) 16 r/w undefined 21.3.18/ 472 4000_90e6 tcd transfer attributes (dma_tcd7_attr) 16 r/w undefined 21.3.19/ 472 4000_90e8 tcd minor byte count (minor loop disabled) (dma_tcd7_nbytes_mlno) 32 r/w undefined 21.3.20/ 473 4000_90e8 tcd signed minor loop offset (minor loop enabled and offset disabled) (dma_tcd7_nbytes_mloffno) 32 r/w undefined 21.3.21/ 474 4000_90e8 tcd signed minor loop offset (minor loop and offset enabled) (dma_tcd7_nbytes_mloffyes) 32 r/w undefined 21.3.22/ 475 4000_90ec tcd last source address adjustment (dma_tcd7_slast) 32 r/w undefined 21.3.23/ 476 4000_90f0 tcd destination address (dma_tcd7_daddr) 32 r/w undefined 21.3.24/ 476 4000_90f4 tcd signed destination address offset (dma_tcd7_doff) 16 r/w undefined 21.3.25/ 477 4000_90f6 tcd current minor loop link, major loop count (channel linking enabled) (dma_tcd7_citer_elinkyes) 16 r/w undefined 21.3.26/ 477 4000_90f6 dma_tcd7_citer_elinkno 16 r/w undefined 21.3.27/ 478 4000_90f8 tcd last destination address adjustment/scatter gather address (dma_tcd7_dlastsga) 32 r/w undefined 21.3.28/ 479 table continues on the next page... chapter 21 direct memory access controller edma 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 441 dma memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4000_90fc tcd control and status (dma_tcd7_csr) 16 r/w undefined 21.3.29/ 480 4000_90fe tcd beginning minor loop link, major loop count (channel linking enabled) (dma_tcd7_biter_elinkyes) 16 r/w undefined 21.3.30/ 482 4000_90fe tcd beginning minor loop link, major loop count (channel linking disabled) (dma_tcd7_biter_elinkno) 16 r/w undefined 21.3.31/ 483 4000_9100 tcd source address (dma_tcd8_saddr) 32 r/w undefined 21.3.17/ 471 4000_9104 tcd signed source address offset (dma_tcd8_soff) 16 r/w undefined 21.3.18/ 472 4000_9106 tcd transfer attributes (dma_tcd8_attr) 16 r/w undefined 21.3.19/ 472 4000_9108 tcd minor byte count (minor loop disabled) (dma_tcd8_nbytes_mlno) 32 r/w undefined 21.3.20/ 473 4000_9108 tcd signed minor loop offset (minor loop enabled and offset disabled) (dma_tcd8_nbytes_mloffno) 32 r/w undefined 21.3.21/ 474 4000_9108 tcd signed minor loop offset (minor loop and offset enabled) (dma_tcd8_nbytes_mloffyes) 32 r/w undefined 21.3.22/ 475 4000_910c tcd last source address adjustment (dma_tcd8_slast) 32 r/w undefined 21.3.23/ 476 4000_9110 tcd destination address (dma_tcd8_daddr) 32 r/w undefined 21.3.24/ 476 4000_9114 tcd signed destination address offset (dma_tcd8_doff) 16 r/w undefined 21.3.25/ 477 4000_9116 tcd current minor loop link, major loop count (channel linking enabled) (dma_tcd8_citer_elinkyes) 16 r/w undefined 21.3.26/ 477 4000_9116 dma_tcd8_citer_elinkno 16 r/w undefined 21.3.27/ 478 4000_9118 tcd last destination address adjustment/scatter gather address (dma_tcd8_dlastsga) 32 r/w undefined 21.3.28/ 479 4000_911c tcd control and status (dma_tcd8_csr) 16 r/w undefined 21.3.29/ 480 4000_911e tcd beginning minor loop link, major loop count (channel linking enabled) (dma_tcd8_biter_elinkyes) 16 r/w undefined 21.3.30/ 482 4000_911e tcd beginning minor loop link, major loop count (channel linking disabled) (dma_tcd8_biter_elinkno) 16 r/w undefined 21.3.31/ 483 4000_9120 tcd source address (dma_tcd9_saddr) 32 r/w undefined 21.3.17/ 471 table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 442 freescale semiconductor, inc. dma memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4000_9124 tcd signed source address offset (dma_tcd9_soff) 16 r/w undefined 21.3.18/ 472 4000_9126 tcd transfer attributes (dma_tcd9_attr) 16 r/w undefined 21.3.19/ 472 4000_9128 tcd minor byte count (minor loop disabled) (dma_tcd9_nbytes_mlno) 32 r/w undefined 21.3.20/ 473 4000_9128 tcd signed minor loop offset (minor loop enabled and offset disabled) (dma_tcd9_nbytes_mloffno) 32 r/w undefined 21.3.21/ 474 4000_9128 tcd signed minor loop offset (minor loop and offset enabled) (dma_tcd9_nbytes_mloffyes) 32 r/w undefined 21.3.22/ 475 4000_912c tcd last source address adjustment (dma_tcd9_slast) 32 r/w undefined 21.3.23/ 476 4000_9130 tcd destination address (dma_tcd9_daddr) 32 r/w undefined 21.3.24/ 476 4000_9134 tcd signed destination address offset (dma_tcd9_doff) 16 r/w undefined 21.3.25/ 477 4000_9136 tcd current minor loop link, major loop count (channel linking enabled) (dma_tcd9_citer_elinkyes) 16 r/w undefined 21.3.26/ 477 4000_9136 dma_tcd9_citer_elinkno 16 r/w undefined 21.3.27/ 478 4000_9138 tcd last destination address adjustment/scatter gather address (dma_tcd9_dlastsga) 32 r/w undefined 21.3.28/ 479 4000_913c tcd control and status (dma_tcd9_csr) 16 r/w undefined 21.3.29/ 480 4000_913e tcd beginning minor loop link, major loop count (channel linking enabled) (dma_tcd9_biter_elinkyes) 16 r/w undefined 21.3.30/ 482 4000_913e tcd beginning minor loop link, major loop count (channel linking disabled) (dma_tcd9_biter_elinkno) 16 r/w undefined 21.3.31/ 483 4000_9140 tcd source address (dma_tcd10_saddr) 32 r/w undefined 21.3.17/ 471 4000_9144 tcd signed source address offset (dma_tcd10_soff) 16 r/w undefined 21.3.18/ 472 4000_9146 tcd transfer attributes (dma_tcd10_attr) 16 r/w undefined 21.3.19/ 472 4000_9148 tcd minor byte count (minor loop disabled) (dma_tcd10_nbytes_mlno) 32 r/w undefined 21.3.20/ 473 4000_9148 tcd signed minor loop offset (minor loop enabled and offset disabled) (dma_tcd10_nbytes_mloffno) 32 r/w undefined 21.3.21/ 474 4000_9148 tcd signed minor loop offset (minor loop and offset enabled) (dma_tcd10_nbytes_mloffyes) 32 r/w undefined 21.3.22/ 475 table continues on the next page... chapter 21 direct memory access controller edma 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 44 dma memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4000_914c tcd last source address adjustment (dma_tcd10_slast) 32 r/w undefined 21.3.23/ 476 4000_9150 tcd destination address (dma_tcd10_daddr) 32 r/w undefined 21.3.24/ 476 4000_9154 tcd signed destination address offset (dma_tcd10_doff) 16 r/w undefined 21.3.25/ 477 4000_9156 tcd current minor loop link, major loop count (channel linking enabled) (dma_tcd10_citer_elinkyes) 16 r/w undefined 21.3.26/ 477 4000_9156 dma_tcd10_citer_elinkno 16 r/w undefined 21.3.27/ 478 4000_9158 tcd last destination address adjustment/scatter gather address (dma_tcd10_dlastsga) 32 r/w undefined 21.3.28/ 479 4000_915c tcd control and status (dma_tcd10_csr) 16 r/w undefined 21.3.29/ 480 4000_915e tcd beginning minor loop link, major loop count (channel linking enabled) (dma_tcd10_biter_elinkyes) 16 r/w undefined 21.3.30/ 482 4000_915e tcd beginning minor loop link, major loop count (channel linking disabled) (dma_tcd10_biter_elinkno) 16 r/w undefined 21.3.31/ 483 4000_9160 tcd source address (dma_tcd11_saddr) 32 r/w undefined 21.3.17/ 471 4000_9164 tcd signed source address offset (dma_tcd11_soff) 16 r/w undefined 21.3.18/ 472 4000_9166 tcd transfer attributes (dma_tcd11_attr) 16 r/w undefined 21.3.19/ 472 4000_9168 tcd minor byte count (minor loop disabled) (dma_tcd11_nbytes_mlno) 32 r/w undefined 21.3.20/ 473 4000_9168 tcd signed minor loop offset (minor loop enabled and offset disabled) (dma_tcd11_nbytes_mloffno) 32 r/w undefined 21.3.21/ 474 4000_9168 tcd signed minor loop offset (minor loop and offset enabled) (dma_tcd11_nbytes_mloffyes) 32 r/w undefined 21.3.22/ 475 4000_916c tcd last source address adjustment (dma_tcd11_slast) 32 r/w undefined 21.3.23/ 476 4000_9170 tcd destination address (dma_tcd11_daddr) 32 r/w undefined 21.3.24/ 476 4000_9174 tcd signed destination address offset (dma_tcd11_doff) 16 r/w undefined 21.3.25/ 477 4000_9176 tcd current minor loop link, major loop count (channel linking enabled) (dma_tcd11_citer_elinkyes) 16 r/w undefined 21.3.26/ 477 4000_9176 dma_tcd11_citer_elinkno 16 r/w undefined 21.3.27/ 478 table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 444 freescale semiconductor, inc. dma memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4000_9178 tcd last destination address adjustment/scatter gather address (dma_tcd11_dlastsga) 32 r/w undefined 21.3.28/ 479 4000_917c tcd control and status (dma_tcd11_csr) 16 r/w undefined 21.3.29/ 480 4000_917e tcd beginning minor loop link, major loop count (channel linking enabled) (dma_tcd11_biter_elinkyes) 16 r/w undefined 21.3.30/ 482 4000_917e tcd beginning minor loop link, major loop count (channel linking disabled) (dma_tcd11_biter_elinkno) 16 r/w undefined 21.3.31/ 483 4000_9180 tcd source address (dma_tcd12_saddr) 32 r/w undefined 21.3.17/ 471 4000_9184 tcd signed source address offset (dma_tcd12_soff) 16 r/w undefined 21.3.18/ 472 4000_9186 tcd transfer attributes (dma_tcd12_attr) 16 r/w undefined 21.3.19/ 472 4000_9188 tcd minor byte count (minor loop disabled) (dma_tcd12_nbytes_mlno) 32 r/w undefined 21.3.20/ 473 4000_9188 tcd signed minor loop offset (minor loop enabled and offset disabled) (dma_tcd12_nbytes_mloffno) 32 r/w undefined 21.3.21/ 474 4000_9188 tcd signed minor loop offset (minor loop and offset enabled) (dma_tcd12_nbytes_mloffyes) 32 r/w undefined 21.3.22/ 475 4000_918c tcd last source address adjustment (dma_tcd12_slast) 32 r/w undefined 21.3.23/ 476 4000_9190 tcd destination address (dma_tcd12_daddr) 32 r/w undefined 21.3.24/ 476 4000_9194 tcd signed destination address offset (dma_tcd12_doff) 16 r/w undefined 21.3.25/ 477 4000_9196 tcd current minor loop link, major loop count (channel linking enabled) (dma_tcd12_citer_elinkyes) 16 r/w undefined 21.3.26/ 477 4000_9196 dma_tcd12_citer_elinkno 16 r/w undefined 21.3.27/ 478 4000_9198 tcd last destination address adjustment/scatter gather address (dma_tcd12_dlastsga) 32 r/w undefined 21.3.28/ 479 4000_919c tcd control and status (dma_tcd12_csr) 16 r/w undefined 21.3.29/ 480 4000_919e tcd beginning minor loop link, major loop count (channel linking enabled) (dma_tcd12_biter_elinkyes) 16 r/w undefined 21.3.30/ 482 4000_919e tcd beginning minor loop link, major loop count (channel linking disabled) (dma_tcd12_biter_elinkno) 16 r/w undefined 21.3.31/ 483 table continues on the next page... chapter 21 direct memory access controller edma 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 44 dma memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4000_91a0 tcd source address (dma_tcd13_saddr) 32 r/w undefined 21.3.17/ 471 4000_91a4 tcd signed source address offset (dma_tcd13_soff) 16 r/w undefined 21.3.18/ 472 4000_91a6 tcd transfer attributes (dma_tcd13_attr) 16 r/w undefined 21.3.19/ 472 4000_91a8 tcd minor byte count (minor loop disabled) (dma_tcd13_nbytes_mlno) 32 r/w undefined 21.3.20/ 473 4000_91a8 tcd signed minor loop offset (minor loop enabled and offset disabled) (dma_tcd13_nbytes_mloffno) 32 r/w undefined 21.3.21/ 474 4000_91a8 tcd signed minor loop offset (minor loop and offset enabled) (dma_tcd13_nbytes_mloffyes) 32 r/w undefined 21.3.22/ 475 4000_91ac tcd last source address adjustment (dma_tcd13_slast) 32 r/w undefined 21.3.23/ 476 4000_91b0 tcd destination address (dma_tcd13_daddr) 32 r/w undefined 21.3.24/ 476 4000_91b4 tcd signed destination address offset (dma_tcd13_doff) 16 r/w undefined 21.3.25/ 477 4000_91b6 tcd current minor loop link, major loop count (channel linking enabled) (dma_tcd13_citer_elinkyes) 16 r/w undefined 21.3.26/ 477 4000_91b6 dma_tcd13_citer_elinkno 16 r/w undefined 21.3.27/ 478 4000_91b8 tcd last destination address adjustment/scatter gather address (dma_tcd13_dlastsga) 32 r/w undefined 21.3.28/ 479 4000_91bc tcd control and status (dma_tcd13_csr) 16 r/w undefined 21.3.29/ 480 4000_91be tcd beginning minor loop link, major loop count (channel linking enabled) (dma_tcd13_biter_elinkyes) 16 r/w undefined 21.3.30/ 482 4000_91be tcd beginning minor loop link, major loop count (channel linking disabled) (dma_tcd13_biter_elinkno) 16 r/w undefined 21.3.31/ 483 4000_91c0 tcd source address (dma_tcd14_saddr) 32 r/w undefined 21.3.17/ 471 4000_91c4 tcd signed source address offset (dma_tcd14_soff) 16 r/w undefined 21.3.18/ 472 4000_91c6 tcd transfer attributes (dma_tcd14_attr) 16 r/w undefined 21.3.19/ 472 4000_91c8 tcd minor byte count (minor loop disabled) (dma_tcd14_nbytes_mlno) 32 r/w undefined 21.3.20/ 473 4000_91c8 tcd signed minor loop offset (minor loop enabled and offset disabled) (dma_tcd14_nbytes_mloffno) 32 r/w undefined 21.3.21/ 474 table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 446 freescale semiconductor, inc. dma memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4000_91c8 tcd signed minor loop offset (minor loop and offset enabled) (dma_tcd14_nbytes_mloffyes) 32 r/w undefined 21.3.22/ 475 4000_91cc tcd last source address adjustment (dma_tcd14_slast) 32 r/w undefined 21.3.23/ 476 4000_91d0 tcd destination address (dma_tcd14_daddr) 32 r/w undefined 21.3.24/ 476 4000_91d4 tcd signed destination address offset (dma_tcd14_doff) 16 r/w undefined 21.3.25/ 477 4000_91d6 tcd current minor loop link, major loop count (channel linking enabled) (dma_tcd14_citer_elinkyes) 16 r/w undefined 21.3.26/ 477 4000_91d6 dma_tcd14_citer_elinkno 16 r/w undefined 21.3.27/ 478 4000_91d8 tcd last destination address adjustment/scatter gather address (dma_tcd14_dlastsga) 32 r/w undefined 21.3.28/ 479 4000_91dc tcd control and status (dma_tcd14_csr) 16 r/w undefined 21.3.29/ 480 4000_91de tcd beginning minor loop link, major loop count (channel linking enabled) (dma_tcd14_biter_elinkyes) 16 r/w undefined 21.3.30/ 482 4000_91de tcd beginning minor loop link, major loop count (channel linking disabled) (dma_tcd14_biter_elinkno) 16 r/w undefined 21.3.31/ 483 4000_91e0 tcd source address (dma_tcd15_saddr) 32 r/w undefined 21.3.17/ 471 4000_91e4 tcd signed source address offset (dma_tcd15_soff) 16 r/w undefined 21.3.18/ 472 4000_91e6 tcd transfer attributes (dma_tcd15_attr) 16 r/w undefined 21.3.19/ 472 4000_91e8 tcd minor byte count (minor loop disabled) (dma_tcd15_nbytes_mlno) 32 r/w undefined 21.3.20/ 473 4000_91e8 tcd signed minor loop offset (minor loop enabled and offset disabled) (dma_tcd15_nbytes_mloffno) 32 r/w undefined 21.3.21/ 474 4000_91e8 tcd signed minor loop offset (minor loop and offset enabled) (dma_tcd15_nbytes_mloffyes) 32 r/w undefined 21.3.22/ 475 4000_91ec tcd last source address adjustment (dma_tcd15_slast) 32 r/w undefined 21.3.23/ 476 4000_91f0 tcd destination address (dma_tcd15_daddr) 32 r/w undefined 21.3.24/ 476 4000_91f4 tcd signed destination address offset (dma_tcd15_doff) 16 r/w undefined 21.3.25/ 477 4000_91f6 tcd current minor loop link, major loop count (channel linking enabled) (dma_tcd15_citer_elinkyes) 16 r/w undefined 21.3.26/ 477 table continues on the next page... chapter 21 direct memory access controller edma 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 447 dma memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4000_91f6 dma_tcd15_citer_elinkno 16 r/w undefined 21.3.27/ 478 4000_91f8 tcd last destination address adjustment/scatter gather address (dma_tcd15_dlastsga) 32 r/w undefined 21.3.28/ 479 4000_91fc tcd control and status (dma_tcd15_csr) 16 r/w undefined 21.3.29/ 480 4000_91fe tcd beginning minor loop link, major loop count (channel linking enabled) (dma_tcd15_biter_elinkyes) 16 r/w undefined 21.3.30/ 482 4000_91fe tcd beginning minor loop link, major loop count (channel linking disabled) (dma_tcd15_biter_elinkno) 16 r/w undefined 21.3.31/ 483 21.3.1 control register (dma_cr) the cr defines the basic operating configuration of the dma. arbitration can be configured to use either a fixed-priority or a round-robin scheme. for fixed-priority arbitration, the highest priority channel requesting service is selected to execute. the channel priority registers assign the priorities; see the dchprin registers. for round-robin arbitration, the channel priorities are ignored and channels are cycled through without regard to priority. note for proper operation, writes to the cr register must be performed only when the dma channels are inactive; that is, when tcdn_csr[active] bits are cleared. address: dma_cr is 4000_8000h base + 0h offset = 4000_8000h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 cx ecx 0 emlm clm halt hoe 0 erca edbg 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dma_cr field descriptions field description 31?18 reserved this read-only field is reserved and always has the value zero. 17 cx cancel transfer table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 448 freescale semiconductor, inc. dma_cr field descriptions (continued) field description 0 normal operation 1 cancel the remaining data transfer. stop the executing channel and force the minor loop to finish. the cancel takes effect after the last write of the current read/write sequence. the cx bit clears itself after the cancel has been honored. this cancel retires the channel normally as if the minor loop was completed. 16 ecx error cancel transfer 0 normal operation 1 cancel the remaining data transfer in the same fashion as the cx bit. stop the executing channel and force the minor loop to finish. the cancel takes effect after the last write of the current read/write sequence. the ecx bit clears itself after the cancel is honored. in addition to cancelling the transfer, ecx treats the cancel as an error condition, thus updating the es register and generating an optional error interrupt. 158 reserved this read-only field is reserved and always has the value zero. 7 emlm enable minor loop mapping 0 disabled. tcdn.word2 is defined as a 32-bit nbytes field. 1 enabled. tcdn.word2 is redefined to include individual enable fields, an offset field, and the nbytes field. the individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. the nbytes field is reduced when either offset is enabled. 6 clm continuous link mode 0 a minor loop channel link made to itself goes through channel arbitration before being activated again. 1 a minor loop channel link made to itself does not go through channel arbitration before being activated again. upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. this effectively applies the minor loop offsets and restarts the next minor loop. 5 halt halt dma operations 0 normal operation 1 stall the start of any new channels. executing channels are allowed to complete. channel execution resumes when this bit is cleared. 4 hoe halt on error 0 normal operation 1 any error causes the halt bit to set. subsequently, all service requests are ignored until the halt bit is cleared. 3 reserved this read-only field is reserved and always has the value zero. 2 erca enable round robin channel arbitration 0 fixed priority arbitration is used for channel selection. 1 round robin arbitration is used for channel selection. 1 edbg enable debug table continues on the next page... chapter 21 direct memory access controller edma 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 44 dma_cr field descriptions (continued) field description 0 when in debug mode, the dma continues to operate. 1 when in debug mode, the dma stalls the start of a new channel. executing channels are allowed to complete. channel execution resumes when the system exits debug mode or the edbg bit is cleared. 0 reserved this read-only field is reserved and always has the value zero. 21.3.2 error status register (dma_es) the es provides information concerning the last recorded channel error. channel errors can be caused by: ? a configuration error, that is: ? an illegal setting in the transfer-control descriptor, or ? an illegal priority register setting in fixed-arbitration ? an error termination to a bus master read or write cycle see the error reporting and handling section for more details. address: dma_es is 4000_8000h base + 4h offset = 4000_8004h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r vld 0 ecx w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 cpe 0 errchn sae soe dae doe nce sge sbe dbe w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dma_es field descriptions field description 31 vld logical or of all err status bits 0 no err bits are set 1 at least one err bit is set indicating a valid error exists that has not been cleared 30?17 reserved this read-only field is reserved and always has the value zero. 16 ecx transfer cancelled 0 no cancelled transfers 1 the last recorded entry was a cancelled transfer by the error cancel transfer input table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 40 freescale semiconductor, inc. dma_es field descriptions (continued) field description 15 reserved this read-only field is reserved and always has the value zero. 14 cpe channel priority error 0 no channel priority error 1 the last recorded error was a configuration error in the channel priorities. channel priorities are not unique. 1312 reserved this read-only field is reserved and always has the value zero. 118 errchn error channel number or cancelled channel number the channel number of the last recorded error (excluding cpe errors) or last recorded error cancelled transfer. 7 sae source address error 0 no source address configuration error. 1 the last recorded error was a configuration error detected in the tcdn_saddr field. tcdn_saddr is inconsistent with tcdn_attr[ssize]. 6 soe source offset error 0 no source offset configuration error 1 the last recorded error was a configuration error detected in the tcdn_soff field. tcdn_soff is inconsistent with tcdn_attr[ssize]. 5 dae destination address error 0 no destination address configuration error 1 the last recorded error was a configuration error detected in the tcdn_daddr field. tcdn_daddr is inconsistent with tcdn_attr[dsize]. 4 doe destination offset error 0 no destination offset configuration error 1 the last recorded error was a configuration error detected in the tcdn_doff field. tcdn_doff is inconsistent with tcdn_attr[dsize]. 3 nce nbytes/citer configuration error 0 no nbytes/citer configuration error 1 the last recorded error was a configuration error detected in the tcdn_nbytes or tcdn_citer fields. ? tcdn_nbytes is not a multiple of tcdn_attr[ssize] and tcdn_attr[dsize], or ? tcdn_citer[citer] is equal to zero, or ? tcdn_citer[elink] is not equal to tcdn_biter[elink] 2 sge scatter/gather configuration error 0 no scatter/gather configuration error 1 the last recorded error was a configuration error detected in the tcdn_dlastsga field. this field is checked at the beginning of a scatter/gather operation after major loop completion if tcdn_csr[esg] is enabled. tcdn_dlastsga is not on a 32 byte boundary. table continues on the next page... chapter 21 direct memory access controller edma 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 41 dma_es field descriptions (continued) field description 1 sbe source bus error 0 no source bus error 1 the last recorded error was a bus error on a source read 0 dbe destination bus error 0 no destination bus error 1 the last recorded error was a bus error on a destination write 21.3.3 enable request register (dma_erq) the erq register provides a bit map for the 16 implemented channels to enable the request signal for each channel. the state of any given channel enable is directly affected by writes to this register; it is also affected by writes to the serq and cerq. the {s,c}erq registers are provided so the request enable for a single channel can easily be modified without needing to perform a read-modify-write sequence to the erq. dma request input signals and this enable request flag must be asserted before a channels hardware service request is accepted. the state of the dma enable request flag does not affect a channel service request made explicitly through software or a linked channel request. address: dma_erq is 4000_8000h base + ch offset = 4000_800ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 erq15 erq14 erq13 erq12 erq11 erq10 erq9 erq8 erq7 erq6 erq5 erq4 erq3 erq2 erq1 erq0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dma_erq field descriptions field description 31?16 reserved this read-only field is reserved and always has the value zero. 15 erq15 enable dma request 15 0 the dma request signal for the corresponding channel is disabled 1 the dma request signal for the corresponding channel is enabled 14 erq14 enable dma request 14 0 the dma request signal for the corresponding channel is disabled 1 the dma request signal for the corresponding channel is enabled table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 42 freescale semiconductor, inc. dma_erq field descriptions (continued) field description 13 erq13 enable dma request 13 0 the dma request signal for the corresponding channel is disabled 1 the dma request signal for the corresponding channel is enabled 12 erq12 enable dma request 12 0 the dma request signal for the corresponding channel is disabled 1 the dma request signal for the corresponding channel is enabled 11 erq11 enable dma request 11 0 the dma request signal for the corresponding channel is disabled 1 the dma request signal for the corresponding channel is enabled 10 erq10 enable dma request 10 0 the dma request signal for the corresponding channel is disabled 1 the dma request signal for the corresponding channel is enabled 9 erq9 enable dma request 9 0 the dma request signal for the corresponding channel is disabled 1 the dma request signal for the corresponding channel is enabled 8 erq8 enable dma request 8 0 the dma request signal for the corresponding channel is disabled 1 the dma request signal for the corresponding channel is enabled 7 erq7 enable dma request 7 0 the dma request signal for the corresponding channel is disabled 1 the dma request signal for the corresponding channel is enabled 6 erq6 enable dma request 6 0 the dma request signal for the corresponding channel is disabled 1 the dma request signal for the corresponding channel is enabled 5 erq5 enable dma request 5 0 the dma request signal for the corresponding channel is disabled 1 the dma request signal for the corresponding channel is enabled 4 erq4 enable dma request 4 0 the dma request signal for the corresponding channel is disabled 1 the dma request signal for the corresponding channel is enabled 3 erq3 enable dma request 3 0 the dma request signal for the corresponding channel is disabled 1 the dma request signal for the corresponding channel is enabled 2 erq2 enable dma request 2 table continues on the next page... chapter 21 direct memory access controller edma 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 4 dma_erq field descriptions (continued) field description 0 the dma request signal for the corresponding channel is disabled 1 the dma request signal for the corresponding channel is enabled 1 erq1 enable dma request 1 0 the dma request signal for the corresponding channel is disabled 1 the dma request signal for the corresponding channel is enabled 0 erq0 enable dma request 0 0 the dma request signal for the corresponding channel is disabled 1 the dma request signal for the corresponding channel is enabled 21.3.4 enable error interrupt register (dma_eei) the eei register provides a bit map for the 16 channels to enable the error interrupt signal for each channel. the state of any given channels error interrupt enable is directly affected by writes to this register; it is also affected by writes to the seei and ceei. the {s,c}eei are provided so the error interrupt enable for a single channel can easily be modified without the need to perform a read-modify-write sequence to the eei register. the dma error indicator and the error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted to the interrupt controller. address: dma_eei is 4000_8000h base + 14h offset = 4000_8014h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 eei15 eei14 eei13 eei12 eei11 eei10 eei9 eei8 eei7 eei6 eei5 eei4 eei3 eei2 eei1 eei0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dma_eei field descriptions field description 31?16 reserved this read-only field is reserved and always has the value zero. 15 eei15 enable error interrupt 15 0 the error signal for corresponding channel does not generate an error interrupt 1 the assertion of the error signal for corresponding channel generates an error interrupt request 14 eei14 enable error interrupt 14 0 the error signal for corresponding channel does not generate an error interrupt 1 the assertion of the error signal for corresponding channel generates an error interrupt request table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 44 freescale semiconductor, inc. dma_eei field descriptions (continued) field description 13 eei13 enable error interrupt 13 0 the error signal for corresponding channel does not generate an error interrupt 1 the assertion of the error signal for corresponding channel generates an error interrupt request 12 eei12 enable error interrupt 12 0 the error signal for corresponding channel does not generate an error interrupt 1 the assertion of the error signal for corresponding channel generates an error interrupt request 11 eei11 enable error interrupt 11 0 the error signal for corresponding channel does not generate an error interrupt 1 the assertion of the error signal for corresponding channel generates an error interrupt request 10 eei10 enable error interrupt 10 0 the error signal for corresponding channel does not generate an error interrupt 1 the assertion of the error signal for corresponding channel generates an error interrupt request 9 eei9 enable error interrupt 9 0 the error signal for corresponding channel does not generate an error interrupt 1 the assertion of the error signal for corresponding channel generates an error interrupt request 8 eei8 enable error interrupt 8 0 the error signal for corresponding channel does not generate an error interrupt 1 the assertion of the error signal for corresponding channel generates an error interrupt request 7 eei7 enable error interrupt 7 0 the error signal for corresponding channel does not generate an error interrupt 1 the assertion of the error signal for corresponding channel generates an error interrupt request 6 eei6 enable error interrupt 6 0 the error signal for corresponding channel does not generate an error interrupt 1 the assertion of the error signal for corresponding channel generates an error interrupt request 5 eei5 enable error interrupt 5 0 the error signal for corresponding channel does not generate an error interrupt 1 the assertion of the error signal for corresponding channel generates an error interrupt request 4 eei4 enable error interrupt 4 0 the error signal for corresponding channel does not generate an error interrupt 1 the assertion of the error signal for corresponding channel generates an error interrupt request 3 eei3 enable error interrupt 3 0 the error signal for corresponding channel does not generate an error interrupt 1 the assertion of the error signal for corresponding channel generates an error interrupt request 2 eei2 enable error interrupt 2 table continues on the next page... chapter 21 direct memory access controller edma 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 4 dma_eei field descriptions (continued) field description 0 the error signal for corresponding channel does not generate an error interrupt 1 the assertion of the error signal for corresponding channel generates an error interrupt request 1 eei1 enable error interrupt 1 0 the error signal for corresponding channel does not generate an error interrupt 1 the assertion of the error signal for corresponding channel generates an error interrupt request 0 eei0 enable error interrupt 0 0 the error signal for corresponding channel does not generate an error interrupt 1 the assertion of the error signal for corresponding channel generates an error interrupt request 21.3.5 clear enable error interrupt register (dma_ceei) the ceei provides a simple memory-mapped mechanism to clear a given bit in the eei to disable the error interrupt for a given channel. the data value on a register write causes the corresponding bit in the eei to be cleared. setting the caee bit provides a global clear function, forcing the eei contents to be cleared, disabling all dma request inputs. if the nop bit is set, the command is ignored. this allows you to write multiple-byte registers as a 32-bit word. reads of this register return all zeroes. address: dma_ceei is 4000_8000h base + 18h offset = 4000_8018h bit 7 6 5 4 3 2 1 0 read 0 0 0 write nop caee 0 ceei reset 0 0 0 0 0 0 0 0 dma_ceei field descriptions field description 7 nop 0 normal operation 1 no operation, ignore the other bits in this register 6 caee clear all enable error interrupts 0 clear only the eei bit specified in the ceei field 1 clear all bits in eei 5?4 reserved this field is reserved. 3?0 ceei clear enable error interrupt clears the corresponding bit in eei memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 456 freescale semiconductor, inc. 21.3.6 set enable error interrupt register (dma_seei) the seei provides a simple memory-mapped mechanism to set a given bit in the eei to enable the error interrupt for a given channel. the data value on a register write causes the corresponding bit in the eei to be set. setting the saee bit provides a global set function, forcing the entire eei contents to be set. if the nop bit is set, the command is ignored. this allows you to write multiple-byte registers as a 32-bit word. reads of this register return all zeroes. address: dma_seei is 4000_8000h base + 19h offset = 4000_8019h bit 7 6 5 4 3 2 1 0 read 0 0 0 write nop saee 0 seei reset 0 0 0 0 0 0 0 0 dma_seei field descriptions field description 7 nop 0 normal operation 1 no operation, ignore the other bits in this register 6 saee sets all enable error interrupts 0 set only the eei bit specified in the seei field. 1 sets all bits in eei 5?4 reserved this field is reserved. 3?0 seei set enable error interrupt sets the corresponding bit in eei chapter 21 direct memory access controller (edma) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 457 21.3.7 clear enable request register (dma_cerq) the cerq provides a simple memory-mapped mechanism to clear a given bit in the erq to disable the dma request for a given channel. the data value on a register write causes the corresponding bit in the erq to be cleared. setting the caer bit provides a global clear function, forcing the entire contents of the erq to be cleared, disabling all dma request inputs. if nop is set, the command is ignored. this allows you to write multiple-byte registers as a 32-bit word. reads of this register return all zeroes. address: dma_cerq is 4000_8000h base + 1ah offset = 4000_801ah bit 7 6 5 4 3 2 1 0 read 0 0 0 write nop caer 0 cerq reset 0 0 0 0 0 0 0 0 dma_cerq field descriptions field description 7 nop 0 normal operation 1 no operation, ignore the other bits in this register 6 caer clear all enable requests 0 clear only the erq bit specified in the cerq field 1 clear all bits in erq 5?4 reserved this field is reserved. 3?0 cerq clear enable request clears the corresponding bit in erq memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 458 freescale semiconductor, inc. 21.3.8 set enable request register (dma_serq) the serq provides a simple memory-mapped mechanism to set a given bit in the erq to enable the dma request for a given channel. the data value on a register write causes the corresponding bit in the erq to be set. setting the saer bit provides a global set function, forcing the entire contents of erq to be set. if the nop bit is set, the command is ignored. this allows you to write multiple-byte registers as a 32-bit word. reads of this register return all zeroes. address: dma_serq is 4000_8000h base + 1bh offset = 4000_801bh bit 7 6 5 4 3 2 1 0 read 0 0 0 write nop saer 0 serq reset 0 0 0 0 0 0 0 0 dma_serq field descriptions field description 7 nop 0 normal operation 1 no operation, ignore the other bits in this register 6 saer set all enable requests 0 set only the erq bit specified in the serq field 1 set all bits in erq 5?4 reserved this field is reserved. 3?0 serq set enable request sets the corresponding bit in erq chapter 21 direct memory access controller (edma) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 459 21.3.9 clear done status bit register (dma_cdne) the cdne provides a simple memory-mapped mechanism to clear the done bit in the tcd of the given channel. the data value on a register write causes the done bit in the corresponding transfer control descriptor to be cleared. setting the cadn bit provides a global clear function, forcing all done bits to be cleared. if the nop bit is set, the command is ignored. this allows you to write multiple-byte registers as a 32-bit word. reads of this register return all zeroes. address: dma_cdne is 4000_8000h base + 1ch offset = 4000_801ch bit 7 6 5 4 3 2 1 0 read 0 0 0 write nop cadn 0 cdne reset 0 0 0 0 0 0 0 0 dma_cdne field descriptions field description 7 nop 0 normal operation 1 no operation, ignore the other bits in this register 6 cadn clears all done bits 0 clears only the tcdn_csr[done] bit specified in the cdne field 1 clears all bits in tcdn_csr[done] 5?4 reserved this field is reserved. 3?0 cdne clear done bit clears the corresponding bit in tcdn_csr[done] memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 460 freescale semiconductor, inc. 21.3.10 set start bit register (dma_ssrt) the ssrt provides a simple memory-mapped mechanism to set the start bit in the tcd of the given channel. the data value on a register write causes the start bit in the corresponding transfer control descriptor to be set. setting the sast bit provides a global set function, forcing all start bits to be set. if the nop bit is set, the command is ignored. this allows you to write multiple-byte registers as a 32-bit word. reads of this register return all zeroes. address: dma_ssrt is 4000_8000h base + 1dh offset = 4000_801dh bit 7 6 5 4 3 2 1 0 read 0 0 0 write nop sast 0 ssrt reset 0 0 0 0 0 0 0 0 dma_ssrt field descriptions field description 7 nop 0 normal operation 1 no operation, ignore the other bits in this register 6 sast set all start bits (activates all channels) 0 set only the tcdn_csr[start] bit specified in the ssrt field 1 set all bits in tcdn_csr[start] 5?4 reserved this field is reserved. 3?0 ssrt set start bit sets the corresponding bit in tcdn_csr[start] chapter 21 direct memory access controller (edma) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 461 21.3.11 clear error register (dma_cerr) the cerr provides a simple memory-mapped mechanism to clear a given bit in the err to disable the error condition flag for a given channel. the given value on a register write causes the corresponding bit in the err to be cleared. setting the caei bit provides a global clear function, forcing the err contents to be cleared, clearing all channel error indicators. if the nop bit is set, the command is ignored. this allows you to write multiple-byte registers as a 32-bit word. reads of this register return all zeroes. address: dma_cerr is 4000_8000h base + 1eh offset = 4000_801eh bit 7 6 5 4 3 2 1 0 read 0 0 0 write nop caei 0 cerr reset 0 0 0 0 0 0 0 0 dma_cerr field descriptions field description 7 nop 0 normal operation 1 no operation, ignore the other bits in this register 6 caei clear all error indicators 0 clear only the err bit specified in the cerr field 1 clear all bits in err 5?4 reserved this field is reserved. 3?0 cerr clear error indicator clears the corresponding bit in err memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 462 freescale semiconductor, inc. 21.3.12 clear interrupt request register (dma_cint) the cint provides a simple, memory-mapped mechanism to clear a given bit in the int to disable the interrupt request for a given channel. the given value on a register write causes the corresponding bit in the int to be cleared. setting the cair bit provides a global clear function, forcing the entire contents of the int to be cleared, disabling all dma interrupt requests. if the nop bit is set, the command is ignored. this allows you to write multiple-byte registers as a 32-bit word. reads of this register return all zeroes. address: dma_cint is 4000_8000h base + 1fh offset = 4000_801fh bit 7 6 5 4 3 2 1 0 read 0 0 0 write nop cair 0 cint reset 0 0 0 0 0 0 0 0 dma_cint field descriptions field description 7 nop 0 normal operation 1 no operation, ignore the other bits in this register 6 cair clear all interrupt requests 0 clear only the int bit specified in the cint field 1 clear all bits in int 5?4 reserved this field is reserved. 3?0 cint clear interrupt request clears the corresponding bit in int 21.3.13 interrupt request register (dma_int) the int register provides a bit map for the 16 channels signaling the presence of an interrupt request for each channel. depending on the appropriate bit setting in the transfer-control descriptors, the edma engine generates an interrupt on data transfer completion. the outputs of this register are directly routed to the interrupt controller (intc). during the interrupt-service routine associated with any given channel, it is the softwares responsibility to clear the appropriate bit, negating the interrupt request. typically, a write to the cint register in the interrupt service routine is used for this purpose. chapter 21 direct memory access controller (edma) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 463 the state of any given channels interrupt request is directly affected by writes to this register; it is also affected by writes to the cint register. on writes to int, a 1 in any bit position clears the corresponding channels interrupt request. a zero in any bit position has no affect on the corresponding channels current interrupt status. the cint register is provided so the interrupt request for a single channel can easily be cleared without the need to perform a read-modify-write sequence to the int register. address: dma_int is 4000_8000h base + 24h offset = 4000_8024h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r int15 int14 int13 int12 int11 int10 int9 int8 int7 int6 int5 int4 int3 int2 int1 int0 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dma_int field descriptions field description 31?16 reserved this read-only field is reserved and always has the value zero. 15 int15 interrupt request 15 0 the interrupt request for corresponding channel is cleared 1 the interrupt request for corresponding channel is active 14 int14 interrupt request 14 0 the interrupt request for corresponding channel is cleared 1 the interrupt request for corresponding channel is active 13 int13 interrupt request 13 0 the interrupt request for corresponding channel is cleared 1 the interrupt request for corresponding channel is active 12 int12 interrupt request 12 0 the interrupt request for corresponding channel is cleared 1 the interrupt request for corresponding channel is active 11 int11 interrupt request 11 table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 464 freescale semiconductor, inc. dma_int field descriptions (continued) field description 0 the interrupt request for corresponding channel is cleared 1 the interrupt request for corresponding channel is active 10 int10 interrupt request 10 0 the interrupt request for corresponding channel is cleared 1 the interrupt request for corresponding channel is active 9 int9 interrupt request 9 0 the interrupt request for corresponding channel is cleared 1 the interrupt request for corresponding channel is active 8 int8 interrupt request 8 0 the interrupt request for corresponding channel is cleared 1 the interrupt request for corresponding channel is active 7 int7 interrupt request 7 0 the interrupt request for corresponding channel is cleared 1 the interrupt request for corresponding channel is active 6 int6 interrupt request 6 0 the interrupt request for corresponding channel is cleared 1 the interrupt request for corresponding channel is active 5 int5 interrupt request 5 0 the interrupt request for corresponding channel is cleared 1 the interrupt request for corresponding channel is active 4 int4 interrupt request 4 0 the interrupt request for corresponding channel is cleared 1 the interrupt request for corresponding channel is active 3 int3 interrupt request 3 0 the interrupt request for corresponding channel is cleared 1 the interrupt request for corresponding channel is active 2 int2 interrupt request 2 0 the interrupt request for corresponding channel is cleared 1 the interrupt request for corresponding channel is active 1 int1 interrupt request 1 0 the interrupt request for corresponding channel is cleared 1 the interrupt request for corresponding channel is active 0 int0 interrupt request 0 0 the interrupt request for corresponding channel is cleared 1 the interrupt request for corresponding channel is active chapter 21 direct memory access controller (edma) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 465 21.3.14 error register (dma_err) the err provides a bit map for the 16 channels, signaling the presence of an error for each channel. the edma engine signals the occurrence of an error condition by setting the appropriate bit in this register. the outputs of this register are enabled by the contents of the eei, and then routed to the interrupt controller. during the execution of the interrupt-service routine associated with any dma errors, it is softwares responsibility to clear the appropriate bit, negating the error-interrupt request. typically, a write to the cerr in the interrupt-service routine is used for this purpose. the normal dma channel completion indicators (setting the transfer control descriptor done flag and the possible assertion of an interrupt request) are not affected when an error is detected. the contents of this register can also be polled because a non-zero value indicates the presence of a channel error regardless of the state of the eei. the state of any given channels error indicators is affected by writes to this register; it is also affected by writes to the cerr. on writes to the err, a one in any bit position clears the corresponding channels error status. a zero in any bit position has no affect on the corresponding channels current error status. the cerr is provided so the error indicator for a single channel can easily be cleared. address: dma_err is 4000_8000h base + 2ch offset = 4000_802ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r err15 err14 err13 err12 err11 err10 err9 err8 err7 err6 err5 err4 err3 err2 err1 err0 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dma_err field descriptions field description 31?16 reserved this read-only field is reserved and always has the value zero. table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 466 freescale semiconductor, inc. dma_err field descriptions (continued) field description 15 err15 error in channel 15 0 an error in the corresponding channel has not occurred 1 an error in the corresponding channel has occurred 14 err14 error in channel 14 0 an error in the corresponding channel has not occurred 1 an error in the corresponding channel has occurred 13 err13 error in channel 13 0 an error in the corresponding channel has not occurred 1 an error in the corresponding channel has occurred 12 err12 error in channel 12 0 an error in the corresponding channel has not occurred 1 an error in the corresponding channel has occurred 11 err11 error in channel 11 0 an error in the corresponding channel has not occurred 1 an error in the corresponding channel has occurred 10 err10 error in channel 10 0 an error in the corresponding channel has not occurred 1 an error in the corresponding channel has occurred 9 err9 error in channel 9 0 an error in the corresponding channel has not occurred 1 an error in the corresponding channel has occurred 8 err8 error in channel 8 0 an error in the corresponding channel has not occurred 1 an error in the corresponding channel has occurred 7 err7 error in channel 7 0 an error in the corresponding channel has not occurred 1 an error in the corresponding channel has occurred 6 err6 error in channel 6 0 an error in the corresponding channel has not occurred 1 an error in the corresponding channel has occurred 5 err5 error in channel 5 0 an error in the corresponding channel has not occurred 1 an error in the corresponding channel has occurred 4 err4 error in channel 4 table continues on the next page... chapter 21 direct memory access controller edma 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 467 dma_err field descriptions (continued) field description 0 an error in the corresponding channel has not occurred 1 an error in the corresponding channel has occurred 3 err3 error in channel 3 0 an error in the corresponding channel has not occurred 1 an error in the corresponding channel has occurred 2 err2 error in channel 2 0 an error in the corresponding channel has not occurred 1 an error in the corresponding channel has occurred 1 err1 error in channel 1 0 an error in the corresponding channel has not occurred 1 an error in the corresponding channel has occurred 0 err0 error in channel 0 0 an error in the corresponding channel has not occurred 1 an error in the corresponding channel has occurred 21.3.15 hardware request status register (dma_hrs) the hrs provides a bit map for the dma channels, signaling the presence of a hardware request for each channel. the hardware request status bits reflect the current state of the register and qualified (via the erq fields) dma request signals as seen by the dmas arbitration logic. this view into the hardware request signals may be used for debug purposes. note these bits reflect the state of the request as seen by the arbitration logic. therefore, this status is affected by the erq bits. address: dma_hrs is 4000_8000h base + 34h offset = 4000_8034h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 hrs15 hrs14 hrs13 hrs12 hrs11 hrs10 hrs9 hrs8 hrs7 hrs6 hrs5 hrs4 hrs3 hrs2 hrs1 hrs0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 468 freescale semiconductor, inc. dma_hrs field descriptions field description 3116 reserved this read-only field is reserved and always has the value zero. 15 hrs15 hardware request status channel 15 0 a hardware service request for the corresponding channel is not present 1 a hardware service request for the corresponding channel is present 14 hrs14 hardware request status channel 14 0 a hardware service request for the corresponding channel is not present 1 a hardware service request for the corresponding channel is present 13 hrs13 hardware request status channel 13 0 a hardware service request for the corresponding channel is not present 1 a hardware service request for the corresponding channel is present 12 hrs12 hardware request status channel 12 0 a hardware service request for the corresponding channel is not present 1 a hardware service request for the corresponding channel is present 11 hrs11 hardware request status channel 11 0 a hardware service request for the corresponding channel is not present 1 a hardware service request for the corresponding channel is present 10 hrs10 hardware request status channel 10 0 a hardware service request for the corresponding channel is not present 1 a hardware service request for the corresponding channel is present 9 hrs9 hardware request status channel 9 0 a hardware service request for the corresponding channel is not present 1 a hardware service request for the corresponding channel is present 8 hrs8 hardware request status channel 8 0 a hardware service request for the corresponding channel is not present 1 a hardware service request for the corresponding channel is present 7 hrs7 hardware request status channel 7 0 a hardware service request for the corresponding channel is not present 1 a hardware service request for the corresponding channel is present 6 hrs6 hardware request status channel 6 0 a hardware service request for the corresponding channel is not present 1 a hardware service request for the corresponding channel is present 5 hrs5 hardware request status channel 5 0 a hardware service request for the corresponding channel is not present 1 a hardware service request for the corresponding channel is present table continues on the next page... chapter 21 direct memory access controller edma 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 46 dma_hrs field descriptions (continued) field description 4 hrs4 hardware request status channel 4 0 a hardware service request for the corresponding channel is not present 1 a hardware service request for the corresponding channel is present 3 hrs3 hardware request status channel 3 0 a hardware service request for the corresponding channel is not present 1 a hardware service request for the corresponding channel is present 2 hrs2 hardware request status channel 2 0 a hardware service request for the corresponding channel is not present 1 a hardware service request for the corresponding channel is present 1 hrs1 hardware request status channel 1 0 a hardware service request for the corresponding channel is not present 1 a hardware service request for the corresponding channel is present 0 hrs0 hardware request status channel 0 0 a hardware service request for the corresponding channel is not present 1 a hardware service request for the corresponding channel is present 21.3.16 channel n priority register (dma_dchpri n when fixed-priority channel arbitration is enabled (cr[erca] = 0), the contents of these registers define the unique priorities associated with each channel. the channel priorities are evaluated by numeric value; for example, 0 is the lowest priority, 1 is the next priority, then 2, 3, etc. software must program the channel priorities with unique values. otherwise, a configuration error is reported. the range of the priority value is limited to the values of 0 through 15. addresses: 4000_8000h base + 100h offset + (1d n , where n 0d to 1d bit 7 6 4 2 1 0 read ecp dpa 0 chpri write reset x* x* x* x* x* x* x* x* * notes x undefined at reset. dma_dchpri n iel escritions fiel escrition nale hannel reetion table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 470 freescale semiconductor, inc. dma_dchpri n iel escritions continue fiel escrition hannel n cannot e susene y a hiher riority channels serice request hannel n can e teorarily susene y the serice request o a hiher riority channel isale reet ility hannel n can susen a lower riority channel hannel n cannot susen any channel rearless o channel riority resere his reaonly iel is resere an always has the alue ero hr hannel n ritration riority hannel riority when ixeriority aritration is enale o: reset alue or the channel riority iels hr is equal to the corresonin channel nuer or each riority reister ie hrhr equals ource ress r resses: h ase h oset n , where n 0d to 1d bit 1 0 2 28 27 26 2 24 2 22 21 20 1 18 17 16 1 14 1 12 11 10 8 7 6 4 2 1 0 r saddr w reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes x undefined at reset. dma_tcd n r iel escritions fiel escrition r ource ress eory aress ointin to the source ata hater irect eory ccess ontroller e ufaily reerence anual re o freescale eiconuctor nc 21.3.18 tcd signed source address offset (dma_tcd_soff) addresses: 4000_8000h base + 1004h offset + (32d ? n , where n 0d to 1d bit 1 14 1 12 11 10 8 7 6 4 2 1 0 read sff write reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes x undefined at reset. dma_tcd n off iel escritions fiel escrition off ource aress sine oset inextene oset alie to the current source aress to or the nextstate alue as each source rea is colete ranser ttriutes r resses: h ase h oset n , where n 0d to 1d bit 1 14 1 12 11 10 8 7 6 4 2 1 0 read smd ssie dmd dsie write reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes x undefined at reset. dma_tcd n r iel escritions fiel escrition o ource ress oulo ource aress oulo eature is isale his alue eines a seciic aress rane seciie to e the alue ater r off calculation is erore or the oriinal reister alue he settin o this iel roies the aility to ileent a circular ata queue easily for ata queues requirin owero sie ytes the queue shoul start at a oulosie aress an the o iel shoul e set to the aroriate alue or the queue reein the esire nuer o uer aress its he alue rorae into this iel seciies the nuer o lower aress its allowe to chane for a circular queue alication the off is tyically set to the transer sie to ileent ostincreent aressin with the o unction constrainin the aresses to a oulosie rane table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 472 freescale semiconductor, inc. dma_tcd n r iel escritions continue fiel escrition ource ata transer sie he attete use o a resere encoin causes a coniuration error it it it resere yte resere resere resere o estination ress oulo ee the o einition estination ata ranser ie ee the einition inor yte ount inor loo isale lo tcd word 2's register definition depends on the status of minor loop mapping. if minor loop mapping is disabled (cr[emlm] = 0), tcd word 2 is defined as follows. if minor loop mapping is enabled, see the tcd_nbytes_mloffno and tcd_nbytes_mloffyes register descriptions for tcd word 2's register definition. addresses: 4000_8000h base + 1008h offset + (32d n , where n 0d to 1d bit 1 0 2 28 27 26 2 24 2 22 21 20 1 18 17 16 1 14 1 12 11 10 8 7 6 4 2 1 0 r nbtes w reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes x undefined at reset. dma_tcd n lo iel escritions fiel escrition inor yte ranser ount uer o ytes to e transerre in each serice request o the channel s a channel actiates the aroriate contents loa into the e enine an the aroriate reas an writes eror until the inor yte transer count has transerre his is an iniisile oeration an cannot e halte lthouh it ay e stalle y usin the anwith control iel or ia reetion ter the inor count hater irect eory ccess ontroller e ufaily reerence anual re o freescale eiconuctor nc dma_tcd n lo iel escritions continue fiel escrition is exhauste the r an r alues are written ac into the eory the aor iteration count is ecreente an restore to the eory the aor iteration count is colete aitional rocessin is erore o: n alue o x is interrete as a transer ine inor loo oset inor loo nale an oset isale loffo tcd word 2 is defined as follows if: ? minor loop mapping is enabled (cr[emlm] = 1) and ? smloe = 0 and dmloe = 0 if minor loop mapping is enabled and smloe or dmloe is set then refer to the tcd_nbytes_mloffyes register description. addresses: 4000_8000h base + 1008h offset + (32d n , where n 0d to 1d bit 1 0 2 28 27 26 2 24 2 22 21 20 1 18 17 16 1 14 1 12 11 10 8 7 6 4 2 1 0 r sme dme nbtes w reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes x undefined at reset. dma_tcd n loffo iel escritions fiel escrition lo ource inor loo oset nale elects whether the inor loo oset is alie to the source aress uon inor loo coletion he inor loo oset is not alie to the r he inor loo oset is alie to the r lo estination inor loo oset enale elects whether the inor loo oset is alie to the estination aress uon inor loo coletion he inor loo oset is not alie to the r he inor loo oset is alie to the r inor yte ranser ount uer o ytes to e transerre in each serice request o the channel table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 474 freescale semiconductor, inc. dma_tcd n loffo iel escritions continue fiel escrition s a channel actiates the aroriate contents loa into the e enine an the aroriate reas an writes eror until the inor yte transer count has transerre his is an iniisile oeration an cannot e halte althouh it ay e stalle y usin the anwith control iel or ia reetion ter the inor count is exhauste the r an r alues are written ac into the eory the aor iteration count is ecreente an restore to the eory the aor iteration count is colete aitional rocessin is erore ine inor loo oset inor loo an oset nale loff tcd word 2 is defined as follows if: ? minor loop mapping is enabled (cr[emlm] = 1) and ? minor loop offset enabled (smloe or dmloe = 1) if minor loop mapping is enabled and smloe and dmloe are cleared then refer to the tcd_nbytes_mloffno register description. addresses: 4000_8000h base + 1008h offset + (32d n , where n 0d to 1d bit 1 0 2 28 27 26 2 24 2 22 21 20 1 18 17 16 1 14 1 12 11 10 8 7 6 4 2 1 0 r sme dme mff nbtes w reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes x undefined at reset. dma_tcd n loff iel escritions fiel escrition lo ource inor loo oset nale elects whether the inor loo oset is alie to the source aress uon inor loo coletion he inor loo oset is not alie to the r he inor loo oset is alie to the r lo estination inor loo oset enale elects whether the inor loo oset is alie to the estination aress uon inor loo coletion he inor loo oset is not alie to the r he inor loo oset is alie to the r loff lo or lo is set this iel reresents a sinextene oset alie to the source or estination aress to or the nextstate alue ater the inor loo coletes table continues on the next page... chapter 21 direct memory access controller edma 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 47 dma_tcd n loff iel escritions continue fiel escrition inor yte ranser ount uer o ytes to e transerre in each serice request o the channel s a channel actiates the aroriate contents loa into the e enine an the aroriate reas an writes eror until the inor yte transer count has transerre his is an iniisile oeration an cannot e halte lthouh it ay e stalle y usin the anwith control iel or ia reetion ter the inor count is exhauste the r an r alues are written ac into the eory the aor iteration count is ecreente an restore to the eory the aor iteration count is colete aitional rocessin is erore last ource ress ustent l resses: h ase h oset n , where n 0d to 1d bit 1 0 2 28 27 26 2 24 2 22 21 20 1 18 17 16 1 14 1 12 11 10 8 7 6 4 2 1 0 r sast w reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes x undefined at reset. dma_tcd n l iel escritions fiel escrition l last source ress ustent ustent alue ae to the source aress at the coletion o the aor iteration count his alue can e alie to restore the source aress to the initial alue or aust the aress to reerence the next ata structure estination ress r resses: h ase h oset n , where n 0d to 1d bit 1 0 2 28 27 26 2 24 2 22 21 20 1 18 17 16 1 14 1 12 11 10 8 7 6 4 2 1 0 r daddr w reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes x undefined at reset. memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 476 freescale semiconductor, inc. dma_tcd n r iel escritions fiel escrition r estination ress eory aress ointin to the estination ata ine estination ress oset off resses: h ase h oset n , where n 0d to 1d bit 1 14 1 12 11 10 8 7 6 4 2 1 0 read dff write reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes x undefined at reset. dma_tcd n off iel escritions fiel escrition off estination ress ine oset inextene oset alie to the current estination aress to or the nextstate alue as each estination write is colete urrent inor loo lin aor loo ount hannel linin nale rl if tcdn_citer[elink] is set, the tcdn_citer register is defined as follows. addresses: 4000_8000h base + 1016h offset + (32d n , where n 0d to 1d bit 1 14 1 12 11 10 8 7 6 4 2 1 0 read ein 0 inch citer write reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes x undefined at reset. chapter 21 direct memory access controller edma 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 477 dma_tcd n rl iel escritions fiel escrition l nale channeltochannel linin on inorloo colete s the channel coletes the inor loo this la enales linin to another channel eine y the lh iel he lin taret channel initiates a channel serice request ia an internal echanis that sets the nrr it o the seciie channel channel linin is isale the r alue is extene to its in lace o a lin channel nuer the aor loo is exhauste this lin echanis is suresse in aor o the orl channel linin o: his it ust e equal to the rl it otherwise a coniuration error is reorte he channeltochannel linin is isale he channeltochannel linin is enale resere his reaonly iel is resere an always has the alue ero lh lin hannel uer channeltochannel linin is enale l then ater the inor loo is exhauste the e enine initiates a channel serice request to the channel eine y these our its y settin that channels nrr it r urrent aor teration ount his it l or it l count reresents the current aor loo count or the channel t is ecreente each tie the inor loo is colete an uate in the transer control escritor eory ter the aor iteration count is exhauste the channel erors a nuer o oerations e inal source an estination aress calculations otionally eneratin an interrut to sinal channel coletion eore reloain the r iel ro the einnin iteration count r iel o: hen the r iel is initially loae y sotware it ust e set to the sae alue as that containe in the r iel o: the channel is coniure to execute a sinle serice request the initial alues o r an r shoul e x urrent inor loo lin aor loo ount hannel linin isale rlo if tcdn_citer[elink] is cleared, the tcdn_citer register is defined as follows. addresses: 4000_8000h base + 1016h offset + (32d n , where n 0d to 1d bit 1 14 1 12 11 10 8 7 6 4 2 1 0 read ein citer write reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes x undefined at reset. memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 478 freescale semiconductor, inc. dma_tcd n rlo iel escritions fiel escrition l nale channeltochannel linin on inorloo colete s the channel coletes the inor loo this la enales linin to another channel eine y the lh iel he lin taret channel initiates a channel serice request ia an internal echanis that sets the nrr it o the seciie channel channel linin is isale the r alue is extene to its in lace o a lin channel nuer the aor loo is exhauste this lin echanis is suresse in aor o the orl channel linin o: his it ust e equal to the rl it otherwise a coniuration error is reorte he channeltochannel linin is isale he channeltochannel linin is enale r urrent aor teration ount his it l or it l count reresents the current aor loo count or the channel t is ecreente each tie the inor loo is colete an uate in the transer control escritor eory ter the aor iteration count is exhauste the channel erors a nuer o oerations e inal source an estination aress calculations otionally eneratin an interrut to sinal channel coletion eore reloain the r iel ro the einnin iteration count r iel o: hen the r iel is initially loae y sotware it ust e set to the sae alue as that containe in the r iel o: the channel is coniure to execute a sinle serice request the initial alues o r an r shoul e x last estination ress ustentcatter ather ress l resses: h ase h oset n , where n 0d to 1d bit 1 0 2 28 27 26 2 24 2 22 21 20 1 18 17 16 1 14 1 12 11 10 8 7 6 4 2 1 0 r dastsa w reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes x undefined at reset. dma_tcd n l iel escritions fiel escrition l estination last aress austent or the eory aress or the next transer control escritor to e loae into this channel scatterather nr then ustent alue ae to the estination aress at the coletion o the aor iteration count his alue can aly to restore the estination aress to the initial alue or aust the aress to reerence the next ata structure hater irect eory ccess ontroller e ufaily reerence anual re o freescale eiconuctor nc dma_tcd n l iel escritions continue fiel escrition else his aress oints to the einnin o a ouloyte reion containin the next transer control escritor to e loae into this channel his channel reloa is erore as the aor iteration count coletes he scatterather aress ust e ouloyte else a coniuration error is reorte ontrol an tatus r resses: h ase h oset n , where n 0d to 1d bit 1 14 1 12 11 10 8 7 6 4 2 1 0 read bwc 0 marinch dne active marein es dre inthaf intmar start write reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes x undefined at reset. dma_tcd n r iel escritions fiel escrition anwith ontrol hrottles the aount o us anwith consue y the e n eneral as the e rocesses the inor loo it continuously enerates reawrite sequences until the inor count is exhauste his iel orces the e to stall ater the coletion o each reawrite access to control the us request anwith seen y the crossar switch o: the source an estination sies are equal this iel is inore etween the irst an secon transers an ater the last write o each inor loo his ehaior is a sie eect o reucin startu latency o e enine stalls resere e enine stalls or cycles ater each rw e enine stalls or cycles ater each rw resere his reaonly iel is resere an always has the alue ero orlh lin hannel uer orl then o channeltochannel linin or chainin is erore ater the aor loo counter is exhauste else table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 480 freescale semiconductor, inc. dma_tcd n r iel escritions continue fiel escrition ter the aor loo counter is exhauste the e enine initiates a channel serice request at the channel eine y these six its y settin that channels nrr it o hannel one his la inicates the e has colete the aor loo he e enine sets it as the r count reaches ero he sotware clears it or the harware when the channel is actiate o: his it ust e cleare to write the orl or its hannel ctie his la sinals the channel is currently in execution t is set when channel serice eins an the e clears it as the inor loo coletes or i any error conition is etecte his it resets to ero orl nale channeltochannel linin on aor loo colete s the channel coletes the aor loo this la enales the linin to another channel eine y orlh he lin taret channel initiates a channel serice request ia an internal echanis that sets the nrr it o the seciie channel o: o suort the ynaic linin coherency oel this iel is orce to ero when written to while the nro it is set he channeltochannel linin is isale he channeltochannel linin is enale nale catterather rocessin s the channel coletes the aor loo this la enales scatterather rocessin in the current channel enale the e enine uses l as a eory ointer to a oulo aress containin a yte ata structure loae as the transer control escritor into the local eory o: o suort the ynaic scatterather coherency oel this iel is orce to ero when written to while the nro it is set he current channels is noral orat he current channels seciies a scatter ather orat he l iel roies a eory ointer to the next to e loae into this channel ater the aor loo coletes its execution r isale request this la is set the e harware autoatically clears the corresonin r it when the current aor iteration count reaches ero he channels r it is not aecte he channels r it is cleare when the aor loo is colete hlf nale an interrut when aor counter is hal colete this la is set the channel enerates an interrut request y settin the aroriate it in the reister when the current aor iteration count reaches the halway oint eciically the coarison erore y the e enine is r r his halway oint interrut request is roie to suort ouleuere aa inon schees or other tyes o ata oeent where the rocessor nees an early inication o the transers roress r is set o not use hlf use or instea table continues on the next page... chapter 21 direct memory access controller edma 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 481 dma_tcd n r iel escritions continue fiel escrition he haloint interrut is isale he haloint interrut is enale or nale an interrut when aor iteration count coletes this la is set the channel enerates an interrut request y settin the aroriate it in the when the current aor iteration count reaches ero he enoaor loo interrut is isale he enoaor loo interrut is enale r hannel tart this la is set the channel is requestin serice he e harware autoatically clears this la ater the channel eins execution he channel is not exlicitly starte he channel is exlicitly starte ia a sotware initiate serice request einnin inor loo lin aor loo ount hannel linin nale rl if the tcdn_biter[elink] bit is set, the tcdn_biter register is defined as follows. addresses: 4000_8000h base + 101eh offset + (32d n , where n 0d to 1d bit 1 14 1 12 11 10 8 7 6 4 2 1 0 read ein 0 inch biter write reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes x undefined at reset. dma_tcd n rl iel escritions fiel escrition l nales channeltochannel linin on inor loo colete s the channel coletes the inor loo this la enales the linin to another channel eine y rlh he lin taret channel initiates a channel serice request ia an internal echanis that sets the nrr it o the seciie channel channel linin isales the r alue extens to its in lace o a lin channel nuer the aor loo is exhauste this lin echanis is suresse in aor o the orl channel linin o: hen the sotware loas the this iel ust e set equal to the corresonin r iel otherwise a coniuration error is reorte s the aor iteration count is exhauste the contents o this iel is reloae into the r iel table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 482 freescale semiconductor, inc. dma_tcd n rl iel escritions continue fiel escrition he channeltochannel linin is isale he channeltochannel linin is enale resere his reaonly iel is resere an always has the alue ero lh lin hannel uer channeltochannel linin is enale l then ater the inor loo is exhauste the e enine initiates a channel serice request at the channel eine y these our its y settin that channels nrr it o: hen the sotware loas the this iel ust e set equal to the corresonin r iel otherwise a coniuration error is reorte s the aor iteration count is exhauste the contents o this iel is reloae into the r iel r tartin aor teration ount s the transer control escritor is irst loae y sotware this it l or it l iel ust e equal to the alue in the r iel s the aor iteration count is exhauste the contents o this iel are reloae into the r iel o: hen the sotware loas the this iel ust e set equal to the corresonin r iel otherwise a coniuration error is reorte s the aor iteration count is exhauste the contents o this iel is reloae into the r iel the channel is coniure to execute a sinle serice request the initial alues o r an r shoul e x einnin inor loo lin aor loo ount hannel linin isale rlo if the tcdn_biter[elink] bit is cleared, the tcdn_biter register is defined as follows. addresses: 4000_8000h base + 101eh offset + (32d n , where n 0d to 1d bit 1 14 1 12 11 10 8 7 6 4 2 1 0 read ein biter write reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes x undefined at reset. dma_tcd n rlo iel escritions fiel escrition l nales channeltochannel linin on inor loo colete s the channel coletes the inor loo this la enales the linin to another channel eine y rlh he lin taret channel initiates a channel serice request ia an internal echanis that sets the nrr it o the seciie channel channel linin is isale the r table continues on the next page... chapter 21 direct memory access controller edma 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 48 dma_tcd n rlo iel escritions continue fiel escrition alue extens to its in lace o a lin channel nuer the aor loo is exhauste this lin echanis is suresse in aor o the orl channel linin o: hen the sotware loas the this iel ust e set equal to the corresonin r iel otherwise a coniuration error is reorte s the aor iteration count is exhauste the contents o this iel is reloae into the r iel he channeltochannel linin is isale he channeltochannel linin is enale r tartin aor teration ount s the transer control escritor is irst loae y sotware this it l or it l iel ust e equal to the alue in the r iel s the aor iteration count is exhauste the contents o this iel are reloae into the r iel o: hen the sotware loas the this iel ust e set equal to the corresonin r iel otherwise a coniuration error is reorte s the aor iteration count is exhauste the contents o this iel is reloae into the r iel the channel is coniure to execute a sinle serice request the initial alues o r an r shoul e x functional escrition e asic ata low the basic flow of a data transfer can be partitioned into three segments. as shown in the following diagram, the first segment involves the channel activation: functional description k60 sub-family reference manual, rev. 6, nov 2011 484 freescale semiconductor, inc. 1 edma engine data path edma 0 program model/ 64 control n-1 to/from crossbar switch 2 channel arbitration address path read data write data address read data write data write address internal peripheral bus edma peripheral request edma done transfer control descriptor (tcd) figure 21-289. edma operation, part 1 this example uses the assertion of the edma peripheral request signal to request service for channel n . channel activation via software and the tcd n _csr[start] bit follows the same basic flow as peripheral requests. the edma request input signal is registered internally and then routed through the edma engine: first through the control module, then into the program model and channel arbitration. in the next cycle, the channel arbitration performs, using the fixed-priority or round-robin algorithm. after arbitration is complete, the activated channel number is sent through the address path and converted into the required address to access the local memory for tcd n . next, the tcd memory is accessed and the required descriptor read from the local memory and loaded into the edma engine address path channel x or y registers. the tcd memory is 64 bits wide to minimize the time needed to fetch the activated channel descriptor and load it into the address path channel x or y registers. the following diagram illustrates the second part of the basic data flow: chapter 21 direct memory access controller (edma) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 485 1 edma engine data path edma 0 program model/ 64 control n-1 to/from crossbar switch 2 channel arbitration address path read data write data address read data write data write address edma peripheral request edma done transfer control descriptor (tcd) internal peripheral bus figure 21-290. edma operation, part 2 the modules associated with the data transfer (address path, data path, and control) sequence through the required source reads and destination writes to perform the actual data movement. the source reads are initiated and the fetched data is temporarily stored in the data path block until it is gated onto the internal bus during the destination write. this source read/destination write processing continues until the minor byte count has transferred. after the minor byte count has moved, the final phase of the basic data flow is performed. in this segment, the address path logic performs the required updates to certain fields in the appropriate tcd, e.g., saddr, daddr, citer. if the major iteration count is exhausted, additional operations are performed. these include the final address adjustments and reloading of the biter field into the citer. assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new tcd from memory using the scatter/gather address pointer included in the descriptor (if scatter/ gather is enabled). the updates to the tcd memory and the assertion of an interrupt request are shown in the following diagram. functional description k60 sub-family reference manual, rev. 6, nov 2011 486 freescale semiconductor, inc. 1 edma en g in e data path edma 0 program model/ 64 control n-1 to/from crossbar switch 2 channel arbitration address path read data write data address read data write data write address edma peripheral request edma done transfer control descriptor (tcd) internal peripheral bus figure 21-291. edma operation, part 3 21.4.2 error reporting and handling channel errors are reported in the es register and can be caused by: ? a configuration error, which is an illegal setting in the transfer-control descriptor or an illegal priority register setting in fixed-arbitration mode, or ? an error termination to a bus master read or write cycle a configuration error is reported when the starting source or destination address, source or destination offsets, minor loop byte count, or the transfer size represent an inconsistent state. each of these possible causes are detailed below: ? the addresses and offsets must be aligned on 0-modulo-transfer-size boundaries. ? the minor loop byte count must be a multiple of the source and destination transfer sizes. chapter 21 direct memory access controller (edma) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 487 ? all source reads and destination writes must be configured to the natural boundary of the programmed transfer size respectively. ? in fixed arbitration mode, a configuration error is caused by any two channel priorities being equal. all channel priority levels must be unique when fixed arbitration mode is enabled. ? if a scatter/gather operation is enabled upon channel completion, a configuration error is reported if the scatter/gather address (dlast_sga) is not aligned on a 32- byte boundary. ? if minor loop channel linking is enabled upon channel completion, a configuration error is reported when the link is attempted if the tcdn_citer[e_link] bit does not equal the tcdn_biter[e_link] bit. if enabled, all configuration error conditions, except the scatter/gather and minor-loop link errors, report as the channel activates and asserts an error interrupt request. a scatter/ gather configuration error is reported when the scatter/gather operation begins at major loop completion when properly enabled. a minor loop channel link configuration error is reported when the link operation is serviced at minor loop completion. if a system bus read or write is terminated with an error, the data transfer is stopped and the appropriate bus error flag set. in this case, the state of the channel's transfer control descriptor is updated by the edma engine with the current source address, destination address, and current iteration count at the point of the fault. when a system-bus error occurs, the channel terminates after the read or write transaction, which is already pipelined after errant access, has completed. if a bus error occurs on the last read prior to beginning the write sequence, the write executes using the data captured during the bus error. if a bus error occurs on the last write prior to switching to the next read sequence, the read sequence executes before the channel terminates due to the destination bus error. a transfer may be cancelled by software with the cr[cx] bit. when a cancel transfer request is recognized, the dma engine stops processing the channel. the current read- write sequence is allowed to finish. if the cancel occurs on the last read-write sequence of a major or minor loop, the cancel request is discarded and the channel retires normally. the error cancel transfer is the same as a cancel transfer except the es register is updated with the cancelled channel number and ecx is set. the tcd of a cancelled channel contains the source and destination addresses of the last transfer saved in the tcd. if the channel needs to be restarted, you must re-initialize the tcd because the aforementioned fields no longer represent the original parameters. when a transfer is cancelled by the error cancel transfer mechanism, the channel number is loaded into dma_es[errchn] and ecx and vld are set. in addition, an error interrupt may be generated if enabled. the occurrence of any error causes the edma engine to stop the active channel immediately, and the appropriate channel bit in the edma error register is asserted. at the same time, the details of the error condition are loaded into the es register. the major functional description k60 sub-family reference manual, rev. 6, nov 2011 488 freescale semiconductor, inc. loop complete indicators, setting the transfer control descriptor done flag and the possible assertion of an interrupt request, are not affected when an error is detected. after the error status has been updated, the edma engine continues operating by servicing the next appropriate channel. a channel that experiences an error condition is not automatically disabled. if a channel is terminated by an error and then issues another service request before the error is fixed, that channel executes and terminates with the same error condition. 21.4.3 channel preemption channel preemption is enabled on a per-channel basis by setting the dchprin[ecp] bit. channel preemption allows the executing channels data transfers to temporarily suspend in favor of starting a higher priority channel. after the preempting channel has completed all its minor loop data transfers, the preempted channel is restored and resumes execution. after the restored channel completes one read/write sequence, it is again eligible for preemption. if any higher priority channel is requesting service, the restored channel is suspended and the higher priority channel is serviced. nested preemption, that is, attempting to preempt a preempting channel, is not supported. after a preempting channel begins execution, it cannot be preempted. preemption is available only when fixed arbitration is selected. a channels ability to preempt another channel can be disabled by setting dchprin[dpa]. when a channels preempt ability is disabled, that channel cannot suspend a lower priority channels data transfer, regardless of the lower priority channels ecp setting. this allows for a pool of low priority, large data-moving channels to be defined. these low priority channels can be configured to not preempt each other, thus preventing a low priority channel from consuming the preempt slot normally available to a true, high priority channel. 21.4.4 performance this section addresses the performance of the edma module, focusing on two separate metrics: ? in the traditional data movement context, performance is best expressed as the peak data transfer rates achieved using the edma. in most implementations, this transfer rate is limited by the speed of the source and destination address spaces. ? in a second context where device-paced movement of single data values to/from peripherals is dominant, a measure of the requests that can be serviced in a fixed time is a more relevant metric. in this environment, the speed of the source and destination chapter 21 direct memory access controller (edma) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 489 address spaces remains important. however, the microarchitecture of the edma also factors significantly into the resulting metric. 21.4.4.1 peak transfer rates the peak transfer rates for several different source and destination transfers are shown in the following tables. these tables assume: ? internal sram can be accessed with zero wait-states when viewed from the system bus data phase ? all internal peripheral bus reads require two wait-states, and internal peripheral bus writes three wait-states, when viewed from the system bus data phase ? all internal peripheral bus accesses are 32-bits in size this table presents a peak transfer rate comparison. table 21-292. edma peak transfer rates (mbytes/sec) system speed, width internal sram-to- internal sram 32b internal peripheral bus- to- internal sram internal sram-to- 32b internal peripheral bus 66.7 mhz, 32b 133.3 66.7 53.3 83.3 mhz, 32b 166.7 83.3 66.7 100.0 mhz, 32b 200.0 100.0 80.0 133.3 mhz, 32b 266.7 133.3 106.7 150.0 mhz, 32b 300.0 150.0 120.0 internal-sram-to-internal-sram transfers occur at the core's datapath width. for all transfers involving the internal peripheral bus, 32-bit transfer sizes are used. in all cases, the transfer rate includes the time to read the source plus the time to write the destination. 21.4.4.2 peak request rates the second performance metric is a measure of the number of dma requests that can be serviced in a given amount of time. for this metric, assume that the peripheral request causes the channel to move a single internal peripheral bus-mapped operand to/from internal sram. the same timing assumptions used in the previous example apply to this calculation. in particular, this metric also reflects the time required to activate the channel. functional description k60 sub-family reference manual, rev. 6, nov 2011 490 freescale semiconductor, inc. the edma design supports the following hardware service request sequence: table 21-293. hardware service request process, cycles 1?7 cycle description 1 edma peripheral request is asserted. 2 the edma peripheral request is registered locally in the edma module and qualified. tcd n _csrstart bit initiated reuests start at this point with the registering of the user write to tcd n word 7. channel arbitration begins. 4 channel arbitration completes. the transfer control descriptor local memory read is initiated. 6 the first two parts of the activated channels tcd is read from the local memory. the memory width to the edma engine is 64 bits, so the entire descriptor can be accessed in four cycles. 7 the first system bus read cycle is initiated, as the third part of the channels tcd is read from the local memory. depending on the state of the crossbar switch, arbitration at the system bus may insert an additional cycle of delay here. the exact timing from this point is a function of the response times for the channel's read and write accesses. in the case of an internal peripheral bus read and internal sram write, the combined data phase time is 4 cycles. for an sram read and internal peripheral bus write, it is 5 cycles. table 21-294. hardware service request process, cycles 8?17 cycle, with internal peripheral bus read and internal sram write cycle, with sram read and internal peripheral bus write description 8?11 8?12 the last part of the tcd is read in. this cycle represents the first data phase for the read, and the address phase for the destination write. 12 13 this cycle represents the data phase of the last destination write. 13 14 the edma engine completes the execution of the inner minor loop and prepares to write back the required tcd n fields into the local memory. the tcd n word 7 is read and checed for channel lining or scattergather reuests. 14 1 the appropriate fields in the first part of the tcd n are written bac into the local memory. 1 16 the fields in the second part of the tcd n are written bac into the local memory. this cycle coincides with the next channel arbitration cycle start. 16 17 the next channel to be activated performs the read of the first part of its tcd from the local memory. this is euivalent to cycle 4 for the first channels service reuest. chapter 21 direct memory access controller edma 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 41 assuming zero wait states on the system bus, dma requests can be processed every 9 cycles. assuming an average of the access times associated with internal peripheral bus- to-sram (4 cycles) and sram-to-internal peripheral bus (5 cycles), dma requests can be processed every 11.5 cycles (4 + (4+5)/2 + 3). this is the time from cycle 4 to cycle ? +5. the resulting peak request rate, as a function of the system frequency, is shown in the following table. table 21-295. edma peak request rate (mreq/sec) system frequecy (mhz) request rate with zero wait states request rate with wait states 66.6 7.4 5.8 83.3 9.2 7.2 100.0 11.1 8.7 133.3 14.8 11.6 150.0 16.6 13.0 a general formula to compute the peak request rate with overlapping requests is: peakreq = freq / [ entry + (1 + read_ws) + (1 + write_ws) + exit ] where: table 21-296. peak request formula legend where represents peakreq peak request rate freq system frequency entry channel startup (4 cycles) read_ws wait states seen during the system bus read data phase write_ws wait states seen during the system bus write data phase xit channel shutdown (3 cycles) for example, consider a system with the following characteristics: ? internal sram can be accessed with one wait-state when viewed from the system bus data phase ? all internal peripheral bus reads require two wait-states, and internal peripheral bus writes three wait-states viewed from the system bus data phase ? system operates at 150 mhz for an sram to internal peripheral bus transfer, functional description k60 sub-family reference manual, rev. 6, nov 2011 492 freescale semiconductor, inc. peakreq = 150 mhz / [ 4 + (1 + 1) + (1 + 3) + 3 ] cycles = 11.5 mreq/sec for an internal peripheral bus to sram transfer, peakreq = 150 mhz / [ 4 + (1 + 2) + (1 + 1) + 3 ] cycles = 12.5 mreq/sec assuming an even distribution of the two transfer types, the average peak request rate would be: peakreq = (11.5 mreq/sec + 12.5 mreq/sec) / 2 = 12.0 mreq/sec the minimum number of cycles to perform a single read/write, zero wait states on the system bus, from a cold start where no channel is executing and edma is idle are: ? 11 cycles for a software, that is, a tcd n _csr[start] bit, request ? 12 cycles for a hardware, that is, an edma peripheral request signal, request two cycles account for the arbitration pipeline and one extra cycle on the hardware request resulting from the internal registering of the edma peripheral request signals. for the peak request rate calculations above, the arbitration and request registering is absorbed in or overlaps the previous executing channel. note when channel linking or scatter/gather is enabled, a two cycle delay is imposed on the next channel selection and startup. this allows the link channel or the scatter/gather channel to be eligible and considered in the arbitration pool for next channel selection. 21.5 initialization/application information the following sections discuss initialization of the edma and programming considerations. 21.5.1 edma initialization a typical initialization of the edma has the following sequence: 1. write the cr register if a configuration other than the default is desired. 2. write the channel priority levels into the dchpri n registers if a configuration other than the default is desired. chapter 21 direct memory access controller (edma) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 493 3. enable error interrupts in the eei register if so desired. 4. write the 32-byte tcd for each channel that may request service. 5. enable any hardware service requests via the erq register. 6. request channel service via either: ? software: setting the tcd n _csr[start] bit ? hardware: slave device asserting its edma peripheral request signal after any channel requests service, a channel is selected for execution based on the arbitration and priority levels written into the programmer's model. the edma engine reads the entire tcd, including the tcd control and status fields, as shown in the following table, for the selected channel into its internal address path module. as the tcd is read, the first transfer is initiated on the internal bus unless a configuration error is detected. transfers from the source, as defined by the source address, tcd n _saddr, to the destination, as defined by the destination address, tcd n _daddr, continue until the specified number of bytes (tcd n _nbytes) are transferred. when the transfer is complete, the edma engine's local tcd n _saddr, tcd n _daddr, and tcd n _citer are written back to the main tcd memory and any minor loop channel linking is performed, if enabled. if the major loop is exhausted, further post processing executes, such as interrupts, major loop channel linking, and scatter/gather operations, if enabled. table 21-297. tcd control and status fields tcd n r iel nae escrition r ontrol it to start channel exlicitly when usin a sotware initiate serice utoatically cleare y harware tatus it inicatin the channel is currently in execution o tatus it inicatin aor loo coletion cleare y sotware when usin a sotware initiate serice r ontrol it to isale request at en o aor loo coletion when usin a harware initiate serice ontrol its or throttlin anwith control o a channel ontrol it to enale scatterather eature hlf ontrol it to enale interrut when aor loo is hal colete ontrol it to enale interrut when aor loo coletes nitialiationalication inoration ufaily reerence anual re o freescale eiconuctor nc the following figure shows how each dma request initiates one minor-loop transfer, or iteration, without cpu intervention. dma arbitration can occur after each minor loop, and one level of minor loop dma preemption is allowed. the number of minor loops in a major loop is specified by the beginning iteration count (biter). dma request dma request dma request minor loop minor loop minor loop major loop current major loop iteration count (citer) 3 2 1 source or destination memory figure 21-292. example of multiple loop iterations the following figure lists the memory array terms and how the tcd settings interrelate. xaddr: (starting address) xlast: number of bytes added to current address after major loop (typically used to loop back) minor loop (nbytes in minor loop, often the same value as xsize) minor loop last minor loop offset (xoff): number of bytes added to current address after each transfer (often the same value as xsize) each dma source (s) and destination (d) has its own: address (xaddr) size (xsize) offset (xoff) modulo (xmod) last address adjustment (xlast) where x = s or d peripheral queues typically have size and offset equal to nbytes. xsize: (size of one data transfer) figure 21-293. memory array terms chapter 21 direct memory access controller (edma) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 495 21.5.2 programming errors the edma performs various tests on the transfer control descriptor to verify consistency in the descriptor data. most programming errors are reported on a per channel basis with the exception of channel priority error (es[cpe]). for all error types other than channel priority error, the channel number causing the error is recorded in the es register. if the error source is not removed before the next activation of the problem channel, the error is detected and recorded again. if priority levels are not unique, when any channel requests service, a channel priority error is reported. the highest channel priority with an active request is selected, but the lowest numbered channel with that priority is selected by arbitration and executed by the edma engine. the hardware service request handshake signals, error interrupts, and error reporting is associated with the selected channel. 21.5.3 arbitration mode considerations 21.5.3.1 fixed channel arbitration in this mode, the channel service request from the highest priority channel is selected to execute. 21.5.3.2 round-robin channel arbitration channels are serviced starting with the highest channel number and rotating through to the lowest channel number without regard to the channel priority levels. 21.5.4 performing dma transfers 21.5.4.1 single request to perform a simple transfer of n bytes of data with one activation, set the major loop to one (tcd n _citer = tcd n _biter = 1). the data transfer begins after the channel service request is acknowledged and the channel is selected to execute. after the transfer is complete, the tcd n _csr[done] bit is set and an interrupt generates if properly enabled. initialization/application information k60 sub-family reference manual, rev. 6, nov 2011 496 freescale semiconductor, inc. for example, the following tcd entry is configured to transfer 16 bytes of data. the edma is programmed for one iteration of the major loop transferring 16 bytes per iteration. the source memory has a byte wide memory port located at 0x1000. the destination memory has a 32-bit port located at 0x2000. the address offsets are programmed in increments to match the transfer size: one byte for the source and four bytes for the destination. the final source and destination addresses are adjusted to return to their beginning values. tcd n _citer = tcd n _biter = 1 tcd n _nbytes = 16 tcd n _saddr = 0x1000 tcd n _soff = 1 tcd n _attr[ssize] = 0 tcd n _slast = -16 tcd n _daddr = 0x2000 tcd n _doff = 4 tcd n _attr[dsize] = 2 tcd n _dlast_sga= C16 tcd n _csr[int_maj] = 1 tcd n _csr[start] = 1 (should be written last after all other fields have been initialized) all other tcd n fields = 0 this generates the following event sequence: 1. user write to the tcd n _csr[start] bit requests channel service. 2. the channel is selected by arbitration for servicing. 3. edma engine writes: tcd n _csr[done] = 0, tcd n _csr[start] = 0, tcd n _csr[active] = 1. 4. edma engine reads: channel tcd data from local memory to internal register file. 5. the source-to-destination transfers are executed as follows: a. read byte from location 0x1000, read byte from location 0x1001, read byte from 0x1002, read byte from 0x1003. b. write 32-bits to location 0x2000 first iteration of the minor loop. c. read byte from location 0x1004, read byte from location 0x1005, read byte from 0x1006, read byte from 0x1007. d. write 32-bits to location 0x2004 second iteration of the minor loop. e. read byte from location 0x1008, read byte from location 0x1009, read byte from 0x100a, read byte from 0x100b. f. write 32-bits to location 0x2008 third iteration of the minor loop. g. read byte from location 0x100c, read byte from location 0x100d, read byte from 0x100e, read byte from 0x100f. chapter 21 direct memory access controller (edma) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 497 h. write 32-bits to location 0x200c last iteration of the minor loop major loop complete. 6. the edma engine writes: tcd n _saddr = 0x1000, tcd n _daddr = 0x2000, tcd n _citer = 1 (tcd n _biter). 7. the edma engine writes: tcd n _csr[active] = 0, tcd n _csr[done] = 1, int[ n ] = 1. 8. the channel retires and the edma goes idle or services the next channel. 21.5.4.2 multiple requests the following example transfers 32 bytes via two hardware requests, but is otherwise the same as the previous example. the only fields that change are the major loop iteration count and the final address offsets. the edma is programmed for two iterations of the major loop transferring 16 bytes per iteration. after the channel's hardware requests are enabled in the erq register, the slave device initiates channel service requests. tcd n _citer = tcd n _biter = 2 tcd n _slast = C32 tcd n _dlast_sga = C32 this would generate the following sequence of events: 1. first hardware, that is, edma peripheral, request for channel service. 2. the channel is selected by arbitration for servicing. 3. edma engine writes: tcd n _csr[done] = 0, tcd n _csr[start] = 0, tcd n _csr[active] = 1. 4. edma engine reads: channel tcd n data from local memory to internal register file. 5. the source to destination transfers are executed as follows: a. read byte from location 0x1000, read byte from location 0x1001, read byte from 0x1002, read byte from 0x1003. b. write 32-bits to location 0x2000 first iteration of the minor loop. c. read byte from location 0x1004, read byte from location 0x1005, read byte from 0x1006, read byte from 0x1007. d. write 32-bits to location 0x2004 second iteration of the minor loop. e. read byte from location 0x1008, read byte from location 0x1009, read byte from 0x100a, read byte from 0x100b. initialization/application information k60 sub-family reference manual, rev. 6, nov 2011 498 freescale semiconductor, inc. f. write 32-bits to location 0x2008 third iteration of the minor loop. g. read byte from location 0x100c, read byte from location 0x100d, read byte from 0x100e, read byte from 0x100f. h. write 32-bits to location 0x200c last iteration of the minor loop. 6. edma engine writes: tcd n _saddr = 0x1010, tcd n _daddr = 0x2010, tcd n _citer = 1. 7. edma engine writes: tcd n _csr[active] = 0. 8. the channel retires one iteration of the major loop. the edma goes idle or services the next channel. 9. second hardware, that is, edma peripheral, requests channel service. 10. the channel is selected by arbitration for servicing. 11. edma engine writes: tcd n _csr[done] = 0, tcd n _csr[start] = 0, tcd n _csr[active] = 1. 12. edma engine reads: channel tcd data from local memory to internal register file. 13. the source to destination transfers are executed as follows: a. read byte from location 0x1010, read byte from location 0x1011, read byte from 0x1012, read byte from 0x1013. b. write 32-bits to location 0x2010 first iteration of the minor loop. c. read byte from location 0x1014, read byte from location 0x1015, read byte from 0x1016, read byte from 0x1017. d. write 32-bits to location 0x2014 second iteration of the minor loop. e. read byte from location 0x1018, read byte from location 0x1019, read byte from 0x101a, read byte from 0x101b. f. write 32-bits to location 0x2018 third iteration of the minor loop. g. read byte from location 0x101c, read byte from location 0x101d, read byte from 0x101e, read byte from 0x101f. h. write 32-bits to location 0x201c last iteration of the minor loop major loop complete. 14. edma engine writes: tcd n _saddr = 0x1000, tcd n _daddr = 0x2000, tcd n _citer = 2 (tcd n _biter). chapter 21 direct memory access controller (edma) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 499 15. edma engine writes: tcd n _csr[active] = 0, tcd n _csr[done] = 1, int[n] = 1. 16. the channel retires major loop complete. the edma goes idle or services the next channel. 21.5.4.3 using the modulo feature the modulo feature of the edma provides the ability to implement a circular data queue in which the size of the queue is a power of 2. mod is a 5-bit field for the source and destination in the tcd, and it specifies which lower address bits increment from their original value after the address+offset calculation. all upper address bits remain the same as in the original value. a setting of 0 for this field disables the modulo feature. the following table shows how the transfer addresses are specified based on the setting of the mod field. here a circular buffer is created where the address wraps to the original value while the 28 upper address bits (0x1234567 x ) retain their original value. in this example the source address is set to 0x12345670, the offset is set to 4 bytes and the mod field is set to 4, allowing for a 2 4 byte (16-byte) size queue. table 21-298. modulo example transfer number address 1 0x12345670 2 0x12345674 3 0x12345678 4 0x1234567c 5 0x12345670 6 0x12345674 21.5.5 monitoring transfer descriptor status 21.5.5.1 testing for minor loop completion there are two methods to test for minor loop completion when using software initiated service requests. the first is to read the tcd n _citer field and test for a change. another method may be extracted from the sequence shown below. the second method is to test the tcd n _csr[start] bit and the tcd n _csr[active] bit. the minor-loop- initialization/application information k60 sub-family reference manual, rev. 6, nov 2011 500 freescale semiconductor, inc. complete condition is indicated by both bits reading zero after the tcd n _csr[start] was set. polling the tcd n _csr[active] bit may be inconclusive, because the active status may be missed if the channel execution is short in duration. the tcd status bits execute the following sequence for a software activated channel: stage tcd n r its tate r o hannel serice request ia sotware hannel is executin a hannel has colete the inor loo an is ile hannel has colete the aor loo an is ile the best method to test for minor-loop completion when using hardware, that is, peripheral, initiated service requests is to read the tcd n _citer field and test for a change. the hardware request and acknowledge handshake signals are not visible in the programmer's model. the tcd status bits execute the following sequence for a hardware-activated channel: stage tcd n r its tate r o hannel serice request ia harware eriheral request asserte hannel is executin a hannel has colete the inor loo an is ile hannel has colete the aor loo an is ile for both activation types, the major-loop-complete status is explicitly indicated via the tcd n _csr[done] bit. the tcd n _csr[start] bit is cleared automatically when the channel begins execution regardless of how the channel activates. 21.5.5.2 reading the transfer descriptors of active channels the edma reads back the true tcd n _saddr, tcd n _daddr, and tcd n _nbytes values if read while a channel executes. the true values of the saddr, daddr, and nbytes are the values the edma engine currently uses in its internal register file and not the values in the tcd local memory for that channel. the addresses, saddr and chapter 21 direct memory access controller (edma) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 501 daddr, and nbytes, decrements to zero as the transfer progresses, can give an indication of the progress of the transfer. all other values are read back from the tcd local memory. 21.5.5.3 checking channel preemption status preemption is available only when fixed arbitration is selected as the channel arbitration mode. a preemptive situation is one in which a preempt-enabled channel runs and a higher priority request becomes active. when the edma engine is not operating in fixed channel arbitration mode, the determination of the actively running relative priority outstanding requests become undefined. channel priorities are treated as equal, that is, constantly rotating, when round-robin arbitration mode is selected. the tcd n _csr[active] bit for the preempted channel remains asserted throughout the preemption. the preempted channel is temporarily suspended while the preempting channel executes one major loop iteration. if two tcd n _csr[active] bits are set simultaneously in the global tcd map, a higher priority channel is actively preempting a lower priority channel. 21.5.6 dynamic programming 21.5.6.1 dynamically changing the channel priority the following two options are recommended for dynamically changing channel priority levels: 1. switch to round-robin channel arbitration mode, change the channel priorities, then switch back to fixed arbitration mode, 2. disable all the channels, change the channel priorities, then enable the appropriate channels. 21.5.6.2 dynamically changing the channel linking and scatter/gather options dynamic channel linking and dynamic scatter/gather is the process of changing the tcd n _csr[major_e_link] or tcd n _csr[e_sg] bits during channel execution. these bits are read from the tcd local memory at the end of channel execution, therefore allowing software to enable either feature during channel execution. initialization/application information k60 sub-family reference manual, rev. 6, nov 2011 502 freescale semiconductor, inc. because software can change the configuration during execution, a coherency sequence must be followed. consider the scenario the user attempts to execute a dynamic channel link by enabling the tcd n _csr[major_e_link] bit as the edma engine retires the channel. the tcd n _csr[major_e_link] would be set in the programmer's model, but it would be indeterminate whether the actual link was made before the channel retired. the following coherency sequence is recommended when executing a dynamic channel link or dynamic scatter/gather request: 1. set the tcd n _csr[major_e_link] bit. 2. read back the tcd n _csr[major_e_link] bit. 3. test the tcd n _csr[major_e_link] request status. a. if the bit is set, the dynamic link attempt was successful. b. if the bit is cleared, the attempted dynamic link did not succeed, the channel was already retiring. this coherency model is true for dynamic scatter/gather operations. for both dynamic requests, the tcd local memory controller forces the tcd n _csr[major_e_link] and tcd n _csr[e_sg] bits to zero on any writes to a tcd n after the tcd n _csr[done] bit for that channel is set, indicating that the major loop is complete. note software must clear the tcd n _csr[done] bit before writing the tcd n _csr[major_e_link] or tcd n _csr[e_sg] bits. the tcd n _csr[done] bit is cleared automatically by the edma engine after a channel begins execution. chapter 21 direct memory access controller (edma) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 503 initialization/application information k60 sub-family reference manual, rev. 6, nov 2011 504 freescale semiconductor, inc. chapter 22 external watchdog monitor (ewm) 22.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the watchdog is generally used to monitor the flow and execution of embedded software within an mcu. the watchdog consists of a counter that if allowed to overflow, forces an internal reset (asynchronous) to all on-chip peripherals and optionally assert the reset pin to reset external devices/circuits. the overflow of the watchdog counter must not occur if the software code works well and services the watchdog to re-start the actual counter. for safety, a redundant watchdog system, external watchdog monitor (ewm), is designed to monitor external circuits, as well as the mcu software flow. this provides a back-up mechanism to the internal watchdog that resets the mcu's cpu and peripherals. the ewm differs from the internal watchdog in that it does not reset the mcu's cpu and peripherals. the ewm if allowed to time-out, provides an independent ewm_out pin that when asserted resets or places an external circuit into a safe mode. the cpu resets the ewm counter that is logically anded with an external digital input pin. this pin allows an external circuit to influence the reset_out signal. 22.1.1 features features of ewm module include: ? independent lpo clock source ? programmable time-out period specified in terms of number of ewm lpo clock cycles. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 505 ? windowed refresh option ? provides robust check that program flow is faster than expected. ? programmable window. ? refresh outside window leads to assertion of ewm_out. ? robust refresh mechanism ? write values of 0xb4 and 0x2c to ewm refresh register within 15 ( ewm_service_time ) peripheral bus clock cycles. ? one output port, ewm_out, when asserted is used to reset or place the external circuit into safe mode. ? one input port, ewm_in, allows an external circuit to control the ewm_out signal. 22.1.2 modes of operation this section describes the module's operating modes. 22.1.2.1 stop mode when the ewm is in stop mode, the cpu services to the ewm cannot occur. on entry to stop mode, the ewms counter freezes. there are two possible ways to exit from stop mode: ? on exit from stop mode through a reset, the ewm remains disabled. ? on exit from stop mode by an interrupt, the ewm is re-enabled, and the counter continues to be clocked from the same value prior to entry to stop mode. note the following if the ewm enters the stop mode during cpu service mechanism: at the exit from stop mode by an interrupt, refresh mechanism state machine starts from the previous state which means, if first service command is written correctly and ewm enters the stop mode immediately, the next command has to be written within the next 15 ( ewm_service_time ) peripheral bus clocks after exiting from stop mode. user must mask all interrupts prior to executing ewm service instructions. introduction k60 sub-family reference manual, rev. 6, nov 2011 506 freescale semiconductor, inc. 22.1.2.2 wait mode the ewm module treats the stop and wait modes as the same. ewm functionality remains the same in both of these modes. 22.1.2.3 debug mode entry to debug mode has no effect on the ewm. ? if the ewm is enabled prior to entry of debug mode, it remains enabled. ? if the ewm is disabled prior to entry of debug mode, it remains disabled. 22.1.3 block diagram this figure shows the ewm block diagram. clock gating cell ewm_out ewm out logic ewm_out or low power clock enable counter overflow cpu reset reset to counter ewm refresh ewm enable counter >compare high counter < compare low and ((ewm_in ^ assert_in) || ~ewm_in_enable) compare high > counter > compare low 1 1 figure 22-1. ewm block diagram chapter 22 external watchdog monitor (ewm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 507 22.2 ewm signal descriptions the ewm has two external signals, as shown in the following table. table 22-1. ewm signal descriptions signal description i/o ewm_in ewm input for safety status of external safety circuits. the polarity of ewm_in is programmable using the ctrl[assin] bit. the default polarity is active-low. i ewm_out ewm reset out signal o 22.3 memory map/register definition this section contains the module memory map and registers. ewm memory map absolute address (hex) register name width (in bits) access reset value section/ page 4006_1000 control register (ewm_ctrl) 8 r/w 00h 22.3.1/ 508 4006_1001 service register (ewm_serv) 8 w (always reads zero) 00h 22.3.2/ 509 4006_1002 compare low register (ewm_cmpl) 8 r/w 00h 22.3.3/ 510 4006_1003 compare high register (ewm_cmph) 8 r/w ffh 22.3.4/ 510 22.3.1 control register (ewm_ctrl) the ctrl register is cleared by any reset. note this register can be written only once after a cpu reset. writing this register more than once, generates a bus transfer error. ewm signal descriptions k60 sub-family reference manual, rev. 6, nov 2011 508 freescale semiconductor, inc. address: ewm_ctrl is 4006_1000h base + 0h offset = 4006_1000h bit 7 6 5 4 3 2 1 0 read 0 inen assin ewmen write reset 0 0 0 0 0 0 0 0 ewm_ctrl field descriptions field description 73 reserved this read-only field is reserved and always has the value zero. 2 inen input enable. this bit when set, enables the ewm_in port. 1 assin ewm_ins assertion state select. default assert state of the ewm_in signal is logic zero. setting assin bit inverts the assert state to a logic one. 0 ewmen ewm enable. this bit when set, enables the ewm module. this resets the ewm counter to zero and deasserts the ewm_out signal. clearing ewmen bit disables the ewm, and therefore it cannot be enabled until a reset occurs, due to the write-once nature of this bit. 22.3.2 service register (ewm_serv) the serv register provides the interface from the cpu to the ewm module. it is write- only and reads of this register return zero. address: ewm_serv is 4006_1000h base + 1h offset = 4006_1001h bit 7 6 5 4 3 2 1 0 read 0 write service reset 0 0 0 0 0 0 0 0 ewm_serv field descriptions field description 7?0 service the ewm service mechanism requires the cpu to write two values to the serv register: a first data byte of 0xb4, followed by a second data byte of 0x2c. the ewm service is illegal if either of the following conditions is true. the first or second data byte is not written correctly. the second data byte is not written within a fixed number of peripheral bus cycles of the first data byte. this fixed number of cycles is called ewm_service_time . chapter 22 external watchdog monitor ewm 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 0 22.3.3 compare low register (ewm_cmpl) the cmpl register is reset to zero after a cpu reset. this provides no minimum time for the cpu to service the ewm counter. note this register can be written only once after a cpu reset. writing this register more than once generates a bus transfer error. address: ewm_cmpl is 4006_1000h base + 2h offset = 4006_1002h bit 7 6 5 4 3 2 1 0 read comparel write reset 0 0 0 0 0 0 0 0 ewm_cmpl field descriptions field description 7?0 comparel to prevent runaway code from changing this field, software should write to this field after a cpu reset even if the (default) minimum service time is required. 22.3.4 compare high register (ewm_cmph) the cmph register is reset to 0xff after a cpu reset. this provides a maximum of 256 clocks time, for the cpu to service the ewm counter. note this register can be written only once after a cpu reset. writing this register more than once generates a bus transfer error. note the valid values for cmph are up to 0xfe because the ewm counter never expires when cmph = 0xff. the expiration happens only if ewm counter is greater than cmph. address: ewm_cmph is 4006_1000h base + 3h offset = 4006_1003h bit 7 6 5 4 3 2 1 0 read compareh write reset 1 1 1 1 1 1 1 1 memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 510 freescale semiconductor, inc. ewm_cmph field descriptions field description 70 compareh to prevent runaway code from changing this field, software should write to this field after a cpu reset even if the (default) maximum service time is required. 22.4 functional description the following sections describe functional details of the ewm module. 22.4.1 the ewm_out signal the ewm_out is a digital output signal used to gate an external circuit (application specific) that controls critical safety functions. for example, the ewm_out could be connected to the high voltage transistors circuits that control an ac motor in a large appliance. the ewm_out signal remains deasserted when the ewm is being regularly serviced by the cpu within the programmable service window, indicating that the application code is executed as expected. the ewm_out signal is asserted in any of the following conditions: ? servicing the ewm when the counter value is less than cmpl value. ? if the ewm counter value reaches the cmph value, and no ewm service has occurred. ? servicing the ewm when the counter value is more than cmpl and less than cmph values and ewm_in signal is asserted. ? after any reset (by the virtue of the external pull-down mechanism on the ewm_out pin) on a normal reset, the ewm_out is asserted. to deassert the ewm_out, set ewmen bit in the ctrl register to enable the ewm. if the ewm_out signal shares its pad with a digital i/o pin, on reset this actual pad defers to being an input signal. it takes the ewm_out output condition only after you enable the ewm by the ewmen bit in the ctrl register. when the ewm_out pin is asserted, it can only be deasserted by forcing a mcu reset. chapter 22 external watchdog monitor (ewm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 511 note ewm_out pad must be in pull down state when ewm functionality is used and when ewm is under reset. 22.4.2 the ewm_in signal the ewm_in is a digital input signal that allows an external circuit to control the ewm_out signal. for example, in the application, an external circuit monitors a critical safety function, and if there is fault with this circuit's behavior, it can then actively initiate the ewm_out signal that controls the gating circuit. the ewm_in signal is ignored if the ewm is disabled, or if inen bit of ctrl register is cleared, as after any reset. on enabling the ewm (setting the ctrl[ewmen] bit) and enabling ewm_in functionality (setting the ctrl[inen] bit), the ewm_in signal must be in the deasserted state prior to the cpu servicing the ewm. this ensures that the ewm_out stays in the deasserted state; otherwise, the ewm_out pin is asserted. note you must update the cmph and cmpl registers prior to enabling the ewm. after enabling the ewm, the counter resets to zero, therefore providing a reasonable time after a power-on reset for the external monitoring circuit to stabilize and ensure that the ewm_in pin is deasserted. 22.4.3 ewm counter it is an 8-bit ripple counter fed from a clock source that is independent of the peripheral bus clock source. as the preferred time-out is between 1 ms and 100 ms the actual clock source should be in the khz range. the counter is reset to zero, after a cpu reset, or a ewm refresh cycle. the counter value is not accessible to the cpu. 22.4.4 ewm compare registers the compare registers cmpl and cmph are write-once after a cpu reset and cannot be modified until another cpu reset occurs. functional description k60 sub-family reference manual, rev. 6, nov 2011 512 freescale semiconductor, inc. the ewm compare registers are used to create a service window, which is used by the cpu to service/refresh the ewm module. ? if the cpu services the ewm when the counter value lies between cmpl value and cmph value, the counter is reset to zero. this is a legal service operation. ? if the cpu executes a ewm service/refresh action outside the legal service window, ewm_out is asserted. it is illegal to program cmpl and cmph with same value. in this case, as soon as counter reaches (cmpl + 1), ewm_out is asserted. 22.4.5 ewm refresh mechanism other than the initial configuration of the ewm, the cpu can only access the ewm by the ewm service register. the cpu must access the ewm service register with correct write of unique data within the windowed time frame as determined by the cmpl and cmph registers. therefore, three possible conditions can occur: table 22-7. ewm refresh mechanisms condition mechanism a unique ewm service occurs when cmpl < counter < cmph. the software behaves as expected and the counter of the ewm is reset to zero, and ewm_out pin remains in the deasserted state. note: ewm_in pin is also assumed to be in the deasserted state. a unique ewm service occurs when counter < cmpl the software services the ewm and therefore resets the counter to zero and asserts the ewm_out pin (irrespective of the ewm_in pin). the ewm_out pin is expected to gate critical safety circuits. counter value reaches cmph prior to a unique ewm service the counter value reaches the cmph value and no service of the ewm resets the counter to zero and assert the ewm_out pin (irrespective of the ewm_in pin). the ewm_out pin is expected to gate critical safety circuits. any illegal service on ewm has no effect on ewm_out. chapter 22 external watchdog monitor (ewm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 513 functional description k60 sub-family reference manual, rev. 6, nov 2011 514 freescale semiconductor, inc. chapter 23 watchdog timer (wdog) 23.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the watchdog timer (wdog) keeps a watch on the system functioning and resets it in case of its failure. some reasons for such failures are: run-away software code and the stoppage of the system clock that in a safety critical system can lead to serious consequences. in such cases, the watchdog brings the system into a safe state of operation. the watchdog monitors the operation of the system by expecting periodic communication from the software, generally known as servicing or refreshing the watchdog. if this periodic refreshing does not occur, the watchdog resets the system. 23.2 features the features of the watchdog timer (wdog) include: ? independent clock source input (independent from cpu/bus clock). choice between two clock sources: ? lpo oscillator ? external system clock ? unlock sequence for allowing updates to write-once wdog control/configuration bits. ? all wdog control/configuration bits are writable once only within 256 bus clock cycles of being unlocked. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 515 ? you need to always update these bits after unlocking within 256 bus clock cycles. failure to update these bits, resets the system. ? programmable time-out period specified in terms of number of wdog clock cycles. ? ability to test wdog timer and reset with a flag indicating watchdog test. ? quick testsmall time-out value programmed for quick test. ? byte testindividual bytes of timer tested one at a time. ? read-only access to the wdog timerallows dynamic check that wdog timer is operational. note reading the watchdog timer counter while running the watchdog on the bus clock might not give the accurate counter value. ? windowed refresh option ? provides robust check that program flow is faster than expected. ? programmable window. ? refresh outside window leads to reset. ? robust refresh mechanism ? write values of 0xa602 and 0xb480 to wdog refresh register within 20 bus clock cycles. ? count of wdog resets as they occur. ? configurable interrupt on time-out to provide debug breadcrumbs. this is followed by a reset after 256 bus clock cycles. features k60 sub-family reference manual, rev. 6, nov 2011 516 freescale semiconductor, inc. 23.3 functional overview 0xc520 0xd928 fast fn test clock allow update for n bus clk cycles n bus clk cycles lpo standbyen n bus clk cycles refresh sequence 2 writes of data within k bus clock cycles of each other unlock sequence 2 writes of data within k bus clock cycles of each other disable control/configuration bit changes n bus clk cycles after unlocking wdogen = wdog enable winen = windowed mode enable wdogt = wdog time-out value wdogclksrc = wdog clock source wdog test = wdog test mode wait en = enable in wait mode stop en = enable in stop mode standby en = enable in standby mode debug en = enable in debug mode srs = system reset status register r = timer reload wdog reset count alt clock osc wdog clock selection wdog clk r system reset and srs register interrupt irq_rst_ en = = 1? invalid unlock seq 32-bit timer timer time-out refresh outside window invalid refresh seq no config after unlocking no unlock after reset 0xb480 0xa602 system bus clock 32-bit modulus reg (time-out value) debugen window_begin wdogtest stopen waiten wdogt wdog clksrc winen wdogen wdog y n figure 23-1. wdog operation the preceding figure shows the operation of the watchdog. the values for n and k are: ? n = 256 ? k = 20 the watchdog is a fail safe mechanism that brings the system into a known initial state in case of its failure due to cpu clock stopping or a run away condition in code execution. in its simplest form, the watchdog timer runs continuously off a clock source and expects chapter 23 watchdog timer (wdog) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 517 to be serviced periodically, failing which it resets the system. this ensures that the software is executing correctly and has not run away in an unintended direction. software can adjust the period of servicing or the time-out value for the watchdog timer to meet the needs of the application. you can select a windowed mode of operation that expects the servicing to be done only in a particular window of the time-out period. an attempted servicing of the watchdog outside this window results in a reset. by operating in this mode, you can get an indication of whether the code is running faster than expected. the window length is also user programmable. if a system fails to update/refresh the watchdog due to an unknown and persistent cause, it will be caught in an endless cycle of resets from the watchdog. to analyze the cause of such conditions, you can program the watchdog to first issue an interrupt, followed a little later by a reset. in the interrupt service routine, the software can analyze the system stack to aid debugging. to enhance the independence of watchdog from the system, it runs off an independent lpo oscillator clock. you can also switch over to an alternate clock source if required, through a control register bit. 23.3.1 unlocking and updating the watchdog you can unlock the write-once-only control and configuration registers for updating them. as a pre-condition, the allow_update bit in the watchdog control register must be set. the actual unlock is accomplished by writing 0xc520 followed by 0xd928 within 20 bus clock cycles to a specific unlock register (wdog_unlock). this opens up an update window equal in length to the watchdog configuration time (wct) within which you can update the configuration and control register bits. you can not update registers on the bus clock cycle immediately following the write of the unlock sequence, but one cycle later. these register bits can be modified only once after unlocking. if none of the configuration and control registers is updated within the update window, the watchdog issues a reset (or interrupt-then-reset) to the system. trying to unlock the watchdog within the wct time after an initial unlock, has no effect. during the update operation, the watchdog timer is not paused and keeps running in the background. after the update window closes, the watchdog timer restarts and the watchdog functions as per the new configuration. functional overview k60 sub-family reference manual, rev. 6, nov 2011 518 freescale semiconductor, inc. the update feature is useful for applications that have an initial, non-safety critical part, where the watchdog is kept disabled or with a conveniently long time-out period. this means the application coder does not have to bother with frequently servicing the watchdog. after the critical part of the application begins, the watchdog can be reconfigured as per need. the watchdog issues a reset (or interrupt-then-reset if enabled) to the system for any of these invalid unlock sequences: ? you write any value other than 0xc520 or 0xd928 to the unlock register. ? allow_update is set and you allow a gap of more than 20 bus clock cycles between the writing of the unlock sequence values. also, an attempted refresh operation between the two writes of the unlock sequence and in the wct time following a successful unlock, goes undetected. also, see watchdog operation with 8-bit access for guidelines related to 8-bit accesses to the unlock register. note a context switch during unlocking and refreshing may lead to a watchdog reset. 23.3.2 the watchdog configuration time (wct) to prevent unintended modification of the watchdog's control and configuration register bits, you are allowed to update them only within a period of 256 bus clock cycles after unlocking. this window period is known as the watchdog configuration time (wct). in addition, these register bits can be modified only once after unlocking them for editing (even after reset). you must unlock the registers within wct time after system reset, failing which the wdog issues a reset to the system. to be more precise, you must write at least the first word of the unlocking sequence within the wct time after reset. once this is done, you get a further 20 bus clock cycles (the maximum allowed gap between the words of the unlock sequence) to complete the unlocking operation. thereafter, to make sure that you do not forget to configure the watchdog, the watchdog issues a reset if none of the wdog control and configuration registers is updated in the wct time after unlock. after the close of this window or after the first write, these register bits are locked out from any further changes. the watchdog timer keeps running as per its default configuration through unlocking and update operations that can extend up to a maximum total of 2xwct time + 20 bus clock cycles. therefore, it must be ensured that the time-out value for the watchdog is always greater than 2xwct time + 20 bus clock cycles. chapter 23 watchdog timer (wdog) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 519 updates in the writeConce registers take effect only after the wct window closes with the following exceptions for which changes take effect immediately: ? the stop, wait, and debug mode enable bits ? the standby mode enable bit ? the irq_rst_en bit the operations of refreshing the watchdog goes undetected during the wct. 23.3.3 refreshing the watchdog a robust refreshing mechanism has been chosen for the watchdog. a valid refresh is a write of 0xa602 followed by 0xb480 within 20 bus clock cycles to watchdog refresh register. if these two values are written more than 20 bus cycles apart or if something other than these two values is written to the register, a watchdog reset (or interrupt-then- reset if enabled) is issued to the system. a valid refresh makes the watchdog timer restart on the next bus clock. also, an attempted unlock operation, in between the two writes of the refresh sequence goes undetected. see watchdog operation with 8-bit access for guidelines related to 8-bit accesses to the refresh register. 23.3.4 windowed mode of operation in this mode of operation a restriction is placed on the point in time within the time-out period at which the watchdog can be refreshed. the refresh is considered valid only when the watchdog timer increments beyond a certain count as specified by the watchdog window register. this is known as refreshing the watchdog within a window of the total time-out period. if a refresh is attempted before the timer reaches the window value, the watchdog generates a reset (or interrupt-then-reset if enabled). of course, if there is no refresh at all, the watchdog times out and generates a reset or interrupt-then-reset if enabled. 23.3.5 watchdog disabled mode of operation when the watchdog is disabled through the wdog_en bit in the watchdog status and control register, the watchdog timer is reset to zero and is disabled from counting until you enable it or it is again enabled by the system reset. in this mode the watchdog timer cannot be refreshed (there is no requirement to do so while the timer is disabled). however, the watchdog still generates a reset (or interrupt-then-reset if enabled) on a functional overview k60 sub-family reference manual, rev. 6, nov 2011 520 freescale semiconductor, inc. non-time-out exception (see generated resets and interrupts ). you need to unlock the watchdog before enabling it. a system reset brings the watchdog out of the disabled mode. 23.3.6 low power modes of operation ? in wait mode, if the wdog is enabled (wait_en = 1), it can run on bus clock or low power oscillator clock (clk_src = x) to generate interrupt (irq_rst_en=1) followed by a reset on time-out. after reset the wdog reset counter increments by one. ? in stop mode where the bus clock is gated, the wdog can run only on low power oscillator clock (clk_src=0) if it is enabled in stop (stop_en=1). in this case, the wdog runs to time-out twice, and then generates a reset from its backup circuitry. therefore, if you program the watchdog to time-out after 100 ms and then enter such a stop mode, the reset will occur after 200 ms. also, in this case no interrupt will be generated irrespective of the value of irq_rst_en bit. after wdog reset, the wdog reset counter will also not increment. ? in power-down mode, the watchdog is powered off. 23.3.7 debug modes of operation you can program the watchdog to disable in debug modes (through dbg_en bit in the watchdog control register). this results in the watchdog timer pausing for the duration of the mode. register read/writes are still allowed, which means that operations like: refresh, unlock etc. are allowed. on exit from the mode, the timer resumes its operation from the point of pausing. the entry of the system into the debug mode does not excuse it from compulsorily configuring the watchdog in the wct time after unlock (unless the system bus clock is gated off, in which case the internal state machine pauses too). failing to do so still results in a reset (or interrupt-then-reset, if enabled) to the system. also, all the exception conditions that result in a reset to the system (see generated resets and interrupts ) are still valid in this mode. so, if an exception condition occurs and the system bus clock is on, a reset occurs (or interrupt-then-reset, if enabled). chapter 23 watchdog timer (wdog) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 521 the entry into debug mode within wct time after reset is treated differently. the wdog timer is kept reset to zero and there is no need to unlock and configure it within wct time. you must not try to refresh or unlock the wdog in this state or unknown behavior may result. upon exit from this mode, the wdog timer restarts and the wdog has to be unlocked and configured within wct time. 23.4 testing the watchdog for iec 60730 and other safety standards, the expectation is that anything that monitors a safety function must be tested and this test is required to be fault tolerant. to test the watchdog, its main timer and its associated compare and reset logic must be tested. towards this end, two tests are implemented for the watchdog that are described in quick test and byte test . while there is a control bit provided to put the watchdog into the test mode (functional), there is an overriding test-disable control bit which once set, disables the test mode permanently until reset. for running a particular test, first select that test. thereafter, set a certain test mode bit to put the watchdog in the functional test mode. setting this bit automatically switches the watchdog timer to a fast clock source. the switching of the clock source is done to achieve a faster time-out and hence a faster test. in a successful test, the timer times out after reaching the programmed time-out value and generates a system reset. note after emerging from a reset due to a watchdog test, you must follow the mandatory steps of unlocking and configuring the watchdog. the refresh and unlock operations and interrupt are not automatically disabled in the test mode. 23.4.1 quick test in this test the time-out value of watchdog timer is programmed to a very low value to achieve quick time-out. the only difference between the quick test and the normal mode of functioning of the watchdog is that the test mode bit is set for the quick test. this allows quick test of the watchdog reset mechanism. testing the watchdog k60 sub-family reference manual, rev. 6, nov 2011 522 freescale semiconductor, inc. 23.4.2 byte test the byte test implements more thorough a test of the watchdog timer. in this test, the timer is split up into its constituent byte-wide stages that are run independently and tested for time-out against the corresponding byte of the time-out value register. the following figure explains the splitting concept: clk wdog en mod = = timer? test 32-bit timer modulus register (time-out value) wdog reset nth stage overflow enables n + 1th stage en en reset value (hardwired) byte stage 4 equality comparison byte 4 byte 2 byte 1 byte 3 byte stage 3 byte stage 2 byte stage 1 figure 23-2. watchdog timer byte splitting each stage is an 8-bit synchronous counter followed by combinational logic that generates an overflow signal. the overflow signal acts as an enable to the n + 1th stage. in the test mode, when an individual byte, n, is tested, byte n C 1 is loaded forcefully with 0xff, and both these bytes are allowed to run off the clock source. by doing so the overflow signal from stage n C 1 is generated immediately, enabling counter stage n. the nth stage runs and compares with the nth byte of the time-out value register. in this way, the byte n is also tested along with the link between it and the preceding stage. no other stages, n C 2, n C 3... and n + 1, n + 2... are enabled for the test on byte n. these disabled stages (except the most significant stage of the counter) are loaded with a value of 0xff. these two testing schemes achieve the overall aim of testing the counter functioning and the compare and reset logic. chapter 23 watchdog timer (wdog) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 523 note do not enable the watchdog interrupt during these tests. if required, you must ensure that the effective time-out value is greater than wct time. see generated resets and interrupts for more details. 23.5 backup reset generator the backup reset generator generates the final reset which goes out to the system. it has a backup mechanism which takes care that in case the bus clock stops and prevents the main state machine from generating a reset exception/interrupt, the watchdog timer's time-out is separately routed out as a reset to the system. two successive timer time-outs without an intervening system reset result in the backup reset generator routing out the time-out signal as a reset to the system. 23.6 generated resets and interrupts the watchdog generates a reset on the following events (referred to as exceptions at some places in this document): ? a watchdog time-out. ? failure to unlock the watchdog within wct time after system reset deassertion. ? no update of the control and configuration registers within the wct window after unlocking. at least one of the following registers must be written to within the wct window to avoid reset: ? wdog_st_ctrl_h, wdog_st_ctrl_l ? wdog_to_val_h, wdog_to_val_l ? wdog_win_h, wdog_win_l ? wdog_prescaler ? a value other than the unlock sequence or the refresh sequence is written to the unlock and/or refresh registers, respectively. backup reset generator k60 sub-family reference manual, rev. 6, nov 2011 524 freescale semiconductor, inc. ? a gap of more than 20 bus cycles exists between the writes of two values of the unlock sequence. ? a gap of more than 20 bus cycles exists between the writes of two values of the refresh sequence. the watchdog can also generate an interrupt. if irq_rst_en is set, then on the above mentioned events wdog_st_ctrl_l[int_flg] is set, generating an interrupt. a watchdog reset is also generated wct time later to ensure the watchdog is fault tolerant. the interrupt can be cleared by writing 1 to int_flg. the gap of wct time between interrupt and reset means that the wdog time-out value must be greater than wct. otherwise, if the interrupt was generated due to a time-out, a second consecutive time-out will occur in that wct gap. this will trigger the backup reset generator to generate a reset to the system, prematurely ending the interrupt service routine execution. also, the jobs like counting the number of watchdog resets would not be done. 23.7 memory map and register definition this section consists of the memory map and register descriptions. wdog memory map absolute address (hex) register name width (in bits) access reset value section/ page 4005_2000 watchdog status and control register high (wdog_stctrlh) 16 r/w 01d3h 23.7.1/ 526 4005_2002 watchdog status and control register low (wdog_stctrll) 16 r/w 0001h 23.7.2/ 528 4005_2004 watchdog time-out value register high (wdog_tovalh) 16 r/w 004ch 23.7.3/ 528 4005_2006 watchdog time-out value register low (wdog_tovall) 16 r/w 4b4ch 23.7.4/ 529 4005_2008 watchdog window register high (wdog_winh) 16 r/w 0000h 23.7.5/ 529 4005_200a watchdog window register low (wdog_winl) 16 r/w 0010h 23.7.6/ 530 4005_200c watchdog refresh register (wdog_refresh) 16 r/w b480h 23.7.7/ 530 table continues on the next page... chapter 2 watchdog timer wd 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 2 wdog memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4005_200e watchdog unlock register (wdog_unlock) 16 r/w d928h 23.7.8/ 530 4005_2010 watchdog timer output register high (wdog_tmrouth) 16 r/w 0000h 23.7.9/ 531 4005_2012 watchdog timer output register low (wdog_tmroutl) 16 r/w 0000h 23.7.10/ 531 4005_2014 watchdog reset count register (wdog_rstcnt) 16 r/w 0000h 23.7.11/ 532 4005_2016 watchdog prescaler register (wdog_presc) 16 r/w 0400h 23.7.12/ 532 23.7.1 watchdog status and control register high (wdog_stctrlh) address: wdog_stctrlh is 4005_2000h base + 0h offset = 4005_2000h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 distestwdog bytesel[1:0] testsel testwdog 0 stndbyen waiten stopen dbgen allowupdate winen irqrsten clksrc wdogen write reset 0 0 0 0 0 0 0 1 1 1 0 1 0 0 1 1 wdog_stctrlh field descriptions field description 15 reserved this read-only field is reserved and always has the value zero. 14 distestwdog allows the wdog?s functional test mode to be disabled permanently. once set, it can only be cleared by a reset. it cannot be unlocked for editing once it is set. 0 wdog functional test mode is not disabled. 1 wdog functional test mode is disabled permanently until reset. 1312 bytesel[1:0] this 2-bit field select the byte to be tested when the watchdog is in the byte test mode. 00 byte 0 selected 01 byte 1 selected 10 byte 2 selected 11 byte 3 selected 11 testsel selects the test to be run on the watchdog timer. effective only if testwdog is set. table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 26 freescale semiconductor, inc. wdog_stctrlh field descriptions (continued) field description 0 quick test. the timer runs in normal operation. you can load a small time-out value to do a quick test. 1 byte test. puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value. select the byte through bytesel[1:0] for testing. 10 testwdog puts the watchdog in the functional test mode. in this mode the watchdog timer and the associated compare and reset generation logic is tested for correct operation. the clock for the timer is switched from the main watchdog clock to the fast clock input for watchdog functional test. the testsel bit selects the test to be run. 9 reserved this read-only field is reserved and always has the value zero. 8 stndbyen enables or disables wdog in standby mode. 0 wdog is disabled in system standby mode. 1 wdog is enabled in system standby mode. 7 waiten enables or disables wdog in wait mode. 0 wdog is disabled in cpu wait mode. 1 wdog is enabled in cpu wait mode. 6 stopen enables or disables wdog in stop mode. 0 wdog is disabled in cpu stop mode. 1 wdog is enabled in cpu stop mode. 5 dbgen enables or disables wdog in debug mode. 0 wdog is disabled in cpu debug mode. 1 wdog is enabled in cpu debug mode. 4 allowupdate enables updates to watchdog write once registers, after initial configuration window (wct) closes, through unlock sequence. 0 no further updates allowed to wdog write once registers. 1 wdog write once registers can be unlocked for updating. 3 winen enable windowing mode. 0 windowing mode is disabled. 1 windowing mode is enabled. 2 irqrsten used to enable the debug breadcrumbs feature. a change in this bit is updated immediately, as opposed to updating after wct. 0 wdog time-out generates reset only. 1 wdog time-out initially generates an interrupt. after wct time, it generates a reset. 1 clksrc selects clock source for the wdog timer and other internal timing operations. 0 dedicated clock source selected as wdog clock (lpo oscillator). 1 wdog clock sourced from alternate clock source. 0 wdogen enables or disables the wdog?s operation. in the disabled state, the watchdog timer is kept in the reset state, but the other exception conditions can still trigger a reset/interrupt. a change in the value of this bit must be held for more than one wdog_clk cycle for the wdog to be enabled or disabled. table continues on the next page... chapter 2 watchdog timer wd 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 27 wdog_stctrlh field descriptions (continued) field description 0 wdog is disabled. 1 wdog is enabled. 23.7.2 watchdog status and control register low (wdog_stctrll) address: wdog_stctrll is 4005_2000h base + 2h offset = 4005_2002h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read intflg reserved write reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wdog_stctrll field descriptions field description 15 intflg interrupt flag. it is set when an exception occurs. irqrsten = 1 is a precondition to set this flag. intflg = 1 results in an interrupt being issued followed by a reset, wct time later. the interrupt can be cleared by writing 1 to this bit. it also gets cleared on a system reset. 140 reserved this field is reserved. note: do not modify this bitfield value. 23.7.3 watchdog time-out value register high (wdog_tovalh) address: wdog_tovalh is 4005_2000h base + 4h offset = 4005_2004h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read tovalhigh write reset 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 wdog_tovalh field descriptions field description 150 tovalhigh defines the upper 16 bits of the 32-bit time-out value for the watchdog timer. it is defined in terms of cycles of the watchdog clock. memory map and register definition k60 sub-family reference manual, rev. 6, nov 2011 528 freescale semiconductor, inc. 23.7.4 watchdog time-out value register low (wdog_tovall) the time-out value of the watchdog must be set to a minimum of four watchdog clock cycles. this is to take into account the delay in new settings taking effect in the watchdog clock domain. address: wdog_tovall is 4005_2000h base + 6h offset = 4005_2006h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read tovallow write reset 0 1 0 0 1 0 1 1 0 1 0 0 1 1 0 0 wdog_tovall field descriptions field description 15?0 tovallow defines the lower 16 bits of the 32-bit time-out value for the watchdog timer. it is defined in terms of cycles of the watchdog clock. 23.7.5 watchdog window register high (wdog_winh) you must set the window register value lower than the time-out value register. address: wdog_winh is 4005_2000h base + 8h offset = 4005_2008h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read winhigh write reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 wdog_winh field descriptions field description 15?0 winhigh defines the upper 16 bits of the 32-bit window for the windowed mode of operation of the watchdog. it is defined in terms of cycles of the watchdog clock. in this mode the watchdog can be refreshed only when the timer has reached a value greater than or equal to this window length. a refresh outside this window resets the system or if irqrsten is set, it interrupts and then resets the system. chapter 23 watchdog timer (wdog) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 529 23.7.6 watchdog window register low (wdog_winl) you must set the window register value lower than the time-out value register. address: wdog_winl is 4005_2000h base + ah offset = 4005_200ah bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read winlow write reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 wdog_winl field descriptions field description 15?0 winlow defines the lower 16 bits of the 32-bit window for the windowed mode of operation of the watchdog. it is defined in terms of cycles of the pre-scaled watchdog clock. in this mode, the watchdog can be refreshed only when the timer reaches a value greater than or equal to this window length value. a refresh outside this window resets the system or if irqrsten is set, it interrupts and then resets the system. 23.7.7 watchdog refresh register (wdog_refresh) address: wdog_refresh is 4005_2000h base + ch offset = 4005_200ch bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read wdogrefresh write reset 1 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 wdog_refresh field descriptions field description 15?0 wdogrefres h watchdog refresh register. a sequence of 0xa602 followed by 0xb480 within 20 bus clock cycles when written to this register, refreshes the wdog and prevents it from resetting the system. writing a value other than the above mentioned sequence or if the sequence is longer than 20 bus cycles, resets the system or if irqrsten is set, it interrupts and then resets the system). 23.7.8 watchdog unlock register (wdog_unlock) address: wdog_unlock is 4005_2000h base + eh offset = 4005_200eh bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read wdogunlock write reset 1 1 0 1 1 0 0 1 0 0 1 0 1 0 0 0 memory map and register definition k60 sub-family reference manual, rev. 6, nov 2011 530 freescale semiconductor, inc. wdog_unlock field descriptions field description 150 wdogunlock you can write the unlock sequence values to this register to make the watchdog write once registers writable again. the required unlock sequence is 0xc520 followed by 0xd928 within 20 bus clock cycles. a valid unlock sequence opens up a window equal in length to the wct within which you can update the registers. writing a value other than the above mentioned sequence or if the sequence is longer than 20 bus cycles, resets the system or if irqrsten is set, it interrupts and then resets the system). the unlock sequence is effective only if allowupdate is set. 23.7.9 watchdog timer output register high (wdog_tmrouth) address: wdog_tmrouth is 4005_2000h base + 10h offset = 4005_2010h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read timerouthigh write reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 wdog_tmrouth field descriptions field description 150 timerouthigh shows the value of the upper 16 bits of the watchdog timer. 23.7.10 watchdog timer output register low (wdog_tmroutl) during stop mode, the wdog_timer_out will be caught at the pre-stop value of the watchdog timer. after exiting stop mode, a maximum delay of 1 wdog_clk cycle + 3 bus clock cycles will occur before the wdog_timer_out starts following the watchdog timer. address: wdog_tmroutl is 4005_2000h base + 12h offset = 4005_2012h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read timeroutlow write reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 wdog_tmroutl field descriptions field description 15?0 timeroutlow shows the value of the lower 16 bits of the watchdog timer. chapter 23 watchdog timer (wdog) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 531 23.7.11 watchdog reset count register (wdog_rstcnt) address: wdog_rstcnt is 4005_2000h base + 14h offset = 4005_2014h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read rstcnt write reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 wdog_rstcnt field descriptions field description 150 rstcnt counts the number of times the watchdog resets the system. this register is reset only on a por. writing 1 to the bit to be cleared, enables you to clear the contents of this register. 23.7.12 watchdog prescaler register (wdog_presc) address: wdog_presc is 4005_2000h base + 16h offset = 4005_2016h bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 prescval 0 write reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 wdog_presc field descriptions field description 1511 reserved this read-only field is reserved and always has the value zero. 108 prescval 3-bit prescaler for the watchdog clock source. a value of zero indicates no division of the input wdog clock. the watchdog clock is divided by (prescval + 1) to provide the prescaled wdog_clk. 70 reserved this read-only field is reserved and always has the value zero. 23.8 watchdog operation with 8-bit access this section discusses 8-bit access considerations. watchdog operation with 8-bit access k60 sub-family reference manual, rev. 6, nov 2011 532 freescale semiconductor, inc. 23.8.1 general guideline when performing 8-bit accesses to the watchdog's 16-bit registers where the intention is to access both the bytes of a register, you must try to place the two 8-bit accesses one after the other in your code. 23.8.2 refresh and unlock operations with 8-bit access one exception condition that generates a reset to the system, is the write of any value other than those required for a legal refresh/update sequence to the respective refresh and unlock registers. for an 8-bit access to these registers, writing a correct value requires at least two bus clock cycles that means there is an invalid value in the registers for one cycle. therefore, the system is reset even if the intention is to write a correct value to the refresh/unlock register. keeping this in mind the exception condition for 8-bit accesses is slightly modified. whereas the match for a correct value for a refresh/unlock sequence is as per the original definition, the match for an incorrect value is done byte-wise on the refresh/ unlock rather than for the whole 16-bit value. this means that if the high byte of the refresh/unlock register contains any value other than high bytes of the two values making up the sequence, it is treated as an exception condition, leading to a reset or interrupt- then-reset. the same holds true for the lower byte of the refresh or unlock register. let us take the refresh operation that expects a write of 0xa602 followed by 0xb480 to the refresh register, as an example. table 23-14. refresh for 8-bit access wdog_refresh[15:8] wdog_refresh[7:0] sequence value1 or value2 match mismatch exception current value 0xb4 0x80 value2 match no write 1 0xb4 0x02 no match no write 2 0xa6 0x02 value1 match no write 3 0xb4 0x02 no match no write 4 0xb4 0x80 value2 match. sequence complete. no write 5 0x02 0x80 no match yes as shown in the preceding table, the refresh register holds its reset value initially. thereafter, two 8-bit accesses are performed on the register to write the first value of the refresh sequence. no mismatch exception is registered on the intermediate write, write1. the sequence is completed by performing two more 8-bit accesses, writing in the second value of the sequence for a successful refresh. it must be noted that the match of value2 chapter 23 watchdog timer (wdog) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 533 takes place only when the complete 16-bit value is correctly written, write4. hence, the requirement of writing value2 of the sequence within 20 bus clock cycles of value1 is checked by measuring the gap between write2 and write4. it is reiterated that the condition for matching values 1 and 2 of the refresh or unlock sequence remains unchanged. it is just the criterion for detecting a wrong value in these registers which has been relaxed, as explained, for 8-bit accesses. any 16-bit access still needs to adhere to the original guidelines, mentioned in the sections refreshing the watchdog . 23.9 restrictions on watchdog operation this section mentions some exceptions to the watchdog operation that may not be apparent to you. ? restriction on unlock / refresh operationsin the period between the closure of the wct window (after unlock) and the actual reload of the watchdog timer, unlock and refresh operations need not be attempted. ? the update and reload of the watchdog timer happens two to three watchdog clocks after wct window closes, following a successful configuration on unlock. ? clock switching delaythe watchdog uses glitch free multiplexers at two places C one to choose between the lpo oscillator input and alternate clock input and the other to choose between the watchdog functional clock and fast clock input for watchdog functional test. a maximum time period of ~ 2 clock a cycles plus ~2 clock b cycles elapses from the time a switch is requested to the occurrence of the actual clock switch (clock a and b are the two input clocks to the clock mux). ? for the windowed mode, there is a two to three bus clock latency between the watchdog counter going past the window value and the same registering in the bus clock domain. ? for proper operation of the watchdog, the watchdog clock must be at least five times slower than the system bus clock at all times. an exception is the case when the watchdog clock is synchronous to the bus clock wherein the watchdog clock can be as fast as the bus clock. ? wct must be equivalent to at least three watchdog clock cycles. if not ensured, this means that even after the close of the wct window, you have to wait for the synchronized system reset to deassert in the watchdog clock domain, before expecting the configuration updates to take effect. restrictions on watchdog operation k60 sub-family reference manual, rev. 6, nov 2011 534 freescale semiconductor, inc. ? the time-out value of the watchdog should be set to a minimum of four watchdog clock cycles. this is to take into account the delay in new settings taking effect in the watchdog clock domain. ? you must take care not only to refresh the watchdog within the watchdog timer's actual time-out period, but also provide enough allowance for the time it takes for the refresh sequence to be detected by the watchdog timer, on the watchdog clock. ? updates cannot be made in the bus clock cycle immediately following the write of the unlock sequence, but one bus clock cycle later. ? it should be ensured that the time-out value for the watchdog is always greater than 2xwct time + 20 bus clock cycles. ? an attempted refresh operation, in between the two writes of the unlock sequence and in the wct time following a successful unlock, will go undetected. ? trying to unlock the watchdog within the wct time after an initial unlock has no effect. ? the refresh and unlock operations and interrupt are not automatically disabled in the watchdog functional test mode. ? after emerging from a reset due to a watchdog functional test, you are still expected to go through the mandatory steps of unlocking and configuring the watchdog. the watchdog continues to be in its functional test mode and therefore you should pull the watchdog out of the functional test mode within wct time of reset. ? after emerging from a reset due to a watchdog functional test, you still need to go through the mandatory steps of unlocking and configuring the watchdog. ? you must ensure that both the clock inputs to the glitchless clock multiplexers are alive during the switching of clocks. failure to do so results in a loss of clock at their outputs. ? there is a gap of two to three watchdog clock cycles from the point that stop mode is entered to the watchdog timer actually pausing, due to synchronization. the same holds true for an exit from the stop mode, this time resulting in a two to three watchdog clock cycle delay in the timer restarting. in case the duration of the stop mode is less than one watchdog clock cycle, the watchdog timer is not guaranteed to pause. ? consider the case when the first refresh value is written, following which the system enters stop mode (with system bus clk still on). now, if the second refresh value is not written within 20 bus cycles of the first value, the system is reset (or interrupt- then-reset if enabled). chapter 23 watchdog timer (wdog) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 535 restrictions on watchdog operation k60 sub-family reference manual, rev. 6, nov 2011 536 freescale semiconductor, inc. chapter 24 multipurpose clock generator (mcg) 24.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the multipurpose clock generator (mcg) module provides several clock source choices for the mcu. the module contains a frequency-locked loop (fll) and a phase-locked loop (pll). the fll is controllable by either an internal or an external reference clock. the pll is controllable by the external reference clock. the module can select either of the fll or pll output clocks, or either of the internal or external reference clocks as a source for the mcu system clock. the mcg operates in conjuction with a crystal oscillator, which allows an external crystal, ceramic resonator, or another external clock source to produce the external reference clock. 24.1.1 features key features of the mcg module are: ? frequency-locked loop (fll) ? digitally-controlled oscillator (dco) ? dco frequency range is programmable for up to four different frequency ranges. ? option to program and maximize dco output frequency for a low frequency external reference clock source. ? option to prevent fll from resetting its current locked frequency when switching clock modes if fll reference frequency is not changed. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 537 ? internal or external reference clock can be used as the fll source. ? can be used as a clock source for other on-chip peripherals. ? phase-locked loop (pll) ? voltage-controlled oscillator (vco) ? external reference clock is used as the pll source ? modulo vco frequency divider ? phase/frequency detector ? integrated loop filter ? can be used as a clock source for other on-chip peripherals. ? internal reference clock generator ? slow clock with nine trim bits for accuracy ? fast clock with four trim bits ? can be used as source clock for the fll. in fei mode, only the slow internal reference clock (irc) can be used as the fll source. ? either the slow or the fast clock can be selected as the clock source for the mcu ? can be used as a clock source for other on-chip peripherals ? control signals for "the mcg external reference low power oscillator clock generators are provided: ? hgo, range, erefs ? external clock from the crystal oscillator ? can be used as a source for the fll and/or the pll. ? can be selected as the clock source for the mcu ? external clock from the real time counter (rtc) ? can only be used as a source for the fll. ? can be selected as the clock source for the mcu ? external clock monitor with reset and interrupt request capability to check for external clock failure when running in fbe, pee, blpe, or fee modes ? lock detector with interrupt request capability for use with the pll introduction k60 sub-family reference manual, rev. 6, nov 2011 538 freescale semiconductor, inc. ? internal reference clocks auto trim machine (atm) capability using an external clock as a reference ? reference dividers for both the fll and pll are provided ? reference dividers for the fast internal reference clock are provided ? mcg pll clock (mcgpllclk) is provided as a clock source for other on-chip peripherals ? mcg fll clock (mcgfllclk) is provided as a clock source for other on-chip peripherals ? mcg fixed frequency clock (mcgffclk) is provided as a clock source for other on-chip peripherals ? mcg internal reference clock (mcgirclk) is provided as a clock source for other on-chip peripherals. chapter 24 multipurpose clock generator (mcg) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 539 mcgoutclk mcgirclk mcgffclk dcoout /(24,25,26,...,55) phase detector charge pump internal filter vco vcoout pll multipurpose clock generator (mcg) vdiv lock clock monitor irclken cme / 2 plls lols lock detector / 2 5 irefst fll dmx32 mcgfllclk crystal oscillator frdiv n=0-7 / 2 n internal reference slow clock fast clock clock generator prdiv lolie sync auto trim machine ircst pllst clkst atms sctrim scftrim fctrim atmst irefsten oscinit erefs hgo range external drs / 2 clock valid peripheral busclk pllclken mcgpllclk ircsclk ircs clksclks dco lp filter /(1,2,3,4,5....,25) irefs stop clks pllclken irefs plls mcg crystal oscillator enable detect external reference clock figure 24-1. multipurpose clock generator (mcg) block diagram introduction k60 sub-family reference manual, rev. 6, nov 2011 540 freescale semiconductor, inc. 24.1.2 modes of operation there are nine modes of operation for the mcg: fei, fee, fbi, fbe, pbe, pee, blpi, blpe, and stop. for details, see mcg modes of operation . 24.2 external signal description there are no mcg signals that connect off chip. 24.3 memory map/register definition this section includes the memory map and register definition. the mcg registers can only be written to when in supervisor mode. write accesses when in user mode will result in a bus error. read accesses may be performed in both supervisor and user modes. mcg memory map absolute address (hex) register name width (in bits) access reset value section/ page 4006_4000 mcg control 1 register (mcg_c1) 8 r/w 04h 24.3.1/ 542 4006_4001 mcg control 2 register (mcg_c2) 8 r/w see section 24.3.2/ 543 4006_4002 mcg control 3 register (mcg_c3) 8 r/w undefined 24.3.3/ 544 4006_4003 mcg control 4 register (mcg_c4) 8 r/w undefined 24.3.4/ 545 4006_4004 mcg control 5 register (mcg_c5) 8 r/w 00h 24.3.5/ 546 4006_4005 mcg control 6 register (mcg_c6) 8 r/w 00h 24.3.6/ 548 4006_4006 mcg status register (mcg_s) 8 r 10h 24.3.7/ 549 4006_4008 mcg auto trim control register (mcg_atc) 8 r/w 00h 24.3.8/ 551 4006_400a mcg auto trim compare value high register (mcg_atcvh) 8 r/w 00h 24.3.9/ 551 4006_400b mcg auto trim compare value low register (mcg_atcvl) 8 r/w 00h 24.3.10/ 552 chapter 24 multipurpose clock generator (mcg) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 541 24.3.1 mcg control 1 register (mcg_c1) address: mcg_c1 is 4006_4000h base + 0h offset = 4006_4000h bit 7 6 5 4 3 2 1 0 read clks frdiv irefs irclken irefsten write reset 0 0 0 0 0 1 0 0 mcg_c1 field descriptions field description 76 clks clock source select selects the clock source for mcgoutclk . 00 encoding 0 output of fll or pll is selected (depends on plls control bit). 01 encoding 1 internal reference clock is selected. 10 encoding 2 external reference clock is selected. 11 encoding 3 reserved, defaults to 00. 53 frdiv fll external reference divider selects the amount to divide down the external reference clock for the fll. the resulting frequency must be in the range 31.25 khz to 39.0625 khz (this is required when fll/dco is the clock source for mcgoutclk . in fbe mode, it is not required to meet this range, but it is recommended in the cases when trying to enter a fll mode from fbe). 000 if range = 0 , divide factor is 1; for all other range values, divide factor is 32. 001 if range = 0 , divide factor is 2; for all other range values, divide factor is 64. 010 if range = 0 , divide factor is 4; for all other range values, divide factor is 128. 011 if range = 0 , divide factor is 8; for all other range values, divide factor is 256. 100 if range = 0 , divide factor is 16; for all other range values, divide factor is 512. 101 if range = 0 , divide factor is 32; for all other range values, divide factor is 1024. 110 if range = 0 , divide factor is 64; for all other range values, divide factor is reserved . 111 if range = 0 , divide factor is 128; for all other range values, divide factor is reserved . 2 irefs internal reference select selects the reference clock source for the fll. 0 external reference clock is selected. 1 the slow internal reference clock is selected. 1 irclken internal reference clock enable enables the internal reference clock for use as mcgirclk. 0 mcgirclk inactive. 1 mcgirclk active. 0 irefsten internal reference stop enable controls whether or not the internal reference clock remains enabled when the mcg enters stop mode. table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 42 freescale semiconductor, inc. mcg_c1 field descriptions (continued) field description 0 internal reference clock is disabled in stop mode. 1 internal reference clock is enabled in stop mode if irclken is set or if mcg is in fei, fbi, or blpi modes before entering stop mode. 24.3.2 mcg control 2 register (mcg_c2) address: mcg_c2 is 4006_4000h base + 1h offset = 4006_4001h bit 7 6 5 4 3 2 1 0 read 0 0 range hgo erefs lp ircs write reset 0 0 0 0 0 0 0 0 mcg_c2 field descriptions field description 7 reserved this read-only field is reserved and always has the value zero. 6 reserved this read-only field is reserved and always has the value zero. 54 range frequency range select selects the frequency range for the crystal oscillator or external clock source. refer to the oscillator (osc) chapter for more details and the device data sheet for the frequency ranges used. 00 encoding 0 low frequency range selected for the crystal oscillator . 01 encoding 1 high frequency range selected for the crystal oscillator . 1x encoding 2 very high frequency range selected for the crystal oscillator . 3 hgo high gain oscillator select controls the crystal oscillator mode of operation. refer to the oscillator (osc) chapter for more details. 0 configure crystal oscillator for low-power operation. 1 configure crystal oscillator for high-gain operation. 2 erefs external reference select selects the source for the external reference clock. refer to the oscillator (osc) chapter for more details. 0 external reference clock requested. 1 oscillator requested. 1 lp low power select controls whether the fll (or pll) is disabled in blpi and blpe modes. in fbe or pbe modes, setting this bit to 1 will transition the mcg into blpe mode; in fbi mode, setting this bit to 1 will transition the mcg into blpi mode. in any other mcg mode, lp bit has no affect. table continues on the next page... chapter 24 multipurpose cloc enerator mc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 4 mcg_c2 field descriptions (continued) field description 0 fll (or pll) is not disabled in bypass modes. 1 fll (or pll) is disabled in bypass modes (lower power) 0 ircs internal reference clock select selects between the fast or slow internal reference clock source. 0 slow internal reference clock selected. 1 fast internal reference clock selected. 24.3.3 mcg control 3 register (mcg_c3) address: mcg_c3 is 4006_4000h base + 2h offset = 4006_4002h bit 7 6 5 4 3 2 1 0 read sctrim write reset x* x* x* x* x* x* x* x* * notes: x = undefined at reset. ? mcg_c3 field descriptions field description 70 sctrim slow internal reference clock trim setting sctrim 1 controls the slow internal reference clock frequency by controlling the slow internal reference clock period. the sctrim bits are binary weighted (that is, bit 1 adjusts twice as much as bit 0). increasing the binary value increases the period, and decreasing the value decreases the period. an additional fine trim bit is available in c4 register as the scftrim bit. upon reset this value is loaded with a factory trim value. if an sctrim value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this register. 1. a value for sctrim is loaded during reset from a factory programmed location . memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 544 freescale semiconductor, inc. 24.3.4 mcg control 4 register (mcg_c4) reset values for drst and dmx32 bits are 0. address: mcg_c4 is 4006_4000h base + 3h offset = 4006_4003h bit 7 6 5 4 3 2 1 0 read dmx32 drst_drs fctrim scftrim write reset 0 0 0 x* x* x* x* x* * notes: x = undefined at reset. a value for fctrim is loaded during reset from a factory programmed location . x = undefined at reset. mcg_c4 field descriptions field description 7 dmx32 dco maximum frequency with 32.768 khz reference the dmx32 bit controls whether or not the dco frequency range is narrowed to its maximum frequency with a 32.768 khz reference. the following table identifies settings for the dco frequency range. note: the system clocks derived from this source should not exceed their specified maximums. drst_drs dmx32 reference range fll factor dco range 00 0 31.25-39.0625 khz 640 20-25 mhz 1 32.768 khz 732 24 mhz 01 0 31.25-39.0625 khz 1280 40-50 mhz 1 32.768 khz 1464 48 mhz 10 0 31.25-39.0625 khz 1920 60-75 mhz 1 32.768 khz 2197 72 mhz 11 0 31.25-39.0625 khz 2560 80-100 mhz 1 32.768 khz 2929 96 mhz 0 dco has a default range of 25%. 1 dco is fine-tuned for maximum frequency with 32.768 khz reference. 6?5 drst_drs dco range select the drs bits select the frequency range for the fll output, dcoout. when the lp bit is set, writes to the drs bits are ignored. the drst read field indicates the current frequency range for dcoout. the drst field does not update immediately after a write to the drs field due to internal synchronization between clock domains. refer to dco frequency range table for more details. 00 encoding 0 low range (reset default). 01 encoding 1 mid range. table continues on the next page... chapter 24 multipurpose cloc enerator mc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 4 mcg_c4 field descriptions (continued) field description 10 encoding 2 mid-high range. 11 encoding 3 high range. 41 fctrim fast internal reference clock trim setting fctrim 1 controls the fast internal reference clock frequency by controlling the fast internal reference clock period. the fctrim bits are binary weighted (that is, bit 1 adjusts twice as much as bit 0). increasing the binary value increases the period, and decreasing the value decreases the period. if an fctrim[3:0] value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this register. 0 scftrim slow internal reference clock fine trim scftrim 2 controls the smallest adjustment of the slow internal reference clock frequency. setting scftrim increases the period and clearing scftrim decreases the period by the smallest amount possible. if an scftrim value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this bit. 1. a value for fctrim is loaded during reset from a factory programmed location . 2. a value for scftrim is loaded during reset from a factory programmed location . 24.3.5 mcg control 5 register (mcg_c5) address: mcg_c5 is 4006_4000h base + 4h offset = 4006_4004h bit 7 6 5 4 3 2 1 0 read 0 pllclken pllsten prdiv write reset 0 0 0 0 0 0 0 0 mcg_c5 field descriptions field description 7 reserved this read-only field is reserved and always has the value zero. 6 pllclken pll clock enable enables the pll independent of plls and enables the pll clock for use as mcgpllclk. (prdiv needs to be programmed to the correct divider to generate a pll reference clock in the range of 2 - 4 mhz range prior to setting the pllclken bit). setting pllclken will enable the external oscillator if not already enabled. whenever the pll is being enabled by means of the pllclken bit, and the external oscillator is being used as the reference clock, the oscinit bit should be checked to make sure it is set. table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 46 freescale semiconductor, inc. mcg_c5 field descriptions (continued) field description 0 mcgpllclk is inactive. 1 mcgpllclk is active. 5 pllsten pll stop enable enables the pll clock during normal stop (in low power stop mode, the pll clock gets disabled even if pllsten =1). all other power modes, pllsten bit has no affect and does not enable the pll clock to run if it is written to 1. 0 mcgpllclk is disabled in any of the stop modes. 1 mcgpllclk is enabled if system is in normal stop mode. 40 prdiv pll external reference divider selects the amount to divide down the external reference clock for the pll. the resulting frequency must be in the range of 2 mhz to 4 mhz. after the pll is enabled (by setting either pllclken or plls), the prdiv value must not be changed when lock is zero. table 24-7. pll external reference divide factor prdiv divide factor prdiv divide factor prdiv divide factor prdiv divide factor 00000 1 01000 9 10000 17 11000 25 00001 2 01001 10 10001 18 11001 reserv ed 00010 3 01010 11 10010 19 11010 reserv ed 00011 4 01011 12 10011 20 11011 reserv ed 00100 5 01100 13 10100 21 11100 reserv ed 00101 6 01101 14 10101 22 11101 reserv ed 00110 7 01110 15 10110 23 11110 reserv ed 00111 8 01111 16 10111 24 11111 reserv ed chapter 24 multipurpose clock generator (mcg) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 547 24.3.6 mcg control 6 register (mcg_c6) address: mcg_c6 is 4006_4000h base + 5h offset = 4006_4005h bit 7 6 5 4 3 2 1 0 read lolie plls cme vdiv write reset 0 0 0 0 0 0 0 0 mcg_c6 field descriptions field description 7 lolie loss of lock interrrupt enable determines if an interrupt request is made following a loss of lock indication. this bit only has an effect when lols is set. 0 no interrupt request is generated on loss of lock. 1 generate an interrupt request on loss of lock. 6 plls pll select controls whether the pll or fll output is selected as the mcg source when clks[1:0]=00. if the plls bit is cleared and pllclken is not set, the pll is disabled in all modes. if the plls is set, the fll is disabled in all modes. 0 fll is selected. 1 pll is selected (prdiv need to be programmed to the correct divider to generate a pll reference clock in the range of 2 - 4 mhz prior to setting the plls bit). 5 cme clock monitor enable determines if a reset request is made following a loss of external clock indication. the cme bit should only be set to a logic 1 when the mcg is in an operational mode that uses the external clock (fee, fbe, pee, pbe, or blpe). whenever the cme bit is set to a logic 1, the value of the range bits in the c2 register should not be changed. cme bit should be set to a logic 0 before the mcg enters any stop mode. otherwise, a reset request may occur while in stop mode. cme should also be set to a logic 0 before entering vlpr or vlpw power modes if the mcg is in blpe mode. 0 external clock monitor is disabled. 1 generate a reset request on loss of external clock. 40 vdiv vco divider selects the amount to divide the vco output of the pll. the vdiv bits establish the multiplication factor (m) applied to the reference clock frequency. after the pll is enabled (by setting either pllclken or plls), the vdiv value must not be changed when lock is zero. table 24-9. pll vco divide factor vdiv multiply factor vdiv multiply factor vdiv multiply factor vdiv multiply factor 00000 24 01000 32 10000 40 11000 48 table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 48 freescale semiconductor, inc. mcg_c6 field descriptions (continued) field description table 24-9. pll vco divide factor (continued) 00001 25 01001 33 10001 41 11001 49 00010 26 01010 34 10010 42 11010 50 00011 27 01011 35 10011 43 11011 51 00100 28 01100 36 10100 44 11100 52 00101 29 01101 37 10101 45 11101 53 00110 30 01110 38 10110 46 11110 54 00111 31 01111 39 10111 47 11111 55 24.3.7 mcg status register (mcg_s) address: mcg_s is 4006_4000h base + 6h offset = 4006_4006h bit 7 6 5 4 3 2 1 0 read lols lock pllst irefst clkst oscinit ircst write reset 0 0 0 1 0 0 0 0 mcg_s field descriptions field description 7 lols loss of lock status this bit is a sticky bit indicating the lock status for the pll. lols is set if after acquiring lock, the pll output frequency has fallen outside the lock exit frequency tolerance, d unl . lolie determines whether an interrupt request is made when lols is set. lolre determines whether a reset request is made when lols0 is set. this bit is cleared by reset or by writing a logic 1 to it when set. writing a logic 0 to this bit has no effect. 0 pll has not lost lock since lols was last cleared. 1 pll has lost lock since lols was last cleared. 6 lock lock status this bit indicates whether the pll has acquired lock. lock detection is disabled when not operating in either pbe or pee mode unless pllclken =1 and the mcg is not configured in blpi or blpe mode. table continues on the next page... chapter 24 multipurpose cloc enerator mc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 4 mcg_s field descriptions (continued) field description while the pll clock is locking to the desired frequency, the mcg pll clock (mcgpllclk) will be gated off until the lock bit gets asserted. if the lock status bit is set, changing the value of the prdiv [4:0] bits in the c5 register or the vdiv0[4:0] bits in the c6 register causes the lock status bit to clear and stay cleared until the pll has reacquired lock. entry into lls, vlps, or regular stop with pllsten =0 also causes the lock status bit to clear and stay cleared until the stop mode is exited and the pll has reacquired lock. any time the pll is enabled and the lock bit is cleared, the mcgpllclk will be gated off until the lock bit is asserted again. 0 pll is currently unlocked. 1 pll is currently locked. 5 pllst pll select status this bit indicates the clock source selected by plls . the pllst bit does not update immediately after a write to the plls bit due to internal synchronization between clock domains. 0 source of plls clock is fll clock. 1 source of plls clock is pll clock. 4 irefst internal reference status this bit indicates the current source for the fll reference clock. the irefst bit does not update immediately after a write to the irefs bit due to internal synchronization between clock domains. 0 source of fll reference clock is the external reference clock. 1 source of fll reference clock is the internal reference clock. 32 clkst clock mode status these bits indicate the current clock mode. the clkst bits do not update immediately after a write to the clks bits due to internal synchronization between clock domains. 00 encoding 0 output of the fll is selected (reset default). 01 encoding 1 internal reference clock is selected. 10 encoding 2 external reference clock is selected. 11 encoding 3 output of the pll is selected. 1 oscinit osc initialization this bit, which resets to 0, is set to 1 after the initialization cycles of the crystal oscillator clock have completed. after being set, the bit is cleared to 0 if the osc is subsequently disabled. refer to the osc modules detailed description for more information. 0 ircst internal reference clock status the ircst bit indicates the current source for the internal reference clock select clock (ircsclk). the ircst bit does not update immediately after a write to the ircs bit due to internal synchronization between clock domains. the ircst bit will only be updated if the internal reference clock is enabled, either by the mcg being in a mode that uses the irc or by setting the c1[irclken] bit . 0 source of internal reference clock is the slow clock (32 khz irc). 1 source of internal reference clock is the fast clock (2 mhz irc). memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 550 freescale semiconductor, inc. 24.3.8 mcg auto trim control register (mcg_atc) address: mcg_atc is 4006_4000h base + 8h offset = 4006_4008h bit 7 6 5 4 3 2 1 0 read atme atms atmf 0 write reset 0 0 0 0 0 0 0 0 mcg_atc field descriptions field description 7 atme automatic trim machine enable enables the auto trim machine to start automatically trimming the selected internal reference clock. note: atme deasserts after the auto trim machine has completed trimming all trim bits of the ircs clock selected by the atms bit. writing to c1, c3, c4, and atc registers or entering stop mode aborts the auto trim operation and clears this bit. 0 auto trim machine disabled. 1 auto trim machine enabled. 6 atms automatic trim machine select selects the ircs clock for auto trim test. 0 32 khz internal reference clock selected. 1 4 mhz internal reference clock selected. 5 atmf automatic trim machine fail flag fail flag for the automatic trim machine (atm). this bit asserts when the automatic trim machine is enabled (atme=1) and a write to the c1, c3, c4, and atc registers is detected or the mcg enters into any stop mode. a write to atmf clears the flag. 0 automatic trim machine completed normally. 1 automatic trim machine failed. 40 reserved this read-only field is reserved and always has the value zero. 24.3.9 mcg auto trim compare value high register (mcg_atcvh) address: mcg_atcvh is 4006_4000h base + ah offset = 4006_400ah bit 7 6 5 4 3 2 1 0 read atcvh write reset 0 0 0 0 0 0 0 0 chapter 24 multipurpose clock generator (mcg) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 551 mcg_atcvh field descriptions field description 70 atcvh atm compare value high values are used by auto trim machine to compare and adjust internal reference trim values during atm sar conversion. 24.3.10 mcg auto trim compare value low register (mcg_atcvl) address: mcg_atcvl is 4006_4000h base + bh offset = 4006_400bh bit 7 6 5 4 3 2 1 0 read atcvl write reset 0 0 0 0 0 0 0 0 mcg_atcvl field descriptions field description 70 atcvl atm compare value low values are used by auto trim machine to compare and adjust internal reference trim values during atm sar conversion. functional description 24.4.1 mcg mode state diagram the nine states of the mcg are shown in the following figure and are described in table 24-14 . the arrows indicate the permitted mcg mode transitions. 24.4 functional description k60 sub-family reference manual, rev. 6, nov 2011 552 freescale semiconductor, inc. fee fei reset blpi fbi fbe blpe pbe pee stop returns to the state that was active before the mcu entered stop mode, unless a reset occurs while in stop mode. entered from any state when the mcu enters stop mode figure 24-12. mcg mode state diagram note ? during exits from lls or vlps when the mcg is in pee mode, the mcg will reset to pbe clock mode and the c1[clks] and s[clkst] will automatically be set to 2b10. ? if entering normal stop mode when the mcg is in pee mode with c5[pllsten]=0, the mcg will reset to pbe clock mode and c1[clks] and s[clkst] will automatically be set to 2b10. 24.4.1.1 mcg modes of operation the mcg operates in one of the following modes. note the mcg restricts transitions between modes. for the permitted transitions, see figure 24-12 . chapter 24 multipurpose clock generator (mcg) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 553 table 24-14. mcg modes of operation mode description fll engaged internal (fei) fll engaged internal (fei) is the default mode of operation and is entered when all the following condtions occur: ? c1[clks] bits are written to 00 ? c1[irefs] bit is written to 1 ? c6[plls] bit is written to 0 in fei mode, mcgoutclk is derived from the fll clock (dcoclk) that is controlled by the 32 khz internal reference clock (irc). the fll loop will lock the dco frequency to the fll factor, as selected by the c4[drst_drs] and c4[dmx32] bits, times the internal reference frequency . refer to the c4[dmx32] bit description for more details. in fei mode, the pll is disabled in a low-power state unless c5[pllclken] is set. fll engaged external (fee) fll engaged external (fee) mode is entered when all the following conditions occur: ? c1[clks] bits are written to 00 ? c1[irefs] bit is written to 0 ? c1[frdiv] must be written to divide external reference clock to be within the range of 31.25 khz to 39.0625 khz ? c6[plls] bit is written to 0 in fee mode, mcgoutclk is derived from the fll clock (dcoclk) that is controlled by the external reference clock. the fll loop will lock the dco frequency to the fll factor, as selected by c4[drst_drs] and c4[dmx32] bits, times the external reference frequency, as specified by the c1[frdiv] and c2[range]. refer to the c4[dmx32] bit description for more details. in fee mode, the pll is disabled in a low-power state unless c5[pllclken] is set. fll bypassed internal (fbi) fll bypassed internal (fbi) mode is entered when all the following conditions occur: ? c1[clks] bits are written to 01 ? c1[irefs] bit is written to 1 ? c6[plls] is written to 0 ? c2[lp] is written to 0 in fbi mode, the mcgoutclk is derived either from the slow (32 khz irc) or fast (2 mhz irc) internal reference clock, as selected by the c2[ircs] bit. the fll is operational but its output is not used. this mode is useful to allow the fll to acquire its target frequency while the mcgoutclk is driven from the c2[ircs] selected internal reference clock. the fll clock (dcoclk) is controlled by the slow internal reference clock, and the dco clock frequency locks to a multiplication factor, as selected by the c4[drst_drs] and c4[dmx32] bits, times the internal reference frequency. refer to the c4[dmx32] bit description for more details. in fbi mode, the pll is disabled in a low- power state unless c5[pllclken] is set. table continues on the next page... functional description 60 sub-family reference manual, rev. 6, nov 2011 4 freescale semiconductor, inc. table 24-14. mcg modes of operation (continued) mode description fll bypassed external (fbe) fll bypassed external (fbe) mode is entered when all the following conditions occur: ? c1[clks] bits are written to 10 ? c1[irefs] bit is written to 0 ? c1[frdiv] must be written to divide external reference clock to be within the range of 31.25 khz to 39.0625 khz. ? c6[plls] bit is written to 0 ? c2[lp] is written to 0 in fbe mode, the mcgoutclk is derived from the oscsel external reference clock. the fll is operational but its output is not used. this mode is useful to allow the fll to acquire its target frequency while the mcgoutclk is driven from the external reference clock. the fll clock (dcoclk) is controlled by the external reference clock, and the dco clock frequency locks to a multiplication factor, as selected by the c4[drst_drs] and c4[dmx32] bits, times the divided external reference frequency. refer to the c4[dmx32] bit description for more details. in fbi mode the pll is disabled in a low-power state unless c5[pllclken] is set. pll engaged external (pee) pll engaged external (pee) mode is entered when all the following conditions occur: ? c1[clks] bits are written to 00 ? c1[irefs] bit is written to 0 ? c6[plls] bit is written to 1 in pee mode, the mcgoutclk is derived from the pll clock, which is controlled by the external reference clock. the pll clock frequency locks to a multiplication factor, as specified by c6[vdiv], times the external reference frequency, as specified by c5[prdiv]. the plls programmable reference divider must be configured to produce a valid pll reference clock. the fll is disabled in a low-power state. pll bypassed external (pbe) pll bypassed external (pbe) mode is entered when all the following conditions occur: ? c1[clks] bits are written to 10 ? c1[irefs] bit is written to 0 ? c6[plls] bit is written to 1 ? c2[lp] bit is written to 0 in pbe mode, mcgoutclk is derived from the oscsel external reference clock; the pll is operational, but its output clock is not used. this mode is useful to allow the pll to acquire its target frequency while mcgoutclk is driven from the external reference clock. the pll clock frequency locks to a multiplication factor, as specified by its [vdiv], times the pll reference frequency, as specified by its [prdiv]. in preparation for transition to pee, the plls programmable reference divider must be configured to produce a valid pll reference clock. the fll is disabled in a low-power state. table continues on the next page... chapter 24 multipurpose cloc enerator mc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. table 24-14. mcg modes of operation (continued) mode description bypassed low power internal (blpi) 1 bypassed low power internal (blpi) mode is entered when all the following conditions occur: ? c1[clks] bits are written to 01 ? c1[irefs] bit is written to 1 ? c6[plls] bit is written to 0 ? c2[lp] bit is written to 1 in blpi mode, mcgoutclk is derived from the internal reference clock. the fll is disabled and pll is disabled even if the c5[pllclken] is set to 1. bypassed low power external (blpe) bypassed low power external (blpe) mode is entered when all the following conditions occur: ? c1[clks] bits are written to 10 ? c1[irefs] bit is written to 0 ? c2[lp] bit is written to 1 in blpe mode, mcgoutclk is derived from the oscsel external reference clock. the fll is disabled and pll is disabled even if the c5[pllclken] is set to 1. stop entered whenever the mcu enters a stop state. the power modes are chip specific. for power mode assignments, see the chapter that describes how modules are configured and mcg behavior during stop recovery. entering stop mode, the fll is disabled, and all mcg clock signals are static except in the following case: mcgpllclk is active in normal stop mode when pllsten=1 mcgirclk is active in stop mode when all the following conditions become true: ? c1[irclken] = 1 ? c1[irefsten] = 1 note: ? when entering low power stop modes (lls or vlps) from pee mode, on exit the mcg clock mode is forced to pbe clock mode, the c1[clks] and s[clkst] will be configured to 2?b10 and s[lock] bit will be cleared without setting s[lols]. ? when entering normal stop mode from pee mode and if c5[pllsten]=0, on exit the mcg clock mode is forced to pbe mode, the c1[clks] and s[clkst] will be configured to 2?b10 and s[lock] bit will clear without setting s[lols]. if c5[pllsten]=1, the s[lock] bit will not get cleared and on exit the mcg will continue to run in pee mode. 1. if entering vlpr mode, mcg has to be configured and enter blpe mode or blpi mode with the 4 mhz irc clock selected (c2[ircs]=1). once in vlpr mode, writes to any of the mcg control registers that can cause a mcg clock mode switch to a non low power clock mode must be avoided. note for the chip-specific modes of operation, refer to the power management chapter of this mcu. functional description k60 sub-family reference manual, rev. 6, nov 2011 556 freescale semiconductor, inc. 24.4.1.2 mcg mode switching the c1[irefs] bit can be changed at any time, but the actual switch to the newly selected reference clocks is shown by the s[irefst] bit. when switching between engaged internal and engaged external modes, the fll will begin locking again after the switch is completed. the c1[clks] bits can also be changed at anytime, but the actual switch to the newly selected clock is shown by the s[clkst] bits. if the newly selected clock is not available, the previous clock will remain selected. the c4[drst_drs] write bits can be changed at anytime except when c2[lp] bit is 1. if the c4[drst_drs] write bits are changed while in fll engaged internal (fei) or fll engaged external (fee), the mcgoutclk will switch to the new selected dco range within three clocks of the selected dco clock. after switching to the new dco, the fll remains unlocked for several reference cycles. dco startup time is equal to the fll acquisition time. after the selected dco startup time is over, the fll is locked. the completion of the switch is shown by the c4[drst_drs] read bits. 24.4.2 low power bit usage the c2[lp] bit is provided to allow the fll or pll to be disabled and thus conserve power when these systems are not being used. the c4[drst_drs] can not be written while c2[lp] bit is 1. however, in some applications, it may be desirable to enable the fll or pll and allow it to lock for maximum accuracy before switching to an engaged mode. do this by writing c2[lp] to 0. 24.4.3 mcg internal reference clocks this module supports two internal reference clocks with nominal frequencies of 32 khz (slow irc) and 4 mhz (fast irc). 24.4.3.1 mcg internal reference clock the mcg internal reference clock (mcgirclk) provides a clock source for other on- chip peripherals and is enabled when c1[irclken]=1. when enabled, mcgirclk is driven by either the fast internal reference clock (2 mhz irc) or the slow internal reference clock (32 khz irc). the ircs clock frequency can be re-targeted by trimming the period of its ircs selected internal reference clock. this can be done by writing a new trim value to the c3[sctrim]:c4[scftrim] bits when the slow irc clock is chapter 24 multipurpose clock generator (mcg) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 557 selected or by writing a new trim value to the c4[fctrim] bits when the fast irc clock is selected. the internal reference clock period is proportional to the trim value written. c3[sctrim]:c4[scftrim] (if c2[ircs]=0) and c4[fctrim] (if c2[ircs]=1) bits affect the mcgoutclk frequency if the mcg is in fbi or blpi modes. c3[sctrim]:c4[scftrim] (if c2[ircs]=0) bits also affect the mcgoutclk frequency if the mcg is in fei mode. additionally, this clock can be enabled in stop mode by setting c1[irclken] and c1[irefsten], otherwise this clock is disabled in stop mode. 24.4.4 external reference clock the mcg module can support an external reference clock in all modes. refer to the device datasheet for external reference frequency range. when c1[irefs] is set, the external reference clock will not be used by the fll or pll. in these modes, the frequency can be equal to the maximum frequency the chip-level timing specifications will support. if the cme is asserted the slow internal reference clock is enabled along with the enabled external clock monitor. for the case when c6[cme]=1, a loss of clock is detected if the osc external reference falls below a minimum frequency (f loc_high or f loc_low depending on c2[range]). upon detect of a loss of clock event, the mcu generates a system reset if the respective locre bit is set. otherwise the mcg sets the respective locs bit and the mcg generates a locs interrupt request. 24.4.5 mcg fixed frequency clock the mcg fixed frequency clock (mcgffclk) provides a fixed frequency clock source for other on-chip peripherals. this clock is driven by either the slow clock from the internal reference clock generator or the external reference clock from the crystal oscillator, divided by the fll reference clock divider. the source of mcgffclk is selected by c1[irefs]. additionally, this clock is divided by two. this clock is synchronized to the peripheral bus clock and is only valid when its frequency is not more than 1/8 of the mcgoutclk frequency. when it is not valid, it is disabled and held high. the mcgffclk is not available when the mcg is in blpi mode. this clock is also disabled in stop mode. the fll reference clock must be set within the valid frequency range for the mcgffclk. functional description k60 sub-family reference manual, rev. 6, nov 2011 558 freescale semiconductor, inc. 24.4.6 mcg pll clock the mcg pll clock (mcgpllclk) is available depending on the device's configuration of the mcg module. for more details, refer to the clock distribution chapter of this mcu. the mcgpllclk is prevented from coming out of the mcg until it is enabled and s[lock] is set. 24.4.7 mcg auto trim (atm) the mcg auto trim (atm) is a mcg feature that when enabled, it configures the mcg hardware to automatically trim the mcg internal reference clocks using an external clock as a reference. the selection between which mcg irc clock gets tested and enabled is controlled by the atc[atms] control bit (atc[atms]=0 selects the 32 khz irc and atc[atms]=1 selects the 4 mhz irc). if 4 mhz irc is selected for the atm, a divide by 128 is enabled to divide down the 4 mhz irc to a range of 31.250 khz. when mcg atm is enabled by writing atc[atme] bit to 1, the atm machine will start auto trimming the selected irc clock. during the autotrim process, atc[atme] will remain asserted and will deassert after atm is completed or an abort occurs. the mcg atm is aborted if a write to any of the following control registers is detected including: c1, c3, c4, or atc or if stop mode is entered. if an abort occurs, atc[atmf] fail flag is asserted. the atm machine uses the bus clock as the external reference clock to perform the irc auto-trim. therefore, it is required that the mcg is configured in a clock mode where the reference clock used to generate the system clock is the external reference clock such as fbe clock mode. the mcg must not be configured in a clock mode where selected irc atm clock is used to generate the system clock. the bus clock is also required to be running with in the range of 8 - 16 mhz. to perform the atm on the selected irc, the atm machine uses the successive approximation technique to adjust the irc trim bits to generate the desired irc trimmed frequency. the atm sars each of the atm irc trim bits starting with the msb. for each trim bit test, the atm uses a pulse that is generated by the atm selected irc clock to enable a counter that counts number of atm external clocks. at end of each trim bit, the atm external counter value is compared to the atcv[15:0] register value. based on the comparison result, the atm trim bit under test will get cleared or stay asserted. this is done until all trim bits have been tested by atm sar machine. chapter 24 multipurpose clock generator (mcg) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 559 before the atm can be enabled, the atm expected count needs to get derived and stored into the atcv register. the atcv expected count is derived based on the required target internal reference clock (irc) frequency, the frequency of the external reference clock, and using the following formula: atcv ? fr = target internal reference clock (irc) trimmed frequency ? fe = external clock frequency if the auto trim is being performed on the 4 mhz irc, the calculated expected count value must be multiplied by 128 before storing it in the atcv register. therefore, the atcv expected count value for trimming the 4 mhz irc is calculated using the following formula. (128) 24.5 initialization / application information this section describes how to initialize and configure the mcg module in an application. the following sections include examples on how to initialize the mcg and properly switch between the various available modes. 24.5.1 mcg module initialization sequence the mcg comes out of reset configured for fei mode. the internal reference will stabilize in t irefsts microseconds before the fll can acquire lock. as soon as the internal reference is stable, the fll will acquire lock in t fll_acquire milliseconds. 24.5.1.1 initializing the mcg because the mcg comes out of reset in fei mode, the only mcg modes that can be directly switched to upon reset are fee, fbe, and fbi modes (see figure 24-12 ). reaching any of the other modes requires first configuring the mcg for one of these three intermediate modes. care must be taken to check relevant status bits in the mcg status register reflecting all configuration changes within each mode. to change from fei mode to fee or fbe modes, follow this procedure: 1. enable the external clock source by setting the appropriate bits in c2 register. initialization / application information k60 sub-family reference manual, rev. 6, nov 2011 560 freescale semiconductor, inc. 2. write to c1 register to select the clock mode. ? if entering fee mode, set c1[frdiv] appropriately, clear the c1[irefs] bit to switch to the external reference, and leave the c1[clks] bits at 2'b00 so that the output of the fll is selected as the system clock source. ? if entering fbe, clear the c1[irefs] bit to switch to the external reference and change the c1[clks] bits to 2'b10 so that the external reference clock is selected as the system clock source. the c1[frdiv] bits should also be set appropriately here according to the external reference frequency to keep the fll reference clock in the range of 31.25 khz to 39.0625 khz. although the fll is bypassed, it is still on in fbe mode. ? the internal reference can optionally be kept running by setting the c1[irclken] bit. this is useful if the application will switch back and forth between internal and external modes. for minimum power consumption, leave the internal reference disabled while in an external clock mode. 3. once the proper configuration bits have been set, wait for the affected bits in the mcg status register to be changed appropriately, reflecting that the mcg has moved into the proper mode. ? if the mcg is in fee, fbe, pee, pbe, or blpe mode, and c2[erefs] was also set in step 1, wait here for s[oscinit] bit to become set indicating that the external clock source has finished its initialization cycles and stabilized. ? if in fee mode, check to make sure the s[irefst] bit is cleared before moving on. ? if in fbe mode, check to make sure the s[irefst] bit is cleared and s[clkst] bits have changed to 2'b10 indicating the external reference clock has been appropriately selected. although the fll is bypassed, it is still on in fbe mode. 4. write to the c4 register to determine the dco output (mcgfllclk) frequency range. ? by default, with c4[dmx32] cleared to 0, the fll multiplier for the dco output is 640. for greater flexibility, if a mid-low-range fll multiplier of 1280 is desired instead, set c4[drst_drs] bits to 2'b01 for a dco output frequency of 40 mhz. if a mid high-range fll multiplier of 1920 is desired instead, set the c4[drst_drs] bits to 2'b10 for a dco output frequency of 60 mhz. if a high- range fll multiplier of 2560 is desired instead, set the c4[drst_drs] bits to 2'b11 for a dco output frequency of 80 mhz. chapter 24 multipurpose clock generator (mcg) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 561 ? when using a 32.768 khz external reference, if the maximum low-range dco frequency that can be achieved with a 32.768 khz reference is desired, set c4[drst_drs] bits to 2'b00 and set c4[dmx32] bit to 1. the resulting dco output (mcgoutclk) frequency with the new multiplier of 732 will be 24 mhz. ? when using a 32.768 khz external reference, if the maximum mid-range dco frequency that can be achieved with a 32.768 khz reference is desired, set c4[drst_drs] bits to 2'b01 and set c4[dmx32] bit to 1. the resulting dco output (mcgoutclk) frequency with the new multiplier of 1464 will be 48 mhz. ? when using a 32.768 khz external reference, if the maximum mid high-range dco frequency that can be achieved with a 32.768 khz reference is desired, set c4[drst_drs] bits to 2'b10 and set c4[dmx32] bit to 1. the resulting dco output (mcgoutclk) frequency with the new multiplier of 2197 will be 72 mhz. ? when using a 32.768 khz external reference, if the maximum high-range dco frequency that can be achieved with a 32.768 khz reference is desired, set c4[drst_drs] bits to 2'b11 and set c4[dmx32] bit to 1. the resulting dco output (mcgoutclk) frequency with the new multiplier of 2929 will be 96 mhz. 5. wait for the fll lock time to guarantee fll is running at new c4[drst_drs] and c4[dmx32] programmed frequency. to change from fei clock mode to fbi clock mode, follow this procedure: 1. change c1[clks] bits in c1 register to 2'b01 so that the internal reference clock is selected as the system clock source. 2. wait for s[clkst] bits in the mcg status register to change to 2'b01, indicating that the internal reference clock has been appropriately selected. 3. write to the c2 register to determine the ircs output (ircsclk) frequency range. ? by default, with c2[ircs] cleared to 0, the ircs selected output clock is the slow internal reference clock (32 khz irc). if the faster irc is desired, set c2[ircs] bit to 1 for a ircs clock derived from the 4 mhz irc source. initialization / application information k60 sub-family reference manual, rev. 6, nov 2011 562 freescale semiconductor, inc. 24.5.2 using a 32.768 khz reference in fee and fbe modes, if using a 32.768 khz external reference, at the default fll multiplication factor of 640, the dco output (mcgfllclk) frequency is 20.97 mhz at low-range. if c4[drst_drs] bits are set to 2'b01, the multiplication factor is doubled to 1280, and the resulting dco output frequency is 41.94 mhz at mid-low-range. if c4[drst_drs] bits are set to 2'b10, the multiplication factor is set to 1920, and the resulting dco output frequency is 62.91 mhz at mid high-range. if c4[drst_drs] bits are set to 2'b11, the multiplication factor is set to 2560, and the resulting dco output frequency is 83.89 mhz at high-range. in fbi and fei modes, setting c4[dmx32] bit is not recommended. if the internal reference is trimmed to a frequency above 32.768 khz, the greater fll multiplication factor could potentially push the microcontroller system clock out of specification and damage the part. the rtc 32 khz oscillator may be used as the fll reference clock. refer to the sim chapter on how this can be selected. the mcg must be in an internal clocking mode (fei, fbi or blpi) when the external clock selection mux is switched. the c2[range] bits must be set to 2'b00 and the c1[frdiv] bits must be set to 3'b000 to ensure this clock is divided by 1 to keep it within the allowed fll reference clock range. 24.5.3 mcg mode switching when switching between operational modes of the mcg, certain configuration bits must be changed in order to properly move from one mode to another. each time any of these bits are changed (c6[plls], c1[irefs], c1[clks], c2[ircs], or c2[erefs]), the corresponding bits in the mcg status register (pllst, irefst, clkst, ircst, or oscinit) must be checked before moving on in the application software. additionally, care must be taken to ensure that the reference clock divider (c1[frdiv] and c5[prdiv]) is set properly for the mode being switched to. for instance, in pee mode, if using a 4 mhz crystal, c5[prdiv] must be set to 5'b000 (divide-by-1) or 5'b001 (divide -by-2) in order to divide the external reference down to the required frequency between 2 and 4 mhz. in fbe, fee, fbi, and fei modes, at any time, the application can switch the fll multiplication factor between 640, 1280, 1920, and 2560 with c4[drst_drs] bits. writes to c4[drst_drs] bits will be ignored if c2[lp]=1. the table below shows mcgoutclk frequency calculations using c1[frdiv], c5[prdiv], and c6[vdiv] settings for each clock mode. chapter 24 multipurpose clock generator (mcg) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 563 table 24-15. mcgoutclk frequency calculation options clock mode f mcgoutclk 1 note fei (fll engaged internal) (f int * f) typical f mcgoutclk = 20 mhz immediately after reset. fee (fll engaged external) (f ext / fll_r) *f f ext / fll_r must be in the range of 31.25 khz to 39.0625 khz fbe (fll bypassed external) f ext f ext / fll_r must be in the range of 31.25 khz to 39.0625 khz fbi (fll bypassed internal) f int typical f int = 32 khz pee (pll engaged external) (f ext / pll_r) * m f ext / pll_r must be in the range of 2 4 mhz pbe (pll bypassed external) f ext f ext / pll_r must be in the range of 2 4 mhz blpi (bypassed low power internal) f int blpe (bypassed low power external) f ext 1. fll_r is the reference divider selected by the c1[frdiv] bits, pll_r is the reference divider selected by c5[prdiv] bits, f is the fll factor selected by c4[drst_drs] and c4[dmx32] bits, and m is the multiplier selected by c6[vdiv] bits. this section will include 3 mode switching examples using an 4 mhz external crystal. if using an external clock source less than 2 mhz, the mcg should not be configured for any of the pll modes (pee and pbe). 24.5.3.1 example 1: moving from fei to pee mode : external crystal = 4 mhz, mcgoutclk frequency = 48 mhz in this example, the mcg will move through the proper operational modes from fei to pee to achieve 48 mhz mcgoutclk frequency from 4 mhz external crystal reference. first, the code sequence will be described. then a flowchart will be included which illustrates the sequence. 1. first, fei must transition to fbe mode: a. c2 = 0x1c ? c2[range] set to 2'b01 because the frequency of 4 mhz is within the high frequency range ? c2[hgo] set to 1 to configure the crystal oscillator for high gain operation ? c2[erefs] set to 1, because a crystal is being used b. c1 = 0x90 initialization / application information k60 sub-family reference manual, rev. 6, nov 2011 564 freescale semiconductor, inc. ? c1[clks] set to 2'b10 in order to select external reference clock as system clock source ? c1[frdiv] set to 3'b010, or divide-by-128 because 4 mhz / 128 = 31.25 khz which is in the 31.25 khz to 39.0625 khz range required by the fll ? c1[irefs] cleared to 0, selecting the external reference clock and enabling the external oscillator. c. loop until s[oscinit] is 1, indicating the crystal selected by c2[erefs] has been initialized.. d. loop until s[irefst] is 0, indicating the external reference is the current source for the reference clock e. loop until s[clkst] is 2'b10, indicating that the external reference clock is selected to feed mcgoutclk 2. then configure c5[prdiv] to generate correct pll reference frequency. a. c5 = 0x01 ? c5[prdiv] set to 5'b001, or divide-by-2 resulting in a pll reference frequency of 4 mhz/2 = 2 mhz. 3. then, fbe must transition either directly to pbe mode or first through blpe mode and then to pbe mode: a. blpe: if a transition through blpe mode is desired, first set c2[lp] to 1. b. blpe/pbe: c6 = 0x40 ? c6[plls] set to 1, selects the pll. at this time, with a c1[prdiv] value of 2'b001, the pll reference divider is 2 (see pll external reference divide factor table), resulting in a reference frequency of 4 mhz/ 2 = 2 mhz. in blpe mode,changing the c6[plls] bit only prepares the mcg for pll usage in pbe mode. ? c6[vdiv] set to 5'b0000, or multiply-by-24 because 2 mhz reference * 24 = 48 mhz. in blpe mode, the configuration of the vdiv bits does not matter because the pll is disabled. changing them only sets up the multiply value for pll usage in pbe mode. c. blpe: if transitioning through blpe mode, clear c2[lp] to 0 here to switch to pbe mode. d. pbe: loop until s[pllst] is set, indicating that the current source for the plls clock is the pll. chapter 24 multipurpose clock generator (mcg) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 565 e. pbe: then loop until s[lock] is set, indicating that the pll has acquired lock. 4. lastly, pbe mode transitions into pee mode: a. c1 = 0x10 ? c1[clks] set to 2'b00 in order to select the output of the pll as the system clock source. b. loop until s[clkst] are 2'b11, indicating that the pll output is selected to feed mcgoutclk in the current clock mode. ? now, with prdiv of divide-by-2, and c6[vdiv] of multiply-by-24, mcgoutclk = [(4 mhz / 2) * 24] = 48 mhz. initialization / application information k60 sub-family reference manual, rev. 6, nov 2011 566 freescale semiconductor, inc. c2 = 0x1c (s[lp]=0) in blpe mode ? c6 = 0x40 c2 = 0x1c start in fei mode no no no no no no no no yes yes yes yes yes yes yes yes check c1 = 0x90 check check enter blpe mode ? c2 = 0x1e (c2[lp] = 1) check check c1 = 0x10 check continue in pee mode s[pllst] = 1? s[lock] = 1? s[clkst] = %10? s[clkst] = %11? (s[lp]=1) s[irefst] = 0? s[oscinit] = 1? c5 = 0x01 (c5[vdiv] = 1) figure 24-13. flowchart of fei to pee mode transition using an 4 mhz crystal chapter 24 multipurpose clock generator (mcg) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 567 24.5.3.2 example 2: moving from pee to blpi mode: mcgoutclk frequency =32 khz in this example, the mcg will move through the proper operational modes from pee mode with a 4 mhz crystal configured for a 48 mhz mcgoutclk frequency (see previous example) to blpi mode with a 32 khz mcgoutclk frequency.first, the code sequence will be described. then a flowchart will be included which illustrates the sequence. 1. first, pee must transition to pbe mode: a. c1 = 0x90 ? c1[clks] set to 2'b10 in order to switch the system clock source to the external reference clock. b. loop until s[clkst] are 2'b10, indicating that the external reference clock is selected to feed mcgoutclk. 2. then, pbe must transition either directly to fbe mode or first through blpe mode and then to fbe mode: a. blpe: if a transition through blpe mode is desired, first set c2[lp] to 1 b. blpe/fbe: c6 = 0x00 ? c6[plls] clear to 0 to select the fll. at this time, with c1[frdiv] value of 3'b010, the fll divider is set to 128, resulting in a reference frequency of 4 mhz / 128 = 31.25 khz. if c1[frdiv] was not previously set to 3'b010 (necessary to achieve required 31.25-39.06 khz fll reference frequency with an 4 mhz external source frequency), it must be changed prior to clearing c6[plls] bit. in blpe mode,changing this bit only prepares the mcg for fll usage in fbe mode. with c6[plls] = 0, the c6[vdiv] value does not matter. c. blpe: if transitioning through blpe mode, clear c2[lp] to 0 here to switch to fbe mode. d. fbe: loop until s[pllst] is cleared, indicating that the current source for the plls clock is the fll. 3. next, fbe mode transitions into fbi mode: a. c1 = 0x54 initialization / application information k60 sub-family reference manual, rev. 6, nov 2011 568 freescale semiconductor, inc. ? c1[clks] set to 2'b01 in order to switch the system clock to the internal reference clock. ? c1[irefs] set to 1 to select the internal reference clock as the reference clock source. ? c1[frdiv] remain unchanged because the reference divider does not affect the internal reference. b. loop until s[irefst] is 1, indicating the internal reference clock has been selected as the reference clock source. c. loop until s[clkst] are 2'b01, indicating that the internal reference clock is selected to feed mcgoutclk. 4. lastly, fbi transitions into blpi mode. a. c2 = 0x02 ? c2[lp] is 1 ? c2[range], c2[hgo], c2[erefs], c1[irclken], and c1[irefsten] bits are ignored when the c1[irefs] bit is set. they can remain set, or be cleared at this point. chapter 24 multipurpose clock generator (mcg) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 569 start in pee mode c1 = 0x90 check s[clkst] = %10 ? no no no no yes c2 = 0x02 continue in blpi mode yes yes check s[pllst] = 0? c1 = 0x54 check s[irefst] = 0? check s[clkst] = %01? yes no yes (c2[lp] = 1) c6 = 0x00 in blpe mode ? in blpe mode ? no yes c2 = 0x1c (c2[lp] = 0) c2 = 0x1e enter blpe mode ? (c2[lp]=1) figure 24-14. flowchart of pee to blpi mode transition using an 4 mhz crystal initialization / application information k60 sub-family reference manual, rev. 6, nov 2011 570 freescale semiconductor, inc. 24.5.3.3 example 3: moving from blpi to fee mode in this example, the mcg will move through the proper operational modes from blpi mode at a 32 khz mcgoutclk frequency running off the internal reference clock (see previous example) to fee mode using a 4 mhz crystal configured for a 20 mhz mcgoutclk frequency. first, the code sequence will be described. then a flowchart will be included which illustrates the sequence. 1. first, blpi must transition to fbi mode. a. c2 = 0x00 ? c2[lp] is 0 2. next, fbi will transition to fee mode. a. c2 = 0x1c ? c2[range] set to 2'b01 because the frequency of 4 mhz is within the high frequency range. ? c2[hgo] set to 1 to configure the crystal oscillator for high gain operation. ? c2[erefs] set to 1, because a crystal is being used. b. c1 = 0x10 ? c1[clks] set to 2'b00 in order to select the output of the fll as system clock source. ? c1[frdiv] remain at 3'b010, or divide-by-128 for a reference of 4 mhz / 128 = 31.25 khz. ? c1[irefs] cleared to 0, selecting the external reference clock. c. loop until s[oscinit] is 1, indicating the crystal selected by the c2[erefs] bit has been initialized. d. loop until s[irefst] is 0, indicating the external reference clock is the current source for the reference clock. e. loop until s[clkst] are 2'b00, indicating that the output of the fll is selected to feed mcgoutclk. f. now, with a 31.25 khz reference frequency, a fixed dco multiplier of 640, mcgoutclk = 31.25 khz * 640 / 1 = 20 mhz. g. at this point, by default, the c4[drst_drs] bits are set to 2'b00 and c4[dmx32] is cleared to 0. if the mcgoutclk frequency of 40 mhz is desired instead, set the c4[drst_drs] bits to 0x01 to switch the fll chapter 24 multipurpose clock generator (mcg) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 571 multiplication factor from 640 to 1280. to return the mcgoutclk frequency to 20 mhz, set c4[drst_drs] bits to 2'b00 again, and the fll multiplication factor will switch back to 640. c1 = 0x10 c2 = 0x00 c2 = 0x1c check check check s[oscinit] = 1 ? continue in fee mode no no no yes yes yes start in blpi mode s[irefst] = 0? s[clkst] = %00? figure 24-15. flowchart of blpi to fee mode transition using an 4 mhz crystal initialization / application information k60 sub-family reference manual, rev. 6, nov 2011 572 freescale semiconductor, inc. chapter 25 oscillator (osc) 25.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the osc module is a crystal oscillator. the module, in conjunction with an external crystal or resonator, generates a reference clock for the mcu. 25.2 features and modes key features of the module are: ? supports 32 khz crystals (low range mode) ? supports 3C8 mhz, 8C32 mhz crystals and resonators (high range mode) ? automatic gain control (agc) to optimize power consumption in high frequency ranges 3C8 mhz, 8C32 mhz using low-power mode ? high gain option in frequency ranges: 32 khz, 3C8 mhz, and 8C32 mhz ? voltage and frequency filtering to guarantee clock frequency and stability ? optionally external input bypass clock from extal signal directly ? one clock for mcu clock system ? two clocks for on-chip peripherals that can work in stop modes functional description describes the module's operation in more detail. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 573 25.3 block diagram the osc module uses a crystal or resonator to generate three filtered oscillator clock signals. three clocks are output from osc module: oscclk for mcu system, oscerclk for on-chip peripherals, and osc32kclk. the oscclk can only work in run mode. oscerclk and osc32kclk can work in low power modes. for the clock source assignments, refer to the clock distribution information of this mcu. refer to the chip configuration chapter for the external reference clock source in this mcu. the following figure shows the block diagram of the osc module. xtal extal xtl_clk cnt_done_4096 osc_clk_out mux 4096 counter osc clock enable stop osc clock selection oscerclk erclken oscclk range selections low power config osc32kclk oscillator circuits e n logic erclken erefsten osc_en figure 25-1. osc module block diagram 25.4 osc signal descriptions the following table shows the user-accessible signals available for the osc module. refer to signal multiplexing information for this mcu for more details. block diagram k60 sub-family reference manual, rev. 6, nov 2011 574 freescale semiconductor, inc. table 25-1. osc signal descriptions signal description i/o extal external clock/oscillator input i xtal oscillator output o 25.5 external crystal / resonator connections the connections for a crystal/resonator frequency reference are shown in the following figures. when using low-frequency, low-power mode, the only external component is the crystal or ceramic resonator itself. in the other oscillator modes, load capacitors (c x , c y ) and feedback resistor (r f ) are required. the following table shows all possible connections. table 25-2. external caystal/resonator connections oscillator mode connections low-frequency (32 khz), low-power connection 1 low-frequency (32 khz), high-gain connection 2/connection 3 1 high-frequency (3~32 mhz), low-power connection 1/connection 3 2 , 2 high-frequency (3~32 mhz), high-gain connection 2/connection 3 2 1. when the load capacitors (cx, cy) are greater than 30 pf, use connection 3. 2. with the low-power mode, the oscillator has the internal feedback resistor r f . therefore, the feedback resistor must not be externally with the connection 3. osc extal crystal or resonator v ss xtal figure 25-2. crystal/ceramic resonator connections - connection 1 chapter 25 oscillator (osc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 575 osc v ss r f crystal or resonator xtal extal figure 25-3. crystal/ceramic resonator connections - connection 2 note connection 1 and connection 2 should use internal capacitors as the load of the oscillator by configuring the cr[scxp] bits. osc v ss c x c y r f crystal or resonator xtal extal figure 25-4. crystal/ceramic resonator connections - connection 3 25.6 external clock connections in external clock mode, the pins can be connected as shown below. note xtal can be used as a gpio when the gpio alternate function is configured for it. external clock connections k60 sub-family reference manual, rev. 6, nov 2011 576 freescale semiconductor, inc. osc v ss clock input i/o xtal extal figure 25-5. external clock connections 25.7 memory map/register definitions some oscillator module register bits are typically incorporated into other peripherals such as mcg or sim. osc memory map/register definition osc memory map absolute address (hex) register name width (in bits) access reset value section/ page 4006_5000 osc control register (osc_cr) 8 r/w 00h 25.71.1/ 577 25.71.1 osc control register (osc_cr) after osc is enabled and starts generating the clocks, the configurations such as low power and frequency range, must not be changed. address: osc_cr is 4006_5000h base + 0h offset = 4006_5000h bit 7 6 5 4 3 2 1 0 read erclken 0 erefsten 0 sc2p sc4p sc8p sc16p write reset 0 0 0 0 0 0 0 0 osc_cr field descriptions field description 7 erclken external reference enable enables external reference clock (oscerclk). table continues on the next page... 2.7.1 chapter 2 scillator sc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 77 osc_cr field descriptions (continued) field description 0 external reference clock is inactive. 1 external reference clock is enabled. 6 reserved this read-only field is reserved and always has the value zero. 5 erefsten external reference stop enable controls whether or not the external reference clock (oscerclk) remains enabled when mcu enters stop mode. 0 external reference clock is disabled in stop mode. 1 external reference clock stays enabled in stop mode if erclken is set before entering stop mode. 4 reserved this read-only field is reserved and always has the value zero. 3 sc2p oscillator 2 pf capacitor load configure configures the oscillator load. 0 disable the selection. 1 add 2 pf capacitor to the oscillator load. 2 sc4p oscillator 4 pf capacitor load configure configures the oscillator load. 0 disable the selection. 1 add 4 pf capacitor to the oscillator load. 1 sc8p oscillator 8 pf capacitor load configure configures the oscillator load. 0 disable the selection. 1 add 8 pf capacitor to the oscillator load. 0 sc16p oscillator 16 pf capacitor load configure configures the oscillator load. 0 disable the selection. 1 add 16 pf capacitor to the oscillator load. 25.8 functional description this following sections provide functional details of the module. functional description k60 sub-family reference manual, rev. 6, nov 2011 578 freescale semiconductor, inc. 25.8.1 osc module states the states of the osc module are shown in the following figure. the states and their transitions between each other are described in this section. stable off oscclk cnt_done_4096 start-up oscclk requested external clock mode oscillator on, stable oscillator off oscillator on, not yet stable oscillator on osc_clk_out = static osc_clk_out = static osc_clk_out = extal osc_clk_out = xtl_clk not requested && select osc internal clock oscclk requested && select clock from extal signal figure 25-7. osc module state diagram note xtl_clk is the clock generated internally from osc circuits. 25.8.1.1 off the osc enters the off state when the system does not require osc clocks. upon entering this state, xtl_clk is static unless osc is configured to select the clock from the extal pad by clearing the external reference clock selection bit. for details regarding the external reference clock source in this mcu, refer to the chip configuration chapter. the extal and xtal pins are also decoupled from all other oscillator circuitry in this state. the osc module circuitry is configured to draw minimal current. chapter 25 oscillator (osc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 579 25.8.1.2 oscillator start-up the osc enters start-up state when it is configured to generate clocks (internally the osc_en transitions high) using the internal oscillator circuits by setting the external reference clock selection bit. in this state, the osc module is enabled and oscillations are starting up, but have not yet stabilized. when the oscillation amplitude becomes large enough to pass through the input buffer, xtl_clk begins clocking the counter. when the counter reaches 4096 cycles of xtl_clk, the oscillator is considered stable and xtl_clk is passed to the output clock osc_clk_out. 25.8.1.3 oscillator stable the osc enters stable state when it is configured to generate clocks (internally the osc_en transitions high) using the internal oscillator circuits by setting the external reference clock selection bit and the counter reaches 4096 cycles of xtl_clk (when cnt_done_4096 is high). in this state, the osc module is producing a stable output clock on osc_clk_out. its frequency is determined by the external components being used. 25.8.1.4 external clock mode the osc enters external clock state when it is enabled and external reference clock selection bit is cleared. for details regarding external reference clock source in this mcu, refer to the chip configuration chapter. in this state, the osc module is set to buffer (with hysteresis) a clock from extal onto the osc_clk_out. its frequency is determined by the external clock being supplied. 25.8.2 osc module modes the osc is a pierce-type oscillator that supports external crystals or resonators operating over the frequency ranges shown in table 25-5 . these modes assume the following conditions: osc is enabled to generate clocks (osc_en=1), configured to generate clocks internally (mcg_c2[erefs] = 1), and some or one of the other peripherals (mcg, timer, and so on) is configured to use the oscillator output clock (osc_clk_out). functional description k60 sub-family reference manual, rev. 6, nov 2011 580 freescale semiconductor, inc. table 25-5. oscillator modes mode frequency range low-frequency, high-gain f osc_lo (1 khz) up to f osc_lo (32.768 khz) low-frequency, low-power (vlp) high-frequency mode1, high-gain f osc_hi_1 (3 mhz) up to f osc_hi_1 (8 mhz) high-frequency mode1, low-power high-frequency mode2, high-gain f osc_hi_2 (8 mhz) up to f osc_hi_2 (32 mhz) high-frequency mode2, low-power note for information about low power modes of operation used in this chip and their alignment with some osc modes, refer to the chip's power management details. 25.8.2.1 low-frequency, high-gain mode in low-frequency, high-gain mode, the oscillator uses a simple inverter-style amplifier. the gain is set to achieve rail-to-rail oscillation amplitudes. the oscillator input buffer in this mode is single-ended. it provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels. in this mode, the internal capacitors could be used. 25.8.2.2 low-frequency, low-power mode in low-frequency, low-power mode, the oscillator uses a gain control loop to minimize power consumption. as the oscillation amplitude increases, the amplifier current is reduced. this continues until a desired amplitude is achieved at steady-state. this mode provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels. in this mode, the internal capacitors could be used, the internal feedback resistor is connected, and no external resistor should be used. in this mode, the amplifier inputs, gain-control input, and input buffer input are all capacitively coupled for leakage tolerance (not sensitive to the dc level of extal). also in this mode, all external components except for the resonator itself are integrated, which includes the load capacitors and feeback resistor that biases extal. chapter 25 oscillator (osc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 581 25.8.2.3 high-frequency, high-gain mode in high-frequency, high-gain mode, the oscillator uses a simple inverter-style amplifier. the gain is set to achieve rail-to-rail oscillation amplitudes. this mode provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels. in this mode, the internal capacitors could be used. 25.8.2.4 high-frequency, low-power mode in high-frequency, low-power mode, the oscillator uses a gain control loop to minimize power consumption. as the oscillation amplitude increases, the amplifier current is reduced. this continues until a desired amplitude is achieved at steady-state. in this mode, the internal capacitors could be used, the internal feedback resistor is connected, and no external resistor should be used. the oscillator input buffer in this mode is differential. it provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels. 25.8.3 counter the oscillator output clock (osc_clk_out) is gated off until the counter has detected 4096 cycles of its input clock (xtl_clk). after 4096 cycles are completed, the counter passes xtl_clk onto osc_clk_out. this counting time-out is used to guarantee output clock stability. 25.8.4 reference clock pin requirements the osc module requires use of both the extal and xtal pins to generate an output clock in oscillator mode, but requires only the extal pin in external clock mode. the extal and xtal pins are available for i/o. for the implementation of these pins on this device, refer to the signal multiplexing chapter. 25.9 reset there is no reset state associated with the osc module. the counter logic is reset when the osc is not configured to generate clocks. there are no sources of reset requests for the osc module. reset k60 sub-family reference manual, rev. 6, nov 2011 582 freescale semiconductor, inc. 25.10 low power modes operation when the mcu enters stop modes, the osc is functional depending on erclken and erefsetn bit settings. if both these bits are set, the osc is in operation. in low leakage stop (lls) modes, the osc holds all register settings. if erclken and erefsten bits are set before entry to low leakage stop modes, the osc is still functional in these modes. after waking up from very low leakage stop (vllsx) modes, all osc register bits are reset and initialization is required through software. 25.11 interrupts the osc module does not generate any interrupts. chapter 25 oscillator (osc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 583 interrupts k60 sub-family reference manual, rev. 6, nov 2011 584 freescale semiconductor, inc. chapter 26 rtc oscillator 26.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the rtc oscillator module provides the clock source for the rtc. the rtc oscillator module, in conjunction with an external crystal, generates a reference clock for the rtc. 26.1.1 features and modes the key features of the rtc oscillator are as follows: ? supports 32 khz crystals with very low power ? consists of internal feed back resistor ? consists of internal programmable capacitors as the cload of the oscillator ? automatic gain control (agc) to optimize power consumption the rtc oscillator operations are described in detail in functional description . 26.1.2 block diagram the following is the block diagram of the rtc oscillator. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 585 gm control clk out for rtc pad pad xtal32 c 2 amplitude extal32 rf c1 detector figure 26-1. rtc oscillator block diagram 26.2 rtc signal descriptions the following table shows the user-accessible signals available for the rtc oscillator. see the chip-level specification to find out which signals are actually connected to the external pins. table 26-1. rtc signal descriptions signal description i/o extal32 oscillator input i xtal32 oscillator output o 26.2.1 extal32 oscillator input this signal is the analog input of the rtc oscillator. 26.2.2 xtal32 oscillator output this signal is the analog output of the rtc oscillator module. rtc signal descriptions k60 sub-family reference manual, rev. 6, nov 2011 586 freescale semiconductor, inc. 26.3 external crystal connections the connections with a crystal is shown in the following figure. external load capacitors and feedback resistor are not required. rtc oscillator module extal32 crystal or resonator xtal32 v ss figure 26-2. crystal connections 26.4 memory map/register descriptions rtc oscillator control bits are part of the rtc registers. refer to rtc_cr for more details. 26.5 functional description as shown in figure 26-1 , the module includes an amplifier which supplies the negative resistor for the rtc oscillator. the gain of the amplifier is controlled by the amplitude detector, which optimizes the power consumption. a schmitt trigger is used to translate the sine-wave generated by this oscillator to a pulse clock out, which is a reference clock for the rtc digital core. the oscillator includes an internal feedback resistor of approximately 100 m between extal32 and xtal32. in addition, there are two programmable capacitors with this oscillator, which can be used as the cload of the oscillator. the programmable range is from 0pf to 30pf. chapter 26 rtc oscillator k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 587 26.6 reset overview there is no reset state associated with the rtc oscillator. 26.7 interrupts the rtc oscillator does not generate any interrupts. reset overview k60 sub-family reference manual, rev. 6, nov 2011 588 freescale semiconductor, inc. chapter 27 flash memory controller (fmc) 27.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the flash memory controller (fmc) is a memory acceleration unit that provides: ? an interface between the device and the dual-bank nonvolatile memory. bank 0 consists of program flash memory, and bank 1 consists of flexnvm. ? buffers that can accelerate flash memory and flexnvm data transfers. 27.1.1 overview the flash memory controller manages the interface between the device and the dual- bank flash memory. the fmc receives status information detailing the configuration of the memory and uses this information to ensure a proper interface. the following table shows the supported 8-bit, 16-bit, and 32-bit read/write operations. flash memory type read write program flash memory x 1 flexnvm used as data flash memory x 1 flexnvm and flexram used as eeprom x x 1. a write operation to program flash memory or to flexnvm used as data flash memory results in a bus error. in addition, for bank 0 and bank 1, the fmc provides three separate mechanisms for accelerating the interface between the device and the flash memory. a 64-bit speculation buffer can prefetch the next 64-bit flash memory location, and both a 4-way, 8-set cache and a single-entry 64-bit buffer can store previously accessed flash memory or flexnvm data for quick access times. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 589 27.1.2 features the fmc's features include: ? interface between the device and the dual-bank flash memory and flexmemory: ? 8-bit, 16-bit, and 32-bit read operations to program flash memory and flexnvm used as data flash memory. ? 8-bit, 16-bit, and 32-bit read and write operations to flexnvm and flexram used as eeprom. ? for bank 0 and bank 1: read accesses to consecutive 32-bit spaces in memory return the second read data with no wait states. the memory returns 64 bits via the 32-bit bus access. ? crossbar master access protection for setting no access, read only access, write only access, or read/write access for each crossbar master. ? for bank 0 and bank 1: acceleration of data transfer from program flash memory and flexmemory to the device: ? 64-bit prefetch speculation buffer with controls for instruction/data access per master and bank ? 4-way, 8-set, 64-bit line size cache for a total of thirty-two 64-bit entries with controls for replacement algorithm and lock per way for each bank ? single-entry buffer with enable per bank ? invalidation control for the speculation buffer and the single-entry buffer 27.2 modes of operation the fmc only operates when the device accesses the flash memory or flexmemory. in terms of device power modes, the fmc only operates in run and wait modes, including vlpr and vlpw modes. for any device power mode where the flash memory or flexmemory cannot be accessed, the fmc is disabled. 27.3 external signal description the fmc has no external signals. modes of operation k60 sub-family reference manual, rev. 6, nov 2011 590 freescale semiconductor, inc. memory map and register descriptions the programming model consists of the fmc control registers and the program visible cache (data and tag/valid entries). note program the registers only while the flash controller is idle (for example, execute from ram). changing configuration settings while a flash access is in progress can lead to non-deterministic behavior. table 27-2. fmc register access registers read access write access mode length mode length control registers: pfapr, pfb0cr, pfb1cr supervisor (privileged) mode or user mode 32 bits supervisor (privileged) mode only 8, 16, or 32 bits cache registers supervisor (privileged) mode or user mode 32 bits supervisor (privileged) mode only 32 bits note accesses to unimplemented registers within the fmc's 4 kb address space return a bus error. the cache entries, both data and tag/valid, can be read at any time. note system software is required to maintain memory coherence when any segment of the flash cache is programmed. for example, all buffer data associated with the reprogrammed flash should be invalidated. accordingly, cache program visible writes must occur after a programming or erase event is completed and before the new memory image is accessed. the cache is a 4-way, set-associative cache with 8 sets. the ways are numbered 0-3 and the sets are numbered 0-7. the following table elaborates on the tag/valid and data entries. 27.4 chapter 27 flash memory controller (fmc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 591 table 27-3. program visible cache registers cache storage based at offset contents of 32-bit read nomenclature nomenclature example tag 100h 13h0, tag[18:6], 5h0, valid in tagvdwxsy, x denotes the way and y denotes the set. tagvdw2s0 is the 13-bit tag and 1-bit valid for cache entry way 2, set 0. data 200h upper or lower word of data in datawxsyu and datawxsyl, x denotes the way, y denotes the set, and u and l represent upper and lower word, respectively. dataw1s0u represents bits [63:32] of data entry way 1, set 0, and dataw1s0l represents bits [31:0] of data entry way 1, set 0. fmc memory map absolute address (hex) register name width (in bits) access reset value section/ page 4001_f000 flash access protection register (fmc_pfapr) 32 r/w 00f8_003fh 27.4.1/ 597 4001_f004 flash bank 0 control register (fmc_pfb0cr) 32 r/w 3002_001fh 27.4.2/ 600 4001_f008 flash bank 1 control register (fmc_pfb1cr) 32 r/w 3002_001fh 27.4.3/ 603 4001_f100 cache tag storage (fmc_tagvdw0s0) 32 r/w 0000_0000h 27.4.4/ 605 4001_f104 cache tag storage (fmc_tagvdw0s1) 32 r/w 0000_0000h 27.4.4/ 605 4001_f108 cache tag storage (fmc_tagvdw0s2) 32 r/w 0000_0000h 27.4.4/ 605 4001_f10c cache tag storage (fmc_tagvdw0s3) 32 r/w 0000_0000h 27.4.4/ 605 4001_f110 cache tag storage (fmc_tagvdw0s4) 32 r/w 0000_0000h 27.4.4/ 605 4001_f114 cache tag storage (fmc_tagvdw0s5) 32 r/w 0000_0000h 27.4.4/ 605 4001_f118 cache tag storage (fmc_tagvdw0s6) 32 r/w 0000_0000h 27.4.4/ 605 4001_f11c cache tag storage (fmc_tagvdw0s7) 32 r/w 0000_0000h 27.4.4/ 605 4001_f120 cache tag storage (fmc_tagvdw1s0) 32 r/w 0000_0000h 27.4.5/ 606 4001_f124 cache tag storage (fmc_tagvdw1s1) 32 r/w 0000_0000h 27.4.5/ 606 4001_f128 cache tag storage (fmc_tagvdw1s2) 32 r/w 0000_0000h 27.4.5/ 606 4001_f12c cache tag storage (fmc_tagvdw1s3) 32 r/w 0000_0000h 27.4.5/ 606 table continues on the next page... memory map and register descriptions 60 sub-family reference manual, rev. 6, nov 2011 2 freescale semiconductor, inc. fmc memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4001_f130 cache tag storage (fmc_tagvdw1s4) 32 r/w 0000_0000h 27.4.5/ 606 4001_f134 cache tag storage (fmc_tagvdw1s5) 32 r/w 0000_0000h 27.4.5/ 606 4001_f138 cache tag storage (fmc_tagvdw1s6) 32 r/w 0000_0000h 27.4.5/ 606 4001_f13c cache tag storage (fmc_tagvdw1s7) 32 r/w 0000_0000h 27.4.5/ 606 4001_f140 cache tag storage (fmc_tagvdw2s0) 32 r/w 0000_0000h 27.4.6/ 607 4001_f144 cache tag storage (fmc_tagvdw2s1) 32 r/w 0000_0000h 27.4.6/ 607 4001_f148 cache tag storage (fmc_tagvdw2s2) 32 r/w 0000_0000h 27.4.6/ 607 4001_f14c cache tag storage (fmc_tagvdw2s3) 32 r/w 0000_0000h 27.4.6/ 607 4001_f150 cache tag storage (fmc_tagvdw2s4) 32 r/w 0000_0000h 27.4.6/ 607 4001_f154 cache tag storage (fmc_tagvdw2s5) 32 r/w 0000_0000h 27.4.6/ 607 4001_f158 cache tag storage (fmc_tagvdw2s6) 32 r/w 0000_0000h 27.4.6/ 607 4001_f15c cache tag storage (fmc_tagvdw2s7) 32 r/w 0000_0000h 27.4.6/ 607 4001_f160 cache tag storage (fmc_tagvdw3s0) 32 r/w 0000_0000h 27.4.7/ 608 4001_f164 cache tag storage (fmc_tagvdw3s1) 32 r/w 0000_0000h 27.4.7/ 608 4001_f168 cache tag storage (fmc_tagvdw3s2) 32 r/w 0000_0000h 27.4.7/ 608 4001_f16c cache tag storage (fmc_tagvdw3s3) 32 r/w 0000_0000h 27.4.7/ 608 4001_f170 cache tag storage (fmc_tagvdw3s4) 32 r/w 0000_0000h 27.4.7/ 608 4001_f174 cache tag storage (fmc_tagvdw3s5) 32 r/w 0000_0000h 27.4.7/ 608 4001_f178 cache tag storage (fmc_tagvdw3s6) 32 r/w 0000_0000h 27.4.7/ 608 4001_f17c cache tag storage (fmc_tagvdw3s7) 32 r/w 0000_0000h 27.4.7/ 608 table continues on the next page... chapter 27 flash memory controller fmc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. fmc memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4001_f200 cache data storage (upper word) (fmc_dataw0s0u) 32 r/w 0000_0000h 27.4.8/ 609 4001_f204 cache data storage (lower word) (fmc_dataw0s0l) 32 r/w 0000_0000h 27.4.9/ 610 4001_f208 cache data storage (upper word) (fmc_dataw0s1u) 32 r/w 0000_0000h 27.4.8/ 609 4001_f20c cache data storage (lower word) (fmc_dataw0s1l) 32 r/w 0000_0000h 27.4.9/ 610 4001_f210 cache data storage (upper word) (fmc_dataw0s2u) 32 r/w 0000_0000h 27.4.8/ 609 4001_f214 cache data storage (lower word) (fmc_dataw0s2l) 32 r/w 0000_0000h 27.4.9/ 610 4001_f218 cache data storage (upper word) (fmc_dataw0s3u) 32 r/w 0000_0000h 27.4.8/ 609 4001_f21c cache data storage (lower word) (fmc_dataw0s3l) 32 r/w 0000_0000h 27.4.9/ 610 4001_f220 cache data storage (upper word) (fmc_dataw0s4u) 32 r/w 0000_0000h 27.4.8/ 609 4001_f224 cache data storage (lower word) (fmc_dataw0s4l) 32 r/w 0000_0000h 27.4.9/ 610 4001_f228 cache data storage (upper word) (fmc_dataw0s5u) 32 r/w 0000_0000h 27.4.8/ 609 4001_f22c cache data storage (lower word) (fmc_dataw0s5l) 32 r/w 0000_0000h 27.4.9/ 610 4001_f230 cache data storage (upper word) (fmc_dataw0s6u) 32 r/w 0000_0000h 27.4.8/ 609 4001_f234 cache data storage (lower word) (fmc_dataw0s6l) 32 r/w 0000_0000h 27.4.9/ 610 4001_f238 cache data storage (upper word) (fmc_dataw0s7u) 32 r/w 0000_0000h 27.4.8/ 609 4001_f23c cache data storage (lower word) (fmc_dataw0s7l) 32 r/w 0000_0000h 27.4.9/ 610 4001_f240 cache data storage (upper word) (fmc_dataw1s0u) 32 r/w 0000_0000h 27.4.10/ 611 4001_f244 cache data storage (lower word) (fmc_dataw1s0l) 32 r/w 0000_0000h 27.4.11/ 612 4001_f248 cache data storage (upper word) (fmc_dataw1s1u) 32 r/w 0000_0000h 27.4.10/ 611 4001_f24c cache data storage (lower word) (fmc_dataw1s1l) 32 r/w 0000_0000h 27.4.11/ 612 table continues on the next page... memory map and register descriptions 60 sub-family reference manual, rev. 6, nov 2011 4 freescale semiconductor, inc. fmc memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4001_f250 cache data storage (upper word) (fmc_dataw1s2u) 32 r/w 0000_0000h 27.4.10/ 611 4001_f254 cache data storage (lower word) (fmc_dataw1s2l) 32 r/w 0000_0000h 27.4.11/ 612 4001_f258 cache data storage (upper word) (fmc_dataw1s3u) 32 r/w 0000_0000h 27.4.10/ 611 4001_f25c cache data storage (lower word) (fmc_dataw1s3l) 32 r/w 0000_0000h 27.4.11/ 612 4001_f260 cache data storage (upper word) (fmc_dataw1s4u) 32 r/w 0000_0000h 27.4.10/ 611 4001_f264 cache data storage (lower word) (fmc_dataw1s4l) 32 r/w 0000_0000h 27.4.11/ 612 4001_f268 cache data storage (upper word) (fmc_dataw1s5u) 32 r/w 0000_0000h 27.4.10/ 611 4001_f26c cache data storage (lower word) (fmc_dataw1s5l) 32 r/w 0000_0000h 27.4.11/ 612 4001_f270 cache data storage (upper word) (fmc_dataw1s6u) 32 r/w 0000_0000h 27.4.10/ 611 4001_f274 cache data storage (lower word) (fmc_dataw1s6l) 32 r/w 0000_0000h 27.4.11/ 612 4001_f278 cache data storage (upper word) (fmc_dataw1s7u) 32 r/w 0000_0000h 27.4.10/ 611 4001_f27c cache data storage (lower word) (fmc_dataw1s7l) 32 r/w 0000_0000h 27.4.11/ 612 4001_f280 cache data storage (upper word) (fmc_dataw2s0u) 32 r/w 0000_0000h 27.4.12/ 613 4001_f284 cache data storage (lower word) (fmc_dataw2s0l) 32 r/w 0000_0000h 27.4.13/ 614 4001_f288 cache data storage (upper word) (fmc_dataw2s1u) 32 r/w 0000_0000h 27.4.12/ 613 4001_f28c cache data storage (lower word) (fmc_dataw2s1l) 32 r/w 0000_0000h 27.4.13/ 614 4001_f290 cache data storage (upper word) (fmc_dataw2s2u) 32 r/w 0000_0000h 27.4.12/ 613 4001_f294 cache data storage (lower word) (fmc_dataw2s2l) 32 r/w 0000_0000h 27.4.13/ 614 4001_f298 cache data storage (upper word) (fmc_dataw2s3u) 32 r/w 0000_0000h 27.4.12/ 613 4001_f29c cache data storage (lower word) (fmc_dataw2s3l) 32 r/w 0000_0000h 27.4.13/ 614 table continues on the next page... chapter 27 flash memory controller fmc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. fmc memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4001_f2a0 cache data storage (upper word) (fmc_dataw2s4u) 32 r/w 0000_0000h 27.4.12/ 613 4001_f2a4 cache data storage (lower word) (fmc_dataw2s4l) 32 r/w 0000_0000h 27.4.13/ 614 4001_f2a8 cache data storage (upper word) (fmc_dataw2s5u) 32 r/w 0000_0000h 27.4.12/ 613 4001_f2ac cache data storage (lower word) (fmc_dataw2s5l) 32 r/w 0000_0000h 27.4.13/ 614 4001_f2b0 cache data storage (upper word) (fmc_dataw2s6u) 32 r/w 0000_0000h 27.4.12/ 613 4001_f2b4 cache data storage (lower word) (fmc_dataw2s6l) 32 r/w 0000_0000h 27.4.13/ 614 4001_f2b8 cache data storage (upper word) (fmc_dataw2s7u) 32 r/w 0000_0000h 27.4.12/ 613 4001_f2bc cache data storage (lower word) (fmc_dataw2s7l) 32 r/w 0000_0000h 27.4.13/ 614 4001_f2c0 cache data storage (upper word) (fmc_dataw3s0u) 32 r/w 0000_0000h 27.4.14/ 615 4001_f2c4 cache data storage (lower word) (fmc_dataw3s0l) 32 r/w 0000_0000h 27.4.15/ 616 4001_f2c8 cache data storage (upper word) (fmc_dataw3s1u) 32 r/w 0000_0000h 27.4.14/ 615 4001_f2cc cache data storage (lower word) (fmc_dataw3s1l) 32 r/w 0000_0000h 27.4.15/ 616 4001_f2d0 cache data storage (upper word) (fmc_dataw3s2u) 32 r/w 0000_0000h 27.4.14/ 615 4001_f2d4 cache data storage (lower word) (fmc_dataw3s2l) 32 r/w 0000_0000h 27.4.15/ 616 4001_f2d8 cache data storage (upper word) (fmc_dataw3s3u) 32 r/w 0000_0000h 27.4.14/ 615 4001_f2dc cache data storage (lower word) (fmc_dataw3s3l) 32 r/w 0000_0000h 27.4.15/ 616 4001_f2e0 cache data storage (upper word) (fmc_dataw3s4u) 32 r/w 0000_0000h 27.4.14/ 615 4001_f2e4 cache data storage (lower word) (fmc_dataw3s4l) 32 r/w 0000_0000h 27.4.15/ 616 4001_f2e8 cache data storage (upper word) (fmc_dataw3s5u) 32 r/w 0000_0000h 27.4.14/ 615 4001_f2ec cache data storage (lower word) (fmc_dataw3s5l) 32 r/w 0000_0000h 27.4.15/ 616 table continues on the next page... memory map and register descriptions 60 sub-family reference manual, rev. 6, nov 2011 6 freescale semiconductor, inc. fmc memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4001_f2f0 cache data storage (upper word) (fmc_dataw3s6u) 32 r/w 0000_0000h 27.4.14/ 615 4001_f2f4 cache data storage (lower word) (fmc_dataw3s6l) 32 r/w 0000_0000h 27.4.15/ 616 4001_f2f8 cache data storage (upper word) (fmc_dataw3s7u) 32 r/w 0000_0000h 27.4.14/ 615 4001_f2fc cache data storage (lower word) (fmc_dataw3s7l) 32 r/w 0000_0000h 27.4.15/ 616 27.4.1 flash access protection register (fmc_pfapr) address: fmc_pfapr is 4001_f000h base + 0h offset = 4001_f000h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 m7pfd m6pfd m5pfd m4pfd m3pfd m2pfd m1pfd m0pfd w reset 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r m7ap[1:0] m6ap[1:0] m5ap[1:0] m4ap[1:0] m3ap[1:0] m2ap[1:0] m1ap[1:0] m0ap[1:0] w reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 fmc_pfapr field descriptions field description 3124 reserved this read-only field is reserved and always has the value zero. 23 m7pfd master 7 prefetch disable these bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. this field is further qualified by the pfbncr[bxdpe,bxipe] bits. 0 prefetching for this master is enabled. 1 prefetching for this master is disabled. 22 m6pfd master 6 prefetch disable these bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. this field is further qualified by the pfbncr[bxdpe,bxipe] bits. table continues on the next page... chapter 27 flash memory controller fmc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 7 fmc_pfapr field descriptions (continued) field description 0 prefetching for this master is enabled. 1 prefetching for this master is disabled. 21 m5pfd master 5 prefetch disable these bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. this field is further qualified by the pfbncr[bxdpe,bxipe] bits. 0 prefetching for this master is enabled. 1 prefetching for this master is disabled. 20 m4pfd master 4 prefetch disable these bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. this field is further qualified by the pfbncr[bxdpe,bxipe] bits. 0 prefetching for this master is enabled. 1 prefetching for this master is disabled. 19 m3pfd master 3 prefetch disable these bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. this field is further qualified by the pfbncr[bxdpe,bxipe] bits. 0 prefetching for this master is enabled. 1 prefetching for this master is disabled. 18 m2pfd master 2 prefetch disable these bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. this field is further qualified by the pfbncr[bxdpe,bxipe] bits. 0 prefetching for this master is enabled. 1 prefetching for this master is disabled. 17 m1pfd master 1 prefetch disable these bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. this field is further qualified by the pfbncr[bxdpe,bxipe] bits. 0 prefetching for this master is enabled. 1 prefetching for this master is disabled. 16 m0pfd master 0 prefetch disable these bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. this field is further qualified by the pfbncr[bxdpe,bxipe] bits. 0 prefetching for this master is enabled. 1 prefetching for this master is disabled. 1514 m7ap[1:0] master 7 access protection this field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master. 00 no access may be performed by this master. 01 only read accesses may be performed by this master. table continues on the next page... memory map and register descriptions 60 sub-family reference manual, rev. 6, nov 2011 8 freescale semiconductor, inc. fmc_pfapr field descriptions (continued) field description 10 only write accesses may be performed by this master. 11 both read and write accesses may be performed by this master. 1312 m6ap[1:0] master 6 access protection this field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master. 00 no access may be performed by this master 01 only read accesses may be performed by this master 10 only write accesses may be performed by this master 11 both read and write accesses may be performed by this master 1110 m5ap[1:0] master 5 access protection this field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master. 00 no access may be performed by this master 01 only read accesses may be performed by this master 10 only write accesses may be performed by this master 11 both read and write accesses may be performed by this master 98 m4ap[1:0] master 4 access protection this field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master. 00 no access may be performed by this master 01 only read accesses may be performed by this master 10 only write accesses may be performed by this master 11 both read and write accesses may be performed by this master 76 m3ap[1:0] master 3 access protection this field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master. 00 no access may be performed by this master 01 only read accesses may be performed by this master 10 only write accesses may be performed by this master 11 both read and write accesses may be performed by this master 54 m2ap[1:0] master 2 access protection this field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master. 00 no access may be performed by this master 01 only read accesses may be performed by this master 10 only write accesses may be performed by this master 11 both read and write accesses may be performed by this master 32 m1ap[1:0] master 1 access protection table continues on the next page... chapter 27 flash memory controller fmc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. fmc_pfapr field descriptions (continued) field description this field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master. 00 no access may be performed by this master 01 only read accesses may be performed by this master 10 only write accesses may be performed by this master 11 both read and write accesses may be performed by this master 10 m0ap[1:0] master 0 access protection this field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master. 00 no access may be performed by this master 01 only read accesses may be performed by this master 10 only write accesses may be performed by this master 11 both read and write accesses may be performed by this master 27.4.2 flash bank 0 control register (fmc_pfb0cr) address: fmc_pfb0cr is 4001_f000h base + 4h offset = 4001_f004h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r b0rwsc[3:0] clck_way[3:0] 0 0 b0mw[1:0] 0 w cinv_way[3:0] s_b_ inv reset 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 crc[2:0] b0dce b0ice b0dpe b0ipe b0sebe w reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 fmc_pfb0cr field descriptions field description 3128 b0rwsc[3:0] bank 0 read wait state control this read-only field defines the number of wait states required to access the bank 0 flash memory. the relationship between the read access time of the flash array (expressed in system clock cycles) and rwsc is defined as: access time of flash array [system clocks] = rwsc + 1 the fmc automatically calculates this value based on the ratio of the system clock speed to the flash clock speed. for example, when this ratio is 4:1, the fields value is 3h. table continues on the next page... memory map and register descriptions 60 sub-family reference manual, rev. 6, nov 2011 600 freescale semiconductor, inc. fmc_pfb0cr field descriptions (continued) field description 2724 clck_way[3:0] cache lock way x these bits determine if the given cache way is locked such that its contents will not be displaced by future misses. the bit setting definitions are for each bit in the field. 0 cache way is unlocked and may be displaced 1 cache way is locked and its contents are not displaced 2320 cinv_way[3:0] cache invalidate way x these bits determine if the given cache way is to be invalidated (cleared). when a bit within this field is written, the corresponding cache way is immediately invalidated: the ways tag, data, and valid contents are cleared. this field always reads as zero. cache invalidation takes precedence over locking. the cache is invalidated by system reset. system software is required to maintain memory coherency when any segment of the flash memory is programmed or erased. accordingly, cache invalidations must occur after a programming or erase event is completed and before the new memory image is accessed. the bit setting definitions are for each bit in the field. 0 no cache way invalidation for the corresponding cache 1 invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected 19 s_b_inv invalidate prefetch speculation buffer this bit determines if the fmcs prefetch speculation buffer and the single entry page buffer are to be invalidated (cleared). when this bit is written, the speculation buffer and single entry buffer are immediately cleared. this bit always reads as zero. 0 speculation buffer and single entry buffer are not affected. 1 invalidate (clear) speculation buffer and single entry buffer. 1817 b0mw[1:0] bank 0 memory width this read-only field defines the width of the bank 0 memory. 00 32 bits 01 64 bits 1x reserved 16 reserved this read-only field is reserved and always has the value zero. 158 reserved this read-only field is reserved and always has the value zero. 75 crc[2:0] cache replacement control this 3-bit field defines the replacement algorithm for accesses that are cached. 000 lru replacement algorithm per set across all four ways 001 reserved 010 independent lru with ways [0-1] for ifetches, [2-3] for data 011 independent lru with ways [0-2] for ifetches, [3] for data 1xx reserved table continues on the next page... chapter 27 flash memory controller fmc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 601 fmc_pfb0cr field descriptions (continued) field description 4 b0dce bank 0 data cache enable this bit controls whether data references are loaded into the cache. 0 do not cache data references. 1 cache data references. 3 b0ice bank 0 instruction cache enable this bit controls whether instruction fetches are loaded into the cache. 0 do not cache instruction fetches. 1 cache instruction fetches. 2 b0dpe bank 0 data prefetch enable this bit controls whether prefetches (or speculative accesses) are initiated in response to data references. 0 do not prefetch in response to data references. 1 enable prefetches in response to data references. 1 b0ipe bank 0 instruction prefetch enable this bit controls whether prefetches (or speculative accesses) are initiated in response to instruction fetches. 0 do not prefetch in response to instruction fetches. 1 enable prefetches in response to instruction fetches. 0 b0sebe bank 0 single entry buffer enable this bit controls whether the single entry page buffer is enabled in response to flash read accesses. its operation is independent from bank 1s cache. a high-to-low transition of this enable forces the page buffer to be invalidated. 0 single entry buffer is disabled. 1 single entry buffer is enabled. memory map and register descriptions k60 sub-family reference manual, rev. 6, nov 2011 602 freescale semiconductor, inc. 27.4.3 flash bank 1 control register (fmc_pfb1cr) this register has a format similar to that for pfb0cr, except it controls the operation of flash bank 1, and the "global" cache control fields are empty. address: fmc_pfb1cr is 4001_f000h base + 8h offset = 4001_f008h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r b1rwsc[3:0] 0 b1mw[1:0] 0 w reset 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 b1dce b1ice b1dpe b1ipe b1sebe w reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 fmc_pfb1cr field descriptions field description 31?28 b1rwsc[3:0] bank 1 read wait state control this read-only field defines the number of wait states required to access the bank 1 flash memory. the relationship between the read access time of the flash array (expressed in system clock cycles) and rwsc is defined as: access time of flash array [system clocks] = rwsc + 1 the fmc automatically calculates this value based on the ratio of the system clock speed to the flash clock speed. for example, when this ratio is 4:1, the field's value is 3h. 27?19 reserved this read-only field is reserved and always has the value zero. 18?17 b1mw[1:0] bank 1 memory width this read-only field defines the width of the bank 1 memory. 00 32 bits 01 64 bits 10 reserved 11 reserved 16 reserved this read-only field is reserved and always has the value zero. 15?8 reserved this read-only field is reserved and always has the value zero. 7?5 reserved this read-only field is reserved and always has the value zero. table continues on the next page... chapter 27 flash memory controller fmc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 60 fmc_pfb1cr field descriptions (continued) field description 4 b1dce bank 1 data cache enable this bit controls whether data references are loaded into the cache. 0 do not cache data references. 1 cache data references. 3 b1ice bank 1 instruction cache enable this bit controls whether instruction fetches are loaded into the cache. 0 do not cache instruction fetches. 1 cache instruction fetches. 2 b1dpe bank 1 data prefetch enable this bit controls whether prefetches (or speculative accesses) are initiated in response to data references. 0 do not prefetch in response to data references. 1 enable prefetches in response to data references. 1 b1ipe bank 1 instruction prefetch enable this bit controls whether prefetches (or speculative accesses) are initiated in response to instruction fetches. 0 do not prefetch in response to instruction fetches. 1 enable prefetches in response to instruction fetches. 0 b1sebe bank 1 single entry buffer enable this bit controls whether the single entry buffer is enabled in response to flash read accesses. its operation is independent from bank 0s cache. a high-to-low transition of this enable forces the page buffer to be invalidated. 0 single entry buffer is disabled. 1 single entry buffer is enabled. memory map and register descriptions k60 sub-family reference manual, rev. 6, nov 2011 604 freescale semiconductor, inc. 27.4.4 cache tag storage (fmc_tagvdw0s n the 32-entry cache is a 4-way, set-associative cache with 8 sets. the ways are numbered 0-3 and the sets are numbered 0-7. in tagvdwxsy, x denotes the way, and y denotes the set. this section represents tag/vld information for all 8 sets (n=0-7) in way 0. addresses: fmc_tagvdw0s0 is 4001_f000h base + 100h offset = 4001_f100h fmc_tagvdw0s1 is 4001_f000h base + 104h offset = 4001_f104h fmc_tagvdw0s2 is 4001_f000h base + 108h offset = 4001_f108h fmc_tagvdw0s3 is 4001_f000h base + 10ch offset = 4001_f10ch fmc_tagvdw0s4 is 4001_f000h base + 110h offset = 4001_f110h fmc_tagvdw0s5 is 4001_f000h base + 114h offset = 4001_f114h fmc_tagvdw0s6 is 4001_f000h base + 118h offset = 4001_f118h fmc_tagvdw0s7 is 4001_f000h base + 11ch offset = 4001_f11ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 tag[18:6] 0 valid w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fmc_tagvdw0s n iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero ta: it ta or cache entry resere his reaonly iel is resere an always has the alue ero ali it ali or cache entry hater flash eory ontroller f ufaily reerence anual re o freescale eiconuctor nc 27.4.5 cache tag storage (fmc_tagvdw1s n the 32-entry cache is a 4-way, set-associative cache with 8 sets. the ways are numbered 0-3 and the sets are numbered 0-7. in tagvdwxsy, x denotes the way, and y denotes the set. this section represents tag/vld information for all 8 sets (n=0-7) in way 1. addresses: fmc_tagvdw1s0 is 4001_f000h base + 120h offset = 4001_f120h fmc_tagvdw1s1 is 4001_f000h base + 124h offset = 4001_f124h fmc_tagvdw1s2 is 4001_f000h base + 128h offset = 4001_f128h fmc_tagvdw1s3 is 4001_f000h base + 12ch offset = 4001_f12ch fmc_tagvdw1s4 is 4001_f000h base + 130h offset = 4001_f130h fmc_tagvdw1s5 is 4001_f000h base + 134h offset = 4001_f134h fmc_tagvdw1s6 is 4001_f000h base + 138h offset = 4001_f138h fmc_tagvdw1s7 is 4001_f000h base + 13ch offset = 4001_f13ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 tag[18:6] 0 valid w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fmc_tagvdw1s n iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero ta: it ta or cache entry resere his reaonly iel is resere an always has the alue ero ali it ali or cache entry eory a an reister escritions ufaily reerence anual re o freescale eiconuctor nc 27.4.6 cache tag storage (fmc_tagvdw2s n the 32-entry cache is a 4-way, set-associative cache with 8 sets. the ways are numbered 0-3 and the sets are numbered 0-7. in tagvdwxsy, x denotes the way, and y denotes the set. this section represents tag/vld information for all 8 sets (n=0-7) in way 2. addresses: fmc_tagvdw2s0 is 4001_f000h base + 140h offset = 4001_f140h fmc_tagvdw2s1 is 4001_f000h base + 144h offset = 4001_f144h fmc_tagvdw2s2 is 4001_f000h base + 148h offset = 4001_f148h fmc_tagvdw2s3 is 4001_f000h base + 14ch offset = 4001_f14ch fmc_tagvdw2s4 is 4001_f000h base + 150h offset = 4001_f150h fmc_tagvdw2s5 is 4001_f000h base + 154h offset = 4001_f154h fmc_tagvdw2s6 is 4001_f000h base + 158h offset = 4001_f158h fmc_tagvdw2s7 is 4001_f000h base + 15ch offset = 4001_f15ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 tag[18:6] 0 valid w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fmc_tagvdw2s n iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero ta: it ta or cache entry resere his reaonly iel is resere an always has the alue ero ali it ali or cache entry hater flash eory ontroller f ufaily reerence anual re o freescale eiconuctor nc 27.4.7 cache tag storage (fmc_tagvdw3s n the 32-entry cache is a 4-way, set-associative cache with 8 sets. the ways are numbered 0-3 and the sets are numbered 0-7. in tagvdwxsy, x denotes the way, and y denotes the set. this section represents tag/vld information for all 8 sets (n=0-7) in way 3. addresses: fmc_tagvdw3s0 is 4001_f000h base + 160h offset = 4001_f160h fmc_tagvdw3s1 is 4001_f000h base + 164h offset = 4001_f164h fmc_tagvdw3s2 is 4001_f000h base + 168h offset = 4001_f168h fmc_tagvdw3s3 is 4001_f000h base + 16ch offset = 4001_f16ch fmc_tagvdw3s4 is 4001_f000h base + 170h offset = 4001_f170h fmc_tagvdw3s5 is 4001_f000h base + 174h offset = 4001_f174h fmc_tagvdw3s6 is 4001_f000h base + 178h offset = 4001_f178h fmc_tagvdw3s7 is 4001_f000h base + 17ch offset = 4001_f17ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 tag[18:6] 0 valid w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fmc_tagvdw3s n iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero ta: it ta or cache entry resere his reaonly iel is resere an always has the alue ero ali it ali or cache entry eory a an reister escritions ufaily reerence anual re o freescale eiconuctor nc 27.4.8 cache data storage (upper word) (fmc_dataw0su) the cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. the ways are numbered 0-3 and the sets are numbered 0-7. in datawxsyu and datawxsyl, x denotes the way, y denotes the set, and u and l represent upper and lower word, respectively. this section represents data for the upper word (bits [63:32]) of all 8 sets (n=0-7) in way 0. addresses: fmc_dataw0s0u is 4001_f000h base + 200h offset = 4001_f200h fmc_dataw0s1u is 4001_f000h base + 208h offset = 4001_f208h fmc_dataw0s2u is 4001_f000h base + 210h offset = 4001_f210h fmc_dataw0s3u is 4001_f000h base + 218h offset = 4001_f218h fmc_dataw0s4u is 4001_f000h base + 220h offset = 4001_f220h fmc_dataw0s5u is 4001_f000h base + 228h offset = 4001_f228h fmc_dataw0s6u is 4001_f000h base + 230h offset = 4001_f230h fmc_dataw0s7u is 4001_f000h base + 238h offset = 4001_f238h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r data[63:32] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fmc_dataw0s n u iel escritions fiel escrition ata: its : o ata entry hater flash eory ontroller f ufaily reerence anual re o freescale eiconuctor nc 27.4.9 cache data storage (lower word) (fmc_dataw0sl) the cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. the ways are numbered 0-3 and the sets are numbered 0-7. in datawxsyu and datawxsyl, x denotes the way, y denotes the set, and u and l represent upper and lower word, respectively. this section represents data for the lower word (bits [31:0]) of all 8 sets (n=0-7) in way 0. addresses: fmc_dataw0s0l is 4001_f000h base + 204h offset = 4001_f204h fmc_dataw0s1l is 4001_f000h base + 20ch offset = 4001_f20ch fmc_dataw0s2l is 4001_f000h base + 214h offset = 4001_f214h fmc_dataw0s3l is 4001_f000h base + 21ch offset = 4001_f21ch fmc_dataw0s4l is 4001_f000h base + 224h offset = 4001_f224h fmc_dataw0s5l is 4001_f000h base + 22ch offset = 4001_f22ch fmc_dataw0s6l is 4001_f000h base + 234h offset = 4001_f234h fmc_dataw0s7l is 4001_f000h base + 23ch offset = 4001_f23ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r data[31:0] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fmc_dataw0s n l iel escritions fiel escrition ata: its : o ata entry eory a an reister escritions ufaily reerence anual re o freescale eiconuctor nc 27.4.10 cache data storage (upper word) (fmc_dataw1su) the cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. the ways are numbered 0-3 and the sets are numbered 0-7. in datawxsyu and datawxsyl, x denotes the way, y denotes the set, and u and l represent upper and lower word, respectively. this section represents data for the upper word (bits [63:32]) of all 8 sets (n=0-7) in way 1. addresses: fmc_dataw1s0u is 4001_f000h base + 240h offset = 4001_f240h fmc_dataw1s1u is 4001_f000h base + 248h offset = 4001_f248h fmc_dataw1s2u is 4001_f000h base + 250h offset = 4001_f250h fmc_dataw1s3u is 4001_f000h base + 258h offset = 4001_f258h fmc_dataw1s4u is 4001_f000h base + 260h offset = 4001_f260h fmc_dataw1s5u is 4001_f000h base + 268h offset = 4001_f268h fmc_dataw1s6u is 4001_f000h base + 270h offset = 4001_f270h fmc_dataw1s7u is 4001_f000h base + 278h offset = 4001_f278h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r data[63:32] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fmc_dataw1s n u iel escritions fiel escrition ata: its : o ata entry hater flash eory ontroller f ufaily reerence anual re o freescale eiconuctor nc 27.4.11 cache data storage (lower word) (fmc_dataw1sl) the cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. the ways are numbered 0-3 and the sets are numbered 0-7. in datawxsyu and datawxsyl, x denotes the way, y denotes the set, and u and l represent upper and lower word, respectively. this section represents data for the lower word (bits [31:0]) of all 8 sets (n=0-7) in way 1. addresses: fmc_dataw1s0l is 4001_f000h base + 244h offset = 4001_f244h fmc_dataw1s1l is 4001_f000h base + 24ch offset = 4001_f24ch fmc_dataw1s2l is 4001_f000h base + 254h offset = 4001_f254h fmc_dataw1s3l is 4001_f000h base + 25ch offset = 4001_f25ch fmc_dataw1s4l is 4001_f000h base + 264h offset = 4001_f264h fmc_dataw1s5l is 4001_f000h base + 26ch offset = 4001_f26ch fmc_dataw1s6l is 4001_f000h base + 274h offset = 4001_f274h fmc_dataw1s7l is 4001_f000h base + 27ch offset = 4001_f27ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r data[31:0] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fmc_dataw1s n l iel escritions fiel escrition ata: its : o ata entry eory a an reister escritions ufaily reerence anual re o freescale eiconuctor nc 27.4.12 cache data storage (upper word) (fmc_dataw2su) the cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. the ways are numbered 0-3 and the sets are numbered 0-7. in datawxsyu and datawxsyl, x denotes the way, y denotes the set, and u and l represent upper and lower word, respectively. this section represents data for the upper word (bits [63:32]) of all 8 sets (n=0-7) in way 2. addresses: fmc_dataw2s0u is 4001_f000h base + 280h offset = 4001_f280h fmc_dataw2s1u is 4001_f000h base + 288h offset = 4001_f288h fmc_dataw2s2u is 4001_f000h base + 290h offset = 4001_f290h fmc_dataw2s3u is 4001_f000h base + 298h offset = 4001_f298h fmc_dataw2s4u is 4001_f000h base + 2a0h offset = 4001_f2a0h fmc_dataw2s5u is 4001_f000h base + 2a8h offset = 4001_f2a8h fmc_dataw2s6u is 4001_f000h base + 2b0h offset = 4001_f2b0h fmc_dataw2s7u is 4001_f000h base + 2b8h offset = 4001_f2b8h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r data[63:32] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fmc_dataw2s n u iel escritions fiel escrition ata: its : o ata entry hater flash eory ontroller f ufaily reerence anual re o freescale eiconuctor nc 27.4.13 cache data storage (lower word) (fmc_dataw2sl) the cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. the ways are numbered 0-3 and the sets are numbered 0-7. in datawxsyu and datawxsyl, x denotes the way, y denotes the set, and u and l represent upper and lower word, respectively. this section represents data for the lower word (bits [31:0]) of all 8 sets (n=0-7) in way 2. addresses: fmc_dataw2s0l is 4001_f000h base + 284h offset = 4001_f284h fmc_dataw2s1l is 4001_f000h base + 28ch offset = 4001_f28ch fmc_dataw2s2l is 4001_f000h base + 294h offset = 4001_f294h fmc_dataw2s3l is 4001_f000h base + 29ch offset = 4001_f29ch fmc_dataw2s4l is 4001_f000h base + 2a4h offset = 4001_f2a4h fmc_dataw2s5l is 4001_f000h base + 2ach offset = 4001_f2ach fmc_dataw2s6l is 4001_f000h base + 2b4h offset = 4001_f2b4h fmc_dataw2s7l is 4001_f000h base + 2bch offset = 4001_f2bch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r data[31:0] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fmc_dataw2s n l iel escritions fiel escrition ata: its : o ata entry eory a an reister escritions ufaily reerence anual re o freescale eiconuctor nc 27.4.14 cache data storage (upper word) (fmc_dataw3su) the cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. the ways are numbered 0-3 and the sets are numbered 0-7. in datawxsyu and datawxsyl, x denotes the way, y denotes the set, and u and l represent upper and lower word, respectively. this section represents data for the upper word (bits [63:32]) of all 8 sets (n=0-7) in way 3. addresses: fmc_dataw3s0u is 4001_f000h base + 2c0h offset = 4001_f2c0h fmc_dataw3s1u is 4001_f000h base + 2c8h offset = 4001_f2c8h fmc_dataw3s2u is 4001_f000h base + 2d0h offset = 4001_f2d0h fmc_dataw3s3u is 4001_f000h base + 2d8h offset = 4001_f2d8h fmc_dataw3s4u is 4001_f000h base + 2e0h offset = 4001_f2e0h fmc_dataw3s5u is 4001_f000h base + 2e8h offset = 4001_f2e8h fmc_dataw3s6u is 4001_f000h base + 2f0h offset = 4001_f2f0h fmc_dataw3s7u is 4001_f000h base + 2f8h offset = 4001_f2f8h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r data[63:32] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fmc_dataw3s n u iel escritions fiel escrition ata: its : o ata entry hater flash eory ontroller f ufaily reerence anual re o freescale eiconuctor nc 27.4.15 cache data storage (lower word) (fmc_dataw3sl) the cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. the ways are numbered 0-3 and the sets are numbered 0-7. in datawxsyu and datawxsyl, x denotes the way, y denotes the set, and u and l represent upper and lower word, respectively. this section represents data for the lower word (bits [31:0]) of all 8 sets (n=0-7) in way 3. addresses: fmc_dataw3s0l is 4001_f000h base + 2c4h offset = 4001_f2c4h fmc_dataw3s1l is 4001_f000h base + 2cch offset = 4001_f2cch fmc_dataw3s2l is 4001_f000h base + 2d4h offset = 4001_f2d4h fmc_dataw3s3l is 4001_f000h base + 2dch offset = 4001_f2dch fmc_dataw3s4l is 4001_f000h base + 2e4h offset = 4001_f2e4h fmc_dataw3s5l is 4001_f000h base + 2ech offset = 4001_f2ech fmc_dataw3s6l is 4001_f000h base + 2f4h offset = 4001_f2f4h fmc_dataw3s7l is 4001_f000h base + 2fch offset = 4001_f2fch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r data[31:0] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fmc_dataw3s n l iel escritions fiel escrition ata: its : o ata entry functional escrition the fmc is a flash acceleration unit with flexible buffers for user configuration. besides managing the interface between the device and the flash memory and flexmemory, the fmc can be used to restrict access from crossbar switch masters and customize the cache and buffers to provide single-cycle system-clock data-access times. whenever a hit occurs for the prefetch speculation buffer, the cache, or the single-entry buffer, the requested data is transferred within a single system clock. upon system reset, the fmc is configured to provide a significant level of buffering for transfers from the flash memory or flexmemory: ? crossbar masters 0, 1, 2 have read access to bank 0 and bank 1. functional description k60 sub-family reference manual, rev. 6, nov 2011 616 freescale semiconductor, inc. ? these masters have write access to a portion of bank 1 when flexnvm is used with flexram as eeprom. ? for bank 0 and bank 1: ? prefetch support for data and instructions is enabled for crossbar masters 0, 1, 2. ? the cache is configured for least recently used (lru) replacement for all four ways. ? the cache is configured for data or instruction replacement. ? the single-entry buffer is enabled. though the default configuration provides a high degree of flash acceleration, advanced users may desire to customize the fmc buffer configurations to maximize throughput for their use cases. when reconfiguring the fmc for custom use cases, do not program the fmc's control registers while the flash memory or flexmemory is being accessed. instead, change the control registers with a routine executing from ram in supervisor mode. the fmc's cache and buffering controls within pfb0cr and pfb1cr allow the tuning of resources to suit particular applications' needs. the cache and two buffers are each controlled individually. the register controls enable buffering and prefetching per memory bank and access type (instruction fetch or data reference). the cache also supports three types of lru replacement algorithms: ? lru per set across all four ways, ? lru with ways [0-1] for instruction fetches and ways [2-3] for data fetches, and ? lru with ways [0-2] for instruction fetches and way [3] for data fetches. as an application example: if both instruction fetches and data references are accessing bank 0, control is available to send instruction fetches, data references, or both to the cache or the single-entry buffer. likewise, speculation can be enabled or disabled for either type of access. if both instruction fetches and data references are cached, the cache's way resources may be divided in several ways between the instruction fetches and data references. in another application example, the cache can be configured for replacement from bank 0, while the single-entry buffer can be enabled for bank 1 only. this configuration is ideal for applications that use bank 0 for program space and bank 1 for data space. chapter 27 flash memory controller (fmc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 617 functional description k60 sub-family reference manual, rev. 6, nov 2011 618 freescale semiconductor, inc. chapter 28 flash memory module (ftfl) 28.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the ftfl module includes the following accessible memory regions: ? program flash memory for vector space and code store ? for flexnvm devices: flexnvm for data store and additional code store ? for flexnvm devices: flexram for high-endurance data store or traditional ram ? for program flash only devices: programming acceleration ram to speed flash programming flash memory is ideal for single-supply applications, permitting in-the-field erase and reprogramming operations without the need for any external high voltage power sources. the ftfl module includes a memory controller that executes commands to modify flash memory contents. an erased bit reads '1' and a programmed bit reads '0'. the programming operation is unidirectional; it can only move bits from the '1' state (erased) to the '0' state (programmed). only the erase operation restores bits from '0' to '1'; bits cannot be programmed from a '0' to a '1'. caution a flash memory location must be in the erased state before being programmed. cumulative programming of bits (back-to- back program operations without an intervening erase) within a flash memory location is not allowed. re-programming of existing 0s to 0 is not allowed as this overstresses the device. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 619 the standard shipping condition for flash memory is erased with security disabled. data loss over time may occur due to degradation of the erased ('1') states and/or programmed ('0') states. therefore, it is recommended that each flash block or sector be re-erased immediately prior to factory programming to ensure that the full data retention capability is achieved. 28.1.1 features the ftfl module includes the following features. note see the device's chip configuration details for the exact amount of flash memory available on your device. 28.1.1.1 program flash memory features ? sector size of 2 kbytes ? program flash protection scheme prevents accidental program or erase of stored data ? automated, built-in, program and erase algorithms with verify ? section programming for faster bulk programming times ? for devices containing only program flash memory: read access to one logical program flash block is possible while programming or erasing data in the other logical program flash block ? for devices containing flexnvm memory: read access to program flash memory possible while programming or erasing data in the data flash memory or flexram 28.1.1.2 flexnvm memory features when flexnvm is partitioned for data flash memory (on devices that contain flexnvm memory): ? sector size of 2 kbytes ? protection scheme prevents accidental program or erase of stored data ? automated, built-in program and erase algorithms with verify introduction k60 sub-family reference manual, rev. 6, nov 2011 620 freescale semiconductor, inc. ? section programming for faster bulk programming times ? read access to data flash memory possible while programming or erasing data in the program flash memory 28.1.1.3 program acceleration ram features ? for devices with only program flash memory: ram to support section programming 28.1.1.4 flexram features for devices with flexnvm memory: ? memory that can be used as traditional ram or as high-endurance eeprom storage ? up to 4 kbytes of flexram configured for eeprom or traditional ram operations ? when configured for eeprom: ? protection scheme prevents accidental program or erase of data written for eeprom ? built-in hardware emulation scheme to automate eeprom record maintenance functions ? programmable eeprom data set size and flexnvm partition code facilitating eeprom memory endurance trade-offs ? supports flexram aligned writes of 1, 2, or 4 bytes at a time ? read access to flexram possible while programming or erasing data in the program or data flash memory ? when configured for traditional ram: ? read and write access possible to the flexram while programming or erasing data in the program or data flash memory 28.1.1.5 other ftfl module features ? internal high-voltage supply generator for flash memory program and erase operations chapter 28 flash memory module (ftfl) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 621 ? optional interrupt generation upon flash command completion ? supports mcu security mechanisms which prevent unauthorized access to the flash memory contents 28.1.2 block diagram the block diagram of the ftfl module is shown in the following figure. for devices with flexnvm feature: flexnvm flexram program flash eeprom backup to mcu's flash controller interrupt control registers status registers register access data flash memory controller figure 28-1. ftfl block diagram for devices that contain only program flash: introduction k60 sub-family reference manual, rev. 6, nov 2011 622 freescale semiconductor, inc. program flash 1 programming acceleration ram program flash 0 to mcu's flash controller interrupt control registers status registers register access memory controller figure 28-2. ftfl block diagram 28.1.3 glossary command write sequence a series of mcu writes to the flash fccob register group that initiates and controls the execution of flash algorithms that are built into the ftfl module. data flash memory partitioned from the flexnvm block, the data flash memory provides nonvolatile storage for user data, boot code, and additional code store. data flash sector the data flash sector is the smallest portion of the data flash memory that can be erased. eeprom using a built-in filing system, the ftfl module emulates the characteristics of an eeprom by effectively providing a high-endurance, byte-writeable (program and erase) nvm. eeprom backup data header the eeprom backup data header is comprised of a 32-bit field found in eeprom backup data memory which contains information used by the eeprom filing system to determine the status of a specific eeprom backup flash sector. chapter 28 flash memory module (ftfl) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 623 eeprom backup data record the eeprom backup data record is comprised of a 2-bit status field, a 14-bit address field, and a 16-bit data field found in eeprom backup data memory which is used by the eeprom filing system. if the status field indicates a record is valid, the data field is mirrored in the flexram at a location determined by the address field. eeprom backup data memory partitioned from the flexnvm block, eeprom backup data memory provides nonvolatile storage for the eeprom filing system representing data written to the flexram requiring highest endurance. eeprom backup data sector the eeprom backup data sector contains one eeprom backup data header and up to 255 eeprom backup data records, which are used by the eeprom filing system. endurance the number of times that a flash memory location can be erased and reprogrammed. fccob (flash common command object) a group of flash registers that are used to pass command, address, data, and any associated parameters to the memory controller in the ftfl module. flash block a macro within the ftfl module which provides the nonvolatile memory storage. flexmemory ftfl configuration that supports data flash, eeprom, and flexram. flexnvm block the flexnvm block can be configured to be used as data flash memory, eeprom backup flash memory, or a combination of both. flexram the flexram refers to a ram, dedicated to the ftfl module, that can be configured to store eeprom data or as traditional ram. when configured for eeprom, valid writes to the flexram generate new eeprom backup data records stored in the eeprom backup flash memory. ftfl module all flash blocks plus a flash management unit providing high-level control and an interface to mcu buses. ifr nonvolatile information register found in each flash block, separate from the main memory array. nvm nonvolatile memory. a memory technology that maintains stored data during power-off. the flash array is an nvm using nor-type flash memory technology. nvm normal mode an nvm mode that provides basic user access to ftfl resources. the cpu or other bus masters initiate flash program and erase operations (or other ftfl commands) using writes to the fccob register group in the ftfl module. introduction k60 sub-family reference manual, rev. 6, nov 2011 624 freescale semiconductor, inc. nvm special mode an nvm mode enabling external, off-chip access to the memory resources in the ftfl module. a reduced ftfl command set is available when the mcu is secured. see the chip configuration details for information on when this mode is used. phrase 64 bits of data with an aligned phrase having byte-address[2:0] = 000. longword 32 bits of data with an aligned longword having byte-address[1:0] = 00. word 16 bits of data with an aligned word having byte-address[0] = 0. program flash the program flash memory provides nonvolatile storage for vectors and code store. program flash sector the smallest portion of the program flash memory (consecutive addresses) that can be erased. retention the length of time that data can be kept in the nvm without experiencing errors upon readout. since erased (1) states are subject to degradation just like programmed (0) states, the data retention limit may be reached from the last erase operation (not from the programming time). rww read-while-write. the ability to simultaneously read from one memory resource while commanded operations are active in another memory resource. section program buffer lower half of the programming acceleration flexram allocated for storing large amounts of data for programming via the program section command. secure an mcu state conveyed to the ftfl module as described in the chip configuration details for this device. in the secure state, reading and changing nvm contents is restricted. 28.2 external signal description the ftfl module contains no signals that connect off-chip. 28.3 memory map and registers this section describes the memory map and registers for the ftfl module. data read from unimplemented memory space in the ftfl module is undefined. writes to unimplemented or reserved memory space (registers) in the ftfl module are ignored. chapter 28 flash memory module (ftfl) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 625 28.3.1 flash configuration field description the program flash memory contains a 16-byte flash configuration field that stores default protection settings (loaded on reset) and security information that allows the mcu to restrict access to the ftfl module. flash configuration field byte address size (bytes) field description 0x0_0400 - 0x0_0407 8 backdoor comparison key. refer to verify backdoor access key command and unsecuring the chip using backdoor key access . 0x0_0408 - 0x0_040b 4 program flash protection bytes. refer to the description of the program flash protection registers (fprot0-3). 0x0_040f 1 program flash only devices: reserved flexnvm devices: data flash protection byte. refer to the description of the data flash protection register (fdprot). 0x0_040e 1 program flash only devices: reserved flexnvm devices: eeprom protection byte. refer to the description of the eeprom protection register (feprot). 0x0_040d 1 flash nonvolatile option byte. refer to the description of the flash option register (fopt). 0x0_040c 1 flash security byte. refer to the description of the flash security register (fsec). 28.3.2 program flash ifr map the program flash ifr is nonvolatile information memory that can be read freely, but the user has no erase and limited program capabilities (see the read once, program once, and read resource commands in read once command , program once command and read resource command ). the contents of the program flash ifr are summarized in the following table and further described in the subsequent paragraphs. for devices that only contain program flash, the program flash ifr is located within the program flash 0 memory block. memory map and registers k60 sub-family reference manual, rev. 6, nov 2011 626 freescale semiconductor, inc. address range size (bytes) field description 0x00 0xbf 192 reserved 0xc0 0xff 64 program once field 28.3.2.1 program once field the program once field in the program flash ifr provides 64 bytes of user data storage separate from the program flash main array. the user can program the program once field one time only as there is no program flash ifr erase mechanism available to the user. the program once field can be read any number of times. this section of the program flash ifr is accessed in 4-byte records using the read once and program once commands (see read once command and program once command ). 28.3.3 data flash ifr map the following only applies to devices with flexnvm. the data flash ifr is a 256 byte nonvolatile information memory that can be read and erased, but the user has limited program capabilities in the data flash ifr (see the program partition command in program partition command , the erase all blocks command in erase all blocks command , and the read resource command in read resource command ). the contents of the data flash ifr are summarized in the following table and further described in the subsequent paragraphs. address range size (bytes) field description 0x00 ? 0xfb, 0xfe ? 0xff 254 reserved 0xfd 1 eeprom data set size 0xfc 1 flexnvm partition code 28.3.3.1 eeprom data set size the eeprom data set size byte in the data flash ifr supplies information which determines the amount of flexram used in each of the available eeprom subsystems. to program the eeesplit and eeesize values, see the program partition command described in program partition command . table 28-1. eeprom data set size data flash ifr: 0x00fd 7 6 5 4 3 2 1 0 table continues on the next page... chapter 28 flash memory module ftf 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 627 table 28-1. eeprom data set size (continued) 1 1 eeesplit eeesize = unimplemented or reserved table 28-2. eeprom data set size field description field description 7-6 reserved this read-only bitfield is reserved and must always be written as one. 5-4 eeesplit eeprom split factor determines the relative sizes of the two eeprom subsystems. 00? = subsystem a: eeesize*1/8, subsystem b: eeesize*7/8 01? = subsystem a: eeesize*1/4, subsystem b: eeesize*3/4 10? = subsystem a: eeesize*1/2, subsystem b: eeesize*1/2 11? = subsystem a: eeesize*1/2, subsystem b: eeesize*1/2 3-0 eeesize eeprom size encoding of the total available flexram for eeprom use. note: eeesize must be 0 bytes (1111b) when the flexnvm partition code ( flexnvm partition code ) is set to no eeprom. 0000 = reserved 0001 = reserved 0010 = 4,096 bytes 0011 = 2,048 bytes 0100 = 1,024 bytes 0101 = 512 bytes 0110 = 256 bytes 0111 = 128 bytes 1000 = 64 bytes 1001 = 32 bytes 1010 = reserved 1011 = reserved 1100 = reserved 1101 = reserved 1110 = reserved 1111 = 0 bytes 28.3.3.2 flexnvm partition code the flexnvm partition code byte in the data flash ifr supplies a code which specifies how to split the flexnvm block between data flash memory and eeprom backup memory supporting eeprom functions. to program the depart value, see the program partition command described in program partition command . memory map and registers k60 sub-family reference manual, rev. 6, nov 2011 628 freescale semiconductor, inc. table 28-3. flexnvm partition code data flash ifr: 0x00fc 7 6 5 4 3 2 1 0 1 1 1 1 depart = unimplemented or reserved table 28-4. flexnvm partition code field description field description 7-4 reserved this read-only bitfield is reserved and must always be written as one. 3-0 depart flexnvm partition code encoding of the data flash / eeprom backup split within the flexnvm memory block. flexnvm memory not partitioned for data flash will be used to store eeprom records. depart data flash (kbyte) eeprom backup (kbyte) 0000 256 0 0001 reserved reserved 0010 reserved reserved 0011 224 32 0100 192 64 0101 128 128 0110 0 256 0111 reserved reserved 1000 0 256 1001 reserved reserved 1010 reserved reserved 1011 32 224 1100 64 192 1101 128 128 1110 256 0 1111 reserved reserved 28.3.4 register descriptions the ftfl module contains a set of memory-mapped control and status registers. note while a command is running (fstat[ccif]=0), register writes are not accepted to any register except fcnfg and fstat. the no-write rule is relaxed during the start-up reset chapter 28 flash memory module (ftfl) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 629 sequence, prior to the initial rise of ccif. during this initialization period the user may write any register. all register writes are also disabled (except for registers fcnfg and fstat) whenever an erase suspend request is active (fcnfg[erssusp]=1). ftfl memory map absolute address (hex) register name width (in bits) access reset value section/ page 4002_0000 flash status register (ftfl_fstat) 8 r/w 00h 28.34.1/ 631 4002_0001 flash configuration register (ftfl_fcnfg) 8 r/w 00h 28.34.2/ 632 4002_0002 flash security register (ftfl_fsec) 8 r undefined 28.34.3/ 634 4002_0003 flash option register (ftfl_fopt) 8 r undefined 28.34.4/ 636 4002_0004 flash common command object registers (ftfl_fccob3) 8 r/w 00h 28.34.5/ 637 4002_0005 flash common command object registers (ftfl_fccob2) 8 r/w 00h 28.34.5/ 637 4002_0006 flash common command object registers (ftfl_fccob1) 8 r/w 00h 28.34.5/ 637 4002_0007 flash common command object registers (ftfl_fccob0) 8 r/w 00h 28.34.5/ 637 4002_0008 flash common command object registers (ftfl_fccob7) 8 r/w 00h 28.34.5/ 637 4002_0009 flash common command object registers (ftfl_fccob6) 8 r/w 00h 28.34.5/ 637 4002_000a flash common command object registers (ftfl_fccob5) 8 r/w 00h 28.34.5/ 637 4002_000b flash common command object registers (ftfl_fccob4) 8 r/w 00h 28.34.5/ 637 4002_000c flash common command object registers (ftfl_fccobb) 8 r/w 00h 28.34.5/ 637 4002_000d flash common command object registers (ftfl_fccoba) 8 r/w 00h 28.34.5/ 637 4002_000e flash common command object registers (ftfl_fccob9) 8 r/w 00h 28.34.5/ 637 4002_000f flash common command object registers (ftfl_fccob8) 8 r/w 00h 28.34.5/ 637 table continues on the next page... memory map and registers 60 sub-family reference manual, rev. 6, nov 2011 60 freescale semiconductor, inc. ftfl memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4002_0010 program flash protection registers (ftfl_fprot3) 8 r/w undefined 28.34.6/ 638 4002_0011 program flash protection registers (ftfl_fprot2) 8 r/w undefined 28.34.6/ 638 4002_0012 program flash protection registers (ftfl_fprot1) 8 r/w undefined 28.34.6/ 638 4002_0013 program flash protection registers (ftfl_fprot0) 8 r/w undefined 28.34.6/ 638 4002_0016 eeprom protection register (ftfl_feprot) 8 r/w undefined 28.34.7/ 639 4002_0017 data flash protection register (ftfl_fdprot) 8 r/w undefined 28.34.8/ 641 28.34.1 flash status register (ftfl_fstat) the fstat register reports the operational status of the ftfl module. the ccif, rdcolerr, accerr, and fpviol bits are readable and writable. the mgstat0 bit is read only. the unassigned bits read 0 and are not writable. note when set, the access error (accerr) and flash protection violation (fpviol) bits in this register prevent the launch of any more commands until the flag is cleared (by writing a one to it). address: ftfl_fstat is 4002_0000h base + 0h offset = 4002_0000h bit 7 6 5 4 3 2 1 0 read ccif rdcolerr accerr fpviol 0 mgstat0 write w1c w1c w1c w1c reset 0 0 0 0 0 0 0 0 ftfl_fstat field descriptions field description 7 ccif command complete interrupt flag the ccif flag indicates that a ftfl command or eeprom file system operation has completed. the ccif flag is cleared by writing a 1 to ccif to launch a command, and ccif stays low until command completion or command violation. the ccif flag is also cleared by a successful write to flexram while enabled for eee, and ccif stays low until the eeprom file system has created the associated eeprom data record. table continues on the next page... chapter 28 flash memory module ftf 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 61 ftfl_fstat field descriptions (continued) field description the ccif bit is reset to 0 but is set to 1 by the memory controller at the end of the reset initialization sequence. depending on how quickly the read occurs after reset release, the user may or may not see the 0 hardware reset value. 0 ftfl command or eeprom file system operation in progress 1 ftfl command or eeprom file system operation has completed 6 rdcolerr ftfl read collision error flag the rdcolerr error bit indicates that the mcu attempted a read from an ftfl resource that was being manipulated by an ftfl command (ccif=0). any simultaneous access is detected as a collision error by the block arbitration logic. the read data in this case cannot be guaranteed. the rdcolerr bit is cleared by writing a 1 to it. writing a 0 to rdcolerr has no effect. 0 no collision error detected 1 collision error detected 5 accerr flash access error flag the accerr error bit indicates an illegal access has occurred to an ftfl resource caused by a violation of the command write sequence or issuing an illegal ftfl command. while accerr is set, the ccif flag cannot be cleared to launch a command. the accerr bit is cleared by writing a 1 to it. writing a 0 to the accerr bit has no effect. 0 no access error detected 1 access error detected 4 fpviol flash protection violation flag the fpviol error bit indicates an attempt was made to program or erase an address in a protected area of program flash or data flash memory during a command write sequence or a write was attempted to a protected area of the flexram while enabled for eeprom . while fpviol is set, the ccif flag cannot be cleared to launch a command. the fpviol bit is cleared by writing a 1 to it. writing a 0 to the fpviol bit has no effect. 0 no protection violation detected 1 protection violation detected 31 reserved this read-only field is reserved and always has the value zero. 0 mgstat0 memory controller command completion status flag the mgstat0 status flag is set if an error is detected during execution of an ftfl command or during the flash reset sequence. as a status flag, this bit cannot (and need not) be cleared by the user like the other error flags in this register. the value of the mgstat0 bit for "command-n" is valid only at the end of the "command-n" execution when ccif=1 and before the next command has been launched. at some point during the execution of "command-n+1," the previous result is discarded and any previous error is cleared. 28.34.2 flash configuration register (ftfl_fcnfg) this register provides information on the current functional state of the ftfl module. memory map and registers k60 sub-family reference manual, rev. 6, nov 2011 632 freescale semiconductor, inc. the erase control bits (ersareq and erssusp) have write restrictions. swap, pflsh, ramrdy , and eeerdy are read-only status bits . the unassigned bits read as noted and are not writable. the reset values for the swap, pflsh, ramrdy , and eeerdy bits are determined during the reset sequence. address: ftfl_fcnfg is 4002_0000h base + 1h offset = 4002_0001h bit 7 6 5 4 3 2 1 0 read ccie rdcollie ersareq erssusp swap pflsh ramrdy eeerdy write reset 0 0 0 0 0 0 0 0 ftfl_fcnfg field descriptions field description 7 ccie command complete interrupt enable the ccie bit controls interrupt generation when an ftfl command completes. 0 command complete interrupt disabled 1 command complete interrupt enabled. an interrupt request is generated whenever the fstat[ccif] flag is set. 6 rdcollie read collision error interrupt enable the rdcollie bit controls interrupt generation when an ftfl read collision error occurs. 0 read collision error interrupt disabled 1 read collision error interrupt enabled. an interrupt request is generated whenever an ftfl read collision error is detected (see the description of fstat[rdcolerr]). 5 ersareq erase all request this bit issues a request to the memory controller to execute the erase all blocks command and release security. ersareq is not directly writable but is under indirect user control. refer to the device's chip configuration details on how to request this command. the ersareq bit sets when an erase all request is triggered external to the ftfl and ccif is set (no command is currently being executed). ersareq is cleared by the ftfl when the operation completes. 0 no request or request complete 1 request to: 1. run the erase all blocks command, 2. verify the erased state, 3. program the security byte in the flash configuration field to the unsecure state, and 4. release mcu security by setting the fsec[sec] field to the unsecure state. 4 erssusp erase suspend the erssusp bit allows the user to suspend (interrupt) the erase flash sector command while it is executing. 0 no suspend requested 1 suspend the current erase flash sector command execution. 3 swap swap table continues on the next page... chapter 28 flash memory module ftf 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 6 ftfl_fcnfg field descriptions (continued) field description for program flash only configurations, the swap flag indicates which physical program flash block is located at relative address 0x0000. the state of the swap flag is set by the ftfl during the reset sequence . see the swap control command section for information on swap management. 0 physical program flash 0 is located at relative address 0x0000 1 if the pflsh flag is set, physical program flash 1 is located at relative address 0x0000. if the pflsh flag is not set, physical program flash 0 is located at relative address 0x0000 2 pflsh ftfl configuration 0 for devices with flexnvm: ftfl configured for flexmemory that supports data flash and/or eeprom for devices with program flash only: reserved 1 for devices with flexnvm: reserved for devices with program flash only: ftfl configured for program flash only, without support for data flash and/or eeprom 1 ramrdy ram ready this flag indicates the current status of the flexram /programming acceleration ram . for devices with flexnvm: the state of the ramrdy flag is normally controlled by the set flexram function command. during the reset sequence, the ramrdy flag is cleared if the flexnvm block is partitioned for eeprom and is set if the flexnvm block is not partitioned for eeprom. the ramrdy flag is cleared if the program partition command is run to partition the flexnvm block for eeprom. the ramrdy flag sets after completion of the erase all blocks command or execution of the erase-all operation triggered external to the ftfl . for devices without flexnvm: this bit should always be set. 0 for devices with flexnvm: flexram is not available for traditional ram access. for devices without flexnvm: programming acceleration ram is not available. 1 for devices with flexnvm: flexram is available as traditional ram only; writes to the flexram do not trigger eeprom operations. for devices without flexnvm: programming acceleration ram is available. 0 eeerdy for devices with flexnvm: this flag indicates if the eeprom backup data has been copied to the flexram and is therefore available for read access. for devices without flexnvm: this field is reserved. 0 for devices with flexnvm: flexram is not available for eeprom operation. 1 for devices with flexnvm: flexram is available for eeprom operations where: ? reads from the flexram return data previously written to the flexram in eeprom mode and ? writes to the flexram clear eeerdy and launch an eeprom operation to store the written data in the flexram and eeprom backup. 28.34.3 flash security register (ftfl_fsec) this read-only register holds all bits associated with the security of the mcu and ftfl module. during the reset sequence, the register is loaded with the contents of the flash security byte in the flash configuration field located in program flash memory. the flash basis for the values is signified by x in the reset value. memory map and registers k60 sub-family reference manual, rev. 6, nov 2011 634 freescale semiconductor, inc. address: ftfl_fsec is 4002_0000h base + 2h offset = 4002_0002h bit 7 6 5 4 3 2 1 0 read keyen meen fslacc sec write reset x* x* x* x* x* x* x* x* * notes: x = undefined at reset. ? ftfl_fsec field descriptions field description 76 keyen backdoor key security enable these bits enable and disable backdoor key access to the ftfl module. 00 backdoor key access disabled 01 backdoor key access disabled (preferred keyen state to disable backdoor key access) 10 backdoor key access enabled 11 backdoor key access disabled 54 meen mass erase enable bits enables and disables mass erase capability of the ftfl module. the state of the meen bits is only relevant when the sec bits are set to secure outside of nvm normal mode. when the sec field is set to unsecure, the meen setting does not matter. 00 mass erase is enabled 01 mass erase is enabled 10 mass erase is disabled 11 mass erase is enabled 32 fslacc freescale failure analysis access code these bits enable or disable access to the flash memory contents during returned part failure analysis at freescale. when sec is secure and fslacc is denied, access to the program flash contents is denied and any failure analysis performed by freescale factory test must begin with a full erase to unsecure the part. when access is granted (sec is unsecure, or sec is secure and fslacc is granted), freescale factory testing has visibility of the current flash contents. the state of the fslacc bits is only relevant when the sec bits are set to secure. when the sec field is set to unsecure, the fslacc setting does not matter. 00 freescale factory access granted 01 freescale factory access denied 10 freescale factory access denied 11 freescale factory access granted 10 sec flash security these bits define the security state of the mcu. in the secure state, the mcu limits access to ftfl module resources. the limitations are defined per device and are detailed in the chip configuration details. if the ftfl module is unsecured using backdoor key access, the sec bits are forced to 10b. 00 mcu security status is secure 01 mcu security status is secure table continues on the next page... chapter 28 flash memory module ftf 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 6 ftfl_fsec field descriptions (continued) field description 10 mcu security status is unsecure (the standard shipping condition of the ftfl is unsecure.) 11 mcu security status is secure 28.34.4 flash option register (ftfl_fopt) the flash option register allows the mcu to customize its operations by examining the state of these read-only bits, which are loaded from nvm at reset. the function of the bits is defined in the device's chip configuration details. all bits in the register are read-only . during the reset sequence, the register is loaded from the flash nonvolatile option byte in the flash configuration field located in program flash memory. the flash basis for the values is signified by x in the reset value. address: ftfl_fopt is 4002_0000h base + 3h offset = 4002_0003h bit 7 6 5 4 3 2 1 0 read opt write reset x* x* x* x* x* x* x* x* * notes: x = undefined at reset. ftfl_fopt field descriptions field description 7?0 opt nonvolatile option these bits are loaded from flash to this register at reset. refer to the device's chip configuration details for the definition and use of these bits. memory map and registers k60 sub-family reference manual, rev. 6, nov 2011 636 freescale semiconductor, inc. 28.34.5 flash common command object registers (ftfl_fccob n the fccob register group provides 12 bytes for command codes and parameters. the individual bytes within the set append a 0-b hex identifier to the fccob register name: fccob0, fccob1, ..., fccobb. addresses: 4002_0000h base + 4h offset + (1d n , where n 0d to 11d bit 7 6 4 2 1 0 read ccbn write reset 0 0 0 0 0 0 0 0 ftf_fccb n iel escritions fiel escrition on he fo reister roies a coan coe an releant araeters to the eory controller he iniiual reisters that coose the fo ata set can e written in any orer ut you ust roie all neee alues which ary ro coan to coan first set u all require fo iels an then initiate the coans execution y writin a to the ff it his clears the f it which locs all fo araeter iels an they cannot e chane y the user until the coan coletes f returns to o coan uerin or queuein is roie the next coan can e loae only ater the current coan coletes oe coans return inoration to the fo reisters ny alues returne to fo are aailale or reain ater the ff la returns to y the eory controller he ollowin tale shows a eneric ffl coan orat he irst fo reister fo always contains the coan coe his it alue eines the coan to e execute he coan coe is ollowe y the araeters require or this seciic ffl coan tyically an aress anor ata alues o: he coan araeter tale is written in ters o fo uer which is equialent to the yte nuer his nuer is a reerence to the fo reister nae an is not the reister aress fo uer yical oan araeter ontents : f a coe that eines the ffl coan flash aress : flash aress : flash aress : ata yte ata yte ata yte ata yte ata yte ata yte hater flash eory oule ffl ufaily reerence anual re o freescale eiconuctor nc ftfl_fccob n iel escritions continue fiel escrition fo uer yical oan araeter ontents : ata yte ata yte fo nianness an ultiyte ccess : he fo reister rou uses a i enian aressin conention for all coan araeter iels larer than yte the ost siniicant ata resies in the lowest fo reister nuer he fo reister rou ay e rea an written as iniiual ytes aline wors ytes or aline lonwors ytes rora flash rotection reisters fflfro n the fprot registers define which logical program flash regions are protected from program and erase operations. protected flash regions cannot have their content changed; that is, these regions cannot be programmed and cannot be erased by any ftfl command. unprotected regions can be changed by program and erase operations. the four fprot registers allow 32 protectable regions. each bit protects a 1/32 region of the program flash memory. the bitfields are defined in each register as follows: program flash protection register program flash protection bits fprot0 prot[31:24] fprot1 prot[23:16] fprot2 prot[15:8] fprot3 prot[7:0] during the reset sequence, the fprot registers are loaded with the contents of the program flash protection bytes in the flash configuration field as indicated in the following table. program flash protection register flash configuration field offset address fprot0 0x0008 fprot1 0x0009 fprot2 0x000a fprot3 0x000b to change the program flash protection that is loaded during the reset sequence, unprotect the sector of program flash memory that contains the flash configuration field. then, reprogram the program flash protection byte. memory map and registers k60 sub-family reference manual, rev. 6, nov 2011 638 freescale semiconductor, inc. addresses: ftfl_fprot3 is 4002_0000h base + 10h offset = 4002_0010h ftfl_fprot2 is 4002_0000h base + 11h offset = 4002_0011h ftfl_fprot1 is 4002_0000h base + 12h offset = 4002_0012h ftfl_fprot0 is 4002_0000h base + 13h offset = 4002_0013h bit 7 6 5 4 3 2 1 0 read prot write reset x* x* x* x* x* x* x* x* * notes: x = undefined at reset. ? ftfl_fprot n iel escritions fiel escrition ro rora flash reion rotect ach rora lash reion can e rotecte ro rora an erase oerations y settin the associate ro it n oral oe: he rotection can only e increase eanin that currently unrotecte eory can e rotecte ut currently rotecte eory cannot e unrotecte ince unrotecte reions are are with a an rotecte reions use a only writes chanin s to s are accete his to transition chec is erore on a ityit asis hose fro its with to transitions are accete while all its with to transitions are inore n ecial oe: ll its o fro are writale without restriction unrotecte areas can e rotecte an rotecte areas can e unrotecte restriction: he user ust neer write to any fro reister while a coan is runnin f ryin to alter ata in any rotecte area in the rora lash eory results in a rotection iolation error an sets the ffol it ull loc erase o a rora lash loc is not ossile i it contains any rotecte reion ach it in the it rotection reister reresents o the total rora lash rora lash reion is rotecte rora lash reion is not rotecte ro rotection reister fflfro for devices with flexnvm: the feprot register defines which eeprom regions of the flexram are protected against program and erase operations. protected eeprom regions cannot have their content changed by writing to it. unprotected regions can be changed by writing to the flexram. for devices with program flash only: this register is reserved and not used. chapter 28 flash memory module (ftfl) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 639 address: ftfl_feprot is 4002_0000h base + 16h offset = 4002_0016h bit 7 6 5 4 3 2 1 0 read eprot write reset x* x* x* x* x* x* x* x* * notes: x = undefined at reset. ? ftfl_feprot field descriptions field description 70 eprot eeprom region protect for devices with program flash only: reserved for devices with flexnvm: individual eeprom regions can be protected from alteration by setting the associated eprot bit. the eprot bits are not used when the flexnvm partition code is set to data flash only. when the flexnvm partition code is set to data flash and eeprom or eeprom only, each eprot bit covers one-eighth of the configured eeprom data (see the eeprom data set size parameter description). in nvm normal mode: the protection can only be increased. this means that currently-unprotected memory can be protected, but currently-protected memory cannot be unprotected. since unprotected regions are marked with a 1 and protected regions use a 0, only writes changing 1s to 0s are accepted. this 1-to-0 transition check is performed on a bit-by-bit basis. those feprot bits with 1-to-0 transitions are accepted while all bits with 0-to-1 transitions are ignored . in nvm special mode : all bits of the feprot register are writable without restriction. unprotected areas can be protected and protected areas can be unprotected. restriction: never write to the feprot register while a command is running (ccif=0). reset: during the reset sequence, the feprot register is loaded with the contents of the flexram protection byte in the flash configuration field located in program flash. the flash basis for the reset values is signified by x in the register diagram. to change the eeprom protection that will be loaded during the reset sequence, the sector of program flash that contains the flash configuration field must be unprotected; then the eeprom protection byte must be erased and reprogrammed. trying to alter data by writing to any protected area in the eeprom results in a protection violation error and sets the fpviol bit in the fstat register. 0 for devices with program flash only: reserved for devices with flexnvm: eeprom region is protected 1 for devices with program flash only: reserved for devices with flexnvm: eeprom region is not protected memory map and registers k60 sub-family reference manual, rev. 6, nov 2011 640 freescale semiconductor, inc. 28.34.8 data flash protection register (ftfl_fdprot) the fdprot register defines which data flash regions are protected against program and erase operations. protected flash regions cannot have their content changed; that is, these regions cannot be programmed and cannot be erased by any ftfl command. unprotected regions can be changed by both program and erase operations. address: ftfl_fdprot is 4002_0000h base + 17h offset = 4002_0017h bit 7 6 5 4 3 2 1 0 read dprot write reset x* x* x* x* x* x* x* x* * notes: x = undefined at reset. ftfl_fdprot field descriptions field description 7?0 dprot data flash region protect individual data flash regions can be protected from program and erase operations by setting the associated dprot bit. each dprot bit protects one-eighth of the partitioned data flash memory space. the granularity of data flash protection cannot be less than the data flash sector size. if an unused dprot bit is set, the erase all blocks command does not execute and the fstat[fpviol] flag is set. in nvm normal mode: the protection can only be increased, meaning that currently unprotected memory can be protected but currently protected memory cannot be unprotected. since unprotected regions are marked with a 1 and protected regions use a 0, only writes changing 1s to 0s are accepted. this 1-to-0 transition check is performed on a bit-by-bit basis. those fdprot bits with 1-to-0 transitions are accepted while all bits with 0-to-1 transitions are ignored . in nvm special mode: all bits of the fdprot register are writable without restriction. unprotected areas can be protected and protected areas can be unprotected. restriction: the user must never write to the fdprot register while a command is running (ccif=0). reset: during the reset sequence, the fdprot register is loaded with the contents of the data flash protection byte in the flash configuration field located in program flash memory. the flash basis for the reset values is signified by x in the register diagram. to change the data flash protection that will be loaded during the reset sequence, unprotect the sector of program flash that contains the flash configuration field. then, erase and reprogram the data flash protection byte. trying to alter data with the program and erase commands in any protected area in the data flash memory results in a protection violation error and sets the fstat[fpviol] bit. a full block erase of the data flash memory (see the erase flash block command description) is not possible if the data flash memory contains any protected region or if the flexnvm block has been partitioned for eeprom. 0 data flash region is protected 1 data flash region is not protected chapter 28 flash memory module (ftfl) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 641 28.4 functional description the following sections describe functional details of the ftfl module. 28.4.1 program flash memory swap for devices that only contain program flash memory: the user can configure the logical memory map of the program flash space such that either of the two physical program flash blocks can exist at relative address 0x0000. this swap feature enables the lower half of the logical program flash space to be operational while the upper half is being updated for future use. the swap control command handles swapping the two logical p-flash memory blocks within the memory map. see swap control command for details. 28.4.2 flash protection individual regions within the flash memory can be protected from program and erase operations. protection is controlled by the following registers: ? fprot n four registers that protect 32 regions of the program flash memory as shown in the following figure program flash size / 32 program flash size / 32 program flash size / 32 program flash size / 32 program flash size / 32 program flash size / 32 program flash size / 32 fprot3[prot0] 0x0_0000 fprot3[prot1] fprot3[prot2] fprot3[prot3] fprot0[prot29] fprot0[prot31] fprot0[prot30] program flash last program flash address figure 28-27. program flash protection functional description k60 sub-family reference manual, rev. 6, nov 2011 642 freescale semiconductor, inc. ? fdprot ? for 2 n data flash sizes, protects eight regions of the data flash memory as shown in the following figure data flash size / 8 dprot0 0x0_0000 dprot1 dprot2 dprot3 dprot5 dprot7 dprot6 flexnvm last data flash address data flash size / 8 data flash size / 8 data flash size / 8 data flash size / 8 data flash size / 8 data flash size / 8 data flash size / 8 dprot4 eeprom backup eeprom backup size (depart) last flexnvm address figure 28-28. data flash protection ? for the non-2 n data flash sizes (192kb and 224kb), the protection granularity is 32kb. therefore, for 192kb data flash size, only the dprot[5:0] bits are used, and for 224kb data flash size, only the dprot[6:0] bits are used. chapter 28 flash memory module (ftfl) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 643 32kb dprot0 0x0_0000 dprot1 dprot2 dprot3 dprot5 dprot6 224kb data flash 0x3_7fff 32kb 32kb 32kb 32kb 32kb 32kb dprot4 32kb eeprom backup 0x3_ffff 32kb dprot0 0x0_0000 dprot1 dprot2 dprot3 dprot5 192kb data flash 0x2_ffff 32kb 32kb 32kb 32kb 32kb dprot4 64kb eeprom backup 0x3_ffff figure 28-29. data flash protection (192 and 224kb) ? feprot protects eight regions of the eeprom memory as shown in the following figure eeprom size / 8 eprot0 0x0_0000 eprot1 eprot2 eprot5 eprot7 eprot6 flexram last eeprom address eeprom size / 8 eeprom size / 8 eeprom size / 8 eeprom size / 8 eeprom size / 8 eeprom size / 8 eeprom size / 8 eprot3 eprot4 unavailable eeprom size (eeesize) last flexram address figure 28-30. eeprom protection functional description k60 sub-family reference manual, rev. 6, nov 2011 644 freescale semiconductor, inc. 28.4.3 flexnvm description this section describes the flexnvm memory. this section does not apply for devices that contain only program flash memory. 28.4.3.1 flexnvm block partitioning for flexram the user can configure the flexnvm block as either: ? basic data flash, ? eeprom flash records to support the built-in eeprom feature, or ? a combination of both. the user's flexnvm configuration choice is specified using the program partition command described in program partition command . caution while different partitions of the flexnvm block are available, the intention is that a single partition choice is used throughout the entire lifetime of a given application. the flexnvm partition code choices affect the endurance and data retention characteristics of the device. 28.4.3.2 eeprom user perspective the eeprom system is shown in the following figure. file system handler user access (effective eeprom) flexram eeprom backup with 1kbyte erase sectors figure 28-31. top level eeprom architecture to handle varying customer requirements, the flexram and flexnvm blocks can be split into partitions as shown in the figure below. 1. eeprom partition (eeesize) the amount of flexram used for eeprom can be set from 0 bytes (no eeprom) to the maximum flexram size (see table 28-2 ). the remainder of the flexram is not accessible while the flexram is chapter 28 flash memory module (ftfl) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 645 configured for eeprom (see set flexram function command ). the eeprom partition grows upward from the bottom of the flexram address space. 2. data flash partition (depart) the amount of flexnvm memory used for data flash can be programmed from 0 bytes (all of the flexnvm block is available for eeprom backup) to the maximum size of the flexnvm block (see table 28-4 ). 3. flexnvm eeprom partition the amount of flexnvm memory used for eeprom backup, which is equal to the flexnvm block size minus the data flash memory partition size. the eeprom backup size must be at least 16 times the eeprom partition size in flexram. 4. eeprom split factor (eeesplit) the flexram partitioned for eeprom can be divided into two subsystems, each backed by half of the partitioned eeprom backup. one subsystem (a) is 1/8, 1/4, or 1/2 of the partitioned flexram with the remainder belonging to the other subsystem (b). the partition information (eeesize, depart, eeesplit) is stored in the data flash ifr and is programmed using the program partition command (see program partition command ). typically, the program partition command is executed only once in the lifetime of the device. data flash memory is useful for applications that need to quickly store large amounts of data or store data that is static. the eeprom partition in flexram is useful for storing smaller amounts of data that will be changed often. the eeprom partition in flexram can be further sub-divided to provide subsystems, each backed by the same amount of eeprom backup with subsystem a having higher endurance if the split factor is 1/8 or 1/4. functional description k60 sub-family reference manual, rev. 6, nov 2011 646 freescale semiconductor, inc. flexram data flash 1 depart /2 eeprom backup b flexnvm block 1 subsystem b eeesize unavailable eeprom partition a depart /2 flexnvm block 0 subsystem a size of eeprom partition a = eeesize x eeesplit data flash 0 and 1 interleaved data flash 0 eeprom partition b eeprom backup a eeesplit = 1/8, 1/4, or 1/2 figure 28-32. flexram to flexnvm memory mapping with 2 sub-systems 28.4.3.3 eeprom implementation overview out of reset with the fstat[ccif] bit clear, the partition settings (eeesize, depart, eeesplit) are read from the data flash ifr and the eeprom file system is initialized accordingly. the eeprom file system locates all valid eeprom data records in eeprom backup and copies the newest data to flexram. the fstat[ccif] and fcnfg[eeerdy] bits are set after data from all valid eeprom data records is copied to the flexram. after the ccif bit is set, the flexram is available for read or write access. when configured for eeprom use, writes to an unprotected location in flexram invokes the eeprom file system to program a new eeprom data record in the eeprom backup memory in a round-robin fashion. as needed, the eeprom file system identifies the eeprom backup sector that is being erased for future use and partially erases that eeprom backup sector. after a write to the flexram, the flexram is not accessible until the fstat[ccif] bit is set. the fcnfg[eeerdy] bit will also be set. if enabled, the interrupt associated with the fstat[ccif] bit can be used to determine when the flexram is available for read or write access. chapter 28 flash memory module (ftfl) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 647 after a sector in eeprom backup is full of eeprom data records, eeprom data records from the sector holding the oldest data are gradually copied over to a previously- erased eeprom backup sector. when the sector copy completes, the eeprom backup sector holding the oldest data is tagged for erase. 28.4.3.4 write endurance to flexram for eeprom when the flexnvm partition code is not set to full data flash, the eeprom data set size can be set to any of several non-zero values. the bytes not assigned to data flash via the flexnvm partition code are used by the ftfl to obtain an effective endurance increase for the eeprom data. the built-in eeprom record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the eeprom data through a larger eeprom nvm storage space. while different partitions of the flexnvm are available, the intention is that a single choice for the flexnvm partition code and eeprom data set size is used throughout the entire lifetime of a given application. the eeprom endurance equation and graph shown below assume that only one configuration is ever used. writes_subsystem = write_efficiency n eeprom ? 2 eeesplit eeesize eeesplit eeesize nvmcycd where ? writes_subsystem minimum number of writes to each flexram location for subsystem (each subsystem can have different endurance) ? eeprom allocated flexnvm for each eeprom subsystem based on depart; entered with program partition command ? eeesplit flexram split factor for subsystem; entered with the program partition command ? eeesize allocated flexram based on depart; entered with program partition command ? write_efficiency ? 0.25 for 8-bit writes to flexram ? 0.50 for 16-bit or 32-bit writes to flexram ? n nvmcycd data flash cycling endurance functional description k60 sub-family reference manual, rev. 6, nov 2011 648 freescale semiconductor, inc. figure 28-33. eeprom backup writes to flexram 28.4.4 interrupts the ftfl module can generate interrupt requests to the mcu upon the occurrence of various ftfl events. these interrupt events and their associated status and control bits are shown in the following table. table 28-30. ftfl interrupt sources ftfl event readable status bit interrupt enable bit ftfl command complete fstat[ccif] fcnfg[ccie] ftfl read collision error fstat[rdcolerr] fcnfg[rdcollie] note vector addresses and their relative interrupt priority are determined at the mcu level. chapter 28 flash memory module (ftfl) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 649 flash operation in low-power modes 28.4.5.1 wait mode when the mcu enters wait mode, the ftfl module is not affected. the ftfl module can recover the mcu from wait via the command complete interrupt (see interrupts ). 28.4.5.2 stop mode when the mcu requests stop mode, if an ftfl command is active (ccif = 0) the command execution completes before the mcu is allowed to enter stop mode. caution the mcu should never enter stop mode while any ftfl command is running (ccif = 0). note while the mcu is in very-low-power modes (vlpr, vlpw, vlps), the ftfl module does not accept flash commands. 28.4.6 functional modes of operation the ftfl module has two operating modes: nvm normal and nvm special. the operating mode affects the command set availability (see table 28-31 ). refer to the chip configuration details of this device for how to activate each mode. 28.4.7 flash reads and ignored writes the ftfl module requires only the flash address to execute a flash memory read. mcu read access is available to all flash blocks. the mcu must not read from the flash memory while commands are running (as evidenced by ccif=0) on that block. read data cannot be guaranteed from a flash block while any command is processing within that block. the block arbitration logic detects any simultaneous access and reports this as a read collision error (see the fstat[rdcolerr] bit). 28.4.5 flash operation in low-power modes k60 sub-family reference manual, rev. 6, nov 2011 650 freescale semiconductor, inc. 28.4.8 read while write (rww) the following simultaneous accesses are allowed for devices with flexnvm: ? the user may read from the program flash memory while commands (typically program and erase operations) are active in the data flash and flexram memory space. ? the mcu can fetch instructions from program flash during both data flash program and erase operations and while eeprom backup data is maintained by the eeprom commands. ? conversely, the user may read from data flash and flexram while program and erase commands are executing on the program flash. ? when configured as traditional ram, writes to the flexram are allowed during program and data flash operations. simultaneous data flash operations and flexram writes, when flexram is used for eeprom, are not possible. the following simultaneous accesses are allowed for devices with program flash only: ? the user may read from one logical program flash memory space while commands (typically program and erase operations) are active in the other logical program flash memory space. simultaneous operations are further discussed in allowed simultaneous flash operations . 28.4.9 flash program and erase all flash functions except read require the user to setup and launch an ftfl command through a series of peripheral bus writes. the user cannot initiate any further ftfl commands until notified that the current command has completed. the ftfl command structure and operation are detailed in ftfl command operations . 28.4.10 ftfl command operations ftfl command operations are typically used to modify flash memory contents. the next sections describe: chapter 28 flash memory module (ftfl) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 651 ? the command write sequence used to set ftfl command parameters and launch execution ? a description of all ftfl commands available 28.4.10.1 command write sequence ftfl commands are specified using a command write sequence illustrated in figure 28-34 . the ftfl module performs various checks on the command (fccob) content and continues with command execution if all requirements are fulfilled. before launching a command, the accerr and fpviol bits in the fstat register must be zero and the ccif flag must read 1 to verify that any previous command has completed. if ccif is zero, the previous command execution is still active, a new command write sequence cannot be started, and all writes to the fccob registers are ignored. 28.4.10.1.1 load the fccob registers the user must load the fccob registers with all parameters required by the desired ftfl command. the individual registers that make up the fccob data set can be written in any order. 28.4.10.1.2 launch the command by clearing ccif once all relevant command parameters have been loaded, the user launches the command by clearing the fstat[ccif] bit by writing a '1' to it. the ccif flag remains zero until the ftfl command completes. the fstat register contains a blocking mechanism, which prevents a new command from launching (can't clear ccif) if the previous command resulted in an access error (fstat[accerr]=1) or a protection violation (fstat[fpviol]=1). in error scenarios, two writes to fstat are required to initiate the next command: the first write clears the error flags, the second write clears ccif. 28.4.10.1.3 command execution and error reporting the command processing has several steps: 1. the ftfl reads the command code and performs a series of parameter checks and protection checks, if applicable, which are unique to each command. flash operation in low-power modes k60 sub-family reference manual, rev. 6, nov 2011 652 freescale semiconductor, inc. if the parameter check fails, the fstat[accerr] (access error) flag is set. accerr reports invalid instruction codes and out-of bounds addresses. usually, access errors suggest that the command was not set-up with valid parameters in the fccob register group. program and erase commands also check the address to determine if the operation is requested to execute on protected areas. if the protection check fails, the fstat[fpviol] (protection error) flag is set. command processing never proceeds to execution when the parameter or protection step fails. instead, command processing is terminated after setting the fstat[ccif] bit. 2. if the parameter and protection checks pass, the command proceeds to execution. run-time errors, such as failure to erase verify, may occur during the execution phase. run-time errors are reported in the fstat[mgstat0] bit. a command may have access errors, protection errors, and run-time errors, but the run-time errors are not seen until all access and protection errors have been corrected. 3. command execution results, if applicalbe, are reported back to the user via the fccob and fstat registers. 4. the ftfl sets the fstat[ccif] bit signifying that the command has completed. the flow for a generic command write sequence is illustrated in the following figure. chapter 28 flash memory module (ftfl) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 653 clear the ccif to launch the command write 0x80 to fstat register clear the old errors access error and protection violation check fccob accerr/ fpviol set? exit write to the fccob registers to load the required command parameter. more parameters? availability check results from previous command read: fstat register write 0x30 to fstat register no yes no yes previous command complete? no ccif = 1? yes start figure 28-34. generic ftfl command write sequence flowchart 28.4.10.2 ftfl commands the following table summarizes the function of all ftfl commands. if the program flash, data flash, or flexram column is marked with an 'x', the ftfl command is relevant to that particular memory resource. flash operation in low-power modes k60 sub-family reference manual, rev. 6, nov 2011 654 freescale semiconductor, inc. fcmd command program flash 0 program flash 1 (devices with only program flash) data flash (devices with flexnvm) flexram (devices with flexnvm) function 0x00 read 1s block ? ? ? verify that a program flash or data flash block is erased. flexnvm block must not be partitioned for eeprom. 0x01 read 1s section ? ? ? verify that a given number of program flash or data flash locations from a starting address are erased. 0x02 program check ? ? ? tests previously- programmed locations at margin read levels. 0x03 read resource ifr ifr ifr read 4 bytes from program flash ifr, data flash ifr, or version id. 0x06 program longword ? ? ? program 4 bytes in a program flash block or a data flash block. 0x08 erase flash block ? ? ? erase a program flash block or data flash block. an erase of any flash block is only possible when unprotected. flexnvm block must not be partitioned for eeprom. 0x09 erase flash sector ? ? ? erase all bytes in a program flash or data flash sector. table continues on the next page... chapter 28 flash memory module ftf 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 6 fcmd command program flash 0 program flash 1 (devices with only program flash) data flash (devices with flexnvm) flexram (devices with flexnvm) function 0x0b program section ? ? ? ? program data from the section program buffer to a program flash or data flash block. 0x40 read 1s all blocks ? ? ? verify that all program flash, data flash blocks, eeprom backup data records, and data flash ifr are erased then release mcu security. 0x41 read once ifr read 4 bytes of a dedicated 64 byte field in the program flash 0 ifr. 0x43 program once ifr one-time program of 4 bytes of a dedicated 64- byte field in the program flash 0 ifr. table continues on the next page... flash peration in ow-power modes 60 sub-family reference manual, rev. 6, nov 2011 66 freescale semiconductor, inc. fcmd command program flash 0 program flash 1 (devices with only program flash) data flash (devices with flexnvm) flexram (devices with flexnvm) function 0x44 erase all blocks ? ? ? ? erase all program flash blocks, program flash 1 ifr, data flash blocks, flexram, eeprom backup data records, and data flash ifr. then, verify- erase and release mcu security. note: an erase is only possible when all memory locations are unprotected. 0x45 verify backdoor access key ? ? release mcu security after comparing a set of user-supplied security keys to those stored in the program flash. 0x46 swap control ? ? handles swap- related activities 0x80 program partition ifr ? program the flexnvm partition code and eeprom data set size into the data flash ifr. format all eeprom backup data sectors allocated for eeprom. initialize the flexram. table continues on the next page... chapter 28 flash memory module ftf 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 67 fcmd command program flash 0 program flash 1 (devices with only program flash) data flash (devices with flexnvm) flexram (devices with flexnvm) function 0x81 set flexram function x ? switches flexram function between ram and eeprom. when switching to eeprom, flexnvm is not available while valid data records are being copied from eeprom backup to flexram. 28.4.10.3 ftfl commands by mode the following table shows the ftfl commands that can be executed in each flash operating mode. table 28-31. ftfl commands by mode fcmd command nvm normal nvm special unsecure secure meen=10 unsecure secure meen=10 0x00 read 1s block 0x01 read 1s section 0x02 program check 0x03 read resource 0x06 program longword 0x08 erase flash block 0x09 erase flash sector 0x0b program section 0x40 read 1s all blocks 0x41 read once 0x43 program once 0x44 erase all blocks 0x45 verify backdoor access key table continues on the next page... flash peration in ow-power modes 60 sub-family reference manual, rev. 6, nov 2011 68 freescale semiconductor, inc. table 28-31. ftfl commands by mode (continued) fcmd command nvm normal nvm special unsecure secure meen=10 unsecure secure meen=10 0x80 program partition ? ? ? ? 0x81 set flexram function ? ? ? ? 28.4.10.4 allowed simultaneous flash operations only the operations marked 'ok' in the following table are permitted to run simultaneously on the program flash, data flash, and flexram memories. some operations cannot be executed simultaneously because certain hardware resources are shared by the memories. the priority has been placed on permitting program flash reads while program and erase operations execute on the flexnvm and flexram. this provides read (program flash) while write (flexnvm, flexram) functionality. for devices containing flexnvm: table 28-32. allowed simultaneous memory operations program flash data flash flexram read program sector erase read program sector erase read e-write 1 r-write 2 program flash read ok ok ok program ok ok ok 3 sector erase ok ok ok data flash read ok ok program ok ok ok sector erase ok ok ok flexram read ok ok ok ok e-write 1 ok r-write 2 ok ok ok ok 1. when flexram configured for eeprom (writes are effectively multi-cycle operations). 2. when flexram configured as traditional ram (writes are single-cycle operations). 3. when flexram configured as traditional ram, writes to the ram are ignored while the program section command is active (ccif = 0). for devices containing program flash only: chapter 28 flash memory module (ftfl) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 659 table 28-33. allowed simultaneous memory operations program flash 0 program flash 1 read program sector erase read program sector erase program flash 0 read ok ok program ok sector erase ok program flash 1 read ok ok program ok sector erase ok 28.4.11 margin read commands the read-1s commands (read 1s all blocks, read 1s block, and read 1s section) and the program check command have a margin choice parameter that allows the user to apply non-standard read reference levels to the program flash and data flash array reads performed by these commands. using the preset 'user' and 'factory' margin levels, these commands perform their associated read operations at tighter tolerances than a 'normal' read. these non-standard read levels are applied only during the command execution. all simple (uncommanded) flash array reads to the mcu always use the standard, un- margined, read reference level. only the 'normal' read level should be employed during normal flash usage. the non- standard, 'user' and 'factory' margin levels should be employed only in special cases. they can be used during special diagnostic routines to gain confidence that the device is not suffering from the end-of-life data loss customary of flash memory devices. erased ('1') and programmed ('0') bit states can degrade due to elapsed time and data cycling (number of times a bit is erased and re-programmed). the lifetime of the erased states is relative to the last erase operation. the lifetime of the programmed states is measured from the last program time. the 'user' and 'factory' levels become, in effect, a minimum safety margin; i.e. if the reads pass at the tighter tolerances of the 'user' and 'factory' margins, then the 'normal' reads have at least this much safety margin before they experience data loss. the 'user' margin is a small delta to the normal read reference level. 'user' margin levels can be employed to check that flash memory contents have adequate margin for normal level read operations. if unexpected read results are encountered when checking flash memory contents at the 'user' margin levels, loss of information might soon occur during 'normal' readout. flash operation in low-power modes k60 sub-family reference manual, rev. 6, nov 2011 660 freescale semiconductor, inc. the 'factory' margin is a bigger deviation from the norm, a more stringent read criteria that should only be attempted immediately (or very soon) after completion of an erase or program command, early in the cycling life. 'factory' margin levels can be used to check that flash memory contents have adequate margin for long-term data retention at the normal level setting. if unexpected results are encountered when checking flash memory contents at 'factory' margin levels, the flash memory contents should be erased and reprogrammed. caution factory margin levels must only be used during verify of the initial factory programming. 28.4.12 ftfl command description this section describes all ftfl commands that can be launched by a command write sequence. the ftfl sets the fstat[accerr] bit and aborts the command execution if any of the following illegal conditions occur: ? there is an unrecognized command code in the fccob fcmd field. ? there is an error in a fccob field for the specific commands. refer to the error handling table provided for each command. ensure that the accerr and fpviol bits in the fstat register are cleared prior to starting the command write sequence. as described in launch the command by clearing ccif , a new command cannot be launched while these error flags are set. do not attempt to read a flash block while the ftfl is running a command (ccif = 0) on that same block. the ftfl may return invalid data to the mcu with the collision error flag (fstat[rdcolerr]) set. when required by the command, address bit 23 selects between: ? program flash 0 (=0) block ? (for devices with flexnvm) data flash (=1) block ? (for devices with program flash only) program flash 1 (=1) block caution flash data must be in the erased state before being programmed. cumulative programming of bits (adding more zeros) is not allowed. chapter 28 flash memory module (ftfl) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 661 28.4.12.1 read 1s block command the read 1s block command checks to see if an entire program flash or data flash block has been erased to the specified margin level. the fccob flash address bits determine which logical block is erase-verified. table 28-34. read 1s block command fccob requirements fccob number fccob contents [7:0] 0 0x00 (rd1blk) 1 flash address [23:16] in the flash block to be verified 2 flash address [15:8] in the flash block to be verified 3 flash address [7:0] 1 in the flash block to be verified 4 read-1 margin choice 1. must be longword aligned (flash address [1:0] = 00). after clearing ccif to launch the read 1s block command, the ftfl sets the read margin for 1s according to table 28-35 and then reads all locations within the selected program flash or data flash block. when the data flash is targeted, depart must be set for no eeprom, else the read 1s block command aborts setting the fstat[accerr] bit. if the ftfl fails to read all 1s (i.e. the flash block is not fully erased), the fstat[mgstat0] bit is set. the ccif flag sets after the read 1s block operation has completed. table 28-35. margin level choices for read 1s block read margin choice margin level description 0x00 use the 'normal' read level for 1s 0x01 apply the 'user' margin to the normal read-1 level 0x02 apply the 'factory' margin to the normal read-1 level table 28-36. read 1s block command error handling error condition error bit command not available in current mode/security fstat[accerr] an invalid margin choice is specified fstat[accerr] program flash is selected and the address is out of program flash range fstat[accerr] data flash is selected and the address is out of data flash range fstat[accerr] data flash is selected with eeprom enabled fstat[accerr] flash address is not longword aligned fstat[accerr] read-1s fails fstat[mgstat0] flash operation in low-power modes k60 sub-family reference manual, rev. 6, nov 2011 662 freescale semiconductor, inc. 28.4.12.2 read 1s section command the read 1s section command checks if a section of program flash or data flash memory is erased to the specified read margin level. the read 1s section command defines the starting address and the number of phrases to be verified. table 28-37. read 1s section command fccob requirements fccob number fccob contents [7:0] 0 0x01 (rd1sec) 1 flash address [23:16] of the first phrase to be verified 2 flash address [15:8] of the first phrase to be verified 3 flash address [7:0] 1 of the first phrase to be verified 4 number of phrases to be verified [15:8] 5 number of phrases to be verified [7:0] 6 read-1 margin choice 1. must be phrase aligned (flash address [2:0] = 000). upon clearing ccif to launch the read 1s section command, the ftfl sets the read margin for 1s according to table 28-38 and then reads all locations within the specified section of flash memory. if the ftfl fails to read all 1s (i.e. the flash section is not erased), the fstat(mgstat0) bit is set. the ccif flag sets after the read 1s section operation completes. table 28-38. margin level choices for read 1s section read margin choice margin level description 0x00 use the 'normal' read level for 1s 0x01 apply the 'user' margin to the normal read-1 level 0x02 apply the 'factory' margin to the normal read-1 level table 28-39. read 1s section command error handling error condition error bit command not available in current mode/security fstat[accerr] an invalid margin code is supplied fstat[accerr] an invalid flash address is supplied fstat[accerr] flash address is not phrase aligned fstat[accerr] the requested section crosses a flash block boundary fstat[accerr] the requested number of phrases is zero fstat[accerr] read-1s fails fstat[mgstat0] chapter 28 flash memory module (ftfl) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 663 28.4.12.3 program check command the program check command tests a previously programmed program flash or data flash longword to see if it reads correctly at the specified margin level. table 28-40. program check command fccob requirements fccob number fccob contents [7:0] 0 0x02 (pgmchk) 1 flash address [23:16] 2 flash address [15:8] 3 flash address [7:0] 1 4 margin choice 8 byte 0 expected data 9 byte 1 expected data a byte 2 expected data b byte 3 expected data 1. must be longword aligned (flash address [1:0] = 00). upon clearing ccif to launch the program check command, the ftfl sets the read margin for 1s according to table 28-41 , reads the specified longword, and compares the actual read data to the expected data provided by the fccob. if the comparison at margin-1 fails, the mgstat0 bit is set. the ftfl then sets the read margin for 0s, re-reads, and compares again. if the comparison at margin-0 fails, the mgstat0 bit is set. the ccif flag is set after the program check operation completes. the supplied address must be longword aligned (the lowest two bits of the byte address must be 00): ? byte 0 data is expected at the supplied address ('start'), ? byte 1 data is expected at byte address start + 0b01, ? byte 2 data is expected at byte address start + 0b10, and ? byte 3 data is expected at byte address start + 0b11. note see the description of margin reads, margin read commands table 28-41. margin level choices for program check read margin choice margin level description 0x01 read at 'user' margin-1 and 'user' margin-0 0x02 read at 'factory' margin-1 and 'factory' margin-0 flash operation in low-power modes k60 sub-family reference manual, rev. 6, nov 2011 664 freescale semiconductor, inc. table 28-42. program check command error handling error condition error bit command not available in current mode/security fstat[accerr] an invalid flash address is supplied fstat[accerr] flash address is not longword aligned fstat[accerr] an invalid margin choice is supplied fstat[accerr] either of the margin reads does not match the expected data fstat[mgstat0] 28.4.12.4 read resource command the read resource command allows the user to read data from special-purpose memory resources located within the ftfl module. the special-purpose memory resources available include program flash ifr space, data flash ifr space, and the version id field. each resource is assigned a select code as shown in table 28-44 . table 28-43. read resource command fccob requirements fccob number fccob contents [7:0] 0 0x03 (rdrsrc) 1 flash address [23:16] 2 flash address [15:8] 3 flash address [7:0] 1 returned values 4 read data [31:24] 5 read data [23:16] 6 read data [15:8] 7 read data [7:0] user-provided values 8 resource select code (see table 28-44 ) 1. must be longword aligned (flash address [1:0] = 00). table 28-44. read resource select codes resource select code 1 description resource size local address range 0x00 ifr 256 bytes 0x0000 - 0x00ff 0x01 2 version id 8 bytes 0x0000 - 0x0007 1. flash address [23] selects between program flash (=0) and data flash (=1) resources. 2. located in program flash 0 reserved space; flash address [23] = 0 chapter 28 flash memory module (ftfl) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 665 after clearing ccif to launch the read resource command, four consecutive bytes are read from the selected resource at the provided relative address and stored in the fccob register. the ccif flag sets after the read resource operation completes. the read resource command exits with an access error if an invalid resource code is provided or if the address for the applicable area is out-of-range. table 28-45. read resource command error handling error condition error bit command not available in current mode/security fstat[accerr] an invalid resource code is entered fstat[accerr] flash address is out-of-range for the targeted resource. fstat[accerr] flash address is not longword aligned fstat[accerr] 28.4.12.5 program longword command the program longword command programs four previously-erased bytes in the program flash memory or in the data flash memory using an embedded algorithm. caution a flash memory location must be in the erased state before being programmed. cumulative programming of bits (back-to- back program operations without an intervening erase) within a flash memory location is not allowed. re-programming of existing 0s to 0 is not allowed as this overstresses the device. table 28-46. program longword command fccob requirements fccob number fccob contents [7:0] 0 0x06 (pgm4) 1 flash address [23:16] 2 flash address [15:8] 3 flash address [7:0] 1 4 byte 0 program value 5 byte 1 program value 6 byte 2 program value 7 byte 3 program value 1. must be longword aligned (flash address [1:0] = 00). flash operation in low-power modes k60 sub-family reference manual, rev. 6, nov 2011 666 freescale semiconductor, inc. upon clearing ccif to launch the program longword command, the ftfl programs the data bytes into the flash using the supplied address. the swap indicator address in each program flash block is implicitly protected from programming. the targeted flash locations must be currently unprotected (see the description of the fprot and fdprot registers) to permit execution of the program longword operation. the programming operation is unidirectional. it can only move nvm bits from the erased state ('1') to the programmed state ('0'). erased bits that fail to program to the '0' state are flagged as errors in mgstat0. the ccif flag is set after the program longword operation completes. the supplied address must be longword aligned (flash address [1:0] = 00): ? byte 0 data is written to the supplied address ('start'), ? byte 1 data is programmed to byte address start+0b01, ? byte 2 data is programmed to byte address start+0b10, and ? byte 3 data is programmed to byte address start+0b11. table 28-47. program longword command error handling error condition error bit command not available in current mode/security fstat[accerr] an invalid flash address is supplied fstat[accerr] flash address is not longword aligned fstat[accerr] flash address points to a protected area fstat[fpviol] any errors have been encountered during the verify operation fstat[mgstat0] 28.4.12.6 erase flash block command the erase flash block operation erases all addresses in a single program flash or data flash block. table 28-48. erase flash block command fccob requirements fccob number fccob contents [7:0] 0 0x08 (ersblk) 1 flash address [23:16] in the flash block to be erased 2 flash address [15:8] in the flash block to be erased 3 flash address [7:0] 1 in the flash block to be erased 1. must be longword aligned (flash address [1:0] = 00). chapter 28 flash memory module (ftfl) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 667 upon clearing ccif to launch the erase flash block command, the ftfl erases the main array of the selected flash block and verifies that it is erased. when the data flash is targeted, depart must be set for no eeprom (see table 28-4 ) else the erase flash block command aborts setting the fstat[accerr] bit. the erase flash block command aborts and sets the fstat[fpviol] bit if any region within the block is protected (see the description of the fprot and fdprot registers). the swap indicator address in each program flash block is implicitly protected from block erase unless the swap system is in the update or update-erased state and the program flash block being erased is the non-active block. if the erase verify fails, the mgstat0 bit in fstat is set. the ccif flag will set after the erase flash block operation has completed. table 28-49. erase flash block command error handling error condition error bit command not available in current mode/security fstat[accerr] program flash is selected and the address is out of program flash range fstat[accerr] data flash is selected and the address is out of data flash range fstat[accerr] data flash is selected with eeprom enabled fstat[accerr] flash address is not longword aligned fstat[accerr] any area of the selected flash block is protected fstat[fpviol] any errors have been encountered during the verify operation fstat[mgstat0] 28.4.12.7 erase flash sector command the erase flash sector operation erases all addresses in a flash sector. table 28-50. erase flash sector command fccob requirements fccob number fccob contents [7:0] 0 0x09 (ersscr) 1 flash address [23:16] in the flash sector to be erased 2 flash address [15:8] in the flash sector to be erased 3 flash address [7:0] 1 in the flash sector to be erased 1. must be phrase aligned (flash address [2:0] = 000). after clearing ccif to launch the erase flash sector command, the ftfl erases the selected program flash or data flash sector and then verifies that it is erased. the erase flash sector command aborts if the selected sector is protected (see the description of the fprot and fdprot registers). the swap indicator address in each program flash block is implicitly protected from sector erase unless the swap system is in the update or update-erased state and the program flash sector containing the swap indicator flash operation in low-power modes k60 sub-family reference manual, rev. 6, nov 2011 668 freescale semiconductor, inc. address being erased is the non-active block. if the erase-verify fails the fstat[mgstat0] bit is set. the ccif flag is set after the erase flash sector operation completes. the erase flash sector command is suspendable (see the fcnfg[erssusp] bit and figure 28-35 ). table 28-51. erase flash sector command error handling error condition error bit command not available in current mode/security fstat[accerr] an invalid flash address is supplied fstat[accerr] flash address is not phrase aligned fstat[accerr] the selected program flash or data flash sector is protected fstat[fpviol] any errors have been encountered during the verify operation fstat[mgstat0] 28.4.12.7.1 suspending an erase flash sector operation to suspend an erase flash sector operation set the fcnfg[erssusp] bit (see flash configuration field description ) when ccif is clear and the ccob command field holds the code for the erase flash sector command. during the erase flash sector operation (see erase flash sector command ), the ftfl samples the state of the erssusp bit at convenient points. if the ftfl detects that the erssusp bit is set, the erase flash sector operation is suspended and the ftfl sets ccif. while erssusp is set, all writes to ftfl registers are ignored except for writes to the fstat and fcnfg registers. if an erase flash sector operation effectively completes before the ftfl detects that a suspend request has been made, the ftfl clears the erssusp bit prior to setting ccif. when an erase flash sector operation has been successfully suspended, the ftfl sets ccif and leaves the erssusp bit set. while ccif is set, the erssusp bit can only be cleared to prevent the withdrawal of a suspend request before the ftfl has acknowledged it. 28.4.12.7.2 resuming a suspended erase flash sector operation if the erssusp bit is still set when ccif is cleared to launch the next command, the previous erase flash sector operation resumes. the ftfl acknowledges the request to resume a suspended operation by clearing the erssusp bit. a new suspend request can then be made by setting erssusp. a single erase flash sector operation can be suspended and resumed multiple times. there is a minimum elapsed time limit between the request to resume the erase flash sector operation (ccif is cleared) and the request to suspend the operation again (erssusp is set). this minimum time period is required to ensure that the erase flash sector operation will eventually complete. if the minimum period is continually violated, chapter 28 flash memory module (ftfl) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 669 i.e. the suspend requests come repeatedly and too quickly, no forward progress is made by the erase flash sector algorithm. the resume/suspend sequence runs indefinitely without completing the erase. 28.4.12.7.3 aborting a suspended erase flash sector operation the user may choose to abort a suspended erase flash sector operation by clearing the erssusp bit prior to clearing ccif for the next command launch. when a suspended operation is aborted, the ftfl starts the new command using the new fccob contents. while fcnfg[erssusp] is set, a write to the flexram while fcnfg[eeerdy] is set clears erssusp and aborts the suspended operation. the flexram write operation is executed by the ftfl. note aborting the erase leaves the bitcells in an indeterminate, partially-erased state. data in this sector is not reliable until a new erase command fully completes. the following figure shows how to suspend and resume the erase flash sector operation. flash operation in low-power modes k60 sub-family reference manual, rev. 6, nov 2011 670 freescale semiconductor, inc. restore erase algo clear suspack = 0 ersscr command (write fccob) launch/resume command (clear ccif) ccif = 1? request suspend (set erssusp) interrupt? ccif = 1? service interrupt (read flash) erssusp=0? next command (write fccob) clear erssusp enter with ccif = 1 resume ersscr no memory controller command processing suspack=1 clear erssusp execute yes done? no erssusp=1? save erase algo set ccif no yes start new resume erase? no, abort user cmd interrupt/suspend set suspack = 1 ersscr suspended command initiation yes no yes yes ersscr completed ersscr suspended erssusp=1 erssusp: bit in fcnfg register suspack: internal suspend acknowledge no yes yes no yes no ersscr completed erssusp=0 figure 28-35. suspend and resume of erase flash sector operation chapter 28 flash memory module (ftfl) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 671 28.4.12.8 program section command the program section operation programs the data found in the section program buffer to previously erased locations in the flash memory using an embedded algorithm. data is preloaded into the section program buffer by writing to the flexram while it is set to function as traditional ram (see flash sector programming ). the section program buffer is limited to the lower half of the ram. data written to the upper half of the ram is ignored and may be overwritten during program section command execution. caution a flash memory location must be in the erased state before being programmed. cumulative programming of bits (back-to- back program operations without an intervening erase) within a flash memory location is not allowed. re-programming of existing 0s to 0 is not allowed as this overstresses the device. table 28-52. program section command fccob requirements fccob number fccob contents [7:0] 0 0x0b (pgmsec) 1 flash address [23:16] 2 flash address [15:8] 3 flash address [7:0] 1 4 number of phrases to program [15:8] 5 number of phrases to program [7:0] 1. must be phrase aligned (flash address [2:0] = 000). after clearing ccif to launch the program section command, the ftfl blocks access to the programming acceleration ram (program flash only devices) or flexram (flexnvm devices) and programs the data residing in the section program buffer into the flash memory starting at the flash address provided. the starting address must be unprotected (see the description of the fprot and fdprot registers) to permit execution of the program section operation. the swap indicator address in each program flash block is implicitly protected from erase. if the swap indicator address is encountered during the program section operation, it is bypassed without setting fpviol and the contents are not programmed. programming, which is not allowed to cross a flash sector boundary, continues until all requested phrases have been programmed. the program section command also verifies that after programming, all bits requested to be programmed are programmed. flash operation in low-power modes k60 sub-family reference manual, rev. 6, nov 2011 672 freescale semiconductor, inc. after the program section operation completes, the ccif flag is set and normal access to the flexram is restored. the contents of the section program buffer may be changed by the program section operation. table 28-53. program section command error handling error condition error bit command not available in current mode/security fstat[accerr] an invalid flash address is supplied fstat[accerr] flash address is not phrase aligned fstat[accerr] the requested section crosses a program flash sector boundary fstat[accerr] the requested number of phrases is zero fstat[accerr] the space required to store data for the requested number of phrases is more than half the size of the programming acceleration ram (program flash only devices) or flexram (flexnvm devices) fstat[accerr] the flexram is not set to function as a traditional ram, i.e. set if ramrdy=0 fstat[accerr] the flash address falls in a protected area fstat[fpviol] any errors have been encountered during the verify operation fstat[mgstat0] 28.4.12.8.1 flash sector programming the process of programming an entire flash sector using the program section command is as follows: 1. if required, execute the set flexram function command to make the flexram available as traditional ram and initialize the flexram to all ones. 2. launch the erase flash sector command to erase the flash sector to be programmed. 3. beginning with the starting address of the programming acceleration ram (program flash only devices) or flexram (flexnvm devices), sequentially write enough data to the ram to fill an entire flash sector. this area of the ram serves as the section program buffer. note in step 1 , the section program buffer was initialized to all ones, the erased state of the flash memory. the section program buffer can be written to while the operation launched in step 2 is executing, i.e. while ccif = 0. 4. execute the program section command to program the contents of the section program buffer into the selected flash sector. 5. if a flash sector is larger than half the flexram, repeat steps 3 and 4 until the sector is completely programmed. 6. to program additional flash sectors, repeat steps 2 through 4 . chapter 28 flash memory module (ftfl) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 673 7. to restore eeprom functionality, execute the set flexram function command to make the flexram available as eeprom. 28.4.12.9 read 1s all blocks command the read 1s all blocks command checks if the program flash blocks, data flash blocks, eeprom backup records, and data flash ifr have been erased to the specified read margin level, if applicable, and releases security if the readout passes, i.e. all data reads as '1'. table 28-54. read 1s all blocks command fccob requirements fccob number fccob contents [7:0] 0 0x40 (rd1all) 1 read-1 margin choice after clearing ccif to launch the read 1s all blocks command, the ftfl : ? sets the read margin for 1s according to table 28-55 , ? checks the contents of the program flash, data flash, eeprom backup records, and data flash ifr are in the erased state. if the ftfl confirms that these memory resources are erased, security is released by setting the fsec[sec] field to the unsecure state. the security byte in the flash configuration field (see flash configuration field description ) remains unaffected by the read 1s all blocks command. if the read fails, i.e. all memory resources are not in the fully erased state, the fstat[mgstat0] bit is set. the eeerdy and ramrdy bits are clear during the read 1s all blocks operation and are restored at the end of the read 1s all blocks operation. the ccif flag sets after the read 1s all blocks operation has completed. table 28-55. margin level choices for read 1s all blocks read margin choice margin level description 0x00 use the 'normal' read level for 1s 0x01 apply the 'user' margin to the normal read-1 level 0x02 apply the 'factory' margin to the normal read-1 level table 28-56. read 1s all blocks command error handling error condition error bit an invalid margin choice is specified fstat[accerr] table continues on the next page... flash peration in ow-power modes 60 sub-family reference manual, rev. 6, nov 2011 674 freescale semiconductor, inc. table 28-56. read 1s all blocks command error handling (continued) error condition error bit read-1s fails fstat[mgstat0] 28.4.12.10 read once command the read once command provides read access to a reserved 64-byte field located in the program flash 0 ifr (see program flash ifr map and program once field ). access to this field is via 16 records, each 4 bytes long. the read once field is programmed using the program once command described in program once command . table 28-57. read once command fccob requirements fccob number fccob contents [7:0] 0 0x41 (rdonce) 1 read once record index (0x00 - 0x0f) 2 not used 3 not used returned values 4 read once byte 0 value 5 read once byte 1 value 6 read once byte 2 value 7 read once byte 3 value after clearing ccif to launch the read once command, a 4-byte read once record is read from the program flash ifr and stored in the fccob register. the ccif flag is set after the read once operation completes. valid record index values for the read once command range from 0x00 to 0x0f. during execution of the read once command, any attempt to read addresses within the program flash block containing this 64-byte field returns invalid data. the read once command can be executed any number of times. table 28-58. read once command error handling error condition error bit command not available in current mode/security fstat[accerr] an invalid record index is supplied fstat[accerr] chapter 28 flash memory module (ftfl) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 675 28.4.12.11 program once command the program once command enables programming to a reserved 64-byte field in the program flash 0 ifr (see program flash ifr map and program once field ). access to the program once field is via 16 records, each 4 bytes long. the program once field can be read using the read once command (see read once command ) or using the read resource command (see read resource command ). each program once record can be programmed only once since the program flash 0 ifr cannot be erased. table 28-59. program once command fccob requirements fccob number fccob contents [7:0] 0 0x43 (pgmonce) 1 program once record index (0x00 - 0x0f) 2 not used 3 not used 4 program once byte 0 value 5 program once byte 1 value 6 program once byte 2 value 7 program once byte 3 value after clearing ccif to launch the program once command, the ftfl first verifies that the selected record is erased. if erased, then the selected record is programmed using the values provided. the program once command also verifies that the programmed values read back correctly. the ccif flag is set after the program once operation has completed. the reserved program flash 0 ifr location accessed by the program once command cannot be erased and any attempt to program one of these records when the existing value is not fs (erased) is not allowed. valid record index values for the program once command range from 0x00 to 0x0f. during execution of the program once command, any attempt to read addresses within program flash 0 returns invalid data. table 28-60. program once command error handling error condition error bit command not available in current mode/security fstat[accerr] an invalid record index is supplied fstat[accerr] the requested record has already been programmed to a non-ffff value 1 fstat[accerr] any errors have been encountered during the verify operation fstat[mgstat0] 1. if a program once record is initially programmed to 0xffff_ffff, the program once command is allowed to execute again on that same record. flash operation in low-power modes k60 sub-family reference manual, rev. 6, nov 2011 676 freescale semiconductor, inc. 28.4.12.12 erase all blocks command the erase all blocks operation erases all flash memory, initializes the flexram, verifies all memory contents, and releases mcu security. table 28-61. erase all blocks command fccob requirements fccob number fccob contents [7:0] 0 0x44 (ersall) after clearing ccif to launch the erase all blocks command, the ftfl erases all program flash memory, program flash 1 ifr space, data flash memory, data flash ifr space, eeprom backup memory, and flexram, then verifies that all are erased. if the ftfl verifies that all flash memories and the flexram were properly erased, security is released by setting the fsec[sec] field to the unsecure state and the fcnfg[ramrdy] bit is set. the erase all blocks command aborts if any flash or flexram region is protected. the swap indicator address in each program flash block is not implicitly protected from the erase all blocks operation. the security byte and all other contents of the flash configuration field (see flash configuration field description ) are erased by the erase all blocks command. if the erase-verify fails, the fstat[mgstat0] bit is set. the ccif flag is set after the erase all blocks operation completes. table 28-62. erase all blocks command error handling error condition error bit command not available in current mode/security fstat[accerr] any region of the program flash memory, data flash memory, or flexram is protected fstat[fpviol] any errors have been encountered during the verify operation fstat[mgstat0] 28.4.12.12.1 triggering an erase all external to the ftfl the functionality of the erase all blocks command is also available in an uncommanded fashion outside of the flash memory. refer to the device's chip configuration details for information on this functionality. before invoking the external erase all function, the fstat[accerr and pviol] flags must be cleared and the fccob0 register must not contain 0x44. when invoked, the erase-all function erases all program flash memory, program flash 1 ifr space, data flash memory, data flash ifr space, eeprom backup, and flexram regardless of the protection settings or if the swap system has been initialized. if the post-erase verify passes, the routine then releases security by setting the fsec[sec] field register to the chapter 28 flash memory module (ftfl) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 677 unsecure state and the fcnfg[ramrdy] bit sets. the security byte in the flash configuration field is also programmed to the unsecure state. the status of the erase-all request is reflected in the fcnfg[ersareq] bit. the fcnfg[ersareq] bit is cleared once the operation completes and the normal fstat error reporting is available as described in erase all blocks command . 28.4.12.13 verify backdoor access key command the verify backdoor access key command only executes if the mode and security conditions are satisfied (see ftfl commands by mode ). execution of the verify backdoor access key command is further qualified by the fsec[keyen] bits. the verify backdoor access key command releases security if user-supplied keys in the fccob match those stored in the backdoor comparison key bytes of the flash configuration field (see flash configuration field description ). the column labelled flash configuration field offset address shows the location of the matching byte in the flash configuration field. table 28-63. verify backdoor access key command fccob requirements fccob number fccob contents [7:0] flash configuration field offset address 0 0x45 (vfykey) 1-3 not used 4 key byte 0 0x0_0000 5 key byte 1 0x0_0001 6 key byte 2 0x0_0002 7 key byte 3 0x0_0003 8 key byte 4 0x0_0004 9 key byte 5 0x0_0005 a key byte 6 0x0_0006 b key byte 7 0x0_0007 after clearing ccif to launch the verify backdoor access key command, the ftfl checks the fsec[keyen] bits to verify that this command is enabled. if not enabled, the ftfl sets the fstat[accerr] bit and terminates. if the command is enabled, the ftfl compares the key provided in fccob to the backdoor comparison key in the flash configuration field. if the backdoor keys match, the fsec[sec] field is changed to the unsecure state and security is released. if the backdoor keys do not match, security is not released and all future attempts to execute the verify backdoor access key command are immediately aborted and the fstat[accerr] bit is (again) set to 1 until a reset of the flash operation in low-power modes k60 sub-family reference manual, rev. 6, nov 2011 678 freescale semiconductor, inc. ftfl module occurs. if the entire 8-byte key is all zeros or all ones, the verify backdoor access key command fails with an access error. the ccif flag is set after the verify backdoor access key operation completes. table 28-64. verify backdoor access key command error handling error condition error bit the supplied key is all-0s or all-fs fstat[accerr] an incorrect backdoor key is supplied fstat[accerr] backdoor key access has not been enabled (see the description of the fsec register) fstat[accerr] this command is launched and the backdoor key has mismatched since the last power down reset fstat[accerr] 28.4.12.14 swap control command the swap control command handles specific activities associated with swapping the two logical program flash memory blocks within the memory map. table 28-65. swap control command fccob requirements fccob number fccob contents [7:0] 0 0x46 (swap) 1 flash address [23:16] 2 flash address [15:8] 3 flash address [7:0] 1 4 swap control code: 0x01 - initialize swap system 0x02 - set swap in update state 0x04 - set swap in complete state 0x08 - report swap status returned values 5 current swap state: 0x00 - uninitialized 0x01 - ready 0x02 - update 0x03 - update-erased 0x04 - complete 6 current swap block status: 0x00 - program flash block 0 at 0x0_0000 0x01 - program flash block 1 at 0x0_0000 table continues on the next page... chapter 28 flash memory module ftf 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 67 table 28-65. swap control command fccob requirements (continued) fccob number fccob contents [7:0] 7 next swap block status (after any reset): 0x00 - program flash block 0 at 0x0_0000 0x01 - program flash block 1 at 0x0_0000 1. must be phrase-aligned (flash address [2:0] = 000). upon clearing ccif to launch the swap control command, the ftfl will handle swap- related activities based on the swap control code provided in fccob4 as follows: ? 0x01 (initialize swap system to update-erased state) - after verifying that the current swap state is uninitialized and that the flash address provided is in program flash block 0 but not in the flash configuration field, the flash address (shifted with bits[2:0] removed) will be programmed into the ifr swap field found in program flash 1 ifr. after the swap indicator address has been programmed into the ifr swap field, the swap enable word will be programmed to 0x0000. after the swap enable word has been programmed, the swap indicator, located within the program flash block 0 address provided, will be programmed to 0xff00. ? 0x02 (progress swap to update state) - after verifying that the current swap state is ready and that the flash address provided matches the one stored in the ifr swap field, the swap indicator located within bits [15:0] of the flash address in the currently active program flash block will be programmed to 0xff00. ? 0x04 (progress swap to complete state) - after verifying that the current swap state is update-erased and that the flash address provided matches the one stored in the ifr swap field, the swap indicator located within bits [15:0] of the flash address in the currently active program flash block will be programmed to 0x0000. before executing with this swap control code, the user must erase the non- active swap indicator using the erase flash block or erase flash sector commands and update the application code or data as needed. the non-active swap indicator will be checked at the erase verify level and if the check fails, the current swap state will be changed to update with accerr set. ? 0x08 (report swap system status) - after verifying that the flash address provided matches the one stored in the ifr swap field, the status of the swap system will be reported as follows: ? fccob5 (current swap state) - indicates the current swap state based on the status of the swap enable word and the swap indicators. if the mgstat0 flag is set after command completion, the swap state returned was not successfully transitioned from and the appropriate swap command code must be attempted again. if the current swap state is update and the non-active swap indicator is 0xffff, the current swap state is changed to update-erased. flash operation in low-power modes k60 sub-family reference manual, rev. 6, nov 2011 680 freescale semiconductor, inc. ? fccob6 (current swap block status) - indicates which program flash block is currently located at relative flash address 0x0_0000. ? fccob7 (next swap block status) - indicates which program flash block will be located at relative flash address 0x0_0000 after the next reset of the ftfl module. note it is recommended that the user execute the swap control command to report swap status (code 0x08) after any reset to determine if issues with the swap system were detected during the swap state determination procedure. note it is recommended that the user write 0xff to fccob5, fccob6, and fccob7 since the swap control command will not always return the swap state and status fields when an accerr is detected. the swap indicators are implicitly protected from being programmed during program longword or program section command operations and are implicitly unprotected during swap control command operations. the swap indicators are implicitly protected from being erased during erase flash block and erase flash sector command operations unless the swap indicator being erased is in the non-active program flash block and the swap system is in the update or update-erased state. once the swap system has been initialized, the erase all blocks command can be used to uninitialize the swap system. table 28-66. swap control command error handling error condition swap control code error bit command not available in current mode/security 1 all fstat[accerr] flash address is not in program flash block 0 all fstat[accerr] flash address is in the flash configuration field all fstat[accerr] flash address is not phrase aligned all fstat[accerr] flash address does not match the swap indicator address in the ifr 2, 4 fstat[accerr] swap initialize requested when swap system is not in the uninitialized state 1 fstat[accerr] swap update requested when swap system is not in the ready state 2 fstat[accerr] swap complete requested when swap system is not in the update-erased state 4 fstat[accerr] an undefined swap control code is provided - fstat[accerr] table continues on the next page... chapter 28 flash memory module ftf 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 681 table 28-66. swap control command error handling (continued) error condition swap control code error bit any errors have been encountered during the swap determination and program-verify operations 1, 2, 4 fstat[mgstat0] any brownouts were detected during the swap determination procedure 8 fstat[mgstat0] 1. returned fields will not be updated, i.e. no swap state or status reporting flash operation in low-power modes k60 sub-family reference manual, rev. 6, nov 2011 682 freescale semiconductor, inc. reset 2 erase 4 erase reset block0 active states block1 active states ready0 update0 complete0 ready1 upers1 complete1 1 0xffff 0x0000 0xff00 0x0000 0x0000 0xffff 0x0000 0xffff 0xffff 0xff00 0xffff 0x0000 swap state indicator0 indicator1 legend swap control code 4 upers0 0xff00 0xffff 2 update1 0x0000 0xff00 erase: ersblk or ersscr commands reset: por, vllsx exit, warm/system reset uninitialized0 0xffff 0xffff figure 28-36. valid swap state sequencing chapter 28 flash memory module (ftfl) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 683 table 28-67. swap state report mapping case swap enable field 1 swap indicator 0 1 swap indicator 1 1 swap state 2 state code mgst at0 active block 1 0xffff - - uninitialized 0 0 0 2 0x0000 0xff00 0x0000 update 2 0 0 3 0x0000 0xff00- 0xffff update-erased 3 0 0 4 0x0000 0x0000 0xffff 3 complete 4 4 0 0 5 0x0000 0x0000 0xffff ready 5 1 0 1 6 0x0000 0x0000 0xff00 update 2 0 1 7 0x0000 0xffff 0xff00 update-erased 3 0 1 8 0x0000 0xffff 3 0x0000 complete 4 4 0 1 9 0x0000 0xffff 0x0000 ready 5 1 0 0 10 0xxxxx - - uninitialized 0 1 0 11 0x0000 0xffff 0xffff uninitialized 0 1 0 12 0x0000 0xffxx 0xffff ready 1 1 0 13 0x0000 0xffxx 0x0000 ready 1 1 0 14 6 0x0000 0xxxxx 0x0000 ready 1 1 0 15 6 0x0000 0xffff 0xffxx ready 1 1 1 16 0x0000 0x0000 0xffxx ready 1 1 1 17 6 0x0000 0x0000 0xxxxx ready 1 1 1 18 0x0000 0xff00 0xffff 7 update 2 1 0 19 0x0000 0xff00 0xxxxx update 2 1 0 20 0x0000 0xff(00) 0xffxx update 2 1 0 21 6 0x0000 0x0000 0x0000 update 2 1 0 22 6 0x0000 0xxxxx 0xxxxx update 2 1 0 23 0x0000 0xffff 7 0xff00 update 2 1 1 24 0x0000 0xxxxx 0xff00 update 2 1 1 25 0x0000 0xffxx 0xff(00) update 2 1 1 26 0x0000 0xxx00 0xffff update-erased 3 1 0 27 0x0000 0xxxxx 0xffff update-erased 3 1 0 28 0x0000 0xffff 0xxx00 update-erased 3 1 1 29 0x0000 0xffff 0xxxxx update-erased 3 1 1 1. 0xxxxx, 0xffxx, 0xxx00 indicates a non-valid value was read; 0xff(00) indicates more 0?s than other indicator (if same number of 0?s, then swap system defaults to block 0 active) 2. cases 10-29 due to brownout (abort) detected during program or erase steps related to swap 3. must read 0xffff with erase verify level before transition to complete allowed 4. no reset since successful swap complete execution 5. reset after successful swap complete execution 6. not a valid case 7. fails to read 0xffff at erase verify level flash operation in low-power modes k60 sub-family reference manual, rev. 6, nov 2011 684 freescale semiconductor, inc. 28.4.12.14.1 swap state determination during the reset sequence, the state of the swap system is determined by evaluating the ifr swap field in the program flash 1 ifr and the swap indicators located in each of the program flash blocks at the swap indicator address stored in the ifr swap field. table 28-68. program flash 1 ifr swap field address range size (bytes) field description 0x00 ? 0x01 2 swap enable word 0x02 ? 0x03 2 swap indicator address 0x04 ? 0xff 252 reserved 28.4.12.15 program partition command the program partition command prepares the flexnvm block for use as data flash, eeprom backup, or a combination of both and initializes the flexram. the program partition command must not be launched from flash memory, since flash memory resources are not accessible during program partition command execution. caution while different partitions of the flexnvm are available, the intention is that a single partition choice is used throughout the entire lifetime of a given application. the flexnvm partition code choices affect the endurance and data retention characteristics of the device. table 28-69. program partition command fccob requirements fccob number fccob contents [7:0] 0 0x80 (pgmpart) 1 not used 2 not used 3 not used 4 eeprom data size code 1 5 flexnvm partition code 2 1. see table 28-70 and eeprom data set size 2. see table 28-71 and chapter 28 flash memory module (ftfl) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 685 table 28-70. valid eeprom data set size codes eeprom data size code (fccob4) 1 eeprom data set size (bytes) subsystem a + b fccob4[eeesplit] fccob4[eeesize] 11 0xf 0 2 00 0x9 4 + 28 01 0x9 8 + 24 10 0x9 16 + 16 11 0x9 16 + 16 00 0x8 8 + 56 01 0x8 16 + 48 10 0x8 32 + 32 11 0x8 32 + 32 00 0x7 16 + 112 01 0x7 32 + 96 10 0x7 64 + 64 11 0x7 64 + 64 00 0x6 32 + 224 01 0x6 64 + 192 10 0x6 128 + 128 11 0x6 128 + 128 00 0x5 64 + 448 01 0x5 128 + 384 10 0x5 256 + 256 11 0x5 256 + 256 00 0x4 128 + 896 01 0x4 256 + 768 10 0x4 512 + 512 11 0x4 512 + 512 00 0x3 256 + 1,792 01 0x3 512 + 1,536 10 0x3 1,024 + 1,024 11 0x3 1,024 + 1,024 00 0x2 512 + 3,584 01 0x2 1,024 + 3,072 10 0x2 2,048 + 2,048 11 0x2 2,048 + 2,048 1. fccob4[7:6] = 00 2. eeprom data set size must be set to 0 bytes when the flexnvm partition code is set for no eeprom. flash operation in low-power modes k60 sub-family reference manual, rev. 6, nov 2011 686 freescale semiconductor, inc. table 28-71. valid flexnvm partition codes flexnvm partition code (fccob5[depart]) 1 data flash size (kbytes) eeprom backup size (kbytes) 0000 256 0 0011 224 32 0100 192 64 0101 128 128 0110 0 256 1000 0 256 1011 32 224 1100 64 192 1101 128 128 1110 256 0 1. fccob5[7:4] = 0000 after clearing ccif to launch the program partition command, the ftfl first verifies that the eeprom data size code and flexnvm partition code in the data flash ifr are erased. if erased, the program partition command erases the contents of the flexnvm memory. if the flexnvm is to be partitioned for eeprom backup, the allocated eeprom backup sectors are formatted for eeprom use. finally, the partition codes are programmed into the data flash ifr using the values provided. the program partition command also verifies that the partition codes read back correctly after programming. if the flexnvm is partitioned for eeprom, the allocated eeprom backup sectors are formatted for eeprom use. the ccif flag is set after the program partition operation completes. prior to launching the program partition command, the data flash ifr must be in an erased state, which can be accomplished by executing the erase all blocks command or by an external request (see erase all blocks command ). the eeprom data size code and flexnvm partition code are read using the read resource command (see read resource command ). table 28-72. program partition command error handling error condition error bit command not available in current mode/security fstat[accerr] the eeprom data size and flexnvm partition code bytes are not initially 0xffff fstat[accerr] invalid eeprom data size code is entered (see table 28-70 for valid codes) fstat[accerr] invalid flexnvm partition code is entered (see table 28-71 for valid codes) fstat[accerr] flexnvm partition code = full data flash (no eeprom) and eeprom data size code allocates flexram for eeprom fstat[accerr] table continues on the next page... chapter 28 flash memory module ftf 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 687 table 28-72. program partition command error handling (continued) error condition error bit flexnvm partition code allocates space for eeprom backup, but eeprom data size code allocates no flexram for eeprom fstat[accerr] fccob4[7:6] != 00 fstat[accerr] fccob5[7:4] != 0000 fstat[accerr] any errors have been encountered during the verify operation fstat[mgstat0] 28.4.12.16 set flexram function command the set flexram function command changes the function of the flexram: ? when not partitioned for eeprom, the flexram is typically used as traditional ram. ? when partitioned for eeprom, the flexram is typically used to store eeprom data. table 28-73. set flexram function command fccob requirements fccob number fccob contents [7:0] 0 0x81 (setram) 1 flexram function control code (see table 28-74 ) table 28-74. flexram function control flexram function control code action 0xff make flexram available as ram: clear the fcnfg[eeerdy] and fcnfg[ramrdy] flags write a background of ones to all flexram locations set the fcnfg[ramrdy] flag 0x00 make flexram available for eeprom: clear the fcnfg[eeerdy] and fcnfg[ramrdy] flags write a background of ones to all flexram locations copy-down existing eeprom data to flexram set the fcnfg[eeerdy] flag after clearing ccif to launch the set flexram function command, the ftfl sets the function of the flexram based on the flexram function control code. when making the flexram available as traditional ram, the ftfl clears the fcnfg[eeerdy] and fcnfg[ramrdy] flags, overwrites the contents of the entire flexram with a background pattern of all ones, and sets the fcnfg[ramrdy] flag. the state of the feprot register does not prevent the flexram from being overwritten. flash operation in low-power modes k60 sub-family reference manual, rev. 6, nov 2011 688 freescale semiconductor, inc. when the flexram is set to function as a ram, normal read and write accesses to the flexram are available. when large sections of flash memory need to be programmed, e.g. during factory programming, the flexram can be used as the section program buffer for the program section command (see program section command ). when making the flexram available for eeprom, the ftfl clears the fcnfg[eeerdy] and fcnfg[ramrdy] flags, overwrites the contents of the flexram allocated for eeprom with a background pattern of all ones, and copies the existing eeprom data from the eeprom backup record space to the flexram. after completion of the eeprom copy-down, the fcnfg[eeerdy] flag is set. when the flexram is set to function as eeprom, normal read and write access to the flexram is available, but writes to the flexram also invoke eeprom activity. table 28-75. set flexram function command error handling error condition error bit command not available in current mode/security fstat[accerr] flexram function control code is not defined fstat[accerr] flexram function control code is set to make the flexram available for eeprom, but flexnvm is not partitioned for eeprom fstat[accerr] 28.4.13 security the ftfl module provides security information to the mcu based on contents of the fsec security register. the mcu then limits access to ftfl resources as defined in the device's chip configuration details. during reset, the ftfl module initializes the fsec register using data read from the security byte of the flash configuration field (see flash configuration field description ). the following fields are available in the fsec register. the settings are described in the flash security register (ftfl_fsec) details. table 28-76. fsec register fields fsec field description keyen backdoor key access meen mass erase capability fslacc freescale factory access sec mcu security chapter 28 flash memory module (ftfl) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 689 28.4.13.1 ftfl access by mode and security the following table summarizes how access to the ftfl module is affected by security and operating mode. table 28-77. ftfl access summary operating mode chip security state unsecure secure nvm normal full command set nvm special full command set only the erase all blocks and read 1s all blocks commands. 28.4.13.2 changing the security state the security state out of reset can be permanently changed by programming the security byte of the flash configuration field. this assumes that you are starting from a mode where the necessary program flash erase and program commands are available and that the region of the program flash containing the flash configuration field is unprotected. if the flash security byte is successfully programmed, its new value takes affect after the next chip reset. 28.4.13.2.1 unsecuring the chip using backdoor key access the chip can be unsecured by using the backdoor key access feature, which requires knowledge of the contents of the 8-byte backdoor key value stored in the flash configuration field (see flash configuration field description ). if the fsec[keyen] bits are in the enabled state, the verify backdoor access key command (see verify backdoor access key command ) can be run; it allows the user to present prospective keys for comparison to the stored keys. if the keys match, the fsec[sec] bits are changed to unsecure the chip. the entire 8-byte key cannot be all 0s or all 1s; that is, 0000_0000_0000_0000h and ffff_ffff_ffff_ffffh are not accepted by the verify backdoor access key command as valid comparison values. while the verify backdoor access key command is active, program flash memory is not available for read access and returns invalid data. the user code stored in the program flash memory must have a method of receiving the backdoor keys from an external stimulus. this external stimulus would typically be through one of the on-chip serial ports. if the keyen bits are in the enabled state, the chip can be unsecured by the following backdoor key access sequence: flash operation in low-power modes k60 sub-family reference manual, rev. 6, nov 2011 690 freescale semiconductor, inc. 1. follow the command sequence for the verify backdoor access key command as explained in verify backdoor access key command 2. if the verify backdoor access key command is successful, the chip is unsecured and the fsec[sec] bits are forced to the unsecure state an illegal key provided to the verify backdoor access key command prohibits further use of the verify backdoor access key command. a reset of the chip is the only method to re-enable the verify backdoor access key command when a comparison fails. after the backdoor keys have been correctly matched, the chip is unsecured by changing the fsec[sec] bits. a successful execution of the verify backdoor access key command changes the security in the fsec register only. it does not alter the security byte or the keys stored in the flash configuration field ( flash configuration field description ). after the next reset of the chip, the security state of the ftfl module reverts back to the flash security byte in the flash configuration field. the verify backdoor access key command sequence has no effect on the program and erase protections defined in the program flash protection registers. if the backdoor keys successfully match, the unsecured chip has full control of the contents of the flash configuration field. the chip may erase the sector containing the flash configuration field and reprogram the flash security byte to the unsecure state and change the backdoor keys to any desired value. 28.4.14 reset sequence on each system reset the ftfl module executes a sequence which establishes initial values for the flash block configuration parameters, fprot, fdprot, feprot, fopt, and fsec registers and the fcnfg[swap, pflsh, ramrdy, eeerdy] bits. ccif is cleared throughout the reset sequence. the ftfl module holds off all cpu access for a portion of the reset sequence. flash reads are possible when the hold is removed. completion of the reset sequence is marked by setting ccif which enables flash user commands. if a reset occurs while any ftfl command is in progress, that command is immediately aborted. the state of the word being programmed or the sector/block being erased is not guaranteed. commands and operations do not automatically resume after exiting reset. chapter 28 flash memory module (ftfl) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 691 flash operation in low-power modes k60 sub-family reference manual, rev. 6, nov 2011 692 freescale semiconductor, inc. chapter 29 external bus interface (flexbus) 29.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. this chapter describes external bus data transfer operations and error conditions. it describes transfers initiated by the core processor (or any other bus master) and includes detailed timing diagrams showing the interaction of signals in supported bus operations. 29.1.1 overview a multi-function external bus interface called the flexbus interface controller is provided on the device with basic functionality of interfacing to slave-only devices. it can be directly connected to the following asynchronous or synchronous devices with little or no additional circuitry: ? external roms ? flash memories ? programmable logic devices ? other simple target (slave) devices for asynchronous devices, a simple chip-select based interface can be used. the flexbus interface has up to six general purpose chip-selects, fb_cs[5:0]. the actual number of chip selects available depends upon the device and its pin configuration. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 693 29.1.2 features key flexbus features include: ? six independent, user-programmable chip-select signals ( fb_cs[5:0]) that can interface with external sram, prom, eprom, eeprom, flash, and other peripherals ? 8-, 16-, and 32-bit port sizes with configuration for multiplexed or non-multiplexed address and data buses ? 8-bit, 16-bit, 32-bit, and 16-byte transfers ? programmable burst- and burst-inhibited transfers selectable for each chip select and transfer direction ? programmable address-setup time with respect to the assertion of chip select ? programmable address-hold time with respect to the negation of chip select and transfer direction ? extended address latch enable option helps with glueless connections to synchronous and asynchronous memory devices 29.1.3 modes of operation the external interface is a configurable multiplexed bus set to one of the following modes: ? multiplexed 32-bit address and 32-bit data ? multiplexed 32-bit address and 16-bit data (non-multiplexed 16-bit address and 16- bit data) ? multiplexed 32-bit address and 8-bit data (non-multiplexed 24-bit address and 8-bit data) ? non-multiplexed 32-bit address and 32-bit data busses 29.2 signal descriptions this section describes the external signals involved in data-transfer operations. note not all of the following signals may be available on a particular device. see the chip configuration details for information on which signals are available. signal descriptions k60 sub-family reference manual, rev. 6, nov 2011 694 freescale semiconductor, inc. table 29-1. flexbus signal summary signal description i/o fb_a[31:0] in a non-multiplexed configuration, this is the address bus. o fb_d[31:0]/ fb_ad[31:0] in a non-multiplexed configuration, this is the data bus. in a multiplexed configuration this bus is the address/data bus, fb_ad[31:0]. in non- multiplexed and multiplexed configurations, during the first cycle, this bus drives the upper address byte, addr[31:24]. i/o fb_cs[5:0] general purpose chip-selects. the actual number of chip selects available depends upon the device and its pin configuration. o fb_be_31_24 fb_be_23_16 fb_be_15_8 fb_be_7_0 byte enables o fb_oe output enable o fb_r/ w read/write. 1 = read, 0 = write o fb_ts transfer start o fb_ale address latch enable (an inverse of fb_ts) o fb_tsiz[1:0] transfer size o fb_tbst burst transfer indicator o fb_ta transfer acknowledge i fb_clk flexbus clock output o 29.2.1 address and data buses (fb_a n f n f n in non-multiplexed mode, the fb_a[31:0] and fb_d[31:0] buses carry the address and data, respectively. the number of byte lanes carrying the data is determined by the port size associated with the matching chip select. in multiplexed mode, the fb_ad[31:0] bus carries the address and data. the full 32-bit address is driven on the first clock of a bus cycle (address phase). following the first clock, the data is driven on the bus (data phase). during the data phase, the address continues driving on the pins not used for data. for example, in 16-bit mode the lower address continues driving on fb_ad[15:0] and in 8-bit mode the lower address continues driving on fb_ad[23:0]. chapter 29 external bus interface (flexbus) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 695 29.2.2 chip selects ( fb_cs[5 :0]) the chip-select signal indicates which device is selected. a particular chip-select asserts when the transfer address is within the device's address space, as defined in the base- and mask-address registers. the actual number of chip selects available depends upon the pin configuration. 29.2.3 byte enables ( fb_be_31_24, fb_be_23_16, fb_be_15_8, fb_be_7_0) when driven low, the byte enable outputs indicate data is to be latched or driven onto a specific byte lane of the data bus. a configuration option is provided to assert these signals on reads and writes or writes only. for external sram or flash devices, the fb_be n outputs must be connected to individual byte strobe signals. 29.2.4 output enable ( fb_oe) the output enable signal ( fb_oe) is sent to the interfacing memory and/or peripheral to enable a read transfer. fb_oe is only asserted during read accesses when a chip select matches the current address decode. 29.2.5 read/write (fb_r/ w) the processor drives the fb_r/ w signal to indicate the current bus operation direction. it is driven high during read bus cycles and low during write bus cycles. 29.2.6 transfer start/address latch enable ( fb_ts/fb_ale) the assertion of fb_ts indicates that the device has begun a bus transaction and the address and attributes are valid. in multiplexed mode, an inverted fb_ts (fb_ale) is available as an address latch enable, which indicates when the address is being driven on the fb_ad bus. fb_ts/fb_ale is asserted for one bus clock cycle. this device can extend this signal until the first positive clock edge after fb_cs n asserts. see cscr n [exts] and extended transfer start/address latch enable . signal descriptions k60 sub-family reference manual, rev. 6, nov 2011 696 freescale semiconductor, inc. 29.2.7 transfer size (fb_tsiz[1:0]) for memory accesses, these signals, along with fb_tbst, indicate the data transfer size of the current bus operation. the interface supports 8-, 16-, and 32-bit operand transfers and allows accesses to 8-, 16-, and 32-bit data ports. for misaligned transfers, fb_tsiz[1:0] indicates the size of each transfer. for example, if a 32-bit access through a 32-bit port device occurs at a misaligned offset of 0x1, 8 bits is transferred first (fb_tsiz[1:0] = 01), 16 bits is transferred next at offset 0x2 (fb_tsiz[1:0] = 10), and the final 8 bits is transferred at offset 0x4 (fb_tsiz[1:0] = 01). for aligned transfers larger than the port size, fb_tsiz[1:0] behaves as follows: ? if bursting is used, fb_tsiz[1:0] is driven to the transfer size. ? if bursting is inhibited, fb_tsiz[1:0] first shows the entire transfer size and then shows the port size. table 29-2. data transfer size fb_tsiz[1:0] transfer size 00 4 bytes 01 1 byte 10 2 bytes 11 16 bytes (line) for burst-inhibited transfers, fb_tsiz[1:0] changes with each fb_ts assertion to reflect the next transfer size. for transfers to port sizes smaller than the transfer size, fb_tsiz[1:0] indicates the size of the entire transfer on the first access and the size of the current port transfer on subsequent transfers. for example, for a 32-bit write to an 8- bit port, fb_tsiz[1:0] equals 00 for the first transaction and 01 for the next three transactions. if bursting is used for a 32-bit write to an 8-bit port, fb_tsiz[1:0] is driven to 00 for the entire transfer. 29.2.8 transfer burst ( fb_tbst) transfer burst indicates that a burst transfer is in progress as driven by the device. a burst transfer can be two to 16 beats depending on fb_tsiz[1:0] and the port size. chapter 29 external bus interface (flexbus) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 697 note when burst ( fb_tbst = 0), transfer size is 16 bytes (fb_tsiz[1:0] = 11) and the address is misaligned within the 16-byte boundary, the external device must be able to wrap around the address. 29.2.9 transfer acknowledge ( fb_ta) this input signal indicates the external data transfer is complete. when the processor recognizes fb_ta during a read cycle, it latches the data and then terminates the bus cycle. when the processor recognizes fb_ta during a write cycle, the bus cycle is terminated. if auto-acknowledge is disabled (cscr n [aa] = 0), the external device drives fb_ta to terminate the bus transfer; if auto-acknowledge is enabled (cscr n [aa] = 1), fb_ta is generated internally after a specified number of wait states, or the external device may assert external fb_ta before the wait-state countdown, terminating the cycle early. the device negates fb_cs n one cycle after the last fb_ta asserts. during read cycles, the peripheral must continue to drive data until fb_ta is recognized. for write cycles, the processor continues driving data one clock after fb_cs n is negated. the number of wait states is determined by cscr n or the external fb_ta input. if the external fb_ta is used, the peripheral has total control on the number of wait states. note external devices should only assert fb_ta while the fb_cs n signal to the external device is asserted. the cspmcr register controls muxing of fb_ta with other signals. if auto-acknowledge is not used and cspmcr does not allow fb_ta control, the flexbus may hang. 29.3 memory map/register definition the following tables describe the registers and bit meanings for configuring chip-select operation. the actual number of chip selects available depends upon the device and its pin configuration. if the device does not support certain chip select signals or the pin is not configured for a chip-select function, then that corresponding set of chip-select registers has no effect on an external pin. memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 698 freescale semiconductor, inc. note you must set csmr0[v] before the chip select registers take effect. a bus error occurs when writing to reserved register locations. fb memory map absolute address (hex) register name width (in bits) access reset value section/ page 4000_c000 chip select address register (fb_csar0) 32 r/w 0000_0000h 29.3.1/ 700 4000_c004 chip select mask register (fb_csmr0) 32 r/w 0000_0000h 29.3.2/ 701 4000_c008 chip select control register (fb_cscr0) 32 r/w 0000_0000h 29.3.3/ 702 4000_c00c chip select address register (fb_csar1) 32 r/w 0000_0000h 29.3.1/ 700 4000_c010 chip select mask register (fb_csmr1) 32 r/w 0000_0000h 29.3.2/ 701 4000_c014 chip select control register (fb_cscr1) 32 r/w 0000_0000h 29.3.3/ 702 4000_c018 chip select address register (fb_csar2) 32 r/w 0000_0000h 29.3.1/ 700 4000_c01c chip select mask register (fb_csmr2) 32 r/w 0000_0000h 29.3.2/ 701 4000_c020 chip select control register (fb_cscr2) 32 r/w 0000_0000h 29.3.3/ 702 4000_c024 chip select address register (fb_csar3) 32 r/w 0000_0000h 29.3.1/ 700 4000_c028 chip select mask register (fb_csmr3) 32 r/w 0000_0000h 29.3.2/ 701 4000_c02c chip select control register (fb_cscr3) 32 r/w 0000_0000h 29.3.3/ 702 4000_c030 chip select address register (fb_csar4) 32 r/w 0000_0000h 29.3.1/ 700 4000_c034 chip select mask register (fb_csmr4) 32 r/w 0000_0000h 29.3.2/ 701 4000_c038 chip select control register (fb_cscr4) 32 r/w 0000_0000h 29.3.3/ 702 4000_c03c chip select address register (fb_csar5) 32 r/w 0000_0000h 29.3.1/ 700 table continues on the next page... chapter 2 external bus interface flexbus 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 6 fb memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4000_c040 chip select mask register (fb_csmr5) 32 r/w 0000_0000h 29.3.2/ 701 4000_c044 chip select control register (fb_cscr5) 32 r/w 0000_0000h 29.3.3/ 702 4000_c060 chip select port multiplexing control register (fb_cspmcr) 32 r/w 0000_0000h 29.3.4/ 705 29.3.1 chip select address register (fb_csar n the csarn registers specify the chip-select base addresses. note because the flexbus module is one of the slaves connected to the crossbar switch, it is only accessible within a certain memory range. refer to the device memory map for the applicable flexbus "expansion" address range for which the chip-selects can be active. set the csarn registers appropriately. addresses: fb_csar0 is 4000_c000h base + 0h offset = 4000_c000h fb_csar1 is 4000_c000h base + ch offset = 4000_c00ch fb_csar2 is 4000_c000h base + 18h offset = 4000_c018h fb_csar3 is 4000_c000h base + 24h offset = 4000_c024h fb_csar4 is 4000_c000h base + 30h offset = 4000_c030h fb_csar5 is 4000_c000h base + 3ch offset = 4000_c03ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r ba 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fb_csar n iel escritions fiel escrition ase aress eines the ase aress or eory eicate to chiselect fn is coare to its on the internal aress us to eterine i chiselect eory is ein accesse resere his reaonly iel is resere an always has the alue ero eory areister einition ufaily reerence anual re o freescale eiconuctor nc 29.3.2 chip select mask register (fb_csmr n csmrn registers specify the address mask and allowable access types for the respective chip-selects. addresses: fb_csmr0 is 4000_c000h base + 4h offset = 4000_c004h fb_csmr1 is 4000_c000h base + 10h offset = 4000_c010h fb_csmr2 is 4000_c000h base + 1ch offset = 4000_c01ch fb_csmr3 is 4000_c000h base + 28h offset = 4000_c028h fb_csmr4 is 4000_c000h base + 34h offset = 4000_c034h fb_csmr5 is 4000_c000h base + 40h offset = 4000_c040h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r bam 0 wp 0 v w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fb_csmr n iel escritions fiel escrition ase aress as eines the chiselect loc sie y asin aress its ettin a it causes the corresonin r it to e a ont care in the ecoe he loc sie or fn is n n nuer o its set in resectie r for exale i r equals x an r equals x f aresses two iscontinuous eory locs: one ro x xffff an one ro x xffff liewise or f to access o aress sace startin at location x f ust ein at the next yte ater f or a aress sace hereore r equals x r equals xff r equals x an r equals xff orresonin aress it is use in chiselect ecoe orresonin aress it is a ont care in chiselect ecoe resere his reaonly iel is resere an always has the alue ero rite rotect ontrols write accesses to the aress rane in the corresonin r ttetin to write to the rane o aresses or which rn is set results in a us error terination o the internal cycle an no external cycle rea an write accesses are allowe only rea accesses are allowe resere his reaonly iel is resere an always has the alue ero ali table continues on the next page... chapter 2 external bus interface flexbus 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 701 fb_csmr n iel escritions continue fiel escrition nicates whether the corresonin r r an r contents are ali rorae chi selects o not assert until it is set excet or f which acts as the loal chiselect reset clears each rn o: t reset no chiselect other than f can e use until the r is set terwar f: unctions as rorae hi select inali hi select ali hi select control reister fr n each cscrn controls the auto-acknowledge, address setup and hold times, port size, burst capability, and number of wait states. to support the global chip-select ( fb_cs0) the cscr0 reset values differ from the other cscrs. note the reset value of cscr0 is as follows: ? bits 31-24 are 0 ? bit 23-3 are device-dependent ? bits 3-0 are 0 see the chip configuration details for your particular device for information on the exact cscr0 reset value. addresses: fb_cscr0 is 4000_c000h base + 8h offset = 4000_c008h fb_cscr1 is 4000_c000h base + 14h offset = 4000_c014h fb_cscr2 is 4000_c000h base + 20h offset = 4000_c020h fb_cscr3 is 4000_c000h base + 2ch offset = 4000_c02ch fb_cscr4 is 4000_c000h base + 38h offset = 4000_c038h fb_cscr5 is 4000_c000h base + 44h offset = 4000_c044h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r sws 0 swsen exts aset rdah wrah ws bls aa ps bem bstr bstw 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fb_cscr n iel escritions fiel escrition econary wait states the it is set the nuer o wait states inserte eore an internal transer acnowlee is enerate or a urst transer excet or the irst terination which is controlle y the wait state count table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 702 freescale semiconductor, inc. fb_cscr n iel escritions continue fiel escrition r n ws. if the swsen bit is cleared, the ws value is used for all burst transfers and this field is ignored. 224 reserved this read-only field is reserved and always has the value zero. 2 swsen secondary wait state enable 0 the ws value inserts wait states before an internal transfer acnowledge is generated for all transfers 1 the sws value inserts wait states before an internal transfer acnowledge is generated for burst transfer secondary terminations 22 exts extended address latch enable 0 fb_tsfb_ae asserts for one bus cloc cycle 1 fb_tsfb_ae remains asserted until the first positive cloc edge after fb_csn asserts 2120 aset address setup controls the assertion of the chip-select with respect to assertion of a valid address and attributes. the address and attributes are considered valid at the same time fb_tsfb_ae asserts. 00 assert fb_csn on first rising cloc edge after address is asserted. default fb_csn 01 assert fb_csn on second rising cloc edge after address is asserted. 10 assert fb_csn on third rising cloc edge after address is asserted. 11 assert fb_csn on fourth rising cloc edge after address is asserted. default fb_cs0 118 rdah read address hold or deselect this field controls the address and attribute hold time after the termination during a read cycle that hits in the chip-select address space. nte the hold time applies only at the end of a transfer. therefore, during a burst transfer or a transfer to a port size smaller than the transfer size, the hold time is only added after the last bus cycle. the number of cycles the address and attributes are held after fb_csn negation depends on the value of cscrnaa. 00 if aa is cleared, 1 cycle. if aa is set, 0 cycles. 01 if aa is cleared, 2 cycles. if aa is set, 1 cycle. 10 if aa is cleared, cycles. if aa is set, 2 cycles. 11 if aa is cleared, 4 cycles. if aa is set, cycles. 1716 wrah write address hold or deselect write address hold or deselect. this field controls the address, data, and attribute hold time after the termination of a write cycle that hits in the chip-select address space. nte the hold time applies only at the end of a transfer. therefore, during a burst transfer or a transfer to a port size smaller than the transfer size, the hold time is only added after the last bus cycle. 00 hold address and attributes one cycle after fb_csn negates on writes. default fb_csn 01 hold address and attributes two cycles after fb_csn negates on writes. 10 hold address and attributes three cycles after fb_csn negates on writes. 11 hold address and attributes four cycles after fb_csn negates on writes. default fb_cs0 110 ws wait states table continues on the next page... chapter 2 external bus interface flexbus 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 70 fb_cscr n iel escritions continue fiel escrition he nuer o wait states inserte ater fn asserts an eore an internal transer acnowlee is enerate inserts ero wait states xf inserts wait states is resere f ust e asserte y the external syste rearless o the nuer o enerate wait states n that case the external transer acnowlee ens the cycle n external f suersees the eneration o an internal f l ytelane shit eterines i ata on f aears letustiie or rihtustiie urin the ata hase o a flexus access ot shite ata is letustie on f hite ata is riht ustiie on f utoacnowlee enale eterines the assertion o the internal transer acnowlee or accesses seciie y the chiselect aress o: is set or a corresonin fn an the external syste asserts an external f eore the waitstate countown asserts the internal f the cycle is terinate urst cycles increent the aress us etween each internal terination o: his it ust e set i r isales f o internal f is asserte ycle is terinate externally nternal transer acnowlee is asserte as seciie y ort sie eciies the ata ort with associate with each chiselect t eterines where ata is rien urin write cycles an where ata is sale urin rea cycles it ort sie ali ata sale an rien on f: it ort sie ali ata sale an rien on f: i l or f: i l it ort sie ali ata sale an rien on f: i l or f: i l it ort sie ali ata sale an rien on f: i l or f: i l yteenale oe eciies the yte enale oeration ertain eories hae yte enales that ust e asserte urin reas an writes can e set in the releant r to roie the aroriate oe o yte enale suort or these rs he f n signals are not asserted for reads. the fb_be n signals are asserted for data write only. 1 the fb_be n signals are asserted for read and write accesses 4 bstr burst-read enable specifies whether burst reads are used for memory associated with each fb_csn. 0 data exceeding the specified port size is broen into individual, port-sized, non-burst reads. for example, a longword read from an 8-bit port is broen into four 8-bit reads. 1 enables data burst reads larger than the specified port size, including longword reads from 8- and 16- bit ports, word reads from 8-bit ports, and line reads from 8, 16-, and 2-bit ports. bstw burst-write enable table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 704 freescale semiconductor, inc. fb_cscr n iel escritions continue fiel escrition eciies whether urst writes are use or eory associate with each fn rea ata larer than the seciie ort sie into iniiual ortsie nonurst writes for exale a lonwor write to an it ort taes our yte writes nales urst write o ata larer than the seciie ort sie incluin lonwor writes to an it orts wor writes to it orts an line writes to an it orts resere his reaonly iel is resere an always has the alue ero hi select ort ultilexin control reister fr the cspmcr register controls the multiplexing of the flexbus signals. note a bus error occurs when: ? writing a reserved value, ? writing to a reserved bit location in this register, or ? not accessing this register as 32-bit. address: fb_cspmcr is 4000_c000h base + 60h offset = 4000_c060h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r group1 group2 group3 group4 group5 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fb_cspmcr field descriptions field description 31?28 group1 flexbus signal group 1 multiplex control controls the multiplexing of the fb_ale, fb_cs1, and fb_ts signals. 0000 fb_ale 0001 fb_cs1 0010 fb_ts else reserved 27?24 group2 flexbus signal group 2 multiplex control controls the multiplexing of the fb_cs4, fb_tsiz0, and fb_be_31_24 signals. 0000 fb_cs4 0001 fb_tsiz0 0010 fb_be_31_24 else reserved table continues on the next page... chapter 2 external bus interface flexbus 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 70 fb_cspmcr field descriptions (continued) field description 2320 group3 flexbus signal group 3 multiplex control controls the multiplexing of the fb_cs5, fb_tsiz1, and fb_be_23_16 signals. 0000 fb_cs5 0001 fb_tsiz1 0010 fb_be_23_16 else reserved 1916 group4 flexbus signal group 4 multiplex control controls the multiplexing of the fb_tbst, fb_cs2, and fb_be_15_8 signals. 0000 fb_tbst 0001 fb_cs2 0010 fb_be_15_8 else reserved 1512 group5 flexbus signal group 5 multiplex control controls the multiplexing of the fb_ta, fb_cs3, and fb_be_7_0 signals. note: when group5 is not 0000, you must set the cscr n aa bit. else, the bus hangs during a transfer. 0000 fb_ta 0001 fb_cs. ou must also set cscr n aa. 0010 fb_be_7_0. ou must also set cscr n aa. else reserved 110 reserved this read-only field is reserved and always has the value zero. 2.4 functional description this section provides the functional description of the module. 29.4.1 chip-select operation each chip-select has a dedicated set of registers for configuration and control: ? chip-select address registers (csar n ) control the base address space of the chip- select. functional description k60 sub-family reference manual, rev. 6, nov 2011 706 freescale semiconductor, inc. ? chip-select mask registers (csmr n ) provide 16-bit address masking and access control. ? chip-select control registers (cscr n ) provide port size and burst capability indication, wait-state generation, address setup and hold times, and automatic acknowledge generation features. 29.4.1.1 general chip-select operation when a bus cycle is routed to the flexbus, the device first compares its address with the base address and mask configurations programmed for chip-selects 0 to 5 (configured in cscr n ). the results depend on if the address matches or not as shown in the following table. table 29-26. results of address comparison address matches csar n result es one r he aroriate chiselect is asserte eneratin a flexus us cycle as eine in the chi select control reister r is set an a write access is erore the internal us cycle terinates with a us error no chi select is asserte an no external us cycle is erore o he access is terinate with a us error resonse no chi select is asserte an no flexus cycle is erore es ultile rs he access is terinate with a us error resonse no chi select is asserte an no flexus cycle is erore an it ort iin static bus sizing is programmable through the port size bits, cscr[ps]. the processor always drives a 32-bit address on the fb_ad bus regardless of the external device's address size. the external device must connect its address/data lines as follows: ? address lines ? fb_ad from fb_ad0 upward ? data lines ? if cscr[bls] = 0, fb_ad from fb_ad31 downward ? if cscr[bls] = 1, fb_ad from fb_ad0 upward chapter 29 external bus interface (flexbus) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 707 no bit ordering is required when connecting address and data lines to the fb_ad bus. for example, a full 16-bit address/16-bit data device connects its addr[15:0] to fb_ad[16:1] and data[15:0] to fb_ad[31:16]. see data byte alignment and physical connections for a graphical connection. 29.4.2 data transfer operation data transfers between the chip and other devices involve these signals: ? address/data bus (fb_ad[31:0]) ? control signals ( fb_ts/fb_ale, fb_ta, fb_cs n , fb_oe, fb_be n ) ? attribute signals (fb_r/ w, fb_tbst, fb_tsiz[1:0]) the address, write data, fb_ts/fb_ale, fb_cs n , and all attribute signals change on the rising edge of the flexbus clock (fb_clk). read data is latched into the device on the rising edge of the clock. the flexbus supports 8-bit, 16-bit, 32-bit, and 16-byte (line) operand transfers and allows accesses to 8-, 16-, and 32-bit data ports. transfer parameters (address setup and hold, port size, the number of wait states for the external device being accessed, automatic internal transfer termination enable or disable, and burst enable or disable) are programmed in the chip-select control registers (cscrs). 29.4.3 data byte alignment and physical connections the device aligns data transfers in flexbus byte lanes with the number of lanes depending on the data port width. the following figure shows the byte lanes that external memory connects to and the sequential transfers of a 32-bit transfer for the supported port sizes when byte lane shift is disabled. for example, an 8-bit memory connects to the single lane fb_ad[31:24] ( fb_be_31_24). a 32-bit transfer through this 8-bit port takes four transfers, starting with the lsb to the msb. a 32-bit transfer through a 32-bit port requires one transfer on each four-byte lane of the flexbus. functional description k60 sub-family reference manual, rev. 6, nov 2011 708 freescale semiconductor, inc. external data bus 32-bit port memory 16-bit port memory 8-bit port memory byte select byte 0 byte 1 byte 2 byte 3 byte 1 byte 0 byte 3 byte 2 b yte 3 byte 2 byte 1 byte 0 driven with address values driven with address values fb_d[31:24] fb_d[23:16] fb_d[15:8] fb_d[7:0] fb_be_7_0 fb_be_15_8 fb_be_23_16 fb_be_31_24 figure 29-23. connections for external memory port sizes (cscr n l the following figure shows the byte lanes that external memory connects to and the sequential transfers of a 32-bit transfer for the supported port sizes when byte lane shift is enabled. external data bus 32-bit port memory 16-bit port memory 8-bit port memory byte select byte 3 byte 2 byte 1 byte 0 driven with address values driven with address values fb_d[31:24] fb_d[23:16] fb_d[15:8] fb_d[7:0] fb_be_7_0 fb_be_15_8 fb_be_23_16 fb_be_31_24 byte 1 byte 0 byte 3 byte 2 byte 0 byte 1 byte 2 byte 3 figure 29-24. connections for external memory port sizes (cscr n l ressata us ultilexin the interface supports a single 32-bit wide multiplexed address and data bus (fb_ad[31:0]). the full 32-bit address is always driven on the first clock of a bus cycle. during the data phase, the fb_ad[31:0] lines used for data are determined by the programmed port size for the corresponding chip select. the device continues to drive the address on any fb_ad[31:0] lines not used for data. the tables below lists the supported combinations of address and data bus widths for each cscr n [bls] setting. chapter 29 external bus interface (flexbus) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 709 table 29-27. flexbus multiplexed operating modes for cscr n l ort ie an hase f : : : : it ress hase ress ata hase ata it ress hase ress ata hase ata ress it ress hase ress ata hase ata ress ale flexus ultilexe oeratin oes or r n l ort ie an hase f : : : : it ress hase ress ata hase ata it ress hase ress ata hase ress ata it ress hase ress ata hase ress ata us ycle xecution as shown in figure 29-27 and figure 29-29 , basic bus operations occur in four clocks: 1. s0: at the first clock edge, the address, attributes, and fb_ts/fb_ale are driven. 2. s1: fb_cs n is asserted at the second rising clock edge to indicate the device selected; by that time, the address and attributes are valid and stable. fb_ts/ fb_ale is negated at this edge. for a write transfer, data is driven on the bus at this clock edge and continues to be driven until one clock cycle after fb_cs n negates. for a read transfer, data is also driven into the device during this cycle. external slave asserts fb_ta at this clock edge. 3. s2: read data and fb_ta are sampled on the third clock edge. fb_ta can be negated after this edge and read data can then be tri-stated. functional description k60 sub-family reference manual, rev. 6, nov 2011 710 freescale semiconductor, inc. 4. s3: fb_cs n is negated at the fourth rising clock edge. this last clock of the bus cycle uses what would be an idle clock between cycles to provide hold time for address, attributes, and write data. 29.4.5.1 data transfer cycle states an on-chip state machine controls the data-transfer operation in the device. the following figure shows the state-transition diagram for basic read and write cycles. s0 s1 s2 wait states s3 next cycle figure 29-25. data-transfer-state-transition diagram the following table describes the states as they appear in subsequent timing diagrams. table 29-29. bus cycle states state cycle description s0 all the read or write cycle is initiated. on the rising clock edge, the device places a valid address on fb_ad n , asserts fb_tsfb_ae, and drives fb_r w high for a read and low for a write. s1 all fb_tsfb_ae is negated on the rising edge of fb_c, and fb_csn is asserted. data is driven on fb_ad1 x for writes, and fb_ad1 x is tristated for reads. address continues to be driven on the fb_ad pins that are unused for data. if fb_ta is recognized asserted, then the cycle moves on to s2. if fb_ta is not asserted internally or externally, then the s1 state continues to repeat. read data is driven by the external device before the next rising edge of fb_c the rising edge that begins s2 with fb_ta asserted. s2 all for internal termination, fb_cs n is negated and the internal system bus transfer is completed. for external termination, the external device should negate fb_ta, and the fb_cs n chip select negates after the rising edge of fb_c at the end of s2. read the processor latches data on the rising cloc edge entering s2. the external device can stop driving data after this edge. however, data can be driven until the end of s or any additional address hold cycles. s all address, data, and fb_r w go invalid off the rising edge of fb_c at the beginning of s, terminating the read or write cycle. chapter 2 external bus interface flexbus 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 711 29.4.6 flexbus timing examples note the timing diagrams throughout this section use signal names that may not be included on your particular device. ignore these extraneous signals. note throughout this section: ? fb_d[ x ] indicates a 32-, 16-, or 8-bit wide data bus ? fb_a[ y ] indicates an address bus that can be 32, 24, or 16 bits wide. 29.4.6.1 basic read bus cycle during a read cycle, the mcu receives data from memory or a peripheral device. the following figure shows a read cycle flowchart. 1. decode address. 3. assert fb_ta (external termination). 1. negate fb_ta (external termination). 1. set fb_r/w to read. 2. assert fb_cs n . auto-acnowledgeinternal termination. 2. sample fb_ta low and latch data. 1. start next cycle. system 2. place address on the external address signals. 2. drive data on the external data signals. 1. select the appropriate slave device. . assert transfer start. 1. negate transfer start. 1. flexbus asserts internal fb_ta microcontroller figure 2-26. read cycle flowchart the read cycle timing diagram is shown in the following figure. functional description k60 sub-family reference manual, rev. 6, nov 2011 712 freescale semiconductor, inc. note fb_ta does not have to be driven by the external device for internally-terminated bus cycles. note the processor drives the data lines during the first clock cycle of the transfer with the full 32-bit address. this may be ignored by standard connected devices using non-multiplexed address and data buses. however, some applications may find this feature beneficial. the address and data busses are muxed between the flexbus and another module. at the end of the read bus cycles the address signals are indeterminate. address address data tsiz aa=1 aa=0 aa=1 aa=0 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_be/bwen fb_ta fb_tsiz[1:0] figure 29-27. basic read-bus cycle 29.4.6.2 basic write bus cycle during a write cycle, the device sends data to memory or to a peripheral device. the following figure shows the write cycle flowchart. chapter 29 external bus interface (flexbus) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 713 1. set fb_r/w to write. 2. place address on the external address signals. 3. assert transfer start. 1. decode address. 1. start next cycle. 2. sample fb_ta low. external memory/peripheral 2. latch data on the external address signals. 3. assert fb_ta (external termination). 1. negate fb_ta (external termination). 1. select the appropriate slave device. 1. negate transfer start. 2. assert fb_cs n . . drive data. 1. flexbus asserts internal fb_ta auto acnowledgeinternal termination. flexbus figure 2-28. write-cycle flowchart the following figure shows the write cycle timing diagram. note the address and data busses are muxed between the flexbus and another module. at the end of the write bus cycles, the address signals are indeterminate. functional description k60 sub-family reference manual, rev. 6, nov 2011 714 freescale semiconductor, inc. address address data tsiz aa=1 aa=0 aa=1 aa=0 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_be/bwen fb_ta fb_tsiz[1:0] figure 29-29. basic write-bus cycle 29.4.6.3 bus cycle sizing this section shows timing diagrams for various port size scenarios. 29.4.6.3.1 bus cycle sizingbyte transfer, 8-bit device, no wait states the following figure illustrates the basic byte read transfer to an 8-bit device with no wait states: ? the address is driven on the full fb_ad[31:8] bus in the first clock. ? the device tristates fb_ad[31:24] on the second clock and continues to drive address on fb_ad[23:0] throughout the bus cycle. ? the external device returns the read data on fb_ad[31:24] and may tristate the data line or continue driving the data one clock after fb_ta is sampled asserted. chapter 29 external bus interface (flexbus) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 715 address address data tsiz = 01 aa=1 aa=0 aa=1 aa=0 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_be/bwen fb_ta fb_tsiz[1:0] figure 29-30. single byte-read transfer the following figure shows the similar configuration for a write transfer. the data is driven from the second clock on fb_ad[31:24]. functional description k60 sub-family reference manual, rev. 6, nov 2011 716 freescale semiconductor, inc. address address data tsiz=01 aa=1 aa=0 aa=1 aa=0 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_be/bwen fb_ta fb_tsiz[1:0] figure 29-31. single byte-write transfer 29.4.6.3.2 bus cycle sizing?word transfer, 16-bit device, no wait states the following figure illustrates the basic word read transfer to a 16-bit device with no wait states. ? the address is driven on the full fb_ad[31:8] bus in the first clock. ? the device tristates fb_ad[31:16] on the second clock and continues to drive address on fb_ad[15:0] throughout the bus cycle. ? the external device returns the read data on fb_ad[31:16] and may tristate the data line or continue driving the data one clock after fb_ta is sampled asserted. chapter 29 external bus interface (flexbus) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 717 address address data tsiz = 10 aa=1 aa=0 aa=1 aa=0 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_be/bwen fb_ta fb_tsiz[1:0] figure 29-32. single word-read transfer the following figure shows the similar configuration for a write transfer. the data is driven from the second clock on fb_ad[31:16]. functional description k60 sub-family reference manual, rev. 6, nov 2011 718 freescale semiconductor, inc. address address data tsiz=10 aa=1 aa=0 aa=1 aa=0 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_be/bwen fb_ta fb_tsiz[1:0] figure 29-33. single word-write transfer 29.4.6.3.3 bus cycle sizing?longword transfer, 32-bit device, no wait states the following figure depicts a longword read from a 32-bit device. chapter 29 external bus interface (flexbus) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 719 address address data tsiz = 00 aa=1 aa=0 aa=1 aa=0 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_be/bwen fb_ta fb_tsiz[1:0] figure 29-34. longword-read transfer the following figure illustrates the longword write to a 32-bit device. functional description k60 sub-family reference manual, rev. 6, nov 2011 720 freescale semiconductor, inc. address address data tsiz=00 aa=1 aa=0 aa=1 aa=0 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_be/bwen fb_ta fb_tsiz[1:0] figure 29-35. longword-write transfer 29.4.6.4 timing variations the flexbus module has several features that can change the timing characteristics of a basic read- or write-bus cycle to provide additional address setup, address hold, and time for a device to provide or latch data. 29.4.6.4.1 wait states wait states can be inserted before each beat of a transfer by programming the cscr n registers. wait states can give the peripheral or memory more time to return read data or sample write data. the following figures show the basic read and write bus cycles (also shown in figure 29-27 and figure 29-32 ) with the default of no wait states respectively. chapter 29 external bus interface (flexbus) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 721 address address data tsiz aa=1 aa=0 aa=1 aa=0 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_be/bwen fb_ta fb_tsiz[1:0] figure 29-36. basic read-bus cycle (no wait states) functional description k60 sub-family reference manual, rev. 6, nov 2011 722 freescale semiconductor, inc. address address data tsiz aa=1 aa=0 aa=1 aa=0 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_be/bwen fb_ta fb_tsiz[1:0] figure 29-37. basic write-bus cycle (no wait states) if wait states are used, the s1 state repeats continuously until the the chip-select auto- acknowledge unit asserts internal transfer acknowledge or the external fb_ta is recognized as asserted. the following figures show a read and write cycle with one wait state respectively. chapter 29 external bus interface (flexbus) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 723 address address data tsiz aa=1 aa=0 aa=1 aa=0 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_be/bwen fb_ta fb_tsiz[1:0] figure 29-38. read-bus cycle (one wait state) functional description k60 sub-family reference manual, rev. 6, nov 2011 724 freescale semiconductor, inc. address address data tsiz aa=1 aa=0 aa=1 aa=0 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_be/bwen fb_ta fb_tsiz[1:0] figure 29-39. write-bus cycle (one wait state) 29.4.6.4.2 address setup and hold the timing of the assertion and negation of the chip selects, byte selects, and output enable can be programmed on a chip-select basis. each chip-select can be programmed to assert one to four clocks after transfer start/address-latch enable ( fb_ts/fb_ale) is asserted. the following figures show read- and write-bus cycles with two clocks of address setup respectively. chapter 29 external bus interface (flexbus) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 725 address address data tsiz aa=1 aa=0 aa=1 aa=0 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_be/bwen fb_ta fb_tsiz[1:0] figure 29-40. read-bus cycle with two-clock address setup (no wait states) functional description k60 sub-family reference manual, rev. 6, nov 2011 726 freescale semiconductor, inc. address address data tsiz aa=1 aa=0 aa=1 aa=0 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_be/bwen fb_ta fb_tsiz[1:0] figure 29-41. write-bus cycle with two clock address setup (no wait states) in addition to address setup, a programmable address hold option for each chip select exists. address and attributes can be held one to four clocks after chip-select, byte- selects, and output-enable negate. the following figures show read and write bus cycles with two clocks of address hold respectively. chapter 29 external bus interface (flexbus) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 727 address address data tsiz aa=1 aa=0 aa=1 aa=0 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_be/bwen fb_ta fb_tsiz[1:0] figure 29-42. read cycle with two-clock address hold (no wait states) functional description k60 sub-family reference manual, rev. 6, nov 2011 728 freescale semiconductor, inc. address address data tsiz aa=1 aa=0 aa=1 aa=0 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_be/bwen fb_ta fb_tsiz[1:0] figure 29-43. write cycle with two-clock address hold (no wait states) the following figure shows a bus cycle using address setup, wait states, and address hold. chapter 29 external bus interface (flexbus) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 729 address address data tsiz aa=1 aa=0 aa=1 aa=0 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_be/bwen fb_ta fb_tsiz[1:0] figure 29-44. write cycle with two-clock address setup and two-clock hold (one wait state) 29.4.7 burst cycles the device can be programmed to initiate burst cycles if its transfer size exceeds the port size of the selected destination. the initiation of a burst cycle is encoded on the size pins. for burst transfers to smaller port sizes, fb_tsiz[1:0] indicates the size of the entire transfer. for example, with bursting enabled, a 16-bit transfer to an 8-bit port takes two beats (two byte-sized transfers), for which fb_tsiz[1:0] equals 10b throughout. a 32-bit transfer to an 8-bit port would take a 4-byte burst cycle, for which fb_tsiz[1:0] equals 00b throughout. with bursting disabled, any transfer larger than the port size breaks into multiple individual transfers. with bursting enabled, an access larger than port size results in a burst cycle of multiple beats. the following table shows the result of such transfer translations. functional description k60 sub-family reference manual, rev. 6, nov 2011 730 freescale semiconductor, inc. table 29-30. transfer size and port size translation port size ps[1:0] transfer size fb_tsiz[1:0] burst-inhibited: number of transfers burst enabled: number of beats 01 (8-bit) 10 (16-bits) 2 00 (32-bits) 4 11 (16 bytes) 16 1 x 16-bit 00 2 bits 2 11 16 bytes 8 00 2-bit 11 line 4 the flexbus can support 2-1-1-1 burst cycles to maximize system performance. delaying termination of the cycle can add wait states. if internal termination is used, different wait state counters can be used for the first access and the following beats. the cscr n registers enable bursting for reads, writes, or both. memory spaces can be declared burst-inhibited for reads and writes by clearing the appropriate cscrn[bstr,bstw] bits. the following figure shows a 32-bit read to an 8-bit device programmed for burst enable. the transfer results in a 4-beat burst and the data is driven on fb_ad[31:24]. the transfer size is driven at 32-bit (00) throughout the bus cycle. note in non-multiplexed address/data mode, the address on fb_a increments only during internally-terminated burst cycles. the first address is driven throughout the entire burst for externally- terminated cycles. in multiplexed address/data mode, the address is driven on fb_ad only during the first cycle for all terminated cycles. chapter 29 external bus interface (flexbus) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 731 address address data tsiz = 11 aa=1 aa=0 aa=1 aa=0 data data data add+1 add+2 add+3 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_be/bwen fb_ta fb_tsiz[1:0] figure 29-45. 32-bit-read burst from 8-bit port 2-1-1-1 (no wait states) the following figure shows a 32-bit write to an 8-bit device with burst enabled. the transfer results in a 4-beat burst and the data is driven on fb_ad[31:24]. the transfer size is driven at 32-bit (00) throughout the bus cycle. note the first beat of any write burst cycle has at least one wait state. if the bus cycle is programmed for zero wait states (cscr n [ws] = 0), one wait state is added. otherwise, the programmed number of wait states are used. functional description k60 sub-family reference manual, rev. 6, nov 2011 732 freescale semiconductor, inc. address address data tsiz aa=1 aa=0 aa=1 aa=0 datadata data add+1 add+2 add+3 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_be/bwen fb_ta fb_tsiz[1:0] figure 29-46. 32-bit-write burst to 8-bit port 3-1-1-1 (no wait states) the following figure shows a 32-bit read from an 8-bit device with burst inhibited. the transfer results in four individual transfers. the transfer size is driven at 32-bit (00) during the first transfer and at byte (01) during the next three transfers. note there is an extra clock of address setup (as) for each burst- inhibited transfer between states s0 and s1. chapter 29 external bus interface (flexbus) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 733 add data tsiz = 00 aa=1 aa=0 aa=1 aa=0 data data data tsiz = 01 add+3add+2 add+1 add+1 add+2 add+3 address fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oe fb_be/bwen fb_ta fb_tbst fb_tsiz[1:0] figure 29-47. 32-bit-read burst-inhibited from 8-bit port (no wait states) the following figure shows a 32-bit write to an 8-bit device with burst inhibited. the transfer results in four individual transfers. the transfer size is driven at 32-bit (00) during the first transfer and at byte (01) during the next three transfers. functional description k60 sub-family reference manual, rev. 6, nov 2011 734 freescale semiconductor, inc. add data tsiz = 00 aa=1 aa=0 aa=1 aa=0 data data data tsiz = 01 add+3add+2 add+1 add+1 add+2 add+3 address fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_be/bwen fb_ta fb_tbst fb_tsiz[1:0] figure 29-48. 32-bit-write burst-inhibited to 8-bit port (no wait states) the following figure illustrates another read burst transfer, but in this case a wait state is added between individual beats. note cscr n [ws] determines the number of wait states in the first beat. however, for subsequent beats, the cscr n [ws] (or cscr n [sws] if cscr n [swsen] is set) determines the number of wait states. chapter 29 external bus interface (flexbus) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 735 address address data tsiz = 00 aa=1 aa=0 aa=1 aa=0 data data add+1 add+2 add+3 data fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_be/bwen fb_ta fb_tsiz[1:0] figure 29-49. 32-bit-read burst from 8-bit port 3-2-2-2 (one wait state) the following figure illustrates a write burst transfer with one wait state. functional description k60 sub-family reference manual, rev. 6, nov 2011 736 freescale semiconductor, inc. address address data tsiz = 00 aa=1 aa=0 aa=1 aa=0 data data add+1 add+2 add+3 data fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_be/bwen fb_ta fb_tsiz[1:0] figure 29-50. 32-bit-write burst to 8-bit port 3-2-2-2 (one wait state) if address setup and hold are used, only the first and last beat of the burst cycle are affected. the following figure shows a read cycle with one clock of address setup and address hold. note in non-multiplexed address/data mode, the address on fb_a increments only during internally-terminated burst cycles (cscr n [aa] = 1). the attached device must be able to account for this, or a wait state must be added. the first address is driven throughout the entire burst for externally-terminated cycles. in multiplexed address/data mode, the address is driven on fb_ad only during the first cycle for internally- and externally-terminated cycles. chapter 29 external bus interface (flexbus) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 737 address address data tsiz=11 aa=1 aa=0 aa=1 aa=0 data data data add+1 add+2 add+3 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_be/bwen fb_ta fb_tsiz[1:0] figure 29-51. 32-bit-read burst from 8-bit port 3-1-1-1 (address setup and hold) the following figure shows a write cycle with one clock of address setup and address hold. address address data tsiz=11 aa=1 aa=0 aa=1 aa=0 data data data add+1 add+2 add+3 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_be/bwen fb_ta fb_tsiz[1:0] figure 29-52. 32-bit-write burst to 8-bit port 3-1-1-1 (address setup and hold) functional description k60 sub-family reference manual, rev. 6, nov 2011 738 freescale semiconductor, inc. 29.4.8 extended transfer start/address latch enable the fb_ts/fb_ale signal indicates that a bus transaction has begun and the address and attributes are valid. by default, the fb_ts/fb_ale signal asserts for a single bus clock cycle. when cscr n [exts] is set, the fb_ts/fb_ale signal asserts and remain asserted until the first positive clock edge after fb_cs n asserts. see the following figure. note when exts is set, cscr n [ws] must be programmed to have at least one primary wait state. address address data tsiz aa=1 aa=0 aa=1 aa=0 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_be/bwen fb_ta fb_tsiz[1:0] figure 29-53. read-bus cycle with cscr n one ait tate us rrors if the auto-acknowledge feature is not enabled for the address that generates the error, the bus cycle can be terminated by asserting fb_ta. if the processor must manage a bus error differently, asserting an interrupt to the core along with fb_ta when the bus error occurs can invoke an interrupt handler. chapter 29 external bus interface (flexbus) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 739 the types of accesses that cause the access to terminate with a bus error are: ? writes to write-protected region ? address with no hit to any chip select ? address with hits to multiple chip selects ? writes to reserved addresses in the memory map ? writes to reserved bits in the cspmcr register ? flexbus accesses when the flexbus is secure also, the device can hang if the flexbus is configured for external termination and the cspmcr is not configured for fb_ta. 29.5 initialization/application information 29.5.1 initializing a chip select to initially use a chip select: 1. configure the csar register. 2. configure the cscr register. 3. configure the csmr register, setting the valid bit. the cspmcr register is not required to be part of this procedure. however, it should only be configured when the flexbus is idle. the corresponding chip select can be valid. 29.5.2 reconfiguring a chip select to reconfigure a previously-used chip select, the chip select must be specified as invalid as shown below: 1. clear the csmr register's valid bit. 2. change settings in the csar register as necessary. 3. change settings in the cscr register as necessary. 4. change settings in the csmr register as necessary, and set the valid bit. the cspmcr register is not required to be part of this procedure. however, it should only be altered when the flexbus is idle. the corresponding chip select can be valid. initialization/application information k60 sub-family reference manual, rev. 6, nov 2011 740 freescale semiconductor, inc. chapter 30 ezport 30.1 overview note for the chip-specific implementation details of this module's instances see the chip configuration chapter. ezport is a serial flash programming interface that allows in-system programming (isp) of flash memory contents on a 32 bit general purpose micro-controller. memory contents can be read, erased and programmed from off-chip in a compatible format to many stand- alone flash memory chips, without necessitating the removal of the micro-controller from the system. 30.1.1 introduction the block diagram of the ezport is as following. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 741 flash controller ezport flash memory micro-controller core ezport enabled g reset controller reset reset out ezp_cs ezp_ck ezp_d ezp_q figure 30-1. ezport block diagram 30.1.2 features the ezport includes the following features: ? serial interface that is compatible with a subset of the spi format. ? able to read, erase and program flash memory. ? able to reset the micro-controller, allowing it to boot from the flash memory after the memory has been configured. 30.1.3 modes of operation the ezport can operate in one of two different modes, enabled or disabled. ? enabled when enabled, the ezport steals access to the flash memory, preventing access from other cores or peripherals. the rest of the microcontroller is disabled to avoid conflicts. the flash is configured for nvm special mode. ? disabled when the ezport is disabled, the rest of the micro-controller can access flash memory as normal. overview k60 sub-family reference manual, rev. 6, nov 2011 742 freescale semiconductor, inc. the ezport provides a simple interface to connect an external device to the flash memory on board a 32 bit micro-controller. the interface itself is compatible with the spi interface (with the ezport operating as a slave) running in either of the two following modes with data transmitted most significant bit first: ? cpol = 0, cpha = 0 ? cpol = 1, cpha = 1 commands are issued by the external device to erase, program or read the contents of the flash memory. the serial data out from the ezport is tri-stated unless data is being driven, allowing the signal to be shared among several different ezport (or compatible) devices in parallel, provided they have different chip selects. 30.2 external signal description the following table contains a list of ezport external signals, and the following sections explain them in detail. table 30-1. ezport external signal descriptions name description i/o ezp_ck ezport clock input ezp_cs ezport chip select input ezp_d ezport serial data in input ezp_q ezport serial data out output 30.2.1 ezport clock (ezp_ck) serial clock for data transfers. the serial data in (ezp_d) and chip select ( ezp_cs) are registered on the rising edge of ezp_ck while serial data out (ezp_q) is driven on the falling edge of ezp_ck. the maximum frequency of the ezport clock is half the system clock frequency for all commands except when executing the read data or read flexram commands. when executing these commands, the ezport clock has a maximum frequency of one-eighth the system clock frequency. chapter 30 ezport k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 743 30.2.2 ezport chip select ( ezp_cs) chip select for signalling the start and end of serial transfers. if ezp_cs is asserted during and when the micro-controller's reset out signal is negated, then ezport is enabled out of reset; otherwise it is disabled. after ezport is enabled, asserting ezp_cs commences a serial data transfer, which continues until ezp_cs is negated again. the negation of ezp_cs indicates the current command is finished and resets the ezport state machine so that it is ready to receive the next command. 30.2.3 ezport serial data in (ezp_d) serial data in for data transfers. ezp_d is registered on the rising edge of ezp_ck. all commands, addresses, and data are shifted in most significant bit first. when the ezport is driving output data on ezp_q, the data shifted in ezp_d is ignored. 30.2.4 ezport serial data out (ezp_q) serial data out for data transfers. ezp_q is driven on the falling edge of ezp_ck. it is tri-stated unless ezp_cs is asserted and the ezport is driving data out. all data is shifted out most significant bit first. 30.3 command definition the ezport receives commands from an external device and translates those commands into flash memory accesses. the following table lists the supported commands. table 30-2. ezport commands command description code address bytes data bytes accepted when secure? wren write enable 0x06 0 0 yes wrdi write disable 0x04 0 0 yes rdsr read status register 0x05 0 1 yes read flash read data 0x03 3 1 1+ no fast_read flash read data at high speed 0x0b 3 1 1+ 2 no sp flash section program 0x02 3 3 8 - section 4 no se flash sector erase 0xd8 3 3 0 no be flash bulk erase 0xc7 0 0 yes 5 table continues on the next page... command definition 60 sub-family reference manual, rev. 6, nov 2011 744 freescale semiconductor, inc. table 30-2. ezport commands (continued) command description code address bytes data bytes accepted when secure? reset reset chip 0xb9 0 0 yes wrfccob write fccob registers 0xba 0 12 yes 6 fast_rdfccob read fccob registers at high speed 0xbb 0 1 - 12 2 no wrflexram write flexram 0xbc 3 1 4 no rdflexram read flexram 0xbd 3 1 1+ no fast_rdflexram read flexram at high speed 0xbe 3 1 1+ 2 no 1. address must be 32-bit aligned (two lsbs must be zero). 2. one byte of dummy data must be shifted in before valid data is shifted out. 3. address must be 64-bit aligned (three lsbs must be zero). 4. a section is defined as the smaller of either half the size of flexram or the flash sector size. total number of data bytes programmed must be a multiple of 8. 5. bulk erase is accepted when security is set only if the bedis status bit is not set. 6. note that the flash will be in nvm special mode, restricting which types of commands can be executed through write_fccob when security is enabled. 30.3.1 command descriptions this section describes the module commands. 30.3.1.1 write enable the write enable command (wren) sets the write enable register bit in the ezport status register. the write enable bit must be set for a write command (sp, se, be, wrfccob or wrflexram) to be accepted. the write enable register bit clears on reset, on a write disable command, and at the completion of write command. this command should not be used if a write is already in progress. 30.3.1.2 write disable the write disable command (wrdi) clears the write enable register bit in the status register. this command should not be used if a write is already in progress. 30.3.1.3 read status register the read status register command (rdsr) returns the contents of the ezport status register. chapter 30 ezport k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 745 table 30-3. ezport status register 7 6 5 4 3 2 1 0 r fs wef flexram bedis wen wip w reset: 0/1 1 0 0 0 0/1 2 0/1 3 0 1 4 1. reset value reflects the status of flash security out of reset. 2. reset value reflects flexnvm flash partitioning. if flexnvm flash has been paritioned for eeprom, this bit is set immediately after reset. note that flexram is cleared after the ezport initialization sequence completes, as indicated by clearing of wip. 3. reset value reflects if bulk erase is enabled or disabled out of reset 4. initial value of wip is 1, but the value clears to 0 after ezport initialization is complete table 30-4. ezport status register field descriptions field description 0 wip write in progress. status flag that sets after a write command (sp, se, be, wrfccob, or wrflexram) is accepted and clears once the flash memory has completed all operations associated with that command as indicated by the command complete interrupt flag (ccif) inside the flash. also asserted on reset and clears when ezport initialization is complete. only the read status register (rdsr) command is accepted while a write is in progress. 0 = write is not in progress. accept any command. 1 = write is in progress. only accept rdsr command. 1 wen write enable control bit that must be set before a write command (sp, se, be, wrfccob, or wrflexram) is accepted. is set by the write enable (wren) command and cleared by reset or a write disable (wrdi) command. it also clears when the flash memory has completed all operations associated with the command. 0 = disables the following write command. 1 = enables the following write command. 2 bedis bulk erase disable status flag which indicates if bulk erase (be) is disabled when flash is secure. 0 = bulk erase is enabled. 1 = bulk erase is disabled if the fs bit is also set. attempts to issue a be command will result in the wef flag being set. 3 flexram for devices with flexram: flexram mode status flag that indicates the current mode of the flexram. only valid when the wip bit is cleared. 0 = flexram is in ram mode. rd/wrflexram command can be used to read/write data in flexram. 1 = flexram is in eeprom mode. sp command is not accepted. rd/wrflexram command can be used to read/write data in the flexram. table continues on the next page... command definition 60 sub-family reference manual, rev. 6, nov 2011 746 freescale semiconductor, inc. table 30-4. ezport status register field descriptions (continued) field description 6 wef write error flag status flag that indicates if there has been an error while executing a write command (sp, se, be, wrfccob, or wrflexram). the wef flag will set if either the flash access error flag (accerr) or the flash protection violation flag (fpviol) or the memory controller command completion status flag (mgstat0) inside the flash memory is set at the completion of the write command. see the flash memory chapter for further description of these flags and their sources. the wef flag clears after a read status register (rdsr) command. 0 = no error on previous write command. 1 = error on previous write command. 7 fs flash security status flag that indicates if the flash is secure. see table 30-2 for the list of commands which will be accepted when flash is secure. flash security can be disabled by performing a bulk erase (be) command. 0 = flash is not secure 1 = flash is secure. 30.3.1.4 read data the read data (read) command returns data from the flash memory or flexnvm, depending on the initial address specified in the command word. the initial address must be 32-bit aligned (the two lsbs must be zero). data continues being returned for as long as the ezport chip select ( ezp_cs) is asserted, with the address automatically incrementing. in this way, the entire contents of flash can be returned by one command. attempts to read from an address which does not fall within the valid address range (see flash memory map for ezport access ) for the flash memory regions returns junk data. for this command to return the correct data, the ezport clock (ezp_ck) must run at the internal system clock divided by eight or slower. this command is not accepted if the wef, wip, or fs bit in the ezport status register is set. 30.3.1.5 read data at high speed the read data at high speed command (fast_read) is identical to the read command, except for the inclusion of a dummy byte following the address bytes and before the first data byte is returned. this command can be run with an ezport clock (ezp_ck) frequency of half the internal system clock frequency of the micro-controller or slower. this command is not accepted if the wef, wip, or fs bit in the ezport status register is set. chapter 30 ezport k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 747 30.3.1.6 section program the section program (sp) command programs up to one section of flash memory which has previously been erased. a section is defined as the smaller of the flash sector size or half the size of the flexram/programming acceleration ram. the starting address of the memory to program is sent after the command word and must be a 64-bit aligned address (the three lsbs must be zero). as data is shifted in, the ezport buffers the data in flexram/programming acceleration ram before executing a 'program section' command within the flash (see flash block guide for more detail). for this reason, the number of bytes to program must be a multiple of 8 and up to one flash section can be programmed at a time. attempts to program more than one section, across a sector boundary or from an initial address which does not fall within the valid address range (see flash memory map for ezport access ) for the flash causes the wef flag to set. for devices with flexram: this command requires the flexram to be configured for traditional ram operation. by default, after entering ezport mode, the flexram is configured for traditional ram operation. if the user reconfigures flexram for eeprom operation (see flash memory chapter for details on how flexram function is modified), then the user should use the wrfccob command to configure flexram back to traditional ram operation before issuing a sp command. this command is not accepted if the wef, wip, flexram, or fs bit is set or if the wen bit is not set in the ezport status register. 30.3.1.7 sector erase the sector erase (se) command erases the contents of one sector of flash memory. the three byte address sent after the command byte can be any address within the sector to erase, but must be a 64-bit aligned address (the three lsbs must be zero). attempts to erase from an initial address which does not fall within the valid address range (see flash memory map for ezport access ) for the flash results in the wef flag being set. this command is not accepted if the wef, wip or fs bit is set or if the wen bit is not set in the ezport status register. command definition k60 sub-family reference manual, rev. 6, nov 2011 748 freescale semiconductor, inc. 30.3.1.8 bulk erase the bulk erase (be) command erases the entire contents of flash memory, ignoring any protected sectors or flash security. flash security is disabled upon successful completion of the be command. attempts to issue a be command while the bedis and fs bits are set results in the wef flag being set in the ezport status register. also, this command is not accepted if the wef or wip bit is set or if the wen bit is not set in the ezport status register. 30.3.1.9 ezport reset chip the reset chip (reset) command forces the chip into the reset state. if the ezport chip select ( ezp_cs) pin is asserted at the end of the reset period then ezport is enabled; otherwise, it is disabled. this command allows the chip to boot up from flash memory after it has been programmed by an external source. this command is not accepted if the wip bit is set in the ezport status register. 30.3.1.10 write fccob registers the write fccob registers (wrfccob) command allows the user to write to the flash common command object registers and execute any command allowed by the flash. note the flash is configured in nvm special mode, restricting which commands can be executed by the flash when security is enabled. after receiving 12 bytes of data, ezport writes the data to the fccob 0-b registers in the flash and then automatically launches the command within the flash. if greater or less than 12 bytes of data is received, this command has unexpected results and may result in the wef flag being set. this command is not accepted if the wef or wip bit is set or if the wen bit is not set in the ezport status register. chapter 30 ezport k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 749 30.3.1.11 read fccob registers at high speed the read fccob registers at high speed (fast_rdfccob) command allows the user to read the contents of the flash common command object registers. after receiving the command, ezport waits for one dummy byte of data before returning fccob register data starting at fccob 0 and ending with fccob b. this command can be run with an ezport clock (ezp_ck) frequency half the internal system clock frequency of the micro-controller or slower. attempts to read greater than 12 bytes of data returns junk data. this command is not be accepted if the wef, wip, or fs bit in the ezport status register is set. 30.3.1.12 write flexram this command is only applicable for devices with flexram. the write flexram (wrflexram) command allows the user to write 4-bytes of data to the flexram. if the flexram is configured for eeprom operation, the wrflexram command can effectively be used to create data records in eeprom- flash memory. by default, after entering ezport mode, the flexram is configured for traditional ram operation and functions as direct ram. the user can alter the flexram configuration by using wrfccob to execute a 'set flexram' or 'program partition' command within the flash. the address of the flexram location to be written is sent after the command word and must be a 32-bit aligned address (the two lsbs must be zero). attempts to write an address which does not fall within the valid address range (see flash memory map for ezport access ) for the flexram results in the wef flag being set. after receiving 4 bytes of data, ezport writes the data to the flexram. if greater or less than 4 bytes of data is received, this command has unexpected results and may result in the wef flag being set. this command is not accepted if the wef, wip or fs bit is set or if the wen bit is not set in the ezport status register. 30.3.1.13 read flexram this command is only applicable for devices with flexram. command definition k60 sub-family reference manual, rev. 6, nov 2011 750 freescale semiconductor, inc. the read flexram (rdflexram) command returns data from the flexram. if the flexram is configured for eeprom operation, the rdflexram command can effectively be used to read data from eeprom-flash memory. data continues being returned for as long as the ezport chip select ( ezp_cs) is asserted, with the address automatically incrementing. in this way, the entire contents of flexram can be returned by one command. the initial address must be 32-bit aligned (the two lsbs must be zero). attempts to read from an address which does not fall within the valid address range (see flash memory map for ezport access ) for the flexram returns junk data. for this command to return the correct data, the ezport clock (ezp_ck) must run at the internal system clock divided by eight or slower. this command is not accepted if the wef, wip, or fs bit in the ezport status register are set. 30.3.1.14 read flexram at high speed this command is only applicable for devices with flexram. the read flexram at high speed (fast_rdflexram) is identical to the rdflexram command, except for the inclusion of a dummy byte following the address bytes and before the first data byte is returned. this command can be run with an ezport clock (ezp_ck) frequency up to and including half the internal system clock frequency of the micro-controller. this command is not accepted if the wef, wip, or fs bit in the ezport status register is set. 30.4 flash memory map for ezport access the following table shows the flash memory map for access through ezport. note the flash block address map for access through ezport may not conform to the system memory map. changes are made to allow the ezport address width to remain at 24-bits. table 30-5. flash memory map for ezport access valid start address size flash block valid commands 0x0000_0000 see device's chip configuration details flash read, fast_read, sp, se, be table continues on the next page... chapter 0 ezport 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 71 table 30-5. flash memory map for ezport access (continued) valid start address size flash block valid commands 0x0080_0000 see devices chip configuration details flexnvm read, fast_read, sp, se, be 0x0000_0000 see devices chip configuration details flexram rdflexram, fast_rdflexram, wrflexram, be flash memory map for ezport access k60 sub-family reference manual, rev. 6, nov 2011 752 freescale semiconductor, inc. chapter 31 cyclic redundancy check (crc) 31.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the cyclic redundancy check (crc) module generates 16/32-bit crc code for error detection. the crc module provides a programmable polynomial, was, and other parameters required to implement a 16-bit or 32-bit crc standard. the 16/32-bit code is calculated for 32 bits of data at a time. 31.1.1 features features of the crc module include: ? hardware crc generator circuit using a 16-bit or 32-bit (programmable) shift register. ? programmable initial seed value and polynomial. ? option to transpose input data or output data (the crc result) bitwise or bytewise. this option is required for certain crc standards. a bytewise transpose operation is not possible when accessing the crc data register via 8-bit accesses. in this case, the user's software must perform the bytewise transpose function. ? option for inversion of final crc result. ? 32-bit cpu register programming interface. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 753 31.1.2 block diagram this is a block diagram of the crc. was [31:24] polynomial mux crc engine not logic reverse logic reverse logic [23:16] [15:8] [7:0] crc data seed data checksum tot totr fxor combine logic tcrc 16-/32-bit select crc data register crc polynomial register [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] crc data register figure 31-1. programmable cyclic redundancy check (crc) block diagram 31.1.3 modes of operation various mcu modes affect the crc module's functionality. 31.1.3.1 run mode this is the basic mode of operation. 31.1.3.2 low power modes (wait or stop) any crc calculation in progress stops when the mcu enters a low power mode that disables the module clock. it resumes after the clock is enabled or via the system reset for exiting the low power mode. clock gating for this module is mcu dependent. 31.2 memory map and register descriptions memory map and register descriptions k60 sub-family reference manual, rev. 6, nov 2011 754 freescale semiconductor, inc. crc memory map absolute address (hex) register name width (in bits) access reset value section/ page 4003_2000 crc data register (crc_crc) 32 r/w ffff_ ffffh 31.2.1/ 755 4003_2004 crc polynomial register (crc_gpoly) 32 r/w 0000_1021h 31.2.2/ 756 4003_2008 crc control register (crc_ctrl) 32 r/w 0000_0000h 31.2.3/ 757 31.2.1 crc data register (crc_crc) the crc data register contains the value of the seed, data, and checksum. when the ctrl[was] bit is set, any write to the data register is regarded as the seed value. when the ctrl[was] bit is cleared, any write to the data register is regarded as data for general crc computation. in 16-bit crc mode, the hu and hl fields are not used for programming the seed value, and reads of these fields return an indeterminate value. in 32-bit crc mode, all fields are used for programming the seed value. when programming data values, the values can be written 8 bits, 16 bits, or 32 bits at a time, provided all bytes are contiguous; with msb of data value written first. after all data values are written, the crc result can be read from this data register. in 16- bit crc mode, the crc result is available in the lu and ll fields. in 32-bit crc mode, all fields contain the result. reads of this register at any time return the intermediate crc value, provided the crc module is configured. address: crc_crc is 4003_2000h base + 0h offset = 4003_2000h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r hu hl lu ll w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 crc_crc field descriptions field description 31?24 hu crc high upper byte in 16-bit crc mode (the ctrl[tcrc] bit is 0), this field is not used for programming a seed value. in 32- bit crc mode (the ctrl[tcrc] bit is 1), values written to this field are part of the seed value when the ctrl[was] bit is 1. when the ctrl[was] bit is 0, data written to this field is used for crc checksum generation in both 16-bit and 32-bit crc modes. table continues on the next page... chapter 1 cyclic redundancy chec crc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 7 crc_crc field descriptions (continued) field description 2316 hl crc high lower byte in 16-bit crc mode (the ctrl[tcrc] bit is 0), this field is not used for programming a seed value. in 32- bit crc mode (the ctrl[tcrc] bit is 1), values written to this field are part of the seed value when the ctrl[was] bit is 1. when the ctrl[was] bit is 0, data written to this field is used for crc checksum generation in both 16-bit and 32-bit crc modes. 158 lu crc low upper byte when the ctrl[was] bit is 1, values written to this field are part of the seed value. when the ctrl[was] bit is 0, data written to this field is used for crc checksum generation. 70 ll crc low lower byte when the ctrl[was] bit is 1, values written to this field are part of the seed value. when the ctrl[was] bit is 0, data written to this field is used for crc checksum generation. 31.2.2 crc polynomial register (crc_gpoly) this register contains the value of the polynomial for the crc calculation. the high field contains the upper 16 bits of the crc polynomial, which are used only in 32-bit crc mode. writes to the high field are ignored in 16-bit crc mode. the low field contains the lower 16 bits of the crc polynomial, which are used in both 16- and 32-bit crc modes. address: crc_gpoly is 4003_2000h base + 4h offset = 4003_2004h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r high low w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 crc_gpoly field descriptions field description 31?16 high high polynominal half-word this field is writable and readable in 32-bit crc mode (the ctrl[tcrc] bit is 1). this field is not writable in 16-bit crc mode (the ctrl[tcrc] bit is 0). 15?0 low low polynominal half-word this field is writable and readable in both 32-bit and 16-bit crc modes. memory map and register descriptions k60 sub-family reference manual, rev. 6, nov 2011 756 freescale semiconductor, inc. 31.2.3 crc control register (crc_ctrl) this register controls the configuration and working of the crc module. appropriate bits must be set before starting a new crc calculation. a new crc calculation is initialized by asserting the ctrl[was] bit and then writing the seed into the crc data register. address: crc_ctrl is 4003_2000h base + 8h offset = 4003_2008h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r tot totr 0 fxor was tcrc 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 crc_ctrl field descriptions field description 31?30 tot type of transpose for writes these bits define the transpose configuration of the data written to the crc data register. refer to the description of the transpose feature for the available transpose options. 00 no transposition. 01 bits in bytes are transposed; bytes are not transposed. 10 both bits in bytes and bytes are transposed. 11 only bytes are transposed; no bits in a byte are transposed. 29?28 totr type of transpose for read these bits identify the transpose configuration of the value read from the crc data register. refer to the description of the transpose feature for the available transpose options. 00 no transposition. 01 bits in bytes are transposed; bytes are not transposed. 10 both bits in bytes and bytes are transposed. 11 only bytes are transposed; no bits in a byte are transposed. 27 reserved this read-only field is reserved and always has the value zero. 26 fxor complement read of crc data register some crc protocols require the final checksum to be xored with 0xffffffff or 0xffff. asserting this bit enables "on the fly" complementing of read data. 0 no xor on reading. 1 invert or complement the read value of the crc data register. 25 was write crc data register as seed when this bit is asserted, a value written to the crc data register is considered a seed value. when this bit is de-asserted, a value written to the crc data register is taken as data for crc computation. 0 writes to the crc data register are data values. 1 writes to the crc data register are seed values. table continues on the next page... chapter 1 cyclic redundancy chec crc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 77 crc_ctrl field descriptions (continued) field description 24 tcrc width of crc protocol. 0 16-bit crc protocol. 1 32-bit crc protocol. 230 reserved this read-only field is reserved and always has the value zero. 31.3 functional description 31.3.1 crc initialization/re-initialization to enable the crc calculation, the user must program the was, polynomial, and necessary parameters for transpose and crc result inversion in the applicable registers. asserting the ctrl[was] bit enables the programming of the seed value into the crc data register. after a completed crc calculation, re-asserting the ctrl[was] bit and programming a seed (whether the value is new or a previously used seed value) re-initialize the crc module for a new crc computation. all other parameters must be set before programming the seed value and subsequent data values. 31.3.2 crc calculations in 16-bit and 32-bit crc modes, data values can be programmed 8 bits, 16 bits, or 32 bits at a time, provided all bytes are contiguous. non-contiguous bytes can lead to an incorrect crc computation. 31.3.2.1 16-bit crc compute a 16-bit crc with the following steps: 1. clear the ctrl[tcrc] bit to enable 16-bit crc mode. 2. program the transpose and complement options in the ctrl register as required for the crc calculation. see transpose feature and crc result complement for details. 3. write a 16-bit polynomial to the gpoly[low] field. the gpoly[high] field is not usable in 16-bit crc mode. 4. set the ctrl[was] bit to program the seed value. functional description k60 sub-family reference manual, rev. 6, nov 2011 758 freescale semiconductor, inc. 5. write a 16-bit seed to crc[lu:ll]. crc[hu:hl] are not used. 6. clear the ctrl[was] bit to start writing data values. 7. write data values into crc[hu:hl:lu:ll]. a crc is computed on every data value write, and the intermediate crc result is stored back into crc[lu:ll]. 8. when all values have been written, read the final crc result from crc[lu:ll]. transpose and complement operations are performed "on the fly" while reading or writing values. see transpose feature and crc result complement for details. 31.3.2.2 32-bit crc compute a 32-bit crc with the following steps: 1. set the ctrl[tcrc] bit to enable 32-bit crc mode. 2. program the transpose and complement options in the ctrl register as required for the crc calculation. see transpose feature and crc result complement for details. 3. write a 32-bit polynomial to gpoly[high:low]. 4. set the ctrl[was] bit to program the seed value. 5. write a 32-bit seed to crc[hu:hl:lu:ll]. 6. clear the ctrl[was] bit to start writing data values. 7. write data values into crc[hu:hl:lu:ll]. a crc is computed on every data value write, and the intermediate crc result is stored back into crc[hu:hl:lu:ll]. 8. when all values have been written, read the final crc result from crc[hu:hl:lu:ll]. the crc is calculated bytewise, and two clocks are required to complete one crc calculation. transpose and complement operations are performed "on the fly" while reading or writing values. see transpose feature and crc result complement for details. 31.3.3 transpose feature by default, the transpose feature is not enabled. however, some crc standards require the input data and/or the final checksum to be transposed. the user software has the option to configure each transpose operation separately, as desired by the crc standard. the data is transposed "on the fly" while being read or written. some protocols use little endian format for the data stream to calculate a crc. in this case, the transpose feature usefully flips the bits. this transpose option is one of the types supported by the crc module. chapter 31 cyclic redundancy check (crc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 759 31.3.3.1 types of transpose the crc module provides several types of transpose functions to flip the bits and/or bytes (for both writing input data and reading the crc result, separately using the ctrl[tot] or ctrl[totr] fields) according to the crc calculation being used. the following types of transpose functions are available for writing to and reading from the crc data register. 1. ctrl[tot] or ctrl[totr] is 00 no transposition occurs. 2. ctrl[tot] or ctrl[totr] is 01 bits in a byte are transposed, while bytes are not transposed. reg[31:0] becomes {reg[24:31], reg[16:23], reg[8:15], reg[0:7]} 15 15 8 7 0 0 7 8 31 31 24 23 16 16 23 24 figure 31-5. transpose type 01 3. ctrl[tot] or ctrl[totr] is 10 both bits in bytes and bytes are transposed. reg[31:0] becomes = {reg[0:7], reg[8:15],reg[16:23], reg[24:31]} 31 31 0 0 figure 31-6. transpose type 10 4. ctrl[tot] or ctrl[totr] is 11 bytes are transposed, but bits are not transposed. reg[31:0] becomes {reg[7:0], reg[15:8], reg[23:16], reg[31:24]} functional description k60 sub-family reference manual, rev. 6, nov 2011 760 freescale semiconductor, inc. 15 2416 0 31 23 7 8 31 8 0 16 15 7 23 24 figure 31-7. transpose type 11 note for 8-bit and 16-bit write accesses to the crc data register, the data is transposed with zeros on the unused byte or bytes (taking 32 bits as a whole), but the crc is calculated on the valid byte(s) only. when reading the crc data register for a 16-bit crc result and using transpose options 10 and 11, the resulting value after transposition resides in the crc[hu:hl] fields. the user software must account for this situation when reading the 16-bit crc result, so reading 32 bits is preferred. 31.3.4 crc result complement when the ctrl[fxor] bit is set, the checksum is complemented: the crc result complement function outputs the complement of the checksum value stored in the crc data register every time the crc data register is read. when the ctrl[fxor] bit is cleared, reading the crc data register accesses the raw checksum value. chapter 31 cyclic redundancy check (crc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 761 functional description k60 sub-family reference manual, rev. 6, nov 2011 762 freescale semiconductor, inc. chapter 32 memory-mapped cryptographic acceleration unit (mmcau) 32.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the memory-mapped cryptographic acceleration unit (mmcau) is a coprocessor that is connected to the processor's private peripheral bus (ppb). it supports the hardware implementation of a set of specialized operations to improve the throughput of software- based security encryption/decryption operations and message digest functions. the mmcau supports acceleration of the des, 3des, aes, md5, sha-1 and sha-256 algorithms. freecsale provides an optimized, callable c-function library that provides the appropriate software building blocks to implement higher-level security functions. 32.2 mmcau block diagram the following simplified block diagram illustrates the mmcau. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 763 control address data 0 1 2 3 control logic cau_str 4 9 32 paddr pwdata & cmd go 15 prdata op1 32 32 result cau mmcau translator 4-entry fifo private peripheral bus (ppb) 32 32 32 32 figure 32-1. mmcau block diagram table 32-1. mmcau parts table item description translator submodule provides the bridge between the private apb interface and the cau module. passes memory- mapped commands and data on the apb to/from the cau 4-entry fifo contains commands and input operands plus the associated control captured from the ppb and sent to the cau cau 3-terminal block with a command and (optional) input operand and a result bus. more details in following figure. the following figure shows the cau block in more detail. mmcau block diagram k60 sub-family reference manual, rev. 6, nov 2011 764 freescale semiconductor, inc. alu cax ca0-ca3 operand1 decode command hash go aes row datapath control result register file des / caa figure 32-2. top level cau block diagram 32.3 overview as the name suggests, the mmcau provides a mechanism for memory-mapped register reads and writes to be transformed into specific commands and operands sent to the cau coprocessor. the mmcau translator module performs all the required control functions affecting the transmission of commands to the cau module and, if needed, stalling the ppb transactions based on the state of the 4-entry command/data fifo, etc. the translator also performs some basic integrity checks on ppb operations. the set of implemented algorithms provides excellent support for network security standards (ssl, ipsec). additionally, using the mmcau efficiently permits the implementation of any higher level functions or modes of operation (hmac, cbc, etc.) based on the supported algorithms. the cryptographic algorithms are implemented partially in software with only functions critical to increasing performance implemented in hardware. the mmcau allows for efficient, fine-grained partitioning of functions between hardware and software: ? implement the innermost security kernel functions using the coprocessor instructions ? implement higher-level functions in software by using the standard processor instructions chapter 32 memory-mapped cryptographic acceleration unit (mmcau) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 765 this partitioning of functions is key to minimizing size of the mmcau while maintaining a high level of throughput. using software for some functions also simplifies the mmcau design. the cau implements a set of coprocessor commands that operate on a register file of 32-bit registers. 32.4 features the mmcau includes these distinctive features: ? supports des, 3des, aes, md5, sha-1, and sha-256 algorithms ? simple, flexible programming model ? ability to send up to three commands in one data write operation 32.5 memory map/register definition the cau contains multiple registers used by each of the supported algorithms. the following table shows which registers are applicable to each supported algorithm, and indicates the corresponding letter designations for each algorithm. for more information on these letter designations, refer to the algorithm specifications. code register des aes md5 sha-1 sha-256 0 cau status register (casr) 1 cau accumulator (caa) a t t 2 general purpose register 0 (ca0) c w0 a a 3 general purpose register 1 (ca1) d w1 b b b 4 general purpose register 2 (ca2) l w2 c c c 5 general purpose register 3 (ca3) r w3 d d d 6 general purpose register 4 (ca4) e e table continues on the next page... features 60 sub-family reference manual, rev. 6, nov 2011 766 freescale semiconductor, inc. code register des aes md5 sha-1 sha-256 7 general purpose register 5 (ca5) w f 8 general purpose register 6 (ca6) g 9 general purpose register 7 (ca7) h 10 general purpose register 8 (ca8) w/t 1 the cau only supports 32-bit operations and register accesses. all registers support read, write, and alu operations. however, only bits 1C0 of the casr are writeable. bits 31C2 of the casr must be written as 0 for compatibility with future versions of the cau. the codes listed in this section are used in the memory-mapped commands. for more details on this, see mmcau programming model . note in the following table, the "address" or "offset" refers to the command code value for the cau registers. cau memory map absolute address (hex) register name width (in bits) access reset value section/ page e008_1000 status register (cau_casr) 32 r/w 2000_0000h 32.5.1/ 768 e008_1001 accumulator (cau_caa) 32 r/w 0000_0000h 32.5.2/ 769 e008_1002 general purpose register (cau_ca0) 32 r/w 0000_0000h 32.5.3/ 769 e008_1003 general purpose register (cau_ca1) 32 r/w 0000_0000h 32.5.3/ 769 e008_1004 general purpose register (cau_ca2) 32 r/w 0000_0000h 32.5.3/ 769 e008_1005 general purpose register (cau_ca3) 32 r/w 0000_0000h 32.5.3/ 769 e008_1006 general purpose register (cau_ca4) 32 r/w 0000_0000h 32.5.3/ 769 table continues on the next page... chapter 2 memory-mapped cryptographic acceleration unit mmcau 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 767 cau memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page e008_1007 general purpose register (cau_ca5) 32 r/w 0000_0000h 32.5.3/ 769 e008_1008 general purpose register (cau_ca6) 32 r/w 0000_0000h 32.5.3/ 769 e008_1009 general purpose register (cau_ca7) 32 r/w 0000_0000h 32.5.3/ 769 e008_100a general purpose register (cau_ca8) 32 r/w 0000_0000h 32.5.3/ 769 32.5.1 status register (cau_casr) casr contains the status and configuration for the cau. address: cau_casr is e008_1000h base + 0h offset = e008_1000h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r ver 0 dpe ic w reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cau_casr field descriptions field description 31?28 ver cau version indicates cau version. 0x1 initial cau version. 0x2 second version, added support for sha-256 algorithm.(this is the value on this device) 27?2 reserved this read-only field is reserved and always has the value zero. reserved, must be cleared. 1 dpe des parity error indicates whether the des parity error is detected. 0 no error detected. 1 des key parity error detected. 0 ic illegal command indicates an illegal instruction has been executed. 0 no illegal commands issued. 1 illegal command issued. memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 768 freescale semiconductor, inc. 32.5.2 accumulator (cau_caa) commands use the cau accumulator for storage of results and as an operand for the cryptographic algorithms. address: cau_caa is e008_1000h base + 1h offset = e008_1001h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r acc w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cau_caa field descriptions field description 31?0 acc accumulator stores results of various cau commands. 32.5.3 general purpose register (cau_ca) the general purpose register is used in the cau commands for storage of results and as operands for the various cryptographic algorithms. addresses: cau_ca0 is e008_1000h base + 2h offset = e008_1002h cau_ca1 is e008_1000h base + 3h offset = e008_1003h cau_ca2 is e008_1000h base + 4h offset = e008_1004h cau_ca3 is e008_1000h base + 5h offset = e008_1005h cau_ca4 is e008_1000h base + 6h offset = e008_1006h cau_ca5 is e008_1000h base + 7h offset = e008_1007h cau_ca6 is e008_1000h base + 8h offset = e008_1008h cau_ca7 is e008_1000h base + 9h offset = e008_1009h cau_ca8 is e008_1000h base + ah offset = e008_100ah bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r can w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cau_ca n iel escritions fiel escrition n eneral urose reisters use y the u coans oe crytorahic oerations wor with seciic reisters hater eoryae rytorahic cceleration unit u ufaily reerence anual re o freescale eiconuctor nc 32.6 functional description this section discusses the programming model and operation of the mmcau. 32.6.1 mmcau programming model the 4-entry fifo is indirectly mapped into a 4-kbyte address space associated with the mmcau (located at byte addresses 0xe008_1000 - 0xe008_1fff on this device). this address space is effectively split into 2 equal regions: ? one used to directly write commands for cau load operations ? the other used to send commands and input operands for cau loads data writes on the ppb are loaded into this fifo and automatically converted into cau load operands by the mmcau translator. data reads on the ppb are converted into cau store register operations where the result is returned to the processor as the read data value. the cau requires a 15-bit command (and optionally, a 32-bit input operand) for each cau load (ppb write). the 15-bit command includes the 9-bit opcode plus other bits statically formed by the mmcau translator logic controlling the cau. the following figure shows the 4-kbyte address space and the mapping of the cau commands into this space. note although the indirect store/load portion of the address space in the figure only shows the indirect load/store commands, direct load commands can also be used in this space. however, it is more efficient to use the direct load portion of the address space. note accesses to the reserved space in the direct load space is terminated with an error, while accesses to the reserved space in the indirect load/store space is detected as an illegal cau command. see mmcau integrity checks for details. functional description k60 sub-family reference manual, rev. 6, nov 2011 770 freescale semiconductor, inc. 0xe008_1000 0xe008_17ff direct loads (commands only) cnop, adra, mvra, mvar, aess, aesis, aesr, aesir, desr, desk, hash, shs, mds, shs2, and ill commands 0xe008_0040 reserved (terminated with error) 0xe008_1fff 0xe008_1800 indirect load/stores (commands & operands) 0xe008_1880 0xe008_18a8 0xe008_1840 0xe008_1868 0xe008_1900 0xe008_1928 0xe008_18c0 0xe008_18e8 0xe008_1980 0xe008_19a8 0xe008_19c0 0xe008_19e8 0xe008_1b00 0xe008_1b28 0xe008_1b40 0xe008_1b68 str cax ldr cax radr cax adr cax rotl cax xor cax aesic cax aesc cax reserved (terminated with illegal command) figure 32-15. mmcau memory map 32.6.1.1 direct loads the mmcau supports writing multiple commands in each 32-bit direct write operation. each 9-bit opcode also includes a valid bit. therefore, one, two, or three commands can be transmitted in a single 32-bit ppb write. the following figure illustrates the accepted formats for the 32-bit mmcau write data value: 1 cau_cmd1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 31 0 4 8 12 16 20 24 28 1 command cau_cmd1 1 0 cau_cmd2 1 0 0 0 0 0 0 0 0 0 00 31 0 4 8 12 16 20 24 28 2 commands cau_cmd1 1 0 cau_cmd2 1 0 1 cau_cmd3 31 0 4 8 12 16 20 24 28 3 commands figure 32-16. direct loads chapter 32 memory-mapped cryptographic acceleration unit (mmcau) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 771 32.6.1.2 indirect loads for cau load operations requiring a 32-bit input operand, the address contains the 9-bit opcode to be passed to the mmcau while the data is the 32-bit operand. specifically, the mmcau address and data for these indirect writes is defined as: mmcau base address 1 0 0 31 0 4 8 12 16 20 24 28 cau_cmd write address op1 31 0 4 8 12 16 20 24 28 write data figure 32-17. indirect loads 32.6.1.3 indirect stores for cau store operations, a ppb read is performed with the appropriate cau store register opcode embedded in the address. this appears as another indirect command. the details are: mmcau base address 1 0 0 31 0 4 8 12 16 20 24 28 cau_str+rn read address cax 31 0 4 8 12 16 20 24 28 read data figure 32-18. indirect store 32.6.2 mmcau integrity checks if an illegal operation or access is attempted, the ppb bus cycle is terminated with an error response and the operation is aborted and not sent to the cau. the mmcau performs a series of address and data integrity checks as described in the following sections. the results of these checks are logically summed together, and if appropriate, a ppb error termination is generated. 32.6.2.1 address integrity checks the mmcau address checking includes the following. see figure 32-15 for the mmcau memory map details. functional description k60 sub-family reference manual, rev. 6, nov 2011 772 freescale semiconductor, inc. ? any mmcau reference using a non-0-modulo-4 byte address (addr[1:0] 00) generates an error termination. ? for mmcau writes: ? only the first 64 bytes of the 2-kbyte direct write address space can be referenced. attempting to access regions beyond the first 64 bytes terminates with an error. ? the second 2-kbyte space defines the indirect address-as-command region and any reference in this space is allowed by the mmcau. note the cau contains error logic to detect any illegal command sent to it. accordingly, there are address values in this upper 2 kbyte region of the address space that are passed to the cau, and then detected as illegal commands. if the cau detects an illegal command, it sets the casr[ic] flag and performs no operation. ? for mmcau reads: ? any attempted read from the first 2-kbyte region of the address space (an attempted direct read) is illegal and produces an error termination. ? within the second 2-kbyte region (addr[11] = 1) of the address space, only a 64- byte space is treated as a legal cau store operation. the allowable addresses are defined as: addr[11:0] = 1000_10xx_xx_00 where the 4-bit xxxx value specifies the cau register number. the cau supports a subset of the allowable register numbers (0x0 - 0xa). attempting a store of a reserved (unsupported) register produces an undefined result. 32.6.2.2 data integrity checks direct writes can send 1, 2, or 3 commands to the cau in a single 32-bit transfer. as shown in figure 32-16 , the commands include a valid bit located at bits 31, 20, and 9 of the write data where: ? bit 31 is the valid bit for the first command ? bit 20 is the valid bit for the second command ? bit 9 is the valid bit for the third command the direct write data check validates the combination of these three valid bits. the following are the three legal states associated with these bits: chapter 32 memory-mapped cryptographic acceleration unit (mmcau) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 773 value of bits 31, 20, and 9 number of commands included 100 1 110 2 111 3 all other combinations of bits 31, 20, and 9 are illegal and generate an error termination. 32.6.3 cau commands the cau supports the commands shown in the following table. all other encodings are reserved. the casr[ic] bit is set if an undefined command is issued. a specific illegal command (ill) is defined to allow software self-checking. reserved commands should not be issued to ensure compatibility with future implementations. the cmd field specifies the 9-bit cau opcode for the operation command. see assembler equate values for a set of assembly constants used in the command descriptions here. if supported by the assembler, macros can also be created for each instruction. the value ca x should be interpreted as any cau register (casr, caa, ca n ). table 32-15. cau commands type command name description cmd operation 8 7 6 5 4 3 2 1 0 direct load cnop no operation 0x000 indirect load ldr load reg 0x01 cax op1 table continues on the next page... functional description 60 sub-family reference manual, rev. 6, nov 2011 774 freescale semiconductor, inc. table 32-15. cau commands (continued) type command name description cmd operation 8 7 6 5 4 3 2 1 0 indirect load aesic aes inv column op 0x0d cax invmixcolumns(cax^op1) the cnop command is the coprocessor no-op. it is issued by the mmcau and consumes a location in the mmcau fifo, but has no effect on any cau register. 32.6.3.2 load register (ldr) the ldr command loads cax with the source data specified by the write data. chapter 32 memory-mapped cryptographic acceleration unit (mmcau) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 775 32.6.3.3 store register (str) the str command returns the value of cax specified in the read address to the destination specified as read data. 32.6.3.4 add to register (adr) the adr command adds the source operand specified by the write data to cax and stores the result in cax. 32.6.3.5 reverse and add to register (radr) the radr command performs a byte reverse on the source operand specified by the write data, adds that value to cax, and stores the result in cax. this table shows an example. table 32-16. radr command example operand cax before cax after 0x0102_0304 0xa0b0_c0d0 0xa4b3_c2d1 32.6.3.6 add register to accumulator (adra) the adra command adds cax to caa and stores the result in caa. 32.6.3.7 exclusive or (xor) the xor command performs an exclusive-or of the source operand specified by the write data with cax and stores the result in cax. 32.6.3.8 rotate left (rotl) rotl rotates the cax bits to the left with the result stored back to cax. the number of bits to rotate is the value specified by the write data modulo 32. functional description k60 sub-family reference manual, rev. 6, nov 2011 776 freescale semiconductor, inc. 32.6.3.9 move register to accumulator (mvra) the mvra command moves the value from the source register cax to the destination register caa. 32.6.3.10 move accumulator to register (mvar) the mvar command moves the value from source register caa to the destination register cax. 32.6.3.11 aes substitution (aess) the aess command performs the aes byte substitution operation on cax and stores the result back to cax. 32.6.3.12 aes inverse substitution (aesis) the aesis command performs the aes inverse byte substitution operation on cax and stores the result back to cax. 32.6.3.13 aes column operation (aesc) the aesc command performs the aes column operation on the contents of cax then performs an exclusive-or of that result with the source operand specified by the write data and stores the result in cax. 32.6.3.14 aes inverse column operation (aesic) the aesic command performs an exclusive-or operation of the source operand specified by the write data on the contents of cax followed by the aes inverse mix column operation on that result and stores the result back in cax. 32.6.3.15 aes shift rows (aesr) the aesr command performs the aes shift rows operation on registers ca0, ca1, ca2, and ca3. this table shows an example. chapter 32 memory-mapped cryptographic acceleration unit (mmcau) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 777 table 32-17. aesr command example register before after ca0 0x0102_0304 0x0106_0b00 ca1 0x0506_0708 0x050a_0f04 ca2 0x090a_0b0c 0x090e_0308 ca3 0x0d0e_0f00 0x0d02_070c 32.6.3.16 aes inverse shift rows (aesir) the aesir command performs the aes inverse shift rows operation on registers ca0, ca1, ca2 and ca3. this table shows an example. table 32-18. aesir command example register before after ca0 0x0106_0b00 0x0102_0304 ca1 0x050a_0f04 0x0506_0708 ca2 0x090e_0308 0x090a_0b0c ca3 0x0d02_070c 0x0d0e_0f00 32.6.3.17 des round (desr) the desr command performs a round of the des algorithm and a key schedule update with the following source and destination designations: ca0=c, ca1=d, ca2=l, ca3=r. if the ip bit is set, des initial permutation performs on ca2 and ca3 before the round operation. if the fp bit is set, des final permutation (inverse initial permutation) performs on ca2 and ca3 after the round operation. the round operation uses the source values from registers ca0 and ca1 for the key addition operation. the ksx field specifies the shift for the key schedule operation to update the values in ca0 and ca1. the following table defines the specific shift function performed based on the ksx field. table 32-19. key shift function codes ksx code ksx define shift function 0 ksl1 left 1 1 ksl2 left 2 2 ksr1 right 1 3 ksr2 right 2 functional description k60 sub-family reference manual, rev. 6, nov 2011 778 freescale semiconductor, inc. 32.6.3.18 des key setup (desk) the desk command performs the initial key transformation (permuted choice 1) defined by the des algorithm on ca0 and ca1 with ca0 containing bits 1C32 of the key and ca1 containing bits 33C64 of the key 1 . if the dc bit is set, no shift operation performs and the values c 0 and d 0 store back to ca0 and ca1 respectively. the dc bit should be set for decrypt operations. if the dc bit is not set, a left shift by one also occurs and the values c 1 and d 1 store back to ca0 and ca1 respectively. the dc bit should be cleared for encrypt operations. if the cp bit is set and a key parity error is detected, casr[dpe] bit is set; otherwise, it is cleared. 32.6.3.19 hash function (hash) the hash command performs a hashing operation on a set of registers and adds that result to the value in caa and stores the result in caa. the specific hash function performed is based on the hfx field as defined in this table. this table uses the following terms: ? rotr n (cax): rotate cax register right n times ? shr n (cax): shift cax register right n times table 32-20. hash function codes hfx code hfx define hash function hash logic 0 hff md5 f() (ca1 & ca2) | ( ca1 & ca3) 1 hfg md5 g() (ca1 & ca3) | (ca2 & ca3) 2 hfh md5 h(), sha parity() ca1 ^ ca2 ^ ca3 3 hfi md5 i() ca2 ^ (ca1 | ca3) 4 hfc sha ch() (ca1 & ca2) ^ ( ca1 & ca3) 5 hfm sha maj() (ca1 & ca2) ^ (ca1 & ca3) ^ (ca2 & ca3) 6 hf2c sha-256 ch() (ca4 & ca5) ^ ( ca1 & ca6) 7 hf2m sha-256 maj() (ca0 & ca1) ^ (ca0 & ca2) ^ (ca1 & ca2) 8 hf2s sha-256 sigma 0 rotr 2 (ca0) ^ rotr 13 (ca0) ^ rotr 22 (ca0) 9 hf2t sha-256 sigma 1 rotr 6 (ca4) ^ rotr 11 (ca4) ^ rotr 25 (ca4) a hf2u sha-256 sigma 0 rotr 7 (ca8) ^ rotr 18 (ca8) ^ shr 3 (ca8) b hf2v sha-256 sigma 1 rotr 17 (ca8) ^ rotr 19 (ca8) ^ shr 10 (ca8) 1. the des algorithm numbers the most significant bit of a block as bit 1 and the least significant as bit 64. chapter 32 memory-mapped cryptographic acceleration unit (mmcau) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 779 32.6.3.20 secure hash shift (shs) the shs command does a set of parallel register-to-register move and shift operations for implementing sha-1. the following source and destination assignments are made: register value prior to command value after command executes ca4 ca4 ca3 ca3 ca3 ca2 ca2 ca2 ca1<<<30 ca1 ca1 ca0 ca0 ca0 caa caa caa caa<<<5 32.6.3.21 message digest shift (mds) the mds command does a set of parallel register-to-register move operations for implementing md5. the following source and destination assignments are made: register value prior to command value after command executes ca3 ca3 ca2 ca2 ca2 ca1 ca1 ca1 caa caa caa ca3 32.6.3.22 secure hash shift 2 (shs2) the shs2 command does an addition and a set of register to register moves in parallel for implementing sha-256. the following source and destination assignments are made: register value prior to command value after command executes ca7 ca7 ca6 ca6 ca6 ca5 ca5 ca5 ca4 ca4 ca4 ca3+ca8 ca3 ca3 ca2 ca2 ca2 ca1 ca1 ca1 ca0 ca0 ca0 caa functional description k60 sub-family reference manual, rev. 6, nov 2011 780 freescale semiconductor, inc. 32.6.3.23 illegal command (ill) the ill command is a specific illegal command that sets casr[ic]. all other illegal commands are reserved for use in future implementations. 32.7 application/initialization information this section discusses how to initialize and use the mmcau. 32.7.1 code example a code fragment is shown below as an example of how the mmcau is used. this example shows the round function of the aes algorithm. core registers are defined as follows: ? r1 points to the key schedule ? r3 contains three direct mmcau commands ? r8 contains two direct mmcau commands ? r9 contains an indirect mmcau command ? fp points to the mmcau indirect command address space ? ip points to the mmcau direct command space movw fp, #:lower16:mmcau_ppb_indirect @ fp -> mmcau_ppb_indirect movt fp, #:upper16:mmcau_ppb_indirect movw ip, #:lower16:mmcau_ppb_direct @ ip -> mmcau_ppb_direct movt ip, #:upper16:mmcau_ppb_direct # r3 = mmcau_3_cmds(aess+ca0,aess+ca1,aess+ca2) movw r3, #:lower16:(0x80100200+(aess+ca0)<<22+(aess+ca1)<<11+aess+ca2) movt r3, #:upper16:(0x80100200+(aess+ca0)<<22+(aess+ca1)<<11+aess+ca2) # r8 = mmcau_2_cmds(aess+ca3,aesr) movw r8, #:lower16:(0x80100000+(aess+ca3)<<22+(aesr)<<11) movt r8, #:upper16:(0x80100000+(aess+ca3)<<22+(aesr)<<11) add r9, fp, $((aesc+ca0)<<2) @ r9 = mmcau_cmd(aesc+ca0) str r3, [ip] @ sub bytes w0, w1, w2 str r8, [ip] @ sub bytes w3, shift rows ldmia r1!, {r4-r7} @ get next 4 keys; r1++ stmia r9, {r4-r7} @ mix columns, add keys 32.7.2 assembler equate values the following equates ease programming of the mmcau. ; cau registers (cax) chapter 32 memory-mapped cryptographic acceleration unit (mmcau) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 781 .set casr,0x0 .set caa,0x1 .set ca0,0x2 .set ca1,0x3 .set ca2,0x4 .set ca3,0x5 .set ca4,0x6 .set ca5,0x7 .set ca6,0x8 .set ca7,0x9 .set ca8,0xa ; cau commands .set cnop,0x000 .set ldr,0x010 .set str,0x020 .set adr,0x030 .set radr,0x040 .set adra,0x050 .set xor,0x060 .set rotl,0x070 .set mvra,0x080 .set mvar,0x090 .set aess,0x0a0 .set aesis,0x0b0 .set aesc,0x0c0 .set aesic,0x0d0 .set aesr,0x0e0 .set aesir,0x0f0 .set desr,0x100 .set desk,0x110 .set hash,0x120 .set shs,0x130 .set mds,0x140 .set shs2,0x150 .set ill,0x1f0 ; desr fields .set ip,0x08 ; initial permutation .set fp,0x04 ; final permutation .set ksl1,0x00 ; key schedule left 1 bit .set ksl2,0x01 ; key schedule left 2 bits .set ksr1,0x02 ; key schedule right 1 bit .set ksr2,0x03 ; key schedule right 2 bits ; desk field .set dc,0x01 ; decrypt key schedule .set cp,0x02 ; check parity ; hash functions codes .set hff,0x0 ; md5 f() ca1&ca2 | ~ca1&ca3 .set hfg,0x1 ; md5 g() ca1&ca3 | ca2&~ca3 .set hfh,0x2 ; md5 h(), sha parity() ca1^ca2^ca3 .set hfi,0x3 ; md5 i() ca2^(ca1|~ca3) .set hfc,0x4 ; sha ch() ca1&ca2 ^ ~ca1&ca3 .set hfm,0x5 ; sha maj() ca1&ca2 ^ ca1&ca3 ^ ca2&ca3 .set hf2c,0x6 ; sha-256 ch() ca4&ca5 ^ ~ca4&ca6 .set hf2m,0x7 ; sha-256 maj() ca0&ca1 ^ ca0&ca2 ^ ca1&ca2 .set hf2s,0x8 ; sha-256 sigma 0 rotr2(ca0)^rotr13(ca0)^rotr22(ca0) .set hf2t,0x9 ; sha-256 sigma 1 rotr6(ca4)^rotr11(ca4)^rotr25(ca4) .set hf2u,0xa ; sha-256 sigma 0 rotr7(ca8)^rotr18(ca8)^shr3(ca8) .set hf2v,0xb ; sha-256 sigma 1 rotr17(ca8)^rotr19(ca8)^shr10(ca8) application/initialization information k60 sub-family reference manual, rev. 6, nov 2011 782 freescale semiconductor, inc. chapter 33 random number generator (rngb) 33.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the purpose of the rngb is to generate cryptographically strong random data. it uses a true random number generator (trng) and a pseudo-random number generator (prng) to achieve true randomness and cryptographic strength. the rngb generates random numbers for secret keys, per message secrets, random challenges, and other similar quantities used in cryptographic algorithms. this chapter describes the random number generator (rngb), including a programming model, functional description, and application information. 33.1.1 block diagram the below figure shows the rngb's three main blocks: prng, trng, and xseed generator. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 783 xseed generator prng internal bus registers & internal bus interface random number generator trng fsm sim reseed figure 33-1. rng block diagram 33.1.2 features the rng includes these distinctive features: ? national institute of standards and technology (nist)-approved pseudo-random number generator ? http://csrc.nist.gov ? supports the key generation algorithm defined in the digital signature standard ? http://www.itl.nist.gov/fipspubs/fip186.htm ? integrated entropy sources capable of providing the prng with entropy for its seed. 33.2 modes of operation the rngb operates in the following modes. 33.2.1 self test mode in this mode the rngb performs a self test of the statistical counters and the prng algorithm to verify that the hardware is functioning properly. the self test takes ~29,000 cycles to complete. when self test completes an interrupt may be generated, if there are no outstanding commands in the command register. this mode is entered by setting the rng_cmd[st] bit. when self test mode completes, the rngb remains idle until seed mode is requested or the rngb transitions to seed mode if automatic seeding is enabled. modes of operation k60 sub-family reference manual, rev. 6, nov 2011 784 freescale semiconductor, inc. 33.2.2 seed generation mode during seed generation, the rngb adds entropy generated in the trng to the 256-bit xkey register. the prng algorithm executes 20,000 times sampling the entropy from the trng to create an initial seed for random number generation. at the same time, the trng runs simple statistical tests on its output. when seed generation is complete, the trng reports the pass/fail result of the tests through rng_esr. if the new seed passes the statistical tests, rng_sr[sdn] is set, signalling that the rng is ready to compute secure pseudo-random data. the rng then transitions to random number generation mode. 33.2.3 random number generation mode when seed generation mode completes and the output fifo is empty, the rng enters this mode automatically. random number generation mode quickly creates computationally random data that is derived by the initial seed produced in seed generation mode. during random number generation, a new 160-bit random number is generated whenever the five word output fifo is empty. when the output fifo contains data, the rngb automatically enters sleep mode, waiting for the data to be read. when the data is read, the rngb generates a new 160-bit word and goes back to sleep. after generating 2 20 words of random data, the rngb lets the user know that it requires reseeding through rng_sr and continues to generate random data until it is directed to reseed. however, if auto-seeding is selected, the rngb automatically completes seeding whenever it is needed. 33.3 memory map/register definition the following table shows the address map for the rngb module. detailed register descriptions are found in the following sections. chapter 33 random number generator (rngb) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 785 rng memory map absolute address (hex) register name width (in bits) access reset value section/ page 400a_0000 rngb version id register (rng_ver) 32 r 1000_0280h 33.3.1/ 786 400a_0004 rngb command register (rng_cmd) 32 r/w 0000_0000h 33.3.2/ 787 400a_0008 rngb control register (rng_cr) 32 r/w 0000_0000h 33.3.3/ 788 400a_000c rngb status register (rng_sr) 32 r 0000_500dh 33.3.4/ 790 400a_0010 rngb error status register (rng_esr) 32 r 0000_0000h 33.3.5/ 792 400a_0014 rngb output fifo (rng_out) 32 r 0000_0000h 33.3.6/ 793 33.3.1 rngb version id register (rng_ver) the read-only rng_ver register contains the current version of the rngb. it consists of the rng type and major and minor revision numbers. address: rng_ver is 400a_0000h base + 0h offset = 400a_0000h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r type 0 major minor w reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 rng_ver field descriptions field description 31?28 type random number generator type 0000 rnga 0001 rngb (this is the type used in this module) 0010 rngc else reserved 27?16 reserved this read-only field is reserved and always has the value zero. reserved, must be cleared. 15?8 major major version number. this field is always set to 0x02. 7?0 minor minor version number. subjiect to change. memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 786 freescale semiconductor, inc. 33.3.2 rngb command register (rng_cmd) rng_cmd controls the rng's operating modes and interrupt status. address: rng_cmd is 400a_0000h base + 4h offset = 400a_0004h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 gs st w sr ce ci reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rng_cmd field descriptions field description 31?7 reserved this read-only field is reserved and always has the value zero. reserved, must be cleared. 6 sr software reset. performs a software reset of the rngb. this bit is self-clearing. 0 do not perform a software reset. 1 software reset. 5 ce clear error. clears the errors in the rng_esr register and the rngb interrupt.this bit is self-clearing. 0 do not clear errors and interrupt. 1 clear errors and interrupt. 4 ci clear interrupt. clears the rngb interrupt if an error is not present. this bit is self-clearing. 0 do not clear interrupt. 1 clear interrupt. 3?2 reserved this read-only field is reserved and always has the value zero. reserved, must be cleared. 1 gs generate seed. initiates the seed generation process. seed generation starts when rng_sr[busy] is cleared if set simultaneously with st, after self-test when the seed generation process completes, this bit automatically clears and an interrupt may be generated if all requested operations are complete. 0 not in seed generation mode. 1 generate seed mode. 0 st self test. initiates a self test of the rngb's internal logic. the self-test starts table continues on the next page... chapter random number enerator rnb 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 787 rng_cmd field descriptions (continued) field description ? when rng_sr[busy] is cleared, or ? if set simultaneously with gs, self test takes precedence and is completed first. when self test completes, this bit automatically clears and an interrupt may be generated if all requested operations are complete. 0 not in self test mode. 1 self test mode. 33.3.3 rngb control register (rng_cr) through use of this register, the rngb can be programmed to provide slightly different functionality based on its desired use. address: rng_cr is 400a_0000h base + 8h offset = 400a_0008h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 maskerr maskdone ar 0 fufmod w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rng_cr field descriptions field description 31?10 reserved this read-only field is reserved and always has the value zero. reserved, must be cleared. 9?7 reserved this read-only field is reserved and always has the value zero. reserved, must be cleared. 6 maskerr mask error interrupt. masks interrupts generated by errors in the rngb. these errors can still be viewed in rng_esr. note: since masked errors do not interrupt the operation of the rngb and thus hide potentially fatal errors or conditions that could result in corrupted results, it is strongly recommended that errors only be masked while debugging. all errors are considered fatal, requiring the rngb to be reset. until the a reset occurs, the rngb does not service any random data. 0 no mask applied. 1 mask applied to the error interrupt. table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 788 freescale semiconductor, inc. rng_cr field descriptions (continued) field description 5 maskdone mask done interrupt. masks interrupts generated upon completion of seed and self test modes. the status of these jobs can be viewed by: ? reading rng_sr and viewing the seed done and self test done bits (rng_sr[sdn, stdn]) ? viewing rng_cmd for generate seed or self test bits (rng_cmd[gs,st]) being set, indicating that the operation is still taking place. 0 no mask applied. 1 mask applied. 4 ar auto-reseed. setting this bit allows the rngb to automatically generate a new seed whenever one is needed. this allows software to never use the rng_cmd[gs], although it is still possible. a new seed is needed whenever the rng_sr[rs] is set. 0 do not enable automatic reseeding. 1 enable automatic reseeding. 32 reserved this read-only field is reserved and always has the value zero. reserved, must be cleared. 10 fufmod fifo underflow response mode. controls the rngbs response to a fifo underflow condition. 00 return all zeros and set rng_esr[fufe] 01 return all zeros and set rng_esr[fufe] 10 generate bus transfer error 11 generate interrupt and return all zeros (overrides rng_cr[maskerr]) chapter 33 random number generator (rngb) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 789 33.3.4 rngb status register (rng_sr) the rngbsr is a read-only register which reflects the internal status of the rngb. address: rng_sr is 400a_0000h base + ch offset = 400a_000ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r statpf st_pf 0 err w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r fifo_size fifo_lvl 0 nsdn sdn stdn rs slp busy 1 w reset 0 1 0 1 0 0 0 0 0 0 0 0 1 1 0 1 rng_sr field descriptions field description 31?24 statpf statistics test pass fail. indicates pass or fail status of the various statistics tests on the last seed generated. bit 31 - long run test (>34) bit 30 - length 6+ run test bit 29 - length 5 run test bit 28 - length 4 run test bit 27 - length 3 run test bit 26 - length 2 run test bit 25 - length 1 run test bit 24 - monobit test 0 pass. 1 fail. 23?21 st_pf self test pass fail. indicates pass or fail status of the trng, prng, and reseed self tests, bit 23 - trng self test pass/fail bit 22 - prng self test pass/fail bit 21 - reseed self test pass/fail 0 pass. 1 fail. 20?17 reserved this read-only field is reserved and always has the value zero. table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 70 freescale semiconductor, inc. rng_sr field descriptions (continued) field description 16 err error. indicates an error was detected in the rngb. read the rng_esr register for details. 0 no error. 1 error detected. 1512 fifo_size fifo size. size of the fifo, and maximum possible fifo level. the bits should be interpreted as an integer. this value is set to five on the default version of rngb. 118 fifo_lvl fifo level. indicates the number of random words currently in the output fifo. the bits should be interpreted as an integer. 7 reserved this read-only field is reserved and always has the value zero. 6 nsdn new seed done. indicates that a new seed is ready for use during the next seed generation process. 5 sdn seed done. indicates the rng has generated the first seed. 0 seed generation process not complete. 1 completed seed generation since the last reset. 4 stdn self test done. indicates the self test is complete. this bit is cleared by hardware reset or a new self test is initiated by setting rng_cmd[st]. 0 self test not complete. 1 completed a self test since the last reset. 3 rs reseed needed. indicates the rngb needs to be reseeded. this is done by setting rng_cmd[gs], or automatically if rng_cr[ar] is set. 0 rngb does not need to be reseeded. 1 rngb needs to be reseeded. 2 slp sleep. indicates if the rngb is in sleep mode. when set, the rngb is in sleep mode and all internal clocks are disabled. while in this mode, access to the fifo is allowed. once the fifo is empty, the rngb fills the fifo and then enters sleep mode again. 0 rngb is not in sleep mode. 1 rngb is in sleep mode. 1 busy busy. table continues on the next page... chapter random number enerator rnb 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 71 rng_sr field descriptions (continued) field description reflects the current state of rngb. if rngb is currently seeding, generating the next seed, creating a new random number, or performing a self test, this bit is set. 0 not busy. 1 busy. 0 reserved this read-only field is reserved and always has the value one. reserved, must be set. 33.3.5 rngb error status register (rng_esr) address: rng_esr is 400a_0000h base + 10h offset = 400a_0010h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 fufe sate ste osce lfe w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rng_esr field descriptions field description 315 reserved this read-only field is reserved and always has the value zero. reserved, must be cleared. 4 fufe fifo underflow error indicates the rngb has experienced a fifo underflow condition resulting in the last random data read being unreliable. this bit can be masked by rng_cr[fufmod] and is cleared by hardware or software reset or by writing one to rng_cmd[ce]. 0 fifo underflow has not occurred. 1 fifo underflow has occurred 3 sate statistical test error. indicates if rngb has failed the statistical tests for the last generated seed. this bit is sticky and is cleared by a hardware or software reset or by writing one to rng_cmd[ce]. 0 rngb has not failed the statistical tests. 1 rngb has failed the statistical tests during initialization. 2 ste self test error. indicates the rngb has failed the most recent self test. this bit is sticky and can only be reset by a hardware reset or by writing one to rng_cmd[ce]. table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 72 freescale semiconductor, inc. rng_esr field descriptions (continued) field description 0 rngb has not failed self test. 1 rngb has failed self test. 1 osce oscillator error. indicates the oscillator in the rng may be broken. this bit is sticky and can only be cleared by a software or hardware reset. 0 rng oscillator is working properly. 1 problem detected with the rng oscillator. 0 lfe linear feedback shift register (lfsr) error. when this bit is set, the interrupt generated was caused by a failure of one of the lfsrs in one of the rngbs three entropy sources. this bit is sticky and can only be cleared by a software or hardware reset. 0 lfsrs are working properly. 1 lfsr failure has occurred. 33.3.6 rngb output fifo (rng_out) the rngbout provides temporary storage for random data generated by the rngb. this allows the user to read multiple random longwords back-to-back. a read of this address when the fifo is not empty, returns 32 bits of random data. if the fifo is read when empty, a fifo underrun response is returned according to rng_cr[fufmod]. for optimal system performance, poll rng_sr[fifo_lvl] to ensure random values are present before reading the fifo. address: rng_out is 400a_0000h base + 14h offset = 400a_0014h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r randout w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rng_out field descriptions field description 31?0 randout random output chapter 33 random number generator (rngb) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 793 33.4 functional description the rngb performs two functional operations, as described in modes of operation : seed generation and random number generation. theses operations are performed with cooperation from the major functional blocks in the rngb described below. 33.4.1 pseudorandom number generator (prng) the prng implements the nist-approved prng described in the digital signature standard . the 160-bit output of the sha-1 block is the next five words of random data. the prng is designed to generate 2 20 words of random data before requiring reseeding, using the trng only during the seeding/initialization process. the initial seed takes approximately two million clock cycles. after this the rngb can generate five 32-bit words every 112 clock cycles. reseeding takes place transparently through use of the simultaneous reseed lfsrs. the entropy stored in this 128-bit lfsr and 128-bit shift register is added directly into the xkey structure via the rngb xseed generator whenever reseeding is required. 33.4.2 true random number generator (trng) the trng is comprised of two entropy sources each providing a single bit of output. concatenated together, these two output bits are expected to provide one bit of entropy every 100 clock cycles. in addition to generating entropy, the trng also performs several statistical tests on its output. the pass/fail status of these tests are reflected in rng_esr. 33.4.3 resets there are two ways to reset the rngb: power-on/hardware reset and software reset. the software reset is functionally equivalent to the power-on/hardware reset. the power-on/ hardware reset is asynchronous. software reset is performed by setting the rng_cmd[sr] bit. these are summarized in the table below. functional description k60 sub-family reference manual, rev. 6, nov 2011 794 freescale semiconductor, inc. table 33-8. reset summary reset source characteristics internally resets: affect on external signal: hardware ipg_hard_async_reset_b active-low, asynchronous, minimum 1-cycle all interface registers and puts rngb into the idle state software rng_cmd[sr] active-high all interface registers and puts rngb into the idle state 33.4.3.1 power-on/hardware reset asserting the ipg_hard_async_reset_b signal sets all interface registers to their default state and puts the state machine into the idle mode. 33.4.3.2 software reset the software reset is functionally equivalent to the hardware reset, but allows the rngb to be fully reset by writing to the sw_rst bit (bit-6) in the rngb command register. this bit is self-resetting. a software reset may be performed at any time. 33.4.4 rng interrupts there is a single rng interrupt generated to the processor's interrupt controller. the source of the interrupt is determined by reading the rng status register. if an error is the cause of the interrupt, further information is available by reading the rng error status register. the interrupts can be masked by the rng_cr[maskdone or maskerr] bits it is strongly recommended that the error interrupt is only masked while debugging, since masking the error interrupt could hide potentially fatal errors or conditions that could result in corrupted results. all errors are considered fatal, requiring the rng to be reset. the rng does not service any random data until a reset occurs. the available interrupt sources are described in the following table. chapter 33 random number generator (rngb) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 795 table 33-9. rng interrupt sources sources status bit field rng_cr mask bit field description seed generation done rng_sr[sdn] maskdone first seed was generated self test done rng_sr[stdn] maskdone self test finished error rng_sr[err] maskerr error detected. see rng_esr for details. linear feedback shift register (lfsr) rng_esr[lsfre] maskerr fault in one of the trngs lfsrs oscillator rng_esr[osce] maskerr trng ring oscillator may be malfunctioning self test rng_esr[ste] maskerr self test failed statistical test rng_esr[sate] maskerr statistics test for last seed generation failed fifo underflow rng_esr[fufe] maskerr fifo read while empty 33.5 initialization/application information this section describes the module initialization. 33.5.1 manual seeding the intended general operation of the rngb is as follows: 1. reset/initialize. 2. write to the rng_cr to setup the rngb for the desired functionality. 3. write to rng_cmd to run self-test or seed generation. 4. wait for interrupt to indicate completion of the requested operation(s). 5. repeat steps 3C4 if seed generation is not complete. 6. poll rng_sr for fifo level. 7. read available random data from output fifo. 8. repeat steps 6 and 7 as needed, until 2 20 words have been generated. 9. write to rng_cmd to run seed mode. 10. repeat steps 4C9. initialization/application information k60 sub-family reference manual, rev. 6, nov 2011 796 freescale semiconductor, inc. 33.5.2 automatic seeding the intended general operation of the rngb with automatic seeding enabled is as follows: 1. reset/initialize. 2. write to the rng_cr to setup the rngb for automatic seeding and the desired functionality. 3. wait for interrupt to indicate completion of first seed 4. poll rng_sr for fifo level. 5. read available random data from output fifo. 6. repeat steps 4 and 5 as needed. automatic seeding occurs when necessary and is transparent to operation. chapter 33 random number generator (rngb) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 797 initialization/application information k60 sub-family reference manual, rev. 6, nov 2011 798 freescale semiconductor, inc. chapter 34 analog-to-digital converter (adc) 34.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the 16-bit analog-to-digital converter (adc) is a successive approximation adc designed for operation within an integrated microcontroller system-on-chip. note for the chip specific modes of operation, refer to the power management information for the device. 34.1.1 features features of the adc module include: ? linear successive approximation algorithm with up to 16-bit resolution ? up to 4 pairs of differential and 24 single-ended external analog inputs ? output modes: differential 16-bit, 13-bit, 11-bit and 9-bit modes, or single-ended 16- bit, 12-bit, 10-bit and 8-bit modes ? output formatted in 2's complement 16-bit sign extended for differential modes ? output in right-justified unsigned format for single-ended ? single or continuous conversion (automatic return to idle after single conversion) ? configurable sample time and conversion speed/power ? conversion complete / hardware average complete flag and interrupt k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 799 ? input clock selectable from up to four sources ? operation in low power modes for lower noise operation ? asynchronous clock source for lower noise operation with option to output the clock ? selectable hardware conversion trigger with hardware channel select ? automatic compare with interrupt for less-than, greater-than or equal-to, within range, or out-of-range, programmable value ? temperature sensor ? hardware average function ? selectable voltage reference: external or alternate ? self-calibration mode ? programmable gain amplifier (pga) with up to x64 gain 34.1.2 block diagram the following figure is the adc module block diagram. introduction k60 sub-family reference manual, rev. 6, nov 2011 800 freescale semiconductor, inc. sc1a adhwtsa adhwtsn c o m p a r e t r u e a d c h c o m p l e t e a d t r g a d c o a d i v a d i c l k clock gen a d a c k e n 2 divide a d c k m o d e t r a n s f e r logic c v 2 a d v i n p a d v i n m a c f e c l m x trigger control mcu stop adhwt ad4 ad23 tempp v refh v alth v refl v altl aien c o c o t r i g g e r diff m o d e adlsmp/adlsts adlpc/adhsc i n i t i a l i z e sample c o n v e r t t r a n s f er a b o r t clpx pg, mg pg, mg clpx c a l i b r ation ofs calf cal sc3 c v1 d f o r matting a v e r ager a v g e , a v gs adcofs the adc module supports up to 4 pairs of differential inputs and up to 24 single-ended inputs. each differential pair requires two inputs, dadpx and dadmx. the adc also requires four supply/reference/ground connections. table 34-1. adc signal descriptions signal description i/o dadp[3:0] differential analog channel inputs i table continues on the next page... chapter 4 analog-to-digital converter adc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 801 table 34-1. adc signal descriptions (continued) signal description i/o dadm[3:0] differential analog channel inputs i ad[23:4] single-ended analog channel inputs i v refsh voltage reference select high i v refsl voltage reference select low i v dda analog power supply i v ssa analog ground i 34.2.1 analog power (v dda ) the adc analog portion uses v dda as its power connection. in some packages, v dda is connected internally to v dd . if externally available, connect the v dda pin to the same voltage potential as v dd . external filtering may be necessary to ensure clean v dda for good results. 34.2.2 analog ground (v ssa ) the adc analog portion uses v ssa as its ground connection. in some packages, v ssa is connected internally to v ss . if externally available, connect the v ssa pin to the same voltage potential as v ss . 34.2.3 voltage reference select v refsh and v refsl are the high and low reference voltages for the converter. the adc can be configured to accept one of two voltage reference pairs for v refsh and v refsl . each pair contains a positive reference that must be between the minimum ref voltage high and v dda , and a ground reference that must be at the same potential as v ssa . the two pairs are external (v refh and v refl ) and alternate (v alth and v altl ). these voltage references are selected using the refsel bits in the sc2 register. the alternate (v alth and v altl ) voltage reference pair may select additional external pins or internal sources depending on mcu configuration. refer to the chip configuration information on the voltage references specific to this mcu. adc signal descriptions k60 sub-family reference manual, rev. 6, nov 2011 802 freescale semiconductor, inc. in some packages, v refh is connected in the package to v dda and v refl to v ssa . if externally available, the positive reference(s) may be connected to the same potential as v dda or may be driven by an external source to a level between the minimum ref voltage high and the v dda potential (v refh must never exceed v dda ). connect the ground references to the same voltage potential as v ssa . 34.2.4 analog channel inputs (adx) the adc module supports up to 24 single-ended analog inputs. a single-ended input is selected for conversion through the adch channel select bits when the diff bit in the sc1n register is low. 34.2.5 differential analog channel inputs (dadx) the adc module supports up to 4 differential analog channel inputs. each differential analog input is a pair of external pins (dadpx and dadmx) referenced to each other to provide the most accurate analog to digital readings. a differential input is selected for conversion through the adch channel select bits when the diff bit in the sc1n register bit is high. all dadpx inputs may be used as single-ended inputs if the diff bit is low. in certain mcu configurations, some dadmx inputs may also be used as single-ended inputs if the diff bit is low. refer to the chip configuration chapter for adc connections specific to this mcu. 34.3 register definition this section describes the adc registers. adc memory map absolute address (hex) register name width (in bits) access reset value section/ page 4003_b000 adc status and control registers 1 (adc0_sc1a) 32 r/w 0000_001fh 34.3.1/ 806 4003_b004 adc status and control registers 1 (adc0_sc1b) 32 r/w 0000_001fh 34.3.1/ 806 4003_b008 adc configuration register 1 (adc0_cfg1) 32 r/w 0000_0000h 34.3.2/ 809 table continues on the next page... chapter 4 analog-to-digital converter adc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 80 adc memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4003_b00c configuration register 2 (adc0_cfg2) 32 r/w 0000_0000h 34.3.3/ 811 4003_b010 adc data result register (adc0_ra) 32 r 0000_0000h 34.3.4/ 812 4003_b014 adc data result register (adc0_rb) 32 r 0000_0000h 34.3.4/ 812 4003_b018 compare value registers (adc0_cv1) 32 r/w 0000_0000h 34.3.5/ 813 4003_b01c compare value registers (adc0_cv2) 32 r/w 0000_0000h 34.3.5/ 813 4003_b020 status and control register 2 (adc0_sc2) 32 r/w 0000_0000h 34.3.6/ 814 4003_b024 status and control register 3 (adc0_sc3) 32 r/w 0000_0000h 34.3.7/ 816 4003_b028 adc offset correction register (adc0_ofs) 32 r/w 0000_0004h 34.3.8/ 817 4003_b02c adc plus-side gain register (adc0_pg) 32 r/w 0000_8200h 34.3.9/ 818 4003_b030 adc minus-side gain register (adc0_mg) 32 r/w 0000_8200h 34.3.10/ 818 4003_b034 adc plus-side general calibration value register (adc0_clpd) 32 r/w 0000_000ah 34.3.11/ 819 4003_b038 adc plus-side general calibration value register (adc0_clps) 32 r/w 0000_0020h 34.3.12/ 820 4003_b03c adc plus-side general calibration value register (adc0_clp4) 32 r/w 0000_0200h 34.3.13/ 820 4003_b040 adc plus-side general calibration value register (adc0_clp3) 32 r/w 0000_0100h 34.3.14/ 821 4003_b044 adc plus-side general calibration value register (adc0_clp2) 32 r/w 0000_0080h 34.3.15/ 821 4003_b048 adc plus-side general calibration value register (adc0_clp1) 32 r/w 0000_0040h 34.3.16/ 822 4003_b04c adc plus-side general calibration value register (adc0_clp0) 32 r/w 0000_0020h 34.3.17/ 822 4003_b050 adc pga register (adc0_pga) 32 r/w 0000_0000h 34.3.18/ 823 4003_b054 adc minus-side general calibration value register (adc0_clmd) 32 r/w 0000_000ah 34.3.19/ 824 4003_b058 adc minus-side general calibration value register (adc0_clms) 32 r/w 0000_0020h 34.3.20/ 825 table continues on the next page... register definition 60 sub-family reference manual, rev. 6, nov 2011 804 freescale semiconductor, inc. adc memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4003_b05c adc minus-side general calibration value register (adc0_clm4) 32 r/w 0000_0200h 34.3.21/ 825 4003_b060 adc minus-side general calibration value register (adc0_clm3) 32 r/w 0000_0100h 34.3.22/ 826 4003_b064 adc minus-side general calibration value register (adc0_clm2) 32 r/w 0000_0080h 34.3.23/ 826 4003_b068 adc minus-side general calibration value register (adc0_clm1) 32 r/w 0000_0040h 34.3.24/ 827 4003_b06c adc minus-side general calibration value register (adc0_clm0) 32 r/w 0000_0020h 34.3.25/ 827 400b_b000 adc status and control registers 1 (adc1_sc1a) 32 r/w 0000_001fh 34.3.1/ 806 400b_b004 adc status and control registers 1 (adc1_sc1b) 32 r/w 0000_001fh 34.3.1/ 806 400b_b008 adc configuration register 1 (adc1_cfg1) 32 r/w 0000_0000h 34.3.2/ 809 400b_b00c configuration register 2 (adc1_cfg2) 32 r/w 0000_0000h 34.3.3/ 811 400b_b010 adc data result register (adc1_ra) 32 r 0000_0000h 34.3.4/ 812 400b_b014 adc data result register (adc1_rb) 32 r 0000_0000h 34.3.4/ 812 400b_b018 compare value registers (adc1_cv1) 32 r/w 0000_0000h 34.3.5/ 813 400b_b01c compare value registers (adc1_cv2) 32 r/w 0000_0000h 34.3.5/ 813 400b_b020 status and control register 2 (adc1_sc2) 32 r/w 0000_0000h 34.3.6/ 814 400b_b024 status and control register 3 (adc1_sc3) 32 r/w 0000_0000h 34.3.7/ 816 400b_b028 adc offset correction register (adc1_ofs) 32 r/w 0000_0004h 34.3.8/ 817 400b_b02c adc plus-side gain register (adc1_pg) 32 r/w 0000_8200h 34.3.9/ 818 400b_b030 adc minus-side gain register (adc1_mg) 32 r/w 0000_8200h 34.3.10/ 818 400b_b034 adc plus-side general calibration value register (adc1_clpd) 32 r/w 0000_000ah 34.3.11/ 819 400b_b038 adc plus-side general calibration value register (adc1_clps) 32 r/w 0000_0020h 34.3.12/ 820 table continues on the next page... chapter 4 analog-to-digital converter adc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 80 adc memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 400b_b03c adc plus-side general calibration value register (adc1_clp4) 32 r/w 0000_0200h 34.3.13/ 820 400b_b040 adc plus-side general calibration value register (adc1_clp3) 32 r/w 0000_0100h 34.3.14/ 821 400b_b044 adc plus-side general calibration value register (adc1_clp2) 32 r/w 0000_0080h 34.3.15/ 821 400b_b048 adc plus-side general calibration value register (adc1_clp1) 32 r/w 0000_0040h 34.3.16/ 822 400b_b04c adc plus-side general calibration value register (adc1_clp0) 32 r/w 0000_0020h 34.3.17/ 822 400b_b050 adc pga register (adc1_pga) 32 r/w 0000_0000h 34.3.18/ 823 400b_b054 adc minus-side general calibration value register (adc1_clmd) 32 r/w 0000_000ah 34.3.19/ 824 400b_b058 adc minus-side general calibration value register (adc1_clms) 32 r/w 0000_0020h 34.3.20/ 825 400b_b05c adc minus-side general calibration value register (adc1_clm4) 32 r/w 0000_0200h 34.3.21/ 825 400b_b060 adc minus-side general calibration value register (adc1_clm3) 32 r/w 0000_0100h 34.3.22/ 826 400b_b064 adc minus-side general calibration value register (adc1_clm2) 32 r/w 0000_0080h 34.3.23/ 826 400b_b068 adc minus-side general calibration value register (adc1_clm1) 32 r/w 0000_0040h 34.3.24/ 827 400b_b06c adc minus-side general calibration value register (adc1_clm0) 32 r/w 0000_0020h 34.3.25/ 827 34.3.1 adc status and control registers 1 (adc x n the sc1a register is used for both software and hardware trigger modes of operation. to allow sequential conversions of the adc to be triggered by internal peripherals, the adc can have more then one status and control register: one for each conversion. the sc1b-sc1n registers indicate potentially multiple sc1 registers for use only in hardware trigger mode. refer to the chip configuration information about the number of sc1n registers specific to this device. the sc1n registers have identical fields, and are used in a "ping-pong" approach to control adc operation. at any one point in time, only one of the sc1n registers is actively controlling adc conversions. updating sc1a while sc1n is actively controlling a conversion is allowed (and vice-versa for any of the sc1n registers specific to this mcu). register definition k60 sub-family reference manual, rev. 6, nov 2011 806 freescale semiconductor, inc. writing sc1a while sc1a is actively controlling a conversion aborts the current conversion. in software trigger mode (adtrg=0), writes to the sc1a register subsequently initiate a new conversion (if the adch bits are equal to a value other than all 1s). similarly, writing any of the sc1n registers while that specific sc1n register is actively controlling a conversion aborts the current conversion. none of the sc1b-sc1n registers are used for software trigger operation and therefore writes to the sc1b - sc1n registers do not initiate a new conversion. addresses: adc0_sc1a is 4003_b000h base + 0h offset = 4003_b000h adc0_sc1b is 4003_b000h base + 4h offset = 4003_b004h adc1_sc1a is 400b_b000h base + 0h offset = 400b_b000h adc1_sc1b is 400b_b000h base + 4h offset = 400b_b004h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 coco aien diff adch w reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 adc x n iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero oo onersion colete la he oo la is a reaonly it that is set each tie a conersion is colete when the coare unction is isale f an the harware aerae unction is isale hen the coare unction is enale f the oo la is set uon coletion o a conersion only i the coare result is true hen the harware aerae unction is enale the oo la is set uon coletion o the selecte nuer o conersions eterine y the its he oo la in is also set at the coletion o a aliration sequence he oo it is cleare when the resectie n reister is written or when the resectie rn reister is rea onersion not colete onersion colete table continues on the next page... chapter 4 analog-to-digital converter adc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 807 adc x n iel escritions continue fiel escrition nterrut enale enales conersion colete interruts hen oo ecoes set while the resectie is hih an interrut is asserte onersion colete interrut isale onersion colete interrut enale ff ierential oe enale ff coniures the to oerate in ierential oe hen enale this oe autoatically selects ro the ierential channels an chanes the conersion alorith an the nuer o cycles to colete a conersion inleene conersions an inut channels are selecte ierential conersions an inut channels are selecte h nut channel select he h its or a it iel that selects one o the inut channels he inut channel ecoe eens on the alue o the ff it are associate with the inut in airs x an x he successie aroxiation conerter susyste is turne o when the channel select its are all set h his eature allows or exlicit isalin o the an isolation o the inut channel ro all sources erinatin continuous conersions this way reents an aitional sinle conersion ro ein erore t is not necessary to set the channel select its to all ones to lace the in a lowower state when continuous conersions are not enale ecause the oule autoatically enters a lowower state when a conersion coletes hen ff is selecte as inut when ff is selecte as inut hen ff is selecte as inut when ff is selecte as inut hen ff is selecte as inut when ff is selecte as inut hen ff is selecte as inut when ff is selecte as inut hen ff is selecte as inut when ff it is resere hen ff is selecte as inut when ff it is resere hen ff is selecte as inut when ff it is resere hen ff is selecte as inut when ff it is resere hen ff is selecte as inut when ff it is resere hen ff is selecte as inut when ff it is resere hen ff is selecte as inut when ff it is resere hen ff is selecte as inut when ff it is resere hen ff is selecte as inut when ff it is resere hen ff is selecte as inut when ff it is resere hen ff is selecte as inut when ff it is resere hen ff is selecte as inut when ff it is resere hen ff is selecte as inut when ff it is resere hen ff is selecte as inut when ff it is resere hen ff is selecte as inut when ff it is resere hen ff is selecte as inut when ff it is resere hen ff is selecte as inut when ff it is resere hen ff is selecte as inut when ff it is resere hen ff is selecte as inut when ff it is resere table continues on the next page... register definition 60 sub-family reference manual, rev. 6, nov 2011 808 freescale semiconductor, inc. adc x n iel escritions continue fiel escrition hen ff is selecte as inut when ff it is resere resere resere hen ff e sensor sinleene is selecte as inut when ff e sensor ierential is selecte as inut hen ff ana sinleene is selecte as inut when ff ana ierential is selecte as inut resere hen ff rfh is selecte as inut when ff rfh ierential is selecte as inut oltae reerence selecte is eterine y the rfl its in the reister hen ff rfl is selecte as inut when ff it is resere oltae reerence selecte is eterine y the rfl its in the reister oule isale coniuration reister x f cfg1 register selects the mode of operation, clock source, clock divide, and configure for low power or long sample time. addresses: adc0_cfg1 is 4003_b000h base + 8h offset = 4003_b008h adc1_cfg1 is 400b_b000h base + 8h offset = 400b_b008h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 adlpc adiv adlsmp mode adiclk w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 adc x f iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero l lowower coniuration l controls the ower coniuration o the successie aroxiation conerter his otiies ower consution when hiher sale rates are not require table continues on the next page... chapter 4 analog-to-digital converter adc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 80 adc x f iel escritions continue fiel escrition oral ower coniuration low ower coniuration he ower is reuce at the exense o axiu cloc see loc iie select selects the iie ratio use y the to enerate the internal cloc he iie ratio is an the cloc rate is inut cloc he iie ratio is an the cloc rate is inut cloc he iie ratio is an the cloc rate is inut cloc he iie ratio is an the cloc rate is inut cloc l ale tie coniuration l selects etween ierent sale ties ase on the conersion oe selecte his it austs the sale erio to allow hiher ieance inuts to e accurately sale or to axiie conersion see or lower ieance inuts loner sale ties can also e use to lower oerall ower consution i continuous conersions are enale an hih conersion rates are not require hen l the lon sale tie select its l: can select the extent o the lon sale tie hort sale tie lon sale tie o onersion oe selection o its are use to select the resolution oe hen ff: t is sinleene it conersion when ff it is ierential it conersion with s coleent outut hen ff: t is sinleene it conersion when ff it is ierential it conersion with s coleent outut hen ff: t is sinleene it conersion when ff it is ierential it conersion with s coleent outut hen ff: t is sinleene it conersion when ff it is ierential it conersion with s coleent outut l nut cloc select l its select the inut cloc source to enerate the internal cloc ote that when the cloc source is selecte it is not require to e actie rior to conersion start hen it is selecte an it is not actie rior to a conersion start the asynchronous cloc is actiate at the start o a conersion an shuts o when conersions are terinate n this case there is an associate cloc startu elay each tie the cloc source is reactiate us cloc us cloc iie y lternate cloc ll synchronous cloc reister einition ufaily reerence anual re o freescale eiconuctor nc 34.3.3 configuration register 2 (adc x f cfg2 register selects the special high speed configuration for very high speed conversions and selects the long sample time duration during long sample mode. addresses: adc0_cfg2 is 4003_b000h base + ch offset = 4003_b00ch adc1_cfg2 is 400b_b000h base + ch offset = 400b_b00ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 muxsel adacken adhsc adlsts w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 adc x f iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero resere his reaonly iel is resere an always has the alue ero ul ux select ux select it is use to chane the ux settin to select etween alternate sets o channels xxa channels are selecte xx channels are selecte synchronous cloc outut enale enales the s asynchronous cloc source an the cloc source outut rearless o the conersion an inut cloc select l its status o the ase on u coniuration the asynchronous cloc ay e use y other oules see hi oniuration inoration ettin this it allows the cloc to e use een while the is ile or oeratin ro a ierent cloc source lso latency o initiatin a sinle or irstcontinuous conersion with the asynchronous cloc selecte is reuce since the cloc is alreay oerational synchronous cloc outut isale synchronous cloc only enale i selecte y l an a conersion is actie synchronous cloc an cloc outut enale rearless o the state o the h hih see coniuration table continues on the next page... chapter 4 analog-to-digital converter adc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 811 adc x f iel escritions continue fiel escrition h coniures the or ery hih see oeration he conersion sequence is altere cycles ae to the conersion tie to allow hiher see conersion clocs oral conersion sequence selecte hih see conersion sequence selecte aitional cycles to total conersion tie l lon sale tie select l selects etween the extene sale ties when lon sale tie is selecte l his allows hiher ieance inuts to e accurately sale or to axiie conersion see or lower ieance inuts loner sale ties can also e use to lower oerall ower consution when continuous conersions are enale i hih conersion rates are not require eault lonest sale tie extra cycles cycles total extra cycles cycles total sale tie extra cycles cycles total sale tie extra cycles cycles total sale tie ata result reister x r n the data result registers (rn) contain the result of an adc conversion of the channel selected by the corresponding status and channel control register (sc1a:sc1n). for every status and channel control register, there is a corresponding data result register. unused bits in the rn register are cleared in unsigned right justified modes and carry the sign bit (msb) in sign extended 2's complement modes. for example, when configured for 10-bit single-ended mode, d[15:10] are cleared. when configured for 11-bit differential mode, d[15:10] carry the sign bit (bit 10 extended through bit 15). the following table describes the behavior of the data result registers in the different modes of operation. table 34-44. data result register description conversion mode d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 format 16-bit differential s d d d d d d d d d d d d d d d signed 2's complement 16-bit single- ended d d d d d d d d d d d d d d d d unsigned right justified 13-bit differential s s s s d d d d d d d d d d d d sign extended 2's complement 12-bit single- ended 0 0 0 0 d d d d d d d d d d d d unsigned right justified table continues on the next page... register definition 60 sub-family reference manual, rev. 6, nov 2011 812 freescale semiconductor, inc. table 34-44. data result register description (continued) conversion mode d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 format 11-bit differential s s s s s s d d d d d d d d d d sign extended 2s complement 10-bit single- ended 0 0 0 0 0 0 d d d d d d d d d d unsigned right justified 9-bit differential s s s s s s s s d d d d d d d d sign extended 2s complement 8-bit single- ended 0 0 0 0 0 0 0 0 d d d d d d d d unsigned right justified note s: sign bit or sign bit extension; d: data (2's complement data if indicated) addresses: adc0_ra is 4003_b000h base + 10h offset = 4003_b010h adc0_rb is 4003_b000h base + 14h offset = 4003_b014h adc1_ra is 400b_b000h base + 10h offset = 400b_b010h adc1_rb is 400b_b000h base + 14h offset = 400b_b014h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 d w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 adc x r n iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero ata result oare alue reisters x n the compare value registers (cv1 and cv2) contain a compare value used to compare with the conversion result when the compare function is enabled (acfe=1). this register is formatted the same for both bit position definition and value format (unsigned or sign- extended 2's complement) as the data result registers (rn) in the different modes of operation. therefore, the compare function only uses the compare value register bits that are related to the adc mode of operation. chapter 34 analog-to-digital converter (adc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 813 the compare value 2 register (cv2) is utilized only when the compare range function is enabled (acren=1). addresses: adc0_cv1 is 4003_b000h base + 18h offset = 4003_b018h adc0_cv2 is 4003_b000h base + 1ch offset = 4003_b01ch adc1_cv1 is 400b_b000h base + 18h offset = 400b_b018h adc1_cv2 is 400b_b000h base + 1ch offset = 400b_b01ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 cv w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 adc x n iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero oare alue tatus an control reister x the sc2 register contains the conversion active, hardware/software trigger select, compare function and voltage reference select of the adc module. addresses: adc0_sc2 is 4003_b000h base + 20h offset = 4003_b020h adc1_sc2 is 400b_b000h base + 20h offset = 400b_b020h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 adact adtrg acfe acfgt acren dmaen refsel w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register definition k60 sub-family reference manual, rev. 6, nov 2011 814 freescale semiconductor, inc. adc x iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero onersion actie inicates that a conersion or harware aerain is in roress is set when a conersion is initiate an cleare when a conersion is colete or aorte onersion not in roress onersion in roress r onersion trier select r selects the tye o trier use or initiatin a conersion wo tyes o trier are selectale: sotware trier an harware trier hen sotware trier is selecte a conersion is initiate ollowin a write to hen harware trier is selecte a conersion is initiate ollowin the assertion o the h inut ater a ulse o the hn inut otware trier selecte harware trier selecte f oare unction enale f enales the coare unction oare unction isale oare unction enale f oare unction reater than enale f coniures the coare unction to chec the conersion result relatie to the coare alue reisters an ase uon the alue o r he f it ust e set or f to hae any eect oniures less than threshol outsie rane not inclusie an insie rane not inclusie unctionality ase on the alues lace in the an reisters oniures reater than or equal to threshol outsie rane inclusie an insie rane inclusie unctionality ase on the alues lace in the an reisters r oare unction rane enale r coniures the coare unction to chec i the conersion result o the inut ein onitore is either etween or outsie the rane ore y the coare alue reisters an eterine y the alue o f he f it ust e set or f to hae any eect rane unction isale only the coare alue reister is coare rane unction enale oth coare alue reisters an are coare enale is isale is enale an will assert the request urin a conersion colete eent note y the assertion o any o the oo las rfl oltae reerence selection rfl its select the oltae reerence source use or conersions table continues on the next page... chapter 4 analog-to-digital converter adc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 81 adc x iel escritions continue fiel escrition eault oltae reerence in air external ins rfh an rfl lternate reerence air lh an ll his air ay e aitional external ins or internal sources eenin on u coniuration onsult the hi oniuration inoration or etails seciic to this u resere resere tatus an control reister x the sc3 register controls the calibration, continuous convert, and hardware averaging functions of the adc module. addresses: adc0_sc3 is 4003_b000h base + 24h offset = 4003_b024h adc1_sc3 is 400b_b000h base + 24h offset = 400b_b024h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 cal calf 0 adco avge avgs w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 adc x iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero l aliration l eins the caliration sequence when set his it stays set while the caliration is in roress an is cleare when the caliration sequence is colete he lf it ust e chece to eterine the result o the caliration sequence once starte the caliration routine cannot e interrute y writes to the reisters or the results will e inali an the lf it will set ettin the l it will aort any current conersion lf aliration aile la lf islays the result o the caliration sequence he caliration sequence will ail i r any reister is written or any sto oe is entere eore the caliration sequence coletes he lf it is cleare y writin a to this it table continues on the next page... register definition 60 sub-family reference manual, rev. 6, nov 2011 816 freescale semiconductor, inc. adc x iel escritions continue fiel escrition aliration colete norally aliration aile accuracy seciications are not uarantee resere his reaonly iel is resere an always has the alue ero o ontinuous conersion enale o enales continuous conersions one conersion or one set o conersions i the harware aerae unction is enale ater initiatin a conersion ontinuous conersions or sets o conersions i the harware aerae unction is enale ater initiatin a conersion harware aerae enale enales the harware aerae unction o the harware aerae unction isale harware aerae unction enale harware aerae select eterines how any conersions will e aerae to create the aerae result sales aerae sales aerae sales aerae sales aerae oset correction reister x of the adc offset correction register (ofs) contains the user selected or calibration generated offset error correction value. this register is a 2s complement, left justified, 16-bit value. the value in the offset correction registers (ofs) is subtracted from the conversion and the result is transferred into the result registers (rn). if the result is above the maximum or below the minimum result value, it is forced to the appropriate limit for the current mode of operation. addresses: adc0_ofs is 4003_b000h base + 28h offset = 4003_b028h adc1_ofs is 400b_b000h base + 28h offset = 400b_b028h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 ofs w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 chapter 34 analog-to-digital converter (adc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 817 adc x of iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero of oset error correction alue lussie ain reister x the plus-side gain register (pg) contains the gain error correction for the plus-side input in differential mode or the overall conversion in single-ended mode. pg, a 16-bit real number in binary format, is the gain adjustment factor, with the radix point fixed between adpg15 and adpg14. this register must be written by the user with the value described in the calibration procedure or the gain error specifications may not be met. addresses: adc0_pg is 4003_b000h base + 2ch offset = 4003_b02ch adc1_pg is 400b_b000h base + 2ch offset = 400b_b02ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 pg w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 adc x iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero lussie ain inussie ain reister x the minus-side gain register (mg) contains the gain error correction for the minus-side input in differential mode. this register is ignored in single-ended mode. mg, a 16-bit real number in binary format, is the gain adjustment factor, with the radix point fixed between admg15 and admg14. this register must be written by the user with the value described in the calibration procedure or the gain error specifications may not be met. register definition k60 sub-family reference manual, rev. 6, nov 2011 818 freescale semiconductor, inc. addresses: adc0_mg is 4003_b000h base + 30h offset = 4003_b030h adc1_mg is 400b_b000h base + 30h offset = 400b_b030h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 mg w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 adc x iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero inussie ain lussie eneral caliration alue reister x l the plus-side general calibration value registers (clpx) contain calibration information that is generated by the calibration function. these registers contain seven calibration values of varying widths: clp0[5:0], clp1[6:0], clp2[7:0], clp3[8:0], clp4[9:0], clps[5:0], and clpd[5:0]. clpx are automatically set once the self calibration sequence is done (cal is cleared). if these registers are written by the user after calibration, the linearity error specifications may not be met. addresses: adc0_clpd is 4003_b000h base + 34h offset = 4003_b034h adc1_clpd is 400b_b000h base + 34h offset = 400b_b034h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 clpd w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 adc x l iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero l aliration alue hater nalotoiital onerter ufaily reerence anual re o freescale eiconuctor nc 34.3.12 adc plus-side general calibration value register (adc x l for more information, refer to clpd register description. addresses: adc0_clps is 4003_b000h base + 38h offset = 4003_b038h adc1_clps is 400b_b000h base + 38h offset = 400b_b038h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 clps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 adc x l iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero l aliration alue lussie eneral caliration alue reister x l for more information, refer to clpd register description. addresses: adc0_clp4 is 4003_b000h base + 3ch offset = 4003_b03ch adc1_clp4 is 400b_b000h base + 3ch offset = 400b_b03ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 clp4 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 adc x l iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero l aliration alue reister einition ufaily reerence anual re o freescale eiconuctor nc 34.3.14 adc plus-side general calibration value register (adc x l for more information, refer to clpd register description. addresses: adc0_clp3 is 4003_b000h base + 40h offset = 4003_b040h adc1_clp3 is 400b_b000h base + 40h offset = 400b_b040h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 clp3 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 adc x l iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero l aliration alue lussie eneral caliration alue reister x l for more information, refer to clpd register description. addresses: adc0_clp2 is 4003_b000h base + 44h offset = 4003_b044h adc1_clp2 is 400b_b000h base + 44h offset = 400b_b044h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 clp2 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 adc x l iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero l aliration alue hater nalotoiital onerter ufaily reerence anual re o freescale eiconuctor nc 34.3.16 adc plus-side general calibration value register (adc x l for more information, refer to clpd register description. addresses: adc0_clp1 is 4003_b000h base + 48h offset = 4003_b048h adc1_clp1 is 400b_b000h base + 48h offset = 400b_b048h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 clp1 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 adc x l iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero l aliration alue lussie eneral caliration alue reister x l for more information, refer to clpd register description. addresses: adc0_clp0 is 4003_b000h base + 4ch offset = 4003_b04ch adc1_clp0 is 400b_b000h base + 4ch offset = 400b_b04ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 clp0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 adc x l iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero l aliration alue reister einition ufaily reerence anual re o freescale eiconuctor nc 34.3.18 adc pga register (adc x resses: is h ase h oset h is h ase h oset h it r l reset it r reset x iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero enale isale enale resere his reaonly iel is resere an always has the alue ero resere his iel is resere l lowower oe control runs in low ower oe runs in noral ower oe ain settin ain resere table continues on the next page... chapter 4 analog-to-digital converter adc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 82 adc x iel escritions continue fiel escrition resere resere resere resere resere resere resere resere resere his reaonly iel is resere an always has the alue ero inussie eneral caliration alue reister x l clmx contain calibration information that is generated by the calibration function. these registers contain seven calibration values of varying widths: clm0[5:0], clm1[6:0], clm2[7:0], clm3[8:0], clm4[9:0], clms[5:0], and clmd[5:0]. clmx are automatically set once the self calibration sequence is done (cal is cleared). if these registers are written by the user after calibration, the linearity error specifications may not be met. addresses: adc0_clmd is 4003_b000h base + 54h offset = 4003_b054h adc1_clmd is 400b_b000h base + 54h offset = 400b_b054h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 clmd w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 adc x l iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero l aliration alue reister einition ufaily reerence anual re o freescale eiconuctor nc 34.3.20 adc minus-side general calibration value register (adc x l for more information, refer to clmd register description. addresses: adc0_clms is 4003_b000h base + 58h offset = 4003_b058h adc1_clms is 400b_b000h base + 58h offset = 400b_b058h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 clms w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 adc x l iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero l aliration alue inussie eneral caliration alue reister x l for more information, refer to clmd register description. addresses: adc0_clm4 is 4003_b000h base + 5ch offset = 4003_b05ch adc1_clm4 is 400b_b000h base + 5ch offset = 400b_b05ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 clm4 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 adc x l iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero l aliration alue hater nalotoiital onerter ufaily reerence anual re o freescale eiconuctor nc 34.3.22 adc minus-side general calibration value register (adc x l for more information, refer to clmd register description. addresses: adc0_clm3 is 4003_b000h base + 60h offset = 4003_b060h adc1_clm3 is 400b_b000h base + 60h offset = 400b_b060h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 clm3 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 adc x l iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero l aliration alue inussie eneral caliration alue reister x l for more information, refer to clmd register description. addresses: adc0_clm2 is 4003_b000h base + 64h offset = 4003_b064h adc1_clm2 is 400b_b000h base + 64h offset = 400b_b064h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 clm2 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 adc x l iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero l aliration alue reister einition ufaily reerence anual re o freescale eiconuctor nc 34.3.24 adc minus-side general calibration value register (adc x l for more information, refer to clmd register description. addresses: adc0_clm1 is 4003_b000h base + 68h offset = 4003_b068h adc1_clm1 is 400b_b000h base + 68h offset = 400b_b068h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 clm1 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 adc x l iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero l aliration alue inussie eneral caliration alue reister x l for more information, refer to clmd register description. addresses: adc0_clm0 is 4003_b000h base + 6ch offset = 4003_b06ch adc1_clm0 is 400b_b000h base + 6ch offset = 400b_b06ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 clm0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 adc x l iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero l aliration alue hater nalotoiital onerter ufaily reerence anual re o freescale eiconuctor nc 34.4 functional description the adc module is disabled during reset, in low power stop mode (refer to the power management information for details), or when the adch bits in sc1n are all high. the module is idle when a conversion has completed and another conversion has not been initiated. when it is idle and the asynchronous clock output enable is disabled (adacken is 0), the module is in its lowest power state. the adc can perform an analog-to-digital conversion on any of the software selectable channels. all modes perform conversion by a successive approximation algorithm. to meet accuracy specifications, the adc module must be calibrated using the on chip calibration function. see calibration function for details on how to perform calibration. when the conversion is completed, the result is placed in the data registers (rn). the respective conversion complete flag (coco) is then set and an interrupt is generated if the respective conversion complete interrupt has been enabled (aien=1). the adc module has the capability of automatically comparing the result of a conversion with the contents of the compare value registers. the compare function is enabled by setting the acfe bit and operates with any of the conversion modes and configurations. the adc module has the capability of automatically averaging the result of multiple conversions. the hardware average function is enabled by setting the avge bit and operates with any of the conversion modes and configurations. note for the chip specific modes of operation, refer to the power management information of this mcu. 34.4.1 pga functional description the programmable gain amplifier (pga) is designed to increase the dynamic range by amplifying low-amplitude signals before they are fed to the 16-bit sar adc. the gain of this amplifier is ranged between 1 to 64 in (2^n) steps (1,2,4,8,16,32,64). this block is designed to work with differential input and output with input signals that range from 0 -1.2 v 10 mv. the output common mode of the pga is determined based on the sar adc requirement. functional description k60 sub-family reference manual, rev. 6, nov 2011 828 freescale semiconductor, inc. the pga has only one voltage reference pair. the positive reference used is chip specific and depends on the mcu configuration. refer to the chip configuration chapter on the pga voltage reference specific to this mcu. the ground reference is the analog ground for the pga. the adc pga register allows to control the pga gain and modes of operation. 34.4.2 clock select and divide control one of four clock sources can be selected as the clock source for the adc module. this clock source is then divided by a configurable value to generate the input clock to the converter (adck). the clock is selected from one of the following sources by means of the adiclk bits. ? the bus clock. this is the default selection following reset. ? the bus clock divided by two. for higher bus clock rates, this allows a maximum divide by 16 of the bus clock with using the adiv bits. ? altclk, as defined for this mcu. refer to the chip configuration information. ? the asynchronous clock (adack). this clock is generated from a clock source within the adc module. note that when the adack clock source is selected, it is not required to be active prior to conversion start. when it is selected and it is not active prior to a conversion start (adacken=0), the asynchronous clock is activated at the start of a conversion and shuts off when conversions are terminated. in this case, there is an associated clock startup delay each time the clock source is re-activated. to avoid the conversion time variability and latency associated with the adack clock startup, set adacken=1 and wait the worst case startup time of 5 s prior to initiating any conversions using the adack clock source. conversions are possible using adack as the input clock source while the mcu is in normal stop mode. refer to power control for more information. whichever clock is selected, its frequency must fall within the specified frequency range for adck. if the available clocks are too slow, the adc may not perform according to specifications. if the available clocks are too fast, the clock must be divided to the appropriate frequency. this divider is specified by the adiv bits and can be divide-by 1, 2, 4, or 8. chapter 34 analog-to-digital converter (adc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 829 34.4.3 voltage reference selection the adc can be configured to accept one of the two voltage reference pairs as the reference voltage (v refsh and v refsl ) used for conversions. each pair contains a positive reference that must be between the minimum ref voltage high and v dda , and a ground reference that must be at the same potential as v ssa . the two pairs are external (v refh and v refl ) and alternate (v alth and v altl ). these voltage references are selected using the refsel bits in the sc2 register. the alternate (v alth and v altl ) voltage reference pair may select additional external pins or internal sources depending on mcu configuration. refer to the chip configuration information on the voltage references specific to this mcu. 34.4.4 hardware trigger and channel selects the adc module has a selectable asynchronous hardware conversion trigger, adhwt, that is enabled when the adtrg bit is set and a hardware trigger select event (adhwtsn) has occurred. this source is not available on all mcus. refer to the chip configuration chapter for information on the adhwt source and the adhwtsn configurations specific to this mcu. when a adhwt source is available and hardware trigger is enabled (adtrg=1), a conversion is initiated on the rising edge of adhwt after a hardware trigger select event (adhwtsn) has occurred. if a conversion is in progress when a rising edge of a trigger occurs, the rising edge is ignored. in continuous convert configuration, only the initial rising edge to launch continuous conversions is observed, and until conversion gets aborted the adc continues to do conversions on the same adc status and control register that initiated the conversion. the hardware trigger function operates in conjunction with any of the conversion modes and configurations. the hardware trigger select event (adhwtsn) must be set prior to the receipt of the adhwt signal. if these conditions are not met, the converter may ignore the trigger or use the incorrect configuration. if a hardware trigger select event gets asserted during a conversion, it must stay asserted until the end of current conversion and remain set until the receipt of the adhwt signal to trigger a new conversion. the channel and status fields selected for the conversion depend on the active trigger select signal (adhwtsa active selects sc1a; adhwtsn active selects sc1n). note asserting more than one hardware trigger select signal (adhwtsn) at the same time results in unknown results. to avoid this, select only one hardware trigger select signal (adhwtsn) prior to the next intended conversion. functional description k60 sub-family reference manual, rev. 6, nov 2011 830 freescale semiconductor, inc. when the conversion is completed, the result is placed in the data registers associated with the adhwtsn received (adhwtsa active selects ra register; adhwtsn active selects rn register). the conversion complete flag associated with the adhwtsn received (the coco bit in sc1n register) is then set and an interrupt is generated if the respective conversion complete interrupt has been enabled (aien=1). 34.4.5 conversion control conversions can be performed as determined by the cfg1[mode] bits and the sc1n[diff] bit as shown in the description of cfg1[mode]. conversions can be initiated by a software or hardware trigger. in addition, the adc module can be configured for low power operation, long sample time, continuous conversion, hardware average, and automatic compare of the conversion result to a software determined compare value. 34.4.5.1 initiating conversions a conversion is initiated: ? following a write to sc1a register (with adch bits not all 1's) if software triggered operation is selected (adtrg=0). ? following a hardware trigger (adhwt) event if hardware triggered operation is selected (adtrg=1) and a hardware trigger select event (adhwtsn) has occurred. the channel and status fields selected depend on the active trigger select signal (adhwtsa active selects sc1a register; adhwtsn active selects sc1n register; if neither is active, the off condition is selected). note selecting more than one hardware trigger select signal (adhwtsn) prior to a conversion completion will result in unknown results. to avoid this, select only one hardware trigger select signal (adhwtsn) prior to a conversion completion. ? following the transfer of the result to the data registers when continuous conversion is enabled (adco=1). chapter 34 analog-to-digital converter (adc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 831 if continuous conversions are enabled, a new conversion is automatically initiated after the completion of the current conversion. in software triggered operation (adtrg=0), continuous conversions begin after sc1a register is written and continue until aborted. in hardware triggered operation (adtrg=1 and one adhwtsn event has occurred), continuous conversions begin after a hardware trigger event and continue until aborted. if hardware averaging is enabled, a new conversion is automatically initiated after the completion of the current conversion until the correct number of conversions is completed. in software triggered operation, conversions begin after sc1a register is written. in hardware triggered operation, conversions begin after a hardware trigger. if continuous conversions are also enabled, a new set of conversions to be averaged are initiated following the last of the selected number of conversions. 34.4.5.2 completing conversions a conversion is completed when the result of the conversion is transferred into the data result registers, rn. if the compare functions are disabled, this is indicated by the setting of the coco bit in the respective sc1n register. if hardware averaging is enabled, the respective coco bit sets only if the last of the selected number of conversions is completed. if the compare function is enabled, the respective coco bit sets and conversion result data is transferred only if the compare condition is true. if both hardware averaging and compare functions are enabled then the respective coco bit sets only if the last of the selected number of conversions is completed and the compare condition is true. an interrupt is generated if the respective aien bit is high at the time that the respective coco bit is set. 34.4.5.3 aborting conversions any conversion in progress is aborted when: ? writing to sc1a register while it is actively controlling a conversion, aborts the current conversion. in software trigger mode (adtrg=0), a write to sc1a register initiates a new conversion (if the adch field in sc1a is equal to a value other than all 1s). writing to any of the sc1(b-n) registers while that specific sc1(b-n) register is actively controlling a conversion aborts the current conversion.the sc1(b-n) registers are not used for software trigger operation and therefore writes to the sc1(b-n) registers do not initiate a new conversion. ? a write to any adc register besides the sc1a:sc1n registers occurs. this indicates a mode of operation change has occurred and the current conversion is therefore invalid. functional description k60 sub-family reference manual, rev. 6, nov 2011 832 freescale semiconductor, inc. ? the mcu is reset or enters low power stop modes. ? the mcu enters normal stop mode with adack not enabled. when a conversion is aborted, the contents of the data registers, rn, are not altered. the data registers continue to be the values transferred after the completion of the last successful conversion. if the conversion was aborted by a reset or low power stop modes, ra and r n return to their reset states. 34.4.5.4 power control the adc module remains in its idle state until a conversion is initiated. if adack is selected as the conversion clock source, but the asynchronous clock output is disabled (adacken=0), the adack clock generator also remains in its idle state (disabled) until a conversion is initiated. if the asynchronous clock output is enabled (adacken=1), it remains active regardless of the state of the adc or the mcu power mode. power consumption when the adc is active can be reduced by setting adlpc. this results in a lower maximum value for f adck . 34.4.5.5 sample time and total conversion time for short sample (adlsmp=0), there is a 2-cycle adder for first conversion over the base sample time of 4 adck cycles. for high speed conversions (adhsc=1), there is an additional 2-cycle adder on any conversion. the table below summarizes sample times for the possible adc configurations. adc configuration sample time (adck cycles) adlsmp adlsts adhsc first or single subsequent 0 x 0 6 4 1 00 0 24 1 01 0 16 1 10 0 10 1 11 0 6 0 x 1 8 6 1 00 1 26 1 01 1 18 1 10 1 12 table continues on the next page... chapter 4 analog-to-digital converter adc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 8 adc configuration sample time (adck cycles) 1 11 1 8 the total conversion time depends upon: the sample time (as determined by adlsmp and adlsts bits), the mcu bus frequency, the conversion mode (as determined by mode and sc1n[diff] bits), the high speed configuration (adhsc bit), and the frequency of the conversion clock (f adck ). the adhsc bit is used to configure a higher clock input frequency. this will allow faster overall conversion times. to meet internal adc timing requirements, the adhsc bit adds additional adck cycles. conversions with adhsc = 1 take two more adck cycles. adhsc should be used when the adclk exceeds the limit for adhsc = 0. after the module becomes active, sampling of the input begins. adlsmp and adlsts select between sample times based on the conversion mode that is selected. when sampling is completed, the converter is isolated from the input channel and a successive approximation algorithm is performed to determine the digital value of the analog signal. the result of the conversion is transferred to rn upon completion of the conversion algorithm. if the bus frequency is less than the f adck frequency, precise sample time for continuous conversions cannot be guaranteed when short sample is enabled (adlsmp=0). the maximum total conversion time is determined by the clock source chosen and the divide ratio selected. the clock source is selectable by the adiclk bits, and the divide ratio is specified by the adiv bits. the maximum total conversion time for all configurations is summarized in the equation below. refer to the following tables for the variables referenced in the equation. figure 34-95. conversion time equation table 34-107. single or first continuous time adder (sfcadder) adlsmp adacke n adiclk single or first continuous time adder (sfcadder) 1 x 0x, 10 3 adck cycles + 5 bus clock cycles 1 1 11 3 adck cycles + 5 bus clock cycles 1 1 0 11 5 5 table 34-108. average number factor (averagenum) avge avgs[1:0] average number factor (averagenum) 0 xx 1 1 00 4 1 01 8 1 10 16 1 11 32 table 34-109. base conversion time (bct) mode base conversion time (bct) 8b s.e. 17 adck cycles 9b diff 27 adck cycles 10b s.e. 20 adck cycles 11b diff 30 adck cycles 12b s.e. 20 adck cycles 13b diff 30 adck cycles 16b s.e. 25 adck cycles 16b diff 34 adck cycles table 34-110. long sample time adder (lstadder) adlsmp adlsts long sample time adder (lstadder) 0 xx 0 adck cycles 1 00 20 adck cycles 1 01 12 adck cycles 1 10 6 adck cycles 1 11 2 adck cycles table 34-111. high speed conversion time adder (hscadder) adhsc high speed conversion time adder (hscadder) 0 0 adck cycles 1 2 adck cycles note the adck frequency must be between f adck minimum and f adck maximum to meet adc specifications. chapter 34 analog-to-digital converter (adc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 835 34.4.5.6 conversion time examples the following examples use figure 34-95 and the information provided in table 34-107 through table 34-111 . 34.4.5.6.1 typical conversion time configuration a typical configuration for adc conversion is: 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1 ratio selected, and a bus frequency of 8 mhz, long sample time disabled and high speed conversion disabled. the conversion time for a single conversion is calculated by using figure 34-95 and the information provided in table 34-107 through table 34-111 . the table below list the variables of figure 34-95 . table 34-112. typical conversion time variable time sfcadder 5 adck cycles + 5 bus clock cycles averagenum 1 bct 20 adck cycles lstadder 0 hscadder 0 the resulting conversion time is generated using the parameters listed in the proceeding table. therefore, for a bus clock equal to 8 mhz and an adck equal to 8 mhz the resulting conversion time is 3.75 s. 34.4.5.6.2 long conversion time configuration a configuration for long adc conversion is: 16-bit differential mode with the bus clock selected as the input clock source, the input clock divide-by-8 ratio selected, a bus frequency of 8 mhz, long sample time enabled, configured for longest adder, high speed conversion disabled, and average enabled for 32 conversions. the conversion time for this conversion is calculated by using figure 34-95 and the information provided in table 34-107 through table 34-111 . the following table lists the variables of the figure 34-95 . table 34-113. typical conversion time variable time sfcadder 3 adck cycles + 5 bus clock cycles averagenum 32 bct 34 adck cycles lstadder 20 adck cycles table continues on the next page... functional description 60 sub-family reference manual, rev. 6, nov 2011 86 freescale semiconductor, inc. table 34-113. typical conversion time (continued) variable time hscadder 0 the resulting conversion time is generated using the parameters listed in the preceding table. therefore, for bus clock equal to 8 mhz and adck equal to 1 mhz, the resulting conversion time is 57.625 s (averagenum). this results in a total conversion time of 1.844 ms. 34.4.5.6.3 short conversion time configuration a configuration for short adc conversion is: 8-bit single ended mode with the bus clock selected as the input clock source, the input clock divide-by-1 ratio selected, a bus frequency of 20 mhz, long sample time disabled, and high speed conversion enabled. the conversion time for this conversion is calculated by using figure 34-95 and the information provided in table 34-107 through table 34-111 . the table below list the variables of figure 34-95 . table 34-114. typical conversion time variable time sfcadder 5 adck cycles + 5 bus clock cycles averagenum 1 bct 17 adck cycles lstadder 0 adck cycles hscadder 2 the resulting conversion time is generated using the parameters listed in in the preceding table. therefore, for bus clock equal to 20 mhz and adck equal to 20 mhz, the resulting conversion time is 1.45 s. 34.4.5.7 hardware average function the hardware average function can be enabled (avge=1) to perform a hardware average of multiple conversions. the number of conversions is determined by the avgs[1:0] bits, which select 4, 8, 16, or 32 conversions to be averaged. while the hardware average function is in progress, the adact bit will be set. chapter 34 analog-to-digital converter (adc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 837 after the selected input is sampled and converted, the result is placed in an accumulator from which an average is calculated once the selected number of conversions has been completed. when hardware averaging is selected, the completion of a single conversion will not set the coco bit. if the compare function is either disabled or evaluates true, after the selected number of conversions are completed, the average conversion result is transferred into the data result registers, rn, and the coco bit is set. an adc interrupt is generated upon the setting of coco if the respective adc interrupt is enabled (aien=1). note the hardware average function can perform conversions on a channel while the mcu is in wait or normal stop modes. the adc interrupt wakes the mcu when the hardware average is completed if sc1n[aien] bit was set. 34.4.6 automatic compare function the compare function can be configured to check if the result is less than or greater-than- or-equal-to a single compare value, or if the result falls within or outside a range determined by two compare values. the compare mode is determined by acfgt, acren, and the values in the compare value registers (cv1 and cv2). after the input is sampled and converted, the compare values (cv1 and cv2) are used as described in the following table.there are six compare modes as shown in the following table. table 34-115. compare modes acfgt acren adccv1 relative to adccv2 function compare mode description 0 0 less than threshold compare true if the result is less than the cv1 registers. 1 0 greater than or equal to threshold compare true if the result is greater than or equal to cv1 registers. 0 1 less than or equal outside range, not inclusive compare true if the result is less than cv1 or the result is greater than cv2. 0 1 greater than inside range, not inclusive compare true if the result is less than cv1 and the result is greater than cv2. 1 1 less than or equal inside range, inclusive compare true if the result is greater than or equal to cv1 and the result is less than or equal to cv2. 1 1 greater than outside range, inclusive compare true if the result is greater than or equal to cv1 or the result is less than or equal to cv2. functional description k60 sub-family reference manual, rev. 6, nov 2011 838 freescale semiconductor, inc. with the adc range enable bit set, acren =1, and if compare value register 1 (cv1 value) is less than or equal to the compare value register 2 (cv2 value), then setting acfgt will select a trigger-if-inside-compare-range inclusive-of-endpoints function. clearing acfgt will select a trigger-if-outside-compare-range, not-inclusive-of- endpoints function. if cv1 is greater than cv2, setting acfgt will select a trigger-if-outside-compare- range, inclusive-of-endpoints function. clearing acfgt will select a trigger-if-inside- compare-range, not-inclusive-of-endpoints function. if the condition selected evaluates true, coco is set. upon completion of a conversion while the compare function is enabled, if the compare condition is not true, coco is not set and the conversion result data will not be transferred to the result register. if the hardware averaging function is enabled, the compare function compares the averaged result to the compare values. the same compare function definitions apply. an adc interrupt is generated upon the setting of coco if the respective adc interrupt is enabled (aien=1). note the compare function can monitor the voltage on a channel while the mcu is in wait or normal stop modes. the adc interrupt wakes the mcu when the compare condition is met. 34.4.7 calibration function the adc contains a self-calibration function that is required to achieve the specified accuracy. calibration must be run, or valid calibration values written, after any reset and before a conversion is initiated. the calibration function sets the offset calibration value, the minus-side calibration values, and the plus-side calibration values. the offset calibration value is automatically stored in the adc offset correction register (ofs), and the plus-side and minus-side calibration values are automatically stored in the adc plus- side and minus-side calibration (clpx and clmx) registers. the user must configure the adc correctly prior to calibration, and must generate the plus-side and minus-side gain calibration results and store them in the adc plus-side gain register (pg) after the calibration function completes. prior to calibration, the user must configure the adc's clock source and frequency, low power configuration, voltage reference selection, sample time, and high speed configuration according to the application's clock source availability and needs. if the application uses the adc in a wide variety of configurations, the configuration for which the highest accuracy is required should be selected, or multiple calibrations can be done chapter 34 analog-to-digital converter (adc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 839 for the different configurations. for best calibration results, it is recommended to set hardware averaging to maximum (avge=1, avgs=11 for average of 32), adc clock frequency f adck less than or equal to 4 mhz, v refh =v dda , and to calibrate at nominal voltage and temperature. the input channel, conversion mode continuous function, compare function, resolution mode, and differential/single-ended mode are all ignored during the calibration function. to initiate calibration, the user sets the cal bit and the calibration will automatically begin if the adtrg bit is 0. if adtrg is 1, the cal bit will not get set and the calibration fail flag (calf) will be set. while calibration is active, no adc register can be written and no stop mode may be entered, or the calibration routine will be aborted causing the cal bit to clear and the calf bit to set. at the end of a calibration sequence, the coco bit of the sc1a register will be set. the aien bit can be used to allow an interrupt to occur at the end of a calibration sequence. at the end of the calibration routine, if the calf bit is not set, the automatic calibration routine completed successfully. to complete calibration, the user must generate the gain calibration values using the following procedure: 1. initialize (clear) a 16-bit variable in ram. 2. add the plus-side calibration results clp0, clp1, clp2, clp3, clp4, and clps to the variable. 3. divide the variable by two. 4. set the msb of the variable. 5. the previous two steps can be achieved by setting the carry bit, rotating to the right through the carry bit on the high byte and again on the low byte. 6. store the value in the plus-side gain calibration register (pg). 7. repeat the procedure for the minus-side gain calibration value. when calibration is complete, the user may reconfigure and use the adc as desired. a second calibration may also be performed if desired by clearing and again setting the cal bit. overall, the calibration routine may take as many as 14k adck cycles and 100 bus cycles, depending on the results and the clock source chosen. for an 8 mhz clock source, this length amounts to about 1.7 ms. to reduce this latency, the calibration values (offset, plus-side and minus-side gain, and plus-side and minus-side calibration values) may be functional description k60 sub-family reference manual, rev. 6, nov 2011 840 freescale semiconductor, inc. stored in flash memory after an initial calibration and recovered prior to the first adc conversion. this method should reduce the calibration latency to 20 register store operations on all subsequent power, reset, or low power stop mode recoveries. 34.4.8 user defined offset function the adc offset correction register (ofs) contains the user selected or calibration generated offset error correction value. this register is a 2s complement, left justified. the value in the offset correction register (ofs) is subtracted from the conversion and the result is transferred into the result registers (rn). if the result is above the maximum or below the minimum result value, it is forced to the appropriate limit for the current mode of operation. the formatting of the adc offset correction register is different from the data result register (rn) to preserve the resolution of the calibration value regardless of the conversion mode selected. lower order bits are ignored in lower resolution modes. for example, in 8-bit single-ended mode, the bits ofs[14:7] are subtracted from d[7:0]; bit ofs[15] indicates the sign (negative numbers are effectively added to the result) and bits ofs[6:0] are ignored. the same bits are used in 9-bit differential mode since bit ofs[15] indicates the sign bit, which maps to bit d[8]. for 16-bit differential mode, all bits ofs[15:0] are directly subtracted from the conversion result data d[15:0]. in 16-bit single-ended mode, there is no bit in the offset correction register corresponding to the least significant result bit d[0], so odd values (-1 or +1, and so on) cannot be subtracted from the result. ofs is automatically set according to calibration requirements once the self calibration sequence is done (cal is cleared). the user may write to ofs to override the calibration result if desired. if the offset correction register is written by the user to a value that is different from the calibration value, the adc error specifications may not be met. it is recommended that the value generated by the calibration function be stored in memory before overwriting with a user specified value. note there is an effective limit to the values of offset that can be set by the user. if the magnitude of the offset is too great, the results of the conversions will cap off at the limits. the offset calibration function may be employed by the user to remove application offsets or dc bias values. the offset correction register, ofs may be written with a number in 2's complement format and this offset will be subtracted from the result (or hardware averaged value). to add an offset, store the negative offset in 2's complement chapter 34 analog-to-digital converter (adc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 841 format and the effect will be an addition. an offset correction that results in an out-of- range value will be forced to the minimum or maximum value (the minimum value for single-ended conversions is 0x0000; for a differential conversion it is 0x8000). to preserve accuracy, the calibrated offset value initially stored in the ofs register must be added to the user defined offset. for applications that may change the offset repeatedly during operation, it is recommended to store the initial offset calibration value in flash so it can be recovered and added to any user offset adjustment value and the sum stored in the ofs register. 34.4.9 temperature sensor the adc module includes a temperature sensor whose output is connected to one of the adc analog channel inputs. the following equation provides an approximate transfer function of the temperature sensor. m figure 34-96. approximate transfer function of the temperature sensor where: ? v temp is the voltage of the temperature sensor channel at the ambient temperature. ? v temp25 is the voltage of the temperature sensor channel at 25 c. ? m is the hot or cold voltage versus temperature slope in v/c. for temperature calculations, use the v temp25 and m values from the adc electricals table. in application code, the user reads the temperature sensor channel, calculates v temp , and compares to v temp25 . if v temp is greater than v temp25 the cold slope value is applied in the preceding equation. if v temp is less than v temp25 , the hot slope value is applied in the preceding equation. for more information on using the temperature sensor, see the application note titled temperature sensor for the hcs08 microcontroller family (document an3031). functional description k60 sub-family reference manual, rev. 6, nov 2011 842 freescale semiconductor, inc. 34.4.10 mcu wait mode operation wait mode is a lower power-consumption standby mode from which recovery is fast because the clock sources remain active. if a conversion is in progress when the mcu enters wait mode, it continues until completion. conversions can be initiated while the mcu is in wait mode by means of the hardware trigger or if continuous conversions are enabled. the bus clock, bus clock divided by two, and adack are available as conversion clock sources while in wait mode. the use of altclk as the conversion clock source in wait is dependent on the definition of altclk for this mcu. refer to the chip configuration information on altclk specific to this mcu. if the compare and hardware averaging functions are disabled, a conversion complete event sets the coco and generates an adc interrupt to wake the mcu from wait mode if the respective adc interrupt is enabled (aien=1). if the hardware averaging function is enabled, the coco will set (and generate an interrupt if enabled) when the selected number of conversions are completed. if the compare function is enabled, the coco will set (and generate an interrupt if enabled) only if the compare conditions are met. if a single conversion is selected and the compare trigger is not met, the adc will return to its idle state and cannot wake the mcu from wait mode unless a new conversion is initiated by the hardware trigger. 34.4.11 mcu normal stop mode operation stop mode is a low power-consumption standby mode during which most or all clock sources on the mcu are disabled. 34.4.11.1 normal stop mode with adack disabled if the asynchronous clock, adack, is not selected as the conversion clock, executing a stop instruction aborts the current conversion and places the adc in its idle state. the contents of the adc registers, including rn, are unaffected by normal stop mode. after exiting from normal stop mode, a software or hardware trigger is required to resume conversions. chapter 34 analog-to-digital converter (adc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 843 34.4.11.2 normal stop mode with adack enabled if adack is selected as the conversion clock, the adc continues operation during normal stop mode. refer to the chip configuration chapter for configuration information for this mcu. if a conversion is in progress when the mcu enters normal stop mode, it continues until completion. conversions can be initiated while the mcu is in normal stop mode by means of the hardware trigger or if continuous conversions are enabled. if the compare and hardware averaging functions are disabled, a conversion complete event sets the coco and generates an adc interrupt to wake the mcu from normal stop mode if the respective adc interrupt is enabled (aien = 1). the result register will contain the data from the first completed conversion that occurred during normal stop mode. if the hardware averaging function is enabled, the coco will set (and generate an interrupt if enabled) when the selected number of conversions are completed. if the compare function is enabled, the coco will set (and generate an interrupt if enabled) only if the compare conditions are met. if a single conversion is selected and the compare is not true, the adc will return to its idle state and cannot wake the mcu from normal stop mode unless a new conversion is initiated by another hardware trigger. 34.4.12 mcu low power stop mode operation the adc module is automatically disabled when the mcu enters low power stop mode. all module registers contain their reset values following exit from low power stop mode. therefore, the module must be re-enabled and re-configured following exit from low power stop mode. note for the chip specific modes of operation, refer to the power management information for the device. 34.5 initialization information this section gives an example that provides some basic direction on how to initialize and configure the adc module. you can configure the module for 16-bit, 12-bit, 10-bit, or 8- bit single-ended resolution or 16-bit, 13-bit, 11-bit, or 9-bit differential resolution, single or continuous conversion, and a polled or interrupt approach, among many other options. refer to table 34-110 , table 34-111 , and table 34-112 for information used in this example. initialization information k60 sub-family reference manual, rev. 6, nov 2011 844 freescale semiconductor, inc. note hexadecimal values are designated by a preceding 0x, binary values designated by a preceding %, and decimal values have no preceding character. 34.5.1 adc module initialization example this section provides details about the adc module initialization. 34.5.1.1 initialization sequence before the adc module can be used to complete conversions, an initialization procedure must be performed. a typical sequence is as follows: 1. calibrate the adc by following the calibration instructions in calibration function . 2. update the configuration register (cfg) to select the input clock source and the divide ratio used to generate the internal clock, adck. this register is also used for selecting sample time and low-power configuration. 3. update status and control register 2 (sc2) to select the conversion trigger (hardware or software) and compare function options, if enabled. 4. update status and control register 3 (sc3) to select whether conversions will be continuous or completed only once (adco) and to select whether to perform hardware averaging. 5. update the status and control register (sc1:sc1n) to select whether conversions will be single-ended or differential and to enable or disable conversion complete interrupts. also, select the input channel on which to perform conversions. 6. update pga register (pga) to enable or disable pga and configure appropriate gain. this register is also used for selecting power mode and whether the module is chopper stabilized. 34.5.1.2 pseudo-code example in this example, the adc module is set up with interrupts enabled to perform a single 10- bit conversion at low power with a long sample time on input channel 1, where the internal adck clock is derived from the bus clock divided by 1. chapter 34 analog-to-digital converter (adc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 845 cfg1 = 0x98 (%10011000) bit 7 adlpc 1 configures for low power (lowers maximum clock speed. bit 6:5 adiv 00 sets the adck to the input clock 1. bit 4 adlsmp 1 configures for long sample time. bit 3:2 mode 10 selects the single-ended 10-bit conversion, differential 11- bit conversion. bit 1:0 adiclk 00 selects the bus clock. sc2 = 0x00 (%00000000) bit 7 adact 0 flag indicates if a conversion is in progress. bit 6 adtrg 0 software trigger selected. bit 5 acfe 0 compare function disabled. bit 4 acfgt 0 not used in this example. bit 3 acren 0 compare range disabled. bit 2 dmaen 0 dma request disabled. bit 1:0 refsel 00 selects default voltage reference pin pair (external pins v refh and v refl ). sc1a = 0x41 (%01000001) bit 7 coco 0 read-only flag which is set when a conversion completes. bit 6 aien 1 conversion complete interrupt enabled. bit 5 diff 0 single-ended conversion selected. bit 4:0 adch 00001 input channel 1 selected as adc input channel. ra = 0xxx holds results of conversion. cv = 0xxx holds compare value when compare function enabled. initialization information k60 sub-family reference manual, rev. 6, nov 2011 846 freescale semiconductor, inc. reset no yes check sc1n[coco]=1? initialize adc cfg1 = 0x98 sc2 = 0x00 sc1n = 0x41 continue read rn to clear sc1n[coco] bit figure 34-97. initialization flowchart for example 34.6 application information this section contains information for using the adc module in applications. the adc has been designed to be integrated into a microcontroller for use in embedded control applications requiring an adc. 34.6.1 external pins and routing the following sections discuss the external pins associated with the adc module and how they should be used for best results. 34.6.1.1 analog supply pins the adc module has analog power and ground supplies (v dda and v ssa ) available as separate pins on some devices. v ssa is shared on the same pin as the mcu digital vss on some devices. on other devices, v ssa and v dda are shared with the mcu digital chapter 34 analog-to-digital converter (adc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 847 supply pins. in these cases, there are separate pads for the analog supplies bonded to the same pin as the corresponding digital supply so that some degree of isolation between the supplies is maintained. when available on a separate pin, both v dda and v ssa must be connected to the same voltage potential as their corresponding mcu digital supply (v dd and v ss ) and must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. if separate power supplies are used for analog and digital power, the ground connection between these supplies must be at the v ssa pin. this should be the only ground connection between these supplies if possible. the v ssa pin makes a good single point ground location. 34.6.1.2 analog voltage reference pins in addition to the analog supplies, the adc module has connections for two reference voltage inputs used by the converter, v refsh and v refsl . v refsh is the high reference voltage for the converter. v refsl is the low reference voltage for the converter. the adc can be configured to accept one of two voltage reference pairs for v refsh and v refsl . each pair contains a positive reference and a ground reference. the two pairs are external (v refh and v refl ) and alternate (v alth and v altl ). these voltage references are selected using the refsel bits in the sc2 register. the alternate (v alth and v altl ) voltage reference pair may select additional external pins or internal sources depending on mcu configuration. refer to the chip configuration information on the voltage references specific to this mcu. in some packages, the external or alternate pairs are connected in the package to v dda and v ssa , respectively. one of these positive references may be shared on the same pin as v dda on some devices. one of these ground references may be shared on the same pin as v ssa on some devices. if externally available, the positive reference may be connected to the same potential as v dda or may be driven by an external source to a level between the minimum ref voltage high and the v dda potential (the positive reference must never exceed v dda ). if externally available, the ground reference must be connected to the same voltage potential as v ssa . the voltage reference pairs must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. ac current in the form of current spikes required to supply charge to the capacitor array at each successive approximation step is drawn through the v refh and v refl loop. the best external component to meet this current demand is a 0.1 f capacitor with good high application information k60 sub-family reference manual, rev. 6, nov 2011 848 freescale semiconductor, inc. frequency characteristics. this capacitor is connected between v refh and v refl and must be placed as near as possible to the package pins. resistance in the path is not recommended because the current causes a voltage drop that could result in conversion errors. inductance in this path must be minimum (parasitic only). 34.6.1.3 analog input pins the external analog inputs are typically shared with digital i/o pins on mcu devices. empirical data shows that capacitors on the analog inputs improve performance in the presence of noise or when the source impedance is high. use of 0.01 f capacitors with good high-frequency characteristics is sufficient. these capacitors are not necessary in all cases, but when used they must be placed as near as possible to the package pins and be referenced to v ssa . for proper conversion, the input voltage must fall between v refh and v refl . if the input is equal to or exceeds v refh , the converter circuit converts the signal to 0xfff (full scale 12-bit representation), 0x3ff (full scale 10-bit representation) or 0xff (full scale 8-bit representation). if the input is equal to or less than v refl , the converter circuit converts it to 0x000. input voltages between v refh and v refl are straight-line linear conversions. there is a brief current associated with v refl when the sampling capacitor is charging. for minimal loss of accuracy due to current injection, pins adjacent to the analog input pins should not be transitioning during conversions. 34.6.2 sources of error several sources of error exist for a/d conversions. these are discussed in the following sections. 34.6.2.1 sampling error for proper conversions, the input must be sampled long enough to achieve the proper accuracy. ras + radin =sc / (fmax * numtau * cadin) figure 34-98. sampling equation where: ras = external analog source resistance chapter 34 analog-to-digital converter (adc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 849 sc = number of adck cycles used during sample window cadin = internal adc input capacitance numtau = -ln(lsberr / 2 n ) lsberr = value of acceptable sampling error in lsbs n = 8 in 8-bit mode, 10 in 10-bit mode, 12 in 12-bit mode or 16 in 16-bit mode higher source resistances or higher-accuracy sampling is possible by setting adlsmp and changing the adlsts bits (to increase the sample window) or decreasing adck frequency to increase sample time. 34.6.2.2 pin leakage error leakage on the i/o pins can cause conversion error if the external analog source resistance (r as ) is high. if this error cannot be tolerated by the application, keep r as lower than v refh / (4 i leak 2 n ) for less than 1/4 lsb leakage error (n = 8 in 8-bit mode, 10 in 10-bit mode, 12 in 12-bit mode, or 16 in 16-bit mode). 34.6.2.3 noise-induced errors system noise that occurs during the sample or conversion process can affect the accuracy of the conversion. the adc accuracy numbers are guaranteed as specified only if the following conditions are met: ? there is a 0.1 f low-esr capacitor from v refh to v refl . ? there is a 0.1 f low-esr capacitor from v dda to v ssa . ? if inductive isolation is used from the primary supply, an additional 1 f capacitor is placed from v dda to v ssa . ? v ssa (and v refl , if connected) is connected to v ss at a quiet point in the ground plane. ? operate the mcu in wait or normal stop mode before initiating (hardware triggered conversions) or immediately after initiating (hardware or software triggered conversions) the adc conversion. application information k60 sub-family reference manual, rev. 6, nov 2011 850 freescale semiconductor, inc. ? for software triggered conversions, immediately follow the write to the sc1 register with a wait instruction or stop instruction. ? for normal stop mode operation, select adack as the clock source. operation in normal stop reduces v dd noise but increases effective conversion time due to stop recovery. ? there is no i/o switching, input or output, on the mcu during the conversion. there are some situations where external system activity causes radiated or conducted noise emissions or excessive v dd noise is coupled into the adc. in these situations, or when the mcu cannot be placed in wait or normal stop or i/o activity cannot be halted, these recommended actions may reduce the effect of noise on the accuracy: ? place a 0.01 f capacitor (c as ) on the selected input channel to v refl or v ssa (this improves noise issues, but affects the sample rate based on the external analog source resistance). ? average the result by converting the analog input many times in succession and dividing the sum of the results. four samples are required to eliminate the effect of a 1 lsb, one-time error. ? reduce the effect of synchronous noise by operating off the asynchronous clock (adack) and averaging. noise that is synchronous to adck cannot be averaged out. 34.6.2.4 code width and quantization error the adc quantizes the ideal straight-line transfer function into 65536 steps (in 16-bit mode). each step ideally has the same height (1 code) and width. the width is defined as the delta between the transition points to one code and the next. the ideal code width for an n bit converter (in this case n can be 16, 12, 10, or 8), defined as 1 lsb, is: lsb figure 34-99. ideal code width for an n bit converter there is an inherent quantization error due to the digitization of the result. for 8-bit, 10- bit, or 12-bit conversions, the code transitions when the voltage is at the midpoint between the points where the straight line transfer function is exactly represented by the actual transfer function. therefore, the quantization error will be 1/2 lsb in 8-bit, 10- bit, or 12-bit modes. as a consequence, however, the code width of the first (0x000) conversion is only 1/2 lsb and the code width of the last (0xff or 0x3ff) is 1.5 lsb. chapter 34 analog-to-digital converter (adc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 851 for 16-bit conversions, the code transitions only after the full code width is present, so the quantization error is -1 lsb to 0 lsb and the code width of each step is 1 lsb. 34.6.2.5 linearity errors the adc may also exhibit non-linearity of several forms. every effort has been made to reduce these errors, but the system designers should be aware of them because they affect overall accuracy. these errors are: ? zero-scale error (e zs ) (sometimes called offset): this error is defined as the difference between the actual code width of the first conversion and the ideal code width (1/2 lsb in 8-bit, 10-bit, or 12-bit modes and 1 lsb in 16-bit mode). if the first conversion is 0x001, the difference between the actual 0x001 code width and its ideal (1 lsb) is used. ? full-scale error (e fs ): this error is defined as the difference between the actual code width of the last conversion and the ideal code width (1.5 lsb in 8-bit, 10-bit, or 12- bit modes and 1 lsb in 16-bit mode). if the last conversion is 0x3fe, the difference between the actual 0x3fe code width and its ideal (1 lsb) is used. ? differential non-linearity (dnl): this error is defined as the worst-case difference between the actual code width and the ideal code width for all conversions. ? integral non-linearity (inl): this error is defined as the highest-value the (absolute value of the) running sum of dnl achieves. more simply, this is the worst-case difference of the actual transition voltage to a given code and its corresponding ideal transition voltage, for all codes. ? total unadjusted error (tue): this error is defined as the difference between the actual transfer function and the ideal straight-line transfer function and includes all forms of error. 34.6.2.6 code jitter, non-monotonicity, and missing codes analog-to-digital converters are susceptible to three special forms of error. these are code jitter, non-monotonicity, and missing codes. code jitter is when, at certain points, a given input voltage converts to one of two values when sampled repeatedly. ideally, when the input voltage is infinitesimally smaller than the transition voltage, the converter yields the lower code (and vice-versa). however, even small amounts of system noise can cause the converter to be indeterminate (between two codes) for a range of input voltages around the transition voltage. application information k60 sub-family reference manual, rev. 6, nov 2011 852 freescale semiconductor, inc. this error may be reduced by repeatedly sampling the input and averaging the result. additionally, the techniques discussed in noise-induced errors reduces this error. non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a higher input voltage. missing codes are those values never converted for any input value. in 8-bit or 10-bit mode, the adc is guaranteed to be monotonic and have no missing codes. chapter 34 analog-to-digital converter (adc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 853 application information k60 sub-family reference manual, rev. 6, nov 2011 854 freescale semiconductor, inc. chapter 35 comparator (cmp) 35.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the comparator module (cmp) provides a circuit for comparing two analog input voltages. the comparator circuit is designed to operate across the full range of the supply voltage (rail to rail operation). the analog mux (anmux) provides a circuit for selecting an analog input signal from eight channels. one signal provided by the 6-bit dac. the mux circuit is designed to operate across the full range of the supply voltage. the 6-bit dac is 64-tap resistor ladder network which provides a selectable voltage reference for applications where voltage reference is needed. the 64-tap resistor ladder network divides the supply reference vin into 64 voltage level. a 6-bit digital signal input selects output voltage level, which varies from vin to vin/64. vin can be selected from two voltage sources, v in1 and v in2 . the 6-bit dac from a comparator is available as an on-chip internal signal only and is not available externally to a pin. 35.2 cmp features the cmp has the following features: ? operates over the entire supply range ? inputs may range from rail to rail ? programmable hysteresis control k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 855 ? selectable interrupt on rising edge, falling edge, or both rising or falling edges of comparator output ? selectable inversion on comparator output ? comparator output may be: ? sampled ? windowed (ideal for certain pwm zero-crossing-detection applications) ? digitally filtered ? filter can be bypassed ? can be clocked via external sample signal or scaled bus clock ? external hysteresis can be used at the same time that the output filter is used for internal functions. ? two software selectable performance levels: ? shorter propagation delay at the expense of higher power ? low power, with longer propagation delay ? support dma transfer ? a comparison event can be selected to trigger a dma transfer. ? functional in all modes of operation. ? the window and filter functions are not available in stop, vlps, lls and vllsx modes. 35.3 6-bit dac key features ? 6-bit resolution ? selectable supply reference source ? power down mode to conserve power when it is not being used ? output can be routed to internal comparator input 6-bit dac key features k60 sub-family reference manual, rev. 6, nov 2011 856 freescale semiconductor, inc. 35.4 anmux key features ? two 8 to 1 channel mux ? operates the entire supply range 35.5 cmp, dac, and anmux diagram the following figure shows the block diagram for the high speed comparator, digital to analog converter, and analog mux modules. chapter 35 comparator (cmp) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 857 vrsel vosel[5:0] mux 64-level psel[2:0] dac mux mux irq anmux msel[2:0] cmp cmp mux dac output dacen v in1 v in2 window and filter control cmpo reference input 0 reference input 1 reference input 2 reference input 3 reference input 4 reference input 5 reference input 6 inp inm sample input figure 35-1. cmp, dac and anmux blocks diagram 35.6 cmp block diagram the following figure shows the block diagram for the comparator module. cmp block diagram k60 sub-family reference manual, rev. 6, nov 2011 858 freescale semiconductor, inc. irq internal bus inp inm filter_cnt inv cout cout ope se cmpo to pad (to other soc functions)) couta 1 we 0 se cgmux cos filt_per + - filt_per bus clock cos ier/f cfr/f window/sample 1 0 en,pmode,hysctrl[1:0] interrupt control filter block window control polarity select clock prescaler divided bus clock cmpo figure 35-2. comparator module block diagram in the cmp block diagram: ? the window control block is bypassed when cr1[we] = 0 ? if cr1[we] = 1, the comparator output will be sampled on every bus clock when window=1 to generate couta. sampling does not occur when window = 0. ? the filter block is bypassed when not in use. ? the filter block acts as a simple sampler if the filter is bypassed and cr0[filter_cnt] is set to 0x01. ? the filter block filters based on multiple samples when the filter is bypassed and cr0[filter_cnt] is set greater than 0x01. ? if cr1[se] = 1, the external sample input is used as sampling clock ? if cr1[se] = 0, the divided bus clock is used as sampling clock chapter 35 comparator (cmp) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 859 ? if enabled, the filter block will incur up to 1 bus clock additional latency penalty on cout due to the fact that cout (which is crossing clock domain boundaries) must be resynchronized to the bus clock. ? cr1[we] and cr1[se] are mutually exclusive. 35.7 memory map/register definitions cmp memory map absolute address (hex) register name width (in bits) access reset value section/ page 4007_3000 cmp control register 0 (cmp0_cr0) 8 r/w 00h 35.7.1/ 861 4007_3001 cmp control register 1 (cmp0_cr1) 8 r/w 00h 35.7.2/ 862 4007_3002 cmp filter period register (cmp0_fpr) 8 r/w 00h 35.7.3/ 863 4007_3003 cmp status and control register (cmp0_scr) 8 r/w 00h 35.7.4/ 864 4007_3004 dac control register (cmp0_daccr) 8 r/w 00h 35.7.5/ 865 4007_3005 mux control register (cmp0_muxcr) 8 r/w 00h 35.7.6/ 866 4007_3008 cmp control register 0 (cmp1_cr0) 8 r/w 00h 35.7.1/ 861 4007_3009 cmp control register 1 (cmp1_cr1) 8 r/w 00h 35.7.2/ 862 4007_300a cmp filter period register (cmp1_fpr) 8 r/w 00h 35.7.3/ 863 4007_300b cmp status and control register (cmp1_scr) 8 r/w 00h 35.7.4/ 864 4007_300c dac control register (cmp1_daccr) 8 r/w 00h 35.7.5/ 865 4007_300d mux control register (cmp1_muxcr) 8 r/w 00h 35.7.6/ 866 4007_3010 cmp control register 0 (cmp2_cr0) 8 r/w 00h 35.7.1/ 861 4007_3011 cmp control register 1 (cmp2_cr1) 8 r/w 00h 35.7.2/ 862 table continues on the next page... memory mapregister definitions 60 sub-family reference manual, rev. 6, nov 2011 860 freescale semiconductor, inc. cmp memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4007_3012 cmp filter period register (cmp2_fpr) 8 r/w 00h 35.7.3/ 863 4007_3013 cmp status and control register (cmp2_scr) 8 r/w 00h 35.7.4/ 864 4007_3014 dac control register (cmp2_daccr) 8 r/w 00h 35.7.5/ 865 4007_3015 mux control register (cmp2_muxcr) 8 r/w 00h 35.7.6/ 866 35.7.1 cmp control register 0 (cmp x r resses: r is h ase h oset h r is h ase h oset h r is h ase h oset h it rea flr hr rite reset x r iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero flr filter ale ount hese its reresent the nuer o consecutie sales that ust aree rior to the coarator ouut ilter accetin a new outut state for inoration rearin ilter rorain an latency reerence the functional escrition filter is isale then ou is a loic ero this is not a leal state an is not recoene ou ou consecutie sale ust aree coarator outut is sily sale consecutie sales ust aree consecutie sales ust aree consecutie sales ust aree consecutie sales ust aree consecutie sales ust aree consecutie sales ust aree resere his reaonly iel is resere an always has the alue ero table continues on the next page... chapter comparator cmp 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 861 cmp x r iel escritions continue fiel escrition resere his reaonly iel is resere an always has the alue ero hr oarator har loc hysteresis control eines the roraale hysteresis leel he hysteresis alues associate with each leel is eice seciic ee the eices ata sheet or the exact alues leel leel leel leel ontrol reister x r resses: r is h ase h oset h r is h ase h oset h r is h ase h oset h it rea o o o rite reset x r iel escritions fiel escrition ale nale t any ien tie either or can e set a write to this reister attets to set oth then is set an is cleare howeer aoi writin ones to oth it locations ecause this case is resere an ay chane in uture ileentations alin oe not selecte alin oe selecte inowin nale t any ien tie either or can e set a write to this reister attets to set oth then is set an is cleare howeer aoi writin ones to oth it locations ecause this case is resere an ay chane in uture ileentations inowin oe not selecte inowin oe selecte resere his reaonly iel is resere an always has the alue ero o ower oe elect table continues on the next page... memory mapregister definitions 60 sub-family reference manual, rev. 6, nov 2011 862 freescale semiconductor, inc. cmp x r iel escritions continue fiel escrition reer to the eice ata sheets electrical seciications tale or etails on the iact o the oes elow low ee l coarison oe selecte n this oe has slower outut roaation elay an lower current consution hih ee h coarison oe selecte n this oe has aster outut roaation elay an hiher current consution oarator r his it allows you to select the olarity o the analo coarator unction t is also rien to the ou outut on oth the eice in an as rou when ro oes not inert the coarator outut nerts the coarator outut o oarator outut elect et o to equal ou iltere coarator outut et o to equal ou uniltere coarator outut o oarator outut in nale he coarator outut o is not aailale on the associate o outut in he coarator outut o is aailale on the associate o outut in oarator oule nale he it enales the nalo oarator oule hen the oule is not enale it reains in the o state an consues no ower hen you select the sae inut ro analo ux to the ositie an neatie ort the coarator is isale autoatically o: his it ust e set in the sae tie with or ater the ux enales ur an ur are set an shoul e nelecte in the sae tie or eore the ux enales nalo oarator isale nalo oarator enale filter erio reister x fr resses: fr is h ase h oset h fr is h ase h oset h fr is h ase h oset h it rea flr rite reset hater oarator ufaily reerence anual re o freescale eiconuctor nc cmp x fr iel escritions fiel escrition flr filter ale erio hen r is equal to ero this iel seciies the salin erio in us cloc cycles o the coarator outut ilter ettin flr to x isales the ilter filter rorain an latency etails aear in the functional escrition his iel has no eect when r is equal to one n that case the external l sinal is use to eterine the salin erio tatus an ontrol reister x r resses: r is h ase h oset h r is h ase h oset h r is h ase h oset h it rea l r f fr ff ou rite wc wc reset x r iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero nale ontrol he it enales the transer triere ro the oule hen this it is set a request is asserte when the fr or ff it is set isale enale l to oe eleel nterrut ontrol his it controls whether the fr an ff its are ee sensitie or leel sensitie in to oe o: his it shoul always e rorae to to ee the coarator worin an to wae u the u frff are leel sensitie in to oe fr will e asserte when ou is hih ff will e asserte when ou is low frff are ee sensitie in to oe n actie lowtohih transition ust e seen on ou to assert fr an an actie hihtolow transition ust e seen on ou to assert ff r oarator nterrut nale risin he r it enales the fr interrut ro the hen this it is set an interrut will e asserte when the fr it is set table continues on the next page... memory mapregister definitions 60 sub-family reference manual, rev. 6, nov 2011 864 freescale semiconductor, inc. cmp x r iel escritions continue fiel escrition nterrut isale nterrut enale f oarator nterrut nale fallin he f it enales the ff interrut ro the hen this it is set an interrut will e asserte when the ff it is set nterrut isale nterrut enale fr nalo oarator fla risin urin noral oeration the fr it is set when a risin ee on ou has een etecte he fr it is cleare y writin a loic one to the it urin to oes fr can e rorae as either ee or leel sensitie ia the l it o: e etection urin to oe is only suorte on lators that allow eriherals to e cloce urin to oes the fr la is actie urin to oe then l ust e set to or cases where it is not receiin a cloc urin to oe risin ee on ou has not een etecte risin ee on ou has occurre ff nalo oarator fla fallin urin noral oeration the ff it is set when a allin ee on ou has een etecte he ff it is cleare y writin a loic one to the it urin to oes ff can e rorae as either ee or leel sensitie ia the l it o: e etection urin to oe is only suorte on lators that allow eriherals to e cloce urin to oes the ff la is actie urin to oe then l ust e set to or cases where it is not receiin a cloc urin to oe fallin ee on ou has not een etecte fallin ee on ou has occurre ou nalo oarator outut reain the ou it will return the current alue o the analo coarator outut he reister it is reset to ero an will rea as r when the nalo oarator oule is isale r rites to this it are inore ontrol reister x r resses: r is h ase h oset h r is h ase h oset h r is h ase h oset h it rea rl ol rite reset hater oarator ufaily reerence anual re o freescale eiconuctor nc cmp x r iel escritions fiel escrition nale his it is use to enale the hen the is isale it is owere own to consere ower is isale is enale rl uly oltae reerence ource elect in is selecte as resistor laer networ suly reerence in in is selecte as resistor laer networ suly reerence in ol outut oltae elect his it selects an outut oltae ro one o istinct leels daco = (vin/64) * (vosel[5:0] + 1) , so the daco range is from vin/64 to vin. 35.7.6 mux control register (cmp x ur pen and men bits should be enabled or disabled together with cr1[en] bit. addresses: cmp0_muxcr is 4007_3000h base + 5h offset = 4007_3005h cmp1_muxcr is 4007_3008h base + 5h offset = 4007_300dh cmp2_muxcr is 4007_3010h base + 5h offset = 4007_3015h bit 7 6 5 4 3 2 1 0 read pen men psel msel write reset 0 0 0 0 0 0 0 0 cmp x ur iel escritions fiel escrition u nale his it is use to enale ositie u hen the u is isale the u outut is in a hih ieance state hen sotware selects the sae inut or lus an inus inuts o the coarator oth u an u are isale autoatically u is isale u is enale u nale his it is use to enale neatie u hen the u is isale the u outut is in a hih ieance state hen sotware selects the sae inut or lus an inus inuts o the coarator oth u an u are isale autoatically u is isale u is enale table continues on the next page... memory mapregister definitions 60 sub-family reference manual, rev. 6, nov 2011 866 freescale semiconductor, inc. cmp x ur iel escritions continue fiel escrition l lus nut u ontrol eterines which inut is selecte or the lus inut o the coarator for x inuts reer to an u locs iara o: hen an inaroriate oeration selects the sae inut or oth ues the coarator autoatically shuts own to reent itsel ro ecoin a noise enerator l inus nut u ontrol eterines which inut is selecte or the inus inut o the coarator for x inuts reer to an u locs iara o: hen an inaroriate oeration selects the sae inut or oth ues the coarator autoatically shuts own to reent itsel ro ecoin a noise enerator functional escrition the comparator can be used to compare two analog input voltages applied to inp and inm. the analog comparator output (cmpo) is high when the non-inverting input is greater than the inverting input, and is low when the non-inverting input is less than the inverting input. this signal can be selectively inverted by setting cr1[inv] = 1. the scr[ier], scr[ief], and scr[smelb] bits are used to select the condition which will cause the comparator module to assert an interrupt to the processor. scr[cff] is set on a falling edge and scr[cfr] is set on rising edge of the comparator output. the (optionally filtered) comparator output can be read directly through the scr[cout] bit. chapter 35 comparator (cmp) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 867 35.8.1 cmp functional modes there are three main sub-blocks to the comparator module: the comparator itself, the window function and the filter function. the filter, cr0[filter_cnt] can be clocked from an internally or external clock source. additionally, the filter is programmable with respect to how many samples must agree before a change on the output is registered. in the simplest case, only 1 sample must agree. in this case, the filter acts as a simple sampler. the external sample input is enabled using cr1[se]. when set, the output of the comparator is sampled only on rising edges of the sample input. the "windowing mode" is enabled by setting cr1[we]. when set, the comparator output is sampled only when the window input signal is equal to one. this feature can be used to ignore the comparator output during time periods in which the input voltages are not valid. this is especially useful when implementing zero-crossing-detection for certain pwm applications. the comparator filter and sampling features can be combined as shown in the following table. individual modes are discussed below. table 35-29. comparator sample/filter controls mode # cr1[en] cr1[we] cr1[se] cr0[filter_c nt] fpr[filt_per] operation 1 0 x x x x disabled refer to the disabled mode (# 1) . 2a 1 0 0 0x00 x continuous mode refer to the continuous mode (#s 2a & 2b) . 2b 1 0 0 x 0x00 3a 1 0 1 0x01 x sampled, non-filtered mode refer to the sampled, non-filtered mode (#s 3a & 3b) . 3b 1 0 0 0x01 > 0x00 4a 1 0 1 > 0x01 x sampled, filtered mode refer to the sampled, filtered mode (#s 4a & 4b) . 4b 1 0 0 > 0x01 > 0x00 5a 1 1 0 0x00 x windowed mode comparator output is sampled on every rising bus clock edge when sample=1 to generate couta refer to the windowed mode (#s 5a & 5b) . 5b 1 1 0 x 0x00 table continues on the next page... cmp functional description 60 sub-family reference manual, rev. 6, nov 2011 868 freescale semiconductor, inc. table 35-29. comparator sample/filter controls (continued) mode # cr1[en] cr1[we] cr1[se] cr0[filter_c nt] fpr[filt_per] operation 6 1 1 0 0x01 0x01 - 0xff windowed/resampled mode comparator output is sampled on every rising bus clock edge when sample=1 to generate couta, which is then resampled on an interval determined by filt_per to generate cout. refer to the windowed/resampled mode (# 6) . 7 1 1 0 > 0x01 0x01 - 0xff windowed/filtered mode comparator output is sampled on every rising bus clock edge when sample=1 to generate couta, which is then resampled and filtered to generate cout. refer to the windowed/filtered mode (#7) . all other combinations of cr1[en], cr1[we], cr1[se], cr0[filter_cnt], and fpr[filt_per] are illegal. for cases where a comparator is used to drive a fault input (for example, for a motor- control module such as ftm), it should generally be configured to operate in continuous mode, so that an external fault can immediately pass through the comparator to the target fault circuitry. note filtering and sampling settings should be changed only after setting cr1[se]=0 and cr0[filter_cnt]=0x00. this has the effect of resetting the filter to a known state. 35.8.1.1 disabled mode (# 1) in disabled mode, the analog comparator is non-functional and consumes no power. the output of the analog comparator block (cmpo) is zero in this mode. chapter 35 comparator (cmp) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 869 35.8.1.2 continuous mode (#s 2a & 2b) irq internal bus inp inm filter_cnt inv cout cout ope se cmpo to pad (to other soc functions)) couta 1 we 0 se cgmux cos filt_per 0 + - filt_per cos ier/f cfr/f window/sample 1 0 en,pmode,hystctr[1:0] polarity select window control filter block interrupt control divided bus clock clock prescaler cmpo bus clock figure 35-27. comparator operation in continuous mode note refer to the chip configuration section for the source of sample/ window input. the analog comparator block is powered and active. cmpo may be optionally inverted, but is not subject to external sampling or filtering. both window control and filter blocks are completely bypassed. scr[cout] is updated continuously. the path from comparator inputs pins to output pin is operating in combinational (unclocked) mode. cout and couta are identical. for control configurations which result in disabling the filter block, refer to filter block bypass logic diagram. cmp functional description k60 sub-family reference manual, rev. 6, nov 2011 870 freescale semiconductor, inc. 35.8.1.3 sampled, non-filtered mode (#s 3a & 3b) + - irq internal bus inp inm filter_cnt inv cout cout ope se cmpo to pad (to other soc functions) couta 1 we 0 se=1 cgmux cos filt_per 1 0 + - filt_per cos 0x01 ier/f cfr/f window/sample 1 0 en,pmode,hystctr[1:0] polarity select window control filter block interrupt control clock prescaler divided bus clock cmpo bus clock figure 35-28. sampled, non-filtered (# 3a): sampling point externally driven in sampled, non-filtered mode, the analog comparator block is powered and active. the path from analog inputs to couta is combinational (unclocked). windowing control is completely bypassed. couta is sampled whenever a rising edge is detected on the filter block clock input. the only difference in operation between sampled, non-filtered (# 3a) and sampled, non-filtered (# 3b) is in how the clock to the filter block is derived. in #3a, the clock to filter block is externally derived while in #3b, the clock to filter block is internally derived. the comparator filter has no other function than sample/hold of the comparator output in this mode (# 3b). chapter 35 comparator (cmp) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 871 irq internal bus inp inm filter_cnt inv cout cout ope se cmpo to pad (to other soc functions)) couta 1 we 0 se=0 cgmux cos filt_per 0 0 + - filt_per cos 0x01 ier/f cfr/f window/sample 1 0 en,pmode,hystctr[1:0] interrupt control filter block window control polarity select clock prescaler divided bus clock cmpo bus clock figure 35-29. sampled, non-filtered (# 3b): sampling interval internally derived 35.8.1.4 sampled, filtered mode (#s 4a & 4b) in sampled, filtered mode, the analog comparator block is powered and active. the path from analog inputs to couta is combinational (unclocked). windowing control is completely bypassed. couta is sampled whenever a rising edge is detected on the filter block clock input. the only difference in operation between sampled, non-filtered (# 3a) and sampled, filtered (# 4a) is that cr0[filter_cnt] is now greater than 1, which activates filter operation. cmp functional description k60 sub-family reference manual, rev. 6, nov 2011 872 freescale semiconductor, inc. + - irq internal bus inp inm filter_cnt inv cout cout ope se cmpo to pad (to other soc functions) couta 1 we 0 se=1 cgmux cos filt_per 1 0 + - filt_per bus clock cos > ier/f cfr/f window/sample 1 0 en, pmode, hystctr[1:0] polarity select window control filter block interrupt control clock prescaler divided bus clock cmpo 0x01 figure 35-30. sampled, filtered (# 4a): sampling point externally driven chapter 35 comparator (cmp) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 873 + - irq internal bus inp inm filter_cnt inv cout cout ope se cmpo to pad (to other soc functions)) couta 0 1 we 1 0 se=0 cgmux cos filt_per 1 0 + - filt_per bus clock cos > ier/f cfr/f window/sample en, pmode,hystctr[1:0 ] polarity select window control filter block interrupt control clock prescaler divided bus clock cmpo 0x01 figure 35-31. sampled, filtered (# 4b): sampling point internally derived the only difference in operation between sampled, non-filtered (# 3b) and sampled, filtered (# 4b) is that cr0[filter_cnt] is now greater than 1, which activates filter operation. 35.8.1.5 windowed mode (#s 5a & 5b) the following figure illustrates comparator operation in the windowed mode, ignoring latency of the analog comparator, polarity select and window control block. it also assumes that the polarity select is set to "non-inverting". note that the analog comparator output is passed to couta only when the window signal is high. in actual operation, couta may lag the analog inputs by up to one bus clock cycle plus the combinational path delay through the comparator and polarity select logic. cmp functional description k60 sub-family reference manual, rev. 6, nov 2011 874 freescale semiconductor, inc. wi ndow couta cmpo minus input plus input figure 35-32. windowed mode operation + - irq internal bus en, pmode,hysctr[1:0] inp inm filter_cnt inv cout cout ope se cmpo to pad (to other soc functions)) couta 0 1 we 1 0 se=0 cgmux cos filt_per 0 + - filt_per bus clock cos 0x01 ier/f cfr/f window/sample polarity select window control filter block interrupt control divided bus clock clock prescaler cmpo figure 35-33. windowed mode for control configurations which result in disabling the filter block, refer to filter block bypass logic diagram. chapter 35 comparator (cmp) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 875 when any windowed mode is active, couta is clocked by the bus clock whenever window = 1. the last latched value is held when window = 0. 35.8.1.6 windowed/resampled mode (# 6) the following figure uses the same input stimulus shown in figure 35-32 , and adds resampling of couta to generate cout. samples are taken at the time points indicated by the arrows. again, prop delays and latency is ignored for clarity's sake. this example was generated solely to demonstrate operation of the comparator in windowing / resampled mode, and does not reflect any specific application. depending upon the sampling rate and window placement, cout may not see zero-crossing events detected by the analog comparator. sampling period and/or window placement must be carefully considered for a given application. wi ndow couta cout cmpo minus input plus input figure 35-34. windowed / resampled mode operation this mode of operation results in an unfiltered string of comparator samples where the interval between the samples is determined by fpr[filt_per] and the bus clock rate. configuration for this mode is virtually identical to that for the windowed/filtered mode shown in the next section. the only difference is that the value of cr0[filter_cnt] must be exactly one. cmp functional description k60 sub-family reference manual, rev. 6, nov 2011 876 freescale semiconductor, inc. 35.8.1.7 windowed/filtered mode (#7) this is the most complex mode of operation for the comparator block, as it utilizes both windowing and filtering features. it also has the highest latency of any of the modes. this can be approximated: up to 1 bus clock synchronization in the window function + ((cr0[filter_cnt] x fpr[filt_per]) + 1) x bus clock for the filter function. when any windowed mode is active, couta is clocked by the bus clock whenever window = 1. the last latched value is held when window = 0. + - irq internal bus en, pmode,hysctr[1:0] inp inm filter_cnt inv cout cout ope se cmpo to pad (to other soc functions)) couta 0 1 we 1 0 se=0 cgmux cos filt_per 01 + - filt_per bus clock cos > ier/f cfr/f window/sample polarity select window control filter block interrupt control divided bus clock clock prescaler cmpo 0x01 figure 35-35. windowed/filtered mode 35.8.2 power modes 35.8.2.1 wait mode operation during wait and vlpw modes and if enabled, the cmp continues to operate normally. also, if enabled, a cmp interrupt can wake the mcu. chapter 35 comparator (cmp) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 877 35.8.2.2 stop mode operation subject to platform-specific clock restrictions, the mcu is brought out of stop when a compare event occurs and the corresponding interrupt is enabled. similarly, if cr1[ope] is enabled, the comparator output operates as in the normal operating mode and comparator output is placed onto the external pin. in stop modes, the comparator can be operational in both high speed (hs) comparison mode (cr1[pmode] = 1) and low speed (ls) comparison mode (cr1[pmode] = 0), but it is recommended to use the low speed mode to minimize power consumption. if stop is exited with a reset, all comparator registers are put into their reset state. 35.8.2.3 low-leakage mode operation when the chip is in low-leakage modes, the cmp module is partially functional and is limited to low speed mode (regardless of the cr1[pmode] bit's setting). windowed, sampled, and filtered modes are not supported. the cmp output pin is latched and does not reflect the compare output state. the positive- and negative-input voltage can be from external pins or the dac output. the mcu can be brought out of the low-leakage mode if a compare event occurs and the cmp interrupt is enabled. after wakeup from low-leakage modes, the cmp module is in the reset state except for the scr[cff] and scr[cfr] flags. 35.8.3 startup and operation a typical startup sequence is as follows. the time required to stabilize cout will be the power-on delay of the comparators plus the largest propagation delay from a selected analog source through the analog comparator, windowing function and filter. power on delay of the comparators are available from data sheets. the windowing function has a maximum of 1 bus clock period delay. filter delay is specified in low pass filter . during operation, the propagation delay of the selected data paths must always be considered. it can take many bus clock cycles for cout and the cfr/cff status bits to reflect an input change or a configuration change to one of the components involved in the data path. when programmed for filtering modes, cout will initially be equal to zero until sufficient clock cycles have elapsed to fill all stages of the filter. this occurs even if couta is at a logic one. cmp functional description k60 sub-family reference manual, rev. 6, nov 2011 878 freescale semiconductor, inc. 35.8.4 low pass filter the low-pass filter operates on the unfiltered and unsynchronized and optionally inverted comparator output couta and generates the filtered and synchronized output cout. both couta and cout can be configured as module outputs and are used for different purposes within the system. synchronization and edge detection are always used to determine status register bit values. they also apply to cout for all sampling and windowed modes. filtering can be performed using an internal timebase defined by fpr[filt_per], or using an external sample input to determine sample time. the need for digital filtering and the amount of filtering is dependent on user requirements. filtering can become more useful in the absence of an external hysteresis circuit. without external hysteresis, high frequency oscillations can be generated at couta when the selected inm and inp input voltages differ by less than the offset voltage of the differential comparator. 35.8.4.1 enabling filter modes filter modes are enabled by setting cr0[filter_cnt] greater than 0x01 and (setting fpr[filt_per] to a non-zero value or setting cr1[se]=1). if using the divided bus clock to drive the filter, it will take samples of couta every fpr[filt_per] bus clock cycles. the filter output will be at logic zero when first initalized, and will subsequently change when cr0[filter_cnt] consecutive samples all agree that the output value has changed. said another way, scr[cout] will be zero for some initial period, even when couta is at logic one. setting both cr1[se] and fpr[filt_per] to 0 disables the filter and eliminates switching current associated with the filtering process. note always switch to this setting prior to making any changes in filter parameters. this resets the filter to a known state. switching cr0[filter_cnt] on the fly without this intermediate step can result in unexpected behavior. chapter 35 comparator (cmp) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 879 if cr1[se]=1, the filter takes samples of couta on each positive transition of the sample input. the output state of the filter changes when cr0[filter_cnt] consecutive samples all agree that the output value has changed. 35.8.4.2 latency issues the fpr[filt_per] value (or sample period) should be set such that the sampling period is just larger than the period of the expected noise. this way a noise spike will only corrupt one sample. the cr0[filter_cnt] value should be chosen to reduce the probability of noisy samples causing an incorrect transition to be recognized. the probability of an incorrect transition is defined as the probability of an incorrect sample raised to the cr0[filter_cnt] power. the following table summarizes maximum latency values for the various modes of operation in the absence of noise . filtering latency is restarted each time an actual output transition is masked by noise. the values of fpr[filt_per] (or sample period) and cr0[filter_cnt] must also be traded off against the desire for minimal latency in recognizing actual comparator output transitions. the probability of detecting an actual output change within the nominal latency is the probability of a correct sample raised to the cr0[filter_cnt] power. table 35-30. comparator sample/filter maximum latencies mode # cr1[ en] cr1[ we] cr1[ se] cr0[filter _cnt] fpr[filt_p er] operation maximum latency 1 1 0 x x x x disabled n/a 2a 1 0 0 0x00 x continuous mode t pd 2b 1 0 0 x 0x00 3a 1 0 1 0x01 x sampled, non-filtered mode t pd + t sample + t per 3b 1 0 0 0x01 > 0x00 t pd + (fpr[filt_per] x t per ) + t per 4a 1 0 1 > 0x01 x sampled, filtered mode t pd + (cr0[filter_cnt] x t sample ) + t per 4b 1 0 0 > 0x01 > 0x00 t pd + (cr0[filter_cnt] x fpr[filt_per] x t per ) + t per 5a 1 1 0 0x00 x windowed mode t pd + t per 5b 1 1 0 x 0x00 t pd + t per 6 1 1 0 0x01 0x01 - 0xff windowed / resampled mode t pd + (fpr[filt_per] x t per ) + 2t per table continues on the next page... cmp functional description 60 sub-family reference manual, rev. 6, nov 2011 880 freescale semiconductor, inc. table 35-30. comparator sample/filter maximum latencies (continued) mode # cr1[ en] cr1[ we] cr1[ se] cr0[filter _cnt] fpr[filt_p er] operation maximum latency 1 7 1 1 0 > 0x01 0x01 - 0xff windowed / filtered mode t pd + (cr0[filter_cnt] x fpr[filt_per] x t per ) + 2t per 1. t pd represents the intrinsic delay of the analog component plus the polarity select logic. t sample is the clock period of the external sample clock. t per is the period of the bus clock. 35.9 cmp interrupts the cmp module is capable of generating an interrupt on either the rising or falling edge of the comparator output (or both). the interrupt request is asserted when both scr[ier] bit and scr[cfr] are set. it is also asserted when both scr[ief] bit and scr[cff] are set. the interrupt is de-asserted by clearing either scr[ier] or scr[cfr] for a rising edge interrupt, or scr[ief] and scr[cff] for a falling edge interrupt. 35.10 cmp dma support normally, the cmp generates a cpu interrupt if there is a change on the cout. when dma support (set scr[dmaen]) enables and the interrupt enables (set scr[ier] or scr[ief] or both), the corresponding change on cout forces a dma transfer request rather than a cpu interrupt instead. when the dma has completed the transfer, it sends a dma_done signal that de-asserts the dma_request and clears the flag to allow a subsequent change on comparator output to occur and force another dma request. 35.11 digital to analog converter block diagram the following figure shows the block diagram of the dac module. it contains a 64-tap resistor ladder network and a 64-to-1 multiplexer, which selects an output voltage from one of 64 distinct levels that outputs from daco. it is controlled through dac control register (daccr). its supply reference source can be selected from two sources v in1 and v in2 . the module can be powered down (disabled) when it is not used. when in disable mode, daco is connected to the analog ground. chapter 35 comparator (cmp) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 881 vosel[5:0] daco mux mux dacen vin vrsel v in1 v in2 figure 35-36. 6-bit dac block diagram 35.12 dac functional description this section provides dac functional description. 35.12.1 voltage reference source select ? v in1 should be used to connect to the primary voltage source as supply reference of 64 tap resistor ladder ? v in2 should be used to connect to alternate voltage source (or primary source if alternate voltage source is not available) 35.13 dac resets this module has a single reset input, corresponding to the chip-wide peripheral reset. 35.14 dac clocks this module has a single clock input, the bus clock. dac functional description k60 sub-family reference manual, rev. 6, nov 2011 882 freescale semiconductor, inc. 35.15 dac interrupts this module has no interrupts. chapter 35 comparator (cmp) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 883 dac interrupts k60 sub-family reference manual, rev. 6, nov 2011 884 freescale semiconductor, inc. chapter 36 12-bit digital-to-analog converter (dac) 36.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the 12-bit digital-to-analog converter (dac) is a low power general purpose dac. the output of this dac can be placed on an external pin or set as one of the inputs to the analog comparator, op-amps, adc, or other peripherals. 36.2 features the dac module features include: ? on-chip programmable reference generator output (voltage output from 1/4096 vin to vin, step is 1/4096 vin) ? vin can be selected from two reference sources ? static operation in normal stop mode ? 16-word data buffer supported with configurable watermark and multiple operation modes ? dma support 36.3 block diagram the block diagram of the dac module is as follows: k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 885 - + mux 4096-level dacen dacdat[11:0] mux dacref_2 dacrfs v vout vdd amp buffer 12 dacbfmd dacswtrg dacbfen dacbfup dacbfwm dacbfrp ardware trigger dacbfwmf dacbwien dacbfrptf dacbtien dacbfrpbf dacbbien or dacinterrupt dactrgse buffer lpen dacrfs dacref1 v in v o data figure 6-1 dac block diagram 64 memory map/register definition the dac has registers to control analog comparator and programmable voltage divider to perform the digital-to-analog functions. the address of a register is the sum of a base address and an address offset. the base address is defined at the chip level. the address offset is defined at the module level. memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 886 freescale semiconductor, inc. dac memory map absolute address (hex) register name width (in bits) access reset value section/ page 400c_c000 dac data low register (dac0_dat0l) 8 r/w 00h 36.4.1/ 888 400c_c001 dac data high register (dac0_dat0h) 8 r/w 00h 36.4.2/ 889 400c_c002 dac data low register (dac0_dat1l) 8 r/w 00h 36.4.1/ 888 400c_c003 dac data high register (dac0_dat1h) 8 r/w 00h 36.4.2/ 889 400c_c004 dac data low register (dac0_dat2l) 8 r/w 00h 36.4.1/ 888 400c_c005 dac data high register (dac0_dat2h) 8 r/w 00h 36.4.2/ 889 400c_c006 dac data low register (dac0_dat3l) 8 r/w 00h 36.4.1/ 888 400c_c007 dac data high register (dac0_dat3h) 8 r/w 00h 36.4.2/ 889 400c_c008 dac data low register (dac0_dat4l) 8 r/w 00h 36.4.1/ 888 400c_c009 dac data high register (dac0_dat4h) 8 r/w 00h 36.4.2/ 889 400c_c00a dac data low register (dac0_dat5l) 8 r/w 00h 36.4.1/ 888 400c_c00b dac data high register (dac0_dat5h) 8 r/w 00h 36.4.2/ 889 400c_c00c dac data low register (dac0_dat6l) 8 r/w 00h 36.4.1/ 888 400c_c00d dac data high register (dac0_dat6h) 8 r/w 00h 36.4.2/ 889 400c_c00e dac data low register (dac0_dat7l) 8 r/w 00h 36.4.1/ 888 400c_c00f dac data high register (dac0_dat7h) 8 r/w 00h 36.4.2/ 889 400c_c010 dac data low register (dac0_dat8l) 8 r/w 00h 36.4.1/ 888 400c_c011 dac data high register (dac0_dat8h) 8 r/w 00h 36.4.2/ 889 400c_c012 dac data low register (dac0_dat9l) 8 r/w 00h 36.4.1/ 888 400c_c013 dac data high register (dac0_dat9h) 8 r/w 00h 36.4.2/ 889 table continues on the next page... chapter 6 12-bit digital-to-analog converter dac 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 887 dac memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 400c_c014 dac data low register (dac0_dat10l) 8 r/w 00h 36.4.1/ 888 400c_c015 dac data high register (dac0_dat10h) 8 r/w 00h 36.4.2/ 889 400c_c016 dac data low register (dac0_dat11l) 8 r/w 00h 36.4.1/ 888 400c_c017 dac data high register (dac0_dat11h) 8 r/w 00h 36.4.2/ 889 400c_c018 dac data low register (dac0_dat12l) 8 r/w 00h 36.4.1/ 888 400c_c019 dac data high register (dac0_dat12h) 8 r/w 00h 36.4.2/ 889 400c_c01a dac data low register (dac0_dat13l) 8 r/w 00h 36.4.1/ 888 400c_c01b dac data high register (dac0_dat13h) 8 r/w 00h 36.4.2/ 889 400c_c01c dac data low register (dac0_dat14l) 8 r/w 00h 36.4.1/ 888 400c_c01d dac data high register (dac0_dat14h) 8 r/w 00h 36.4.2/ 889 400c_c01e dac data low register (dac0_dat15l) 8 r/w 00h 36.4.1/ 888 400c_c01f dac data high register (dac0_dat15h) 8 r/w 00h 36.4.2/ 889 400c_c020 dac status register (dac0_sr) 8 r 02h 36.4.3/ 889 400c_c021 dac control register (dac0_c0) 8 r/w 00h 36.4.4/ 890 400c_c022 dac control register 1 (dac0_c1) 8 r/w 00h 36.4.5/ 891 400c_c023 dac control register 2 (dac0_c2) 8 r/w 0fh 36.4.6/ 892 36.4.1 dac data low register (dac x l resses: h ase h oset n , where n 0d to 1d bit 7 6 4 2 1 0 read data70 write reset 0 0 0 0 0 0 0 0 memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 888 freescale semiconductor, inc. dac x n l iel escritions fiel escrition : hen the uer is not enale : controls the outut oltae ase on the ollowin orula out in : hen the uer is enale is ae to the wor uer ata hih reister x h resses: h ase h oset n , where n 0d to 1d bit 7 6 4 2 1 0 read 0 data118 write reset 0 0 0 0 0 0 0 0 dac x n h iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero : hen the uer is not enale : controls the outut oltae ase on the ollowin orula out in : hen the uer is enale : is ae to the wor uer tatus reister x r if dma is enabled, the flags can be cleared automatically by dma when the dma request is done. write zero to a bit to clear it. writing one has no effect. after reset dacbfrptf is set and can be cleared by software, if needed. the flags are set only when the data buffer status is changed. addresses: dac0_sr is 400c_c000h base + 20h offset = 400c_c020h bit 7 6 5 4 3 2 1 0 read 0 dacbfwmf dacbfrptf dacbfrpbf write reset 0 0 0 0 0 0 1 0 dac x r iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero resere table continues on the next page... chapter 6 12-bit digital-to-analog converter dac 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 88 dac x r iel escritions continue fiel escrition ff uer waterar la he uer rea ointer has not reache the waterar leel he uer rea ointer has reache the waterar leel frf uer rea ointer to osition la he uer rea ointer is not ero he uer rea ointer is ero frf uer rea ointer otto osition la he uer rea ointer is not equal to the fu he uer rea ointer is equal to the fu ontrol reister x resses: is h ase h oset h it rea rf rl l rite r reset x iel escritions fiel escrition enale he it starts the roraale reerence enerator oeration he syste is isale he syste is enale rf reerence elect he selets rf as the reerence oltae he selets rf as the reerence oltae rl trier select he harware trier is selecte he sotware trier is selecte r sotware trier ctie hih his is a writeonly it rea it always e sotware trier is selecte an uer enale write to this it will aance the uer rea ointer once he sot trier is not ali he sot trier is ali table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 80 freescale semiconductor, inc. dac x iel escritions continue fiel escrition l low ower control reer to the eice ata sheets it electrical characteristics or etails on the iact o the oes elow hih ower oe low ower oe uer waterar interrut enale he uer waterar interrut is isale he uer waterar interrut is enale uer rea ointer to la interrut enale he uer rea ointer to la interrut is isale he uer rea ointer to la interrut is enale uer rea ointer otto la interrut enale he uer rea ointer otto la interrut is isale he uer rea ointer otto la interrut is enale ontrol reister x resses: is h ase h oset h it rea f f f rite reset x iel escritions fiel escrition enale select isale enale hen enale request will e enerate y oriinal interruts n interruts will not e resente on this oule at the sae tie resere his reaonly iel is resere an always has the alue ero f uer waterar select his itiel controls when the uer waterar la will e set hen the uer rea ointer reaches the wor eine y this itiel ro to wors away ro the uer liit u the uer waterar la will e set his allows user coniuration o the waterar interrut wor table continues on the next page... chapter 6 12-bit digital-to-analog converter dac 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 81 dac x iel escritions continue fiel escrition wors wors wors f uer wor oe select oral oe win oe oneie can oe resere f uer enale uer rea ointer isale he conerte ata is always the irst wor o the uer uer rea ointer enale he conerte ata is the wor that the rea ointer oints to t eans conerte ata can e ro any wor o the uer ontrol reister x resses: is h ase h oset h it rea fr fu rite reset x iel escritions fiel escrition fr uer rea ointer hese its ee the current alue o the uer rea ointer fu uer uer liit hese its select the uers uer liit he uer rea ointer cannot excee it functional escrition the 12-bit dac module can select one of the two reference inputs dacref_1 and dacref_2 as the dac reference voltage (v in ) by dacrfs bit of c0 register. refer to the module introduction for information on the source for dacref_1 and dacref_2. when the dac is enabled, it converts the data in dacdat0[11:0] or the data from the dac data buffer to a stepped analog output voltage. the output voltage range is from v in /4096 to v in , and the step is v in /4096. functional description k60 sub-family reference manual, rev. 6, nov 2011 892 freescale semiconductor, inc. 36.5.1 dac data buffer operation when the dac is enabled and the buffer is not enabled, the dac module always converts the data in dat0 to analog output voltage. when both the dac and the buffer are enabled, the dac converts the data in the data buffer to analog output voltage. the data buffer read pointer advances to the next word in the event the hardware trigger or the software trigger occurs. refer to the pdb module interconnections section in chip configuration chapter for the hardware trigger connection. the data buffer can be configured to operate in normal mode, swing mode or one-time scan mode. when the buffer operation is switched from one mode to another, the read pointer does not change. the read pointer can be set to any value between "0" and dacbfup by writing dacbfrp in c2 register. 36.5.1.1 dac data buffer interrupts there are several interrupts and associated flags that can be configured for the dac buffer. the dac read pointer bottom position flag is set when the dac buffer read pointer reaches the dac buffer upper limit. ( dacbfrp = dacbfup). the dac read pointer top position flag is set when the dac read pointer is equal to the start position, 0. finally, the dac buffer watermark flag is set when the dac buffer read pointer has reached the position defined by the dac watermark select bit field. the dac watermark select (dacbfwm) can be used to generate an interrupt when the dac buffer read pointer is between 1 to 4 words from the dac buffer upper limit. 36.5.1.2 buffer normal mode this is the default mode. the buffer works as a circular buffer. the read pointer increases by one, every time when the trigger occurs. when the read pointer reaches the upper limit, it goes to the zero directly in the next trigger event. 36.5.1.3 buffer swing mode this mode is similar to the normal mode. but when the read pointer reaches the upper limit, it does not go to the zero. it will descend by one in the next trigger events until zero is reached. chapter 36 12-bit digital-to-analog converter (dac) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 893 36.5.1.4 buffer one-time scan mode the read pointer increases by one every time when the trigger occurs. when it reaches the upper limit, it stops at there. if read pointer is reset to the address other than the upper limit, it will increase to the upper address and stop at there again. note if the software set the read pointer to the upper limit, the read pointer will not advance in this mode. 36.5.2 dma operation when dma is enabled, interrupt requests are not generated. dma requests are generated instead. dma done signal clears the dma request. the status register flags are still set and are cleared automatically when the dma completes. 36.5.3 resets during reset the dac is configured in the default mode. dac is disabled. 36.5.4 low power mode operation this section describes the wait mode and the stop mode operation of the dac module. 36.5.4.1 wait mode operation in wait mode, the dac will operate normally if enabled. 36.5.4.2 stop mode operation the dac continues to operate in normal stop mode if enabled, the output voltage will hold the value before stop. in low power stop modes, the dac is fully shut-down. functional description k60 sub-family reference manual, rev. 6, nov 2011 894 freescale semiconductor, inc. note the assignment of module modes to core modes is chip- specific. for module-to-core mode assignments, see the chapter that describes how modules are configured. chapter 36 12-bit digital-to-analog converter (dac) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 895 functional description k60 sub-family reference manual, rev. 6, nov 2011 896 freescale semiconductor, inc. chapter 37 voltage reference (vrefv1) 37.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the vrefv1 voltage reference is intended to supply an accurate voltage output that can be trimmed in 0.5 mv steps. the vrefv1 can be used in applications to provide a reference voltage to external devices or used internally as a reference to analog peripherals such as the adc, dac, or cmp. the voltage reference has two operating modes that provide different levels of supply rejection and power consumption. the following figure is a block diagram of the voltage reference. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 897 6 bits trm sc[vrefen] 2 bits sc[mode_lv] regulation buffer bandgap 100 nf vref_out dedicated output pin sc[vrefst] 1.75 v regulator 1.75 v vdda vssa figure 37-1. voltage reference block diagram 37.1.1 overview the voltage reference provides a buffered reference voltage with high output current for use as an external reference. in addition, the buffered reference is available internally for use with on chip peripherals such as adcs and dacs. refer to the chip configuration chapter for a description of these options. the reference voltage is output on a dedicated output pin when the vref is enabled. the voltage reference output can be trimmed with a resolution of 0.5mv by means of the trm register trim[5:0] bitfield. 37.1.2 features the voltage reference has the following features: ? programmable trim register with 0.5 mv steps, automatically loaded with factory trimmed value upon reset ? programmable buffer mode selection: ? off introduction k60 sub-family reference manual, rev. 6, nov 2011 898 freescale semiconductor, inc. ? bandgap enabled/standby (output buffer disabled) ? tight-regulation buffer mode (output buffer enabled) ? 1.2 v output at room temperature ? dedicated output pin, vref_out ? load regulation in tight-regulation mode 37.1.3 modes of operation the voltage reference continues normal operation in run, wait, and stop modes. the voltage reference can also run in very low power run (vlpr), very low power wait (vlpw) and very low power stop (vlps). the vref regulator is not available in any very low power modes and must be disabled (sc[regen]=0) before entering these modes. note however that the accuracy of the output voltage will be reduced (by as much as several mvs) when the vref regulator is not used. note the assignment of module modes to core modes is chip- specific. for module-to-core mode assignments, see the chapter that describes how modules are configured. 37.1.4 vref signal descriptions the following table shows the voltage reference signals properties. table 37-1. vref signal descriptions signal description i/o vref_out internally-generated voltage reference output o note ? in disable mode, the status of the vref_out signal is high-impedence. memory map and register definition 37.2 chapter 37 voltage reference (vrefv1) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 899 vref memory map absolute address (hex) register name width (in bits) access reset value section/ page 4007_4000 vref trim register (vref_trm) 8 r/w undefined 37.2.1/ 900 4007_4001 vref status and control register (vref_sc) 8 r/w 00h 37.2.2/ 901 37.2.1 vref trim register (vref_trm) this register contains bits that contain the trim data for the voltage reference. address: vref_trm is 4007_4000h base + 0h offset = 4007_4000h bit 7 6 5 4 3 2 1 0 read reserved 0 trim write reset x* x* x* x* x* x* x* x* * notes: x = undefined at reset. vref_trm field descriptions field description 7 reserved this field is reserved. upon reset this value is loaded with a factory trim value. this bit must always be written with the original reset value. 6 reserved this read-only field is reserved and always has the value zero. 5?0 trim trim bits upon reset this value is loaded with a factory trim value. these bits change the resulting vref by approximately ? 0.5 mv for each step. note: min = minimum and max = maximum voltage reference output. for minimum and maximum voltage reference output values, refer to the data sheet for this chip. 000000 min .... .... 111111 max memory map and register definition k60 sub-family reference manual, rev. 6, nov 2011 900 freescale semiconductor, inc. 37.2.2 vref status and control register (vref_sc) this register contains the control bits used to enable the internal voltage reference and to select the vref mode to be used. address: vref_sc is 4007_4000h base + 1h offset = 4007_4001h bit 7 6 5 4 3 2 1 0 read vrefen regen reserved 0 0 vrefst mode_lv write reset 0 0 0 0 0 0 0 0 vref_sc field descriptions field description 7 vrefen internal voltage reference enable this bit is used to enable the bandgap reference within the voltage reference module. note: after the vref is enabled, turning off the clock to the vref module via the corresponding clock gate register will not disable the vref. vref must be disabled via this vrefen bit. 0 the module is disabled. 1 the module is enabled. 6 regen regulator enable this bit is used to enable the internal 1.75 v vref regulator to produce a constant internal voltage supply in order to reduce the sensitivity to external supply noise and variation. the vref regulator must not be enabled when entering vlpr, vlpw or vlps modes. 0 internal 1.75 v regulator is disabled. 1 internal 1.75 v regulator is enabled. 5 reserved this field is reserved. this bit must always be written to zero. 4 reserved this read-only field is reserved and always has the value zero. 3 reserved this read-only field is reserved and always has the value zero. 2 vrefst internal voltage reference has settled this bit indicates that the bandgap reference within the voltage reference module has completed its startup and stabilization. 0 the bandgap is disabled or not ready. 1 the bandgap is ready. 1?0 mode_lv buffer mode selection these bits select the buffer modes for the voltage reference module. 00 bandgap on only, for stabilization and startup 01 reserved table continues on the next page... chapter 7 voltage reference vrefv1 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 01 vref_sc field descriptions (continued) field description 10 tight-regulation buffer enabled 11 reserved 37.3 functional description the voltage reference is a bandgap buffer system. unity gain amplifiers are used. the vref_out signal is available as an internal reference when it is enabled. a 100 nf capacitor must be connected between vref_out and vssa. the following table shows all possible function configurations of the voltage reference. table 37-5. voltage reference function configurations sc[vrefen] sc[mode_lv] configuration functionality 0 x voltage reference disabled off 1 00 voltage reference enabled, only the vref bandgap is on startup and standby 1 01 reserved reserved 1 10 voltage reference enabled, vref bandgap and tight- regulation buffer on vref_out available for internal and external use. 100 nf capacitor is required. 1 11 reserved reserved 37.3.1 voltage reference disabled, sc[vrefen] = 0 when sc[vrefen] = 0, the voltage reference is disabled, all bandgap and buffers are disabled. the voltage reference is in off mode. 37.3.2 voltage reference enabled, sc[vrefen] = 1 when sc[vrefen] = 1, the voltage reference is enabled, and different modes can be set by the sc[mode_lv] bits. functional description k60 sub-family reference manual, rev. 6, nov 2011 902 freescale semiconductor, inc. 37.3.2.1 sc[mode_lv]=00 the internal bandgap is enabled to generate an accurate 1.2 v output that can be trimmed with the trm register's trim[5:0] bitfield. the bandgap requires some time for startup and stabilization. sc[vrefst] can be monitored to determine if the stabilization and startup is complete. the output buffer is disabled in this mode, and there is no buffered voltage output. the voltage reference is in standby mode. if this mode is first selected and the tight regulation buffer mode is subsequently enabled, there will be a delay before the buffer output is settled at the final value. this is the buffer start up delay (tstup) and the value is specified in the appropriate device data sheet. 37.3.2.2 sc[mode_lv] = 01 reserved 37.3.2.3 sc[mode_lv] = 10 the tight regulation buffer is enabled to generate a buffered 1.2 v voltage to vref_out. if this mode is entered from the standby mode (sc[mode_lv] = 00, sc[vrefen] = 1) there will be a delay before the buffer output is settled at the final value. this is the buffer start up delay (tstup) and the value is specified in the appropriate device data sheet. if this mode is entered when the vref module is enabled then you must wait the longer of tstup or until sc[vrefst] = 1. 37.3.2.4 sc[mode_lv] = 11 reserved 37.4 initialization/application information the voltage reference requires some time for startup and stabilization. after sc[vrefen] = 1, sc[vrefst] can be monitored to determine if the stabilization and startup of the vref bandgap is complete. chapter 37 voltage reference (vrefv1) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 903 when the voltage reference is already enabled and stabilized, changing sc[mode_lv] will not clear sc[vrefst] but there will be some startup time before the output voltage at the vref_out pin has settled. this is the buffer start up delay (tstup) and the value is specified in the appropriate device data sheet. also, there will be some settling time when a step change of the load current is applied to the vref_out pin. when the 1.75v vref regulator is disabled, the vref_out voltage will be more sensitive to supply voltage variation. it is recommended to use this regulator to achieve optimum vref_out performance. initialization/application information k60 sub-family reference manual, rev. 6, nov 2011 904 freescale semiconductor, inc. chapter 38 programmable delay block (pdb) 38.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the programmable delay block (pdb) provides controllable delays from either an internal or an external trigger, or a programmable interval tick, to the hardware trigger inputs of adcs and/or generates the interval triggers to dacs, so that the precise timing between adc conversions and/or dac updates can be achieved. the pdb can optionally provides pulse outputs (pulse-out's) that are used as the sample window in the cmp block. 38.1.1 features ? up to 15 trigger input sources and software trigger source ? up to eight configurable pdb channels for adc hardware trigger ? one pdb channel is associated with one adc. ? one trigger output for adc hardware trigger and up to eight pre-trigger outputs for adc trigger select per pdb channel ? trigger outputs can be enabled or disabled independently. ? one 16-bit delay register per pre-trigger output ? optional bypass of the delay registers of the pre-trigger outputs ? operation in one-shot or continuous modes k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 905 ? optional back-to-back mode operation, which enables the adc conversions complete to trigger the next pdb channel ? one programmable delay interrupt ? one sequence error interrupt ? one channel flag and one sequence error flag per pre-trigger ? dma support ? up to eight dac interval triggers ? one interval trigger output per dac ? one 16-bit delay interval register per dac trigger output ? optional bypass the delay interval trigger registers ? optional external triggers ? up to eight pulse outputs (pulse-out's) ? pulse-out's can be enabled or disabled independently. ? programmable pulse width note the number of pdb input and output triggers are chip-specific. refer to the chip configuration information for details. 38.1.2 implementation in this chapter, the following letters refers to the number of output triggers. ? n total available number of pdb channels. ? n pdb channel number, valid from 0 to n -1. ? m total available pre-trigger per pdb channel. ? m pre-trigger number, valid from 0 to m -1. ? x total number of dac interval triggers. ? x dac interval trigger output number, valid from 0 to x -1. introduction k60 sub-family reference manual, rev. 6, nov 2011 906 freescale semiconductor, inc. ? y total number of pulse-out's. ? y pulse-out number, valid value is 0 to y -1. note the number of module output triggers to core are chip-specific. for module to core output triggers implementation, refer to the chip configuration information. 38.1.3 back-to-back acknowledgement connections pdb back-to-back operation acknowledgment connections are chip-specific. for implementation, refer to the chip configuration information. 38.1.4 dac external trigger input connections the implementation of dac external trigger inputs is chip-specific. refer to the chip configuration information for details. 38.1.5 block diagram this diagram illustrates the major components of the pdb. chapter 38 programmable delay block (pdb) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 907 ch n trigger pdbch n d 0 pdbch n d m ac 0 pre-trigger 0 ch n pre-trigger 0 ch n pre-trigger m bb m , ts m bb 0 , ts 0 en 0 en m mut ac m pre-trigger m trigger-in 0 dac interval trigger x seuence error detection err m - 10 prescaer pdb counter pdbcnt pdbmd control ogic cnt trigger-in 1 trigger-in 14 swtri trise dacint x dac interval counter x ext x dac ext trigger input x dac interval trigger x te x pdbid pdb interrupt te x p y d2 p y d1 pulse eneration pulse-ut y pdbpen y pulse-ut y figure 8-1. pdb bloc diagram in this diagram, only one pdb channel n , one dac interval trigger x , and one pulse-out y is shown. the pdb enable control logic and the sequence error interrupt logic is not shown. introduction k60 sub-family reference manual, rev. 6, nov 2011 908 freescale semiconductor, inc. 38.1.6 modes of operation pdb adc trigger operates in the following modes. disabled : counter is off, all pre-trigger and trigger outputs are low if pdb is not in back- to-back operation of bypass mode. debug : counter is paused when processor is in debug mode, the counter for dac trigger also paused in debug mode. enabled one-shot : counter is enabled and restarted at count zero upon receiving a positive edge on the selected trigger input source or software trigger is selected and sc[swtrig] is written with 1. in each pdb channel, an enabled pre-trigger asserts once per trigger input event; the trigger output asserts whenever any of pre-triggers is asserted. enabled continuous : counter is enabled and restarted at count zero. the counter is rolled over to zero again when the count reaches the value specified in the modulus register, and the counting is restarted. this enables a continuous stream of pre-triggers/ trigger outputs as a result of a single trigger input event. enabled bypassed : the pre-trigger and trigger outputs assert immediately after a positive edge on the selected trigger input source or software trigger is selected and sc[swtrig] is written with 1, that is the delay registers are bypassed. it is possible to bypass any one or more of the delay registers; therefore this mode can be used in conjunction with one-shot or continuous mode. 38.2 pdb signal descriptions this table shows the detailed description of the external signal. table 38-1. pdb signal descriptions signal description i/o extrg external trigger input source. if the pdb is enabled and external trigger input source is selected, a positive edge on the extrg signal resets and starts the counter. i 38.3 memory map and register definition chapter 38 programmable delay block (pdb) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 909 pdb memory map absolute address (hex) register name width (in bits) access reset value section/ page 4003_6000 status and control register (pdb0_sc) 32 r/w 0000_0000h 38.3.1/ 911 4003_6004 modulus register (pdb0_mod) 32 r/w 0000_ffffh 38.3.2/ 913 4003_6008 counter register (pdb0_cnt) 32 r 0000_0000h 38.3.3/ 914 4003_600c interrupt delay register (pdb0_idly) 32 r/w 0000_ffffh 38.3.4/ 914 4003_6010 channel n control register 1 (pdb0_ch0c1) 32 r/w 0000_0000h 38.3.5/ 915 4003_6014 channel n status register (pdb0_ch0s) 32 w1c 0000_0000h 38.3.6/ 916 4003_6018 channel n delay 0 register (pdb0_ch0dly0) 32 r/w 0000_0000h 38.3.7/ 917 4003_601c channel n delay 1 register (pdb0_ch0dly1) 32 r/w 0000_0000h 38.3.8/ 917 4003_6038 channel n control register 1 (pdb0_ch1c1) 32 r/w 0000_0000h 38.3.5/ 915 4003_603c channel n status register (pdb0_ch1s) 32 w1c 0000_0000h 38.3.6/ 916 4003_6040 channel n delay 0 register (pdb0_ch1dly0) 32 r/w 0000_0000h 38.3.7/ 917 4003_6044 channel n delay 1 register (pdb0_ch1dly1) 32 r/w 0000_0000h 38.3.8/ 917 4003_6150 dac interval trigger n control register (pdb0_dacintc0) 32 r/w 0000_0000h 38.3.9/ 918 4003_6154 dac interval n register (pdb0_dacint0) 32 r/w 0000_0000h 38.3.10/ 918 4003_6158 dac interval trigger n control register (pdb0_dacintc1) 32 r/w 0000_0000h 38.3.9/ 918 4003_615c dac interval n register (pdb0_dacint1) 32 r/w 0000_0000h 38.3.10/ 918 4003_6190 pulse-out n enable register (pdb0_po0en) 32 r/w 0000_0000h 38.3.11/ 919 4003_6194 pulse-out n delay register (pdb0_po0dly) 32 r/w 0000_0000h 38.3.12/ 919 memory map and register definition k60 sub-family reference manual, rev. 6, nov 2011 910 freescale semiconductor, inc. 38.3.1 status and control register (pdb x resses: is h ase h oset h it r lo r reset it r rlr rl f ul o lo reset x iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero lo loa oe elect elects the oe to loa the o l h n d m , int x , and p y d registers, after 1 is written to d. 00 the internal registers are loaded with the values from their buffers immediately after 1 is written to d. 01 the internal registers are loaded with the values from their buffers when the pdb counter reaches the md register value after 1 is written to d. 10 the internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to d. 11 the internal registers are loaded with the values from their buffers when either the pdb counter reaches the md register value or a trigger input event is detected, after 1 is written to d. 17 pdbeie pdb seuence error interrupt enable this bit enables the pdb seuence error interrupt. when this bit is set, any of the pdb channel seuence error flags generates a pdb seuence error interrupt. 0 pdb seuence error interrupt disabled. 1 pdb seuence error interrupt enabled. 16 swtri software trigger when pdb is enabled and the software trigger is selected as the trigger input source, writing 1 to this bit reset and restarts the counter. writing 0 to this bit has no effect. reading this bit results 0. table continues on the next page... chapter 8 programmable delay bloc pdb 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 11 pdb x iel escritions continue fiel escrition nale hen is enale the f la enerates a request instea o an interrut isale enale rlr rescaler iier elect ountin uses the eriheral cloc iie y ultilication actor selecte y ul ountin uses the eriheral cloc iie y twice o the ultilication actor selecte y ul ountin uses the eriheral cloc iie y our ties o the ultilication actor selecte y ul ountin uses the eriheral cloc iie y eiht ties o the ultilication actor selecte y ul ountin uses the eriheral cloc iie y ties o the ultilication actor selecte y ul ountin uses the eriheral cloc iie y ties o the ultilication actor selecte y ul ountin uses the eriheral cloc iie y ties o the ultilication actor selecte y ul ountin uses the eriheral cloc iie y ties o the ultilication actor selecte y ul rl rier nut ource elect elects the trier inut source or the he trier inut source can e internal or external r in or the sotware trier riern is selecte riern is selecte riern is selecte riern is selecte riern is selecte riern is selecte riern is selecte riern is selecte riern is selecte riern is selecte riern is selecte riern is selecte riern is selecte riern is selecte riern is selecte otware trier is selecte nale isale ounter is o enale f nterrut fla table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 12 freescale semiconductor, inc. pdb x iel escritions continue fiel escrition his it is set when the counter alue is equal to the l reister ritin ero clears this it nterrut nale his it enales the interrut hen this it is set an is cleare f enerates a interrut interrut isale interrut enale resere his reaonly iel is resere an always has the alue ero ul ultilication factor elect or rescaler his it selects the ultilication actor o the rescaler iier or the counter cloc ultilication actor is ultilication actor is ultilication actor is ultilication actor is o ontinuous oe nale his it enales the oeration in ontinuous oe oeration in onehot oe oeration in ontinuous oe lo loa o ritin to this it uates the internal reisters o o l hnl x an oyl with the alues written to their uers he o l hnl x an oyl will tae eect accorin to the lo ter is written to lo it the alues in the uers o aoe reisters are not eectie an the uers cannot e written until the alues in uers are loae into their internal reisters lo can e written only when is set or it can e written at the sae tie with ein written to t is autoatically cleare when the alues in uers are loae into the internal reisters or the is cleare ritin to it has no eect oulus reister x o resses: o is h ase h oset h it r o reset hater roraale elay loc ufaily reerence anual re o freescale eiconuctor nc pdb x o iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero o oulus hese its seciy the erio o the counter hen the counter reaches this alue it will e reset ac to ero the is in ontinuous oe the count eins anew reain these its returns the alue o internal reister that is eectie or the current cycle o ounter reister x resses: is h ase h oset h it r reset x iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero ounter hese reaonly its contain the current alue o the counter nterrut elay reister x l resses: l is h ase h oset h it r l reset x l iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero l nterrut elay table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 14 freescale semiconductor, inc. pdb x l iel escritions continue fiel escrition hese its seciy the elay alue to scheule the interrut t can e use to scheule an ineenent interrut at soe oint in the cycle enale a interrut is enerate when the counter is equal to the l reain these its returns the alue o internal reister that is eectie or the current cycle o the hannel n ontrol reister x h each pdb channel has one control register, chnc1. the bits in this register control the functionality of each pdb channel operation. addresses: pdb0_ch0c1 is 4003_6000h base + 10h offset = 4003_6010h pdb0_ch1c1 is 4003_6000h base + 38h offset = 4003_6038h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 bb tos en w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pdb x h n iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero hannel rerier actoac oeration nale hese its enale the retrier oeration as actoac oe only lower retrier its are ileente in this u actoac oeration enales the conersions colete to trier the next channel retrier an trier outut so that the conersions can e triere on next set o coniuration an results reisters lication coe ust only enale the actoac oeration o the retriers at the leain o the actoac connection chain channels corresonin retrier actoac oeration isale channels corresonin retrier actoac oeration enale o hannel rerier outut elect hese its select the retrier oututs only lower retrier its are ileente in this u channels corresonin retrier is in yasse oe he retrier asserts one eriheral cloc cycle ater a risin ee is etecte on selecte trier inut source or sotware trier is selecte an r is written with channels corresonin retrier asserts when the counter reaches the channel elay reister lus one eriheral cloc cycle ater a risin ee is etecte on selecte trier inut source or sotware trier is selecte an r is written with hannel rerier nale table continues on the next page... chapter 8 programmable delay bloc pdb 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1 pdb x h n iel escritions continue fiel escrition hese its enale the retrier oututs only lower retrier its are ileente in this u channels corresonin retrier isale channels corresonin retrier enale hannel n tatus reister x h resses: h is h ase h oset h h is h ase h oset h it r f rr reset x h n iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero f hannel flas he f m bit is set when the pdb counter matches the ch n d m . write 0 to clear these bits. 18 reserved this read-only field is reserved and always has the value zero. 70 err pdb channel seuence error flags nly the lower m bits are implemented in this mcu. 0 seuence error not detected on pdb channels corresponding pre-trigger. 1 seuence error detected on pdb channels corresponding pre-trigger. adcn bloc can be triggered for a conversion by one pre-trigger from pdb channel n . when one conversion, which is triggered by one of the pre-triggers from pdb channel n , is in progress, new trigger from pdb channels corresponding pre-trigger m cannot be accepted by adcn, and errm is set. writing 1s to clear the seuence error flags. memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 16 freescale semiconductor, inc. 38.3.7 channel n delay 0 register (pdb x hl resses: hl is h ase h oset h hl is h ase h oset h it r l reset x h n l iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero l hannel elay hese its seciy the elay alue or the channels corresonin retrier he retrier asserts when the counter is equal to l reain these its returns the alue o internal reister that is eectie or the current cycle hannel n elay reister x hl resses: hl is h ase h oset h hl is h ase h oset h it r l reset x h n l iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero l hannel elay hese its seciy the elay alue or the channels corresonin retrier he retrier asserts when the counter is equal to l reain these its returns the alue o internal reister that is eectie or the current cycle hater roraale elay loc ufaily reerence anual re o freescale eiconuctor nc 38.3.9 dac interval trigger n control register (pdb x n resses: is h ase h oset h is h ase h oset h it r o reset x n iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero xternal rier nut nale his it enales the external trier or interal counter external trier inut isale interal counter is reset an starte countin when a risin ee is etecte on selecte trier inut source or sotware trier is selecte an r is written with external trier inut enale interal counter is yasse an external trier inut triers the interal trier o nteral rier nale his it enales the interal trier interal trier isale interal trier enale nteral n reister x n resses: is h ase h oset h is h ase h oset h it r reset x n iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 18 freescale semiconductor, inc. pdb x n iel escritions continue fiel escrition nteral hese its seciy the interal alue or interal trier interal trier triers : uate when the interal counter is equal to the reain these its returns the alue o internal reister that is eectie or the current cycle ulseout n nale reister x o resses: o is h ase h oset h it r o reset x o n iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero o ulseout nale hese its enale the ulse outut only lower its are ileente in this u ulseout isale ulseout enale ulseout n elay reister x ol resses: ol is h ase h oset h it r l l reset x o n l iel escritions fiel escrition l ulseout elay table continues on the next page... chapter 8 programmable delay bloc pdb 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1 pdb x o n l iel escritions continue fiel escrition hese its seciy the elay alue or the ulseout ulseout oes hih when the counter is equal to the l reain these its returns the alue o internal reister that is eectie or the current cycle l ulseout elay hese its seciy the elay alue or the ulseout ulseout oes low when the counter is equal to the l reain these its returns the alue o internal reister that is eectie or the current cycle functional escrition retrier an rier oututs the pdb contains a counter whose output is compared against several different digital values. if the pdb is enabled, a trigger input event will reset the counter and make it start to count. a trigger input event is defined as a rising edge being detected on selected trigger input source or software trigger being selected and sc[swtrig] is written with 1. for each channel, delay m determines the time between assertion of the trigger input event to the point at which changes in the pre-trigger m output signal is initiated. the time is defined as: ? trigger input event to pre-trigger m = (prescaler x multiplication factor x delay m ) + 2 peripheral clock cycles ? add one additional peripheral clock cycle to determine the time at which the channel trigger output change. each channel is associated with one adc block. pdb channel n pre-trigger outputs 0 to m and trigger output is connected to adc hardware trigger select and hardware trigger inputs. the pre-triggers are used to precondition the adc block prior to the actual trigger. the adc contains m sets of configuration and result registers, allowing it to operate in a ping-pong fashion, alternating conversions between m different analog sources. the pre-trigger outputs are used to specify which signal will be sampled next. when pre-trigger m is asserted, the adc conversion is triggered with set m of the configuration and result registers. the waveforms shown in the following diagram illuminate the pre-trigger and trigger outputs of pdb channel n . the delays can be independently set via the ch n dly m registers. and the pre-triggers can be enabled or disabled in ch n c1[en[ m ]]. functional description k60 sub-family reference manual, rev. 6, nov 2011 920 freescale semiconductor, inc. trigger input event ch n pre-trigger 0 ch n pre-trigger 1 ch n pre-trigger m ch n trigger ... ... ... ... figure 8-4. pre-trigger and trigger utputs the delay in ch n dly m register can be optionally bypassed, if ch n c1[tos[ m ]] is cleared. in this case, when the trigger input event occurs, the pre-trigger m is asserted after two peripheral clock cycles. the pdb can be configured in back-to-back (b2b) operation. b2b operation enables the adc conversions complete to trigger the next pdb channel pre-trigger and trigger outputs, so that the adc conversions can be triggered on next set of configuration and results registers. when b2b is enabled by setting ch n c1[bb[ m ]], the delay m is ignored and the pre-trigger m is asserted two peripheral cycles after the acknowledgment m is received. the acknowledgment connections in this mcu is described in back-to-back acknowledgement connections . when an adc conversion, which is triggered by one of the pre-triggers from pdb channel n , is in progress and adc n sc1[coco] is not set, a new trigger from pdb channel n pre-trigger m cannot be accepted by adc n . therefore every time when one pdb channel n pre-trigger and trigger output starts an adc conversion, an internal lock associated with the corresponding pre-trigger is activated. the lock becomes inactive when the corresponding adc n sc1[coco] is set, or the corresponding pdb pre-trigger is disabled, or the pdb is disabled. the channel n trigger output is suppressed when any of the locks of the pre-triggers in channel n is active. if a new pre-trigger m asserts when there is active lock in the pdb channel n , a register flag bit, ch n s[err[ m ]], associated with the pre-trigger m is set. if sc[pdbeie] is set, the sequence error interrupt is generated. sequence error is typically happened because the delay m is set too short and the pre-trigger m asserts before the previous triggered adc conversion is completed. when the pdb counter reaches the value set in idly register, the sc[pdbif] flag is set. a pdb interrupt can be generated if sc[pdbie] is set and sc[dmaen] is cleared. if sc[dmaen] is set, pdb requests a dma transfer when sc[pdbif] is set. the modulus value in mod register, is used to reset the counter back to zero at the end of the count. if sc[cont] bit is set, the counter will then resume a new count. otherwise, the counter operation will cease until the next trigger input event occurs. chapter 38 programmable delay block (pdb) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 921 38.4.2 pdb trigger input source selection the pdb has up to 15 trigger input sources, namely trigger-in 0 to 14. they are connected to on-chip or off-chip event sources. the pdb can be triggered by software through the sc[swtrig]. sc[trigsel] bits select the active trigger input source or software trigger. for the trigger input sources implemented in this mcu, refer to chip configuration information. 38.4.3 dac interval trigger outputs pdb can generate the interval triggers for dacs to update their outputs periodically. dac interval counter x is reset and started when a trigger input event occurs if dacintc x [ext] is cleared. when the interval counter x is equal to the value set in dacint x register, the dac interval trigger x output generates a pulse of one peripheral clock cycle width to update the dac x . if dacintc x [ext] is set, the dac interval counter is bypassed and the interval trigger output x generates a pulse following the detection of a rising edge on the dac external trigger input. the counter and interval trigger can be disabled by clearing the dacintc x [toe]. dac interval counters are also reset when the pdb counter reaches the mod register value, therefore when the pdb counter rolls over to zero, the dac interval counters starts anew. together, the dac interval trigger pulse and the adc pre-trigger/trigger pulses allow precise timing of dac updates and adc measurements. this is outlined in the typical use case described in the following diagram. functional description k60 sub-family reference manual, rev. 6, nov 2011 922 freescale semiconductor, inc. pdb counter mod, idly 0 dacint x dacint x x dacint x x2 ... ... ch n d1 ch n d0 dac internal trigger x ch n pre-trigger 0 ch n pre-trigger 1 ch n trigger pdb interrupt ... ... trigger input event figure 8-. pdb adc triggers and dac interval triggers use case nte because the dac interval counters share the prescaler with pdb counter, pdb must be enabled if the dac interval trigger outputs are used in the applications. 38.4.4 pulse-outCs pdb can generate pulse outputs of configurable width. when pdb counter reaches the value set in po y dly[dly1], the pulse-out goes high; when the counter reaches po y dly[dly2], it goes low. po y dly[dly2] can be set either greater or less than po y dly[dly1]. because the pdb counter is shared by both adc pre-trigger/trigger outputs and pulse- out generation, they have the same time base. the pulse-out connections implemented in this mcu are described in the device's chip configuration details. 38.4.5 updating the delay registers the following registers control the timing of the pdb operation; and in some of the applications, they may need to become effective at the same time. chapter 38 programmable delay block (pdb) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 923 ? pdb modulus register (mod) ? pdb interrupt delay register (idly) ? pdb channel n delay m register (ch n dly m ) ? dac interval x register (dacint x ) ? pdb pulse-out y delay register (po y dly) the internal registers of them are buffered and any values written to them are written first to their buffers. the circumstances that cause their internal registers to be updated with the values from the buffers are summarized as below table. table 38-56. circumstances of update to the delay registers sc[ldmod] update to the delay registers 00 the internal registers are loaded with the values from their buffers immediately after 1 is written to sc[ldok]. 01 the pdb counter reaches the mod register value after 1 is written to sc[ldok]. 10 a trigger input event is detected after 1 is written to sc[ldok]. 11 either the pdb counter reaches the mod register value, or a trigger input event is detected, after 1 is written to sc[ldok]. after 1 is written to sc[ldok], the buffers cannot be written until the values in buffers are loaded into their internal registers. sc[ldok] is self-cleared when the internal registers are loaded, so the application code can read it to determine the updates of the internal registers. the following diagrams show the cases of the internal registers being updated with sc[ldmod] is 00 and x1. pdb counter ch n pre-trigger 0 ch n pre-trigger 1 ch n d1 ch n d0 scd figure 8-6. registers update with scdmd 00 functional description 60 sub-family reference manual, rev. 6, nov 2011 24 freescale semiconductor, inc. pdb counter ch n pre-trigger 0 ch n pre-trigger 1 ch n d1 ch n d0 scd figure 8-7. registers update with scdmd x1 8.4.6 interrupts pdb can generate two interrupts, pdb interrupt and pdb sequence error interrupt. the following table summarizes the interrupts. table 38-57. pdb interrupt summary interrupt flags enable bit pdb interrupt sc[pdbif] sc[pdbie] = 1 and sc[dmaen] = 0 pdb sequence error interrupt ch n serr m scpdbeie 1 8.4.7 dma if sc[dmaen] is set, pdb can generate dma transfer request when sc[pdbif] is set. when dma is enabled, the pdb interrupt will not be issued. 38.5 application information 38.5.1 impact of using the prescaler and multiplication factor on timing resolution use of prescaler and multiplication factor greater than 1 limits the count/delay accuracy in terms of peripheral clock cycles (to the modulus of the prescaler x multiplication factor). if the multiplication factor is set to 1 and the prescaler is set to 2 then the only chapter 38 programmable delay block (pdb) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 925 values of total peripheral clocks that can be detected are even values; if prescaler is set to 4 then the only values of total peripheral clocks that can be decoded as detected are mod(4) and so forth. if the applications need a really long delay value and use 128, then the resolution would be limited to 128 peripheral clock cycles. therefore, use the lowest possible prescaler and multiplication factor for a given application. application information k60 sub-family reference manual, rev. 6, nov 2011 926 freescale semiconductor, inc. chapter 39 flextimer (ftm) 39.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the flextimer module (ftm) is a two to eight channel timer which supports input capture, output compare, and the generation of pwm signals to control electric motor and power management applications. the ftm time reference is a 16-bit counter that can be used as an unsigned or signed counter. 39.1.1 flextimer philosophy the flextimer is built upon a very simple timer (hcs08 timer pwm module C tpm) used for many years on freescales 8 bit microcontrollers. the flextimer extends the functionality to meet the demands of motor control, digital lighting solutions and power conversion yet providing low cost and backwards compatibility with the tpm module. several key enhancements are made; signed up counter, deadtime insertion hardware, fault control inputs, enhanced triggering functionality and initialization and polarity control. all the features common with the tpm module have fully backwards compatible register assignments and the flextimer can use code on the same core platform without change to perform the same functions. motor control and power conversion features have been added through a dedicated set of registers and defaults turn off all new features. the new features such as hardware deadtime insertion, polarity, fault control and output forcing and masking greatly reduce loading on the execution software and are usually each controlled by a group of registers. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 927 flextimer input triggers can be from comparators, adc or other sub modules to initiate timer functions automatically. these triggers can be linked in a variety of ways during integration of the sub modules so please note carefully the options available for used flextimer configuration. several flextimers may be synchronized to provide a larger timer with their counters incrementing in unison, assuming the initialization, the input clocks, the initial and final counting values are the same in each flextimer. all main user access registers are buffered to ease the load on the executing software. a number of trigger options exist to determine which registers are updated with this user defined data. 39.1.2 features the ftm features include: ? ftm source clock is selectable ? source clock can be the system clock, the fixed frequency clock, or an external clock ? fixed frequency clock is an additional clock input to allow the selection of an on chip clock source other than the system clock ? selecting external clock connects ftm clock to a chip level input pin therefore allowing to synchronize the ftm counter with an off chip clock source ? prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128 ? ftm has a 16-bit counter ? it can be a free-running counter or a counter with initial and final value ? the counting can be up or up-down ? each channel can be configured for input capture, output compare, or edge-aligned pwm mode ? in input capture mode ? the capture can occur on rising edges, falling edges or both edges ? an input filter can be selected for some channels ? in output compare mode the output signal can be set, cleared, or toggled on match ? all channels can be configured for center-aligned pwm mode introduction k60 sub-family reference manual, rev. 6, nov 2011 928 freescale semiconductor, inc. ? each pair of channels can be combined to generate a pwm signal (with independent control of both edges of pwm signal) ? the ftm channels can operate as pairs with equal outputs, pairs with complementary outputs, or independent channels (with independent outputs) ? the deadtime insertion is available for each complementary pair ? generation of triggers (match trigger) ? software control of pwm outputs ? up to 4 fault inputs for global fault control ? the polarity of each channel is configurable ? the generation of an interrupt per channel ? the generation of an interrupt when the counter overflows ? the generation of an interrupt when the fault condition is detected ? synchronized loading of write buffered ftm registers ? write protection for critical registers ? backwards compatible with tpm ? testing of input captures for a stuck at zero and one conditions ? dual edge capture for pulse and period width measurement ? quadrature decoder with input filters, relative position counting and interrupt on position count or capture of position count on external event 39.1.3 modes of operation when the mcu is in an active bdm mode, the ftm temporarily suspends all counting until the mcu returns to normal user operating mode. during stop mode, all ftm input clocks are stopped, so the ftm is effectively disabled until clocks resume. during wait mode, the ftm continues to operate normally. if the ftm does not need to produce a real time reference or provide the interrupt sources needed to wake the mcu from wait mode, the power can then be saved by disabling ftm functions before entering wait mode. chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 929 39.1.4 block diagram the ftm uses one input/output (i/o) pin per channel, chn (ftm channel (n)) where n is the channel number (0C7). the following figure shows the ftm structure. the central component of the ftm is the 16-bit counter with programmable initial and final values and its counting can be up or up-down. introduction k60 sub-family reference manual, rev. 6, nov 2011 930 freescale semiconductor, inc. captest no clock selected (ftm counter disable) system clock fixed frequency clock external clock phase a phase b clks ftmen quaden synchronizer quadrature decoder quaden cpwms ps inittrigen toie tof tofdir quadir cntin mod faultin faultf faultfn* ftm counter faultm[1:0] ffval[3:0] faultie faultnen* ffltrnen* fault input n* fault control *where n = 3, 2, 1, 0 initialization trigger timer overflow interrupt fault condition fault interrupt pair channels 0 - channels 0 and 1 decapen combine0 cpwms ms0b:ms0a els0b:els0a dual edge capture mode logic input capture mode logic input capture mode logic channel 0 input channel 1 input decapen combine0 cpwms ms1b:ms1a els1b:els1a decapen combine3 cpwms ms6b:ms6a els6b:els6a channel 6 input channel 7 input decapen combine3 cpwms ms7b:ms7a els7b:els7a dual edge capture mode logic input capture mode logic input capture mode logic c0v c1v c6v c7v ch6ie ch6f ch1ie ch0ie ch7ie ch7f ch1f ch0f channel 0 interrupt channel 1 interrupt channel 6 interrupt channel 7 interrupt channel 7 match trigger channel 6 output signal channel 6 match trigger channel 1 match trigger channel 0 output signal channel 0 match trigger channel 1 output signal channel 7 output signal ch7trig ch6trig ch1trig ch0trig pair channels 3 - channels 6 and 7 (generation of channels 0 and 1 outputs signals in output compare, epwm, cpwm and combine modes according to initialization, complementary mode, inverting, software output control, deadtime insertion, output mask, fault control and polarity control) output modes logic (generation of channels 6 and 7 outputs signals in output compare, epwm, cpwm and combine modes according to initialization, complementary mode, inverting, software output control, deadtime insertion, output mask, fault control and polarity control) output modes logic prescaler 3 ( 1, 2, 4, 8, 16, 32, 64 or 128) figure 39-1. ftm block diagram chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 931 39.2 ftm signal descriptions table 39-1 shows the user-accessible signals for the ftm. table 39-1. ftm signal descriptions signal description i/o extclk external clock. ftm external clock can be selected to drive the ftm counter. i chn ftm channel (n), where n can be 7-0 i/o faultj fault input (j), where j can be 3-0 i pha quadrature decoder phase a input. input pin associated with quadrature decoder phase a. i phb quadrature decoder phase b input. input pin associated with quadrature decoder phase b. i 39.2.1 extclk ftm external clock the external clock input signal is used as the ftm counter clock if selected by clks[1:0] bits in the sc register. this clock signal must not exceed 1/4 of system clock frequency. the ftm counter prescaler selection and settings are also used when an external clock is selected. 39.2.2 chn ftm channel (n) i/o pin each ftm channel can be configured to operate either as input or output. the direction associated with each channel, input or output, is selected according to the mode assigned for that channel. 39.2.3 faultj ftm fault input the fault input signals are used to control the chn channel output state. if a fault is detected, the faultj signal is asserted and the channel output is put in a safe state. the behavior of the fault logic is defined by the faultm[1:0] control bits in the mode register and faulten bit in the combinem register. note that each faultj input may affect all channels selectively since faultm[1:0] and faulten control bits are ftm signal descriptions k60 sub-family reference manual, rev. 6, nov 2011 932 freescale semiconductor, inc. defined for each pair of channels. since there are several faultj inputs, maximum of 4 for the ftm module, each one of these inputs is activated by the faultjen bit in the fltctrl register. 39.2.4 pha ftm quadrature decoder phase a input the quadrature decoder phase a input is used as the quadrature decoder mode is selected. the phase a input signal is one of the signals that control the ftm counter increment or decrement in the quadrature decoder mode ( quadrature decoder mode ). 39.2.5 phb ftm quadrature decoder phase b input the quadrature decoder phase b input is used as the quadrature decoder mode is selected. the phase b input signal is one of the signals that control the ftm counter increment or decrement in the quadrature decoder mode ( quadrature decoder mode ). 39.3 memory map and register definition this section provides a detailed description of all ftm registers. 39.3.1 module memory map this section presents a high-level summary of the ftm registers and how they are mapped. the first set has the original tpm registers. the second set has the ftm specific registers. any second set registers (or bits within these registers) that are used by an unavailable function in the ftm configuration remain in the memory map and in the reset value, so they have no active function. note do not write to the ftm specific registers (second set registers) when ftmen = 0. chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 933 39.3.2 register descriptions this section consists of register descriptions in address order. accesses to reserved addresses result in transfer errors. registers for absent channels are considered reserved. ftm memory map absolute address (hex) register name width (in bits) access reset value section/ page 4003_8000 status and control (ftm0_sc) 32 r/w 0000_0000h 39.3.3/ 940 4003_8004 counter (ftm0_cnt) 32 r/w 0000_0000h 39.3.4/ 941 4003_8008 modulo (ftm0_mod) 32 r/w 0000_0000h 39.3.5/ 942 4003_800c channel (n) status and control (ftm0_c0sc) 32 r/w 0000_0000h 39.3.6/ 943 4003_8010 channel (n) value (ftm0_c0v) 32 r/w 0000_0000h 39.3.7/ 946 4003_8014 channel (n) status and control (ftm0_c1sc) 32 r/w 0000_0000h 39.3.6/ 943 4003_8018 channel (n) value (ftm0_c1v) 32 r/w 0000_0000h 39.3.7/ 946 4003_801c channel (n) status and control (ftm0_c2sc) 32 r/w 0000_0000h 39.3.6/ 943 4003_8020 channel (n) value (ftm0_c2v) 32 r/w 0000_0000h 39.3.7/ 946 4003_8024 channel (n) status and control (ftm0_c3sc) 32 r/w 0000_0000h 39.3.6/ 943 4003_8028 channel (n) value (ftm0_c3v) 32 r/w 0000_0000h 39.3.7/ 946 4003_802c channel (n) status and control (ftm0_c4sc) 32 r/w 0000_0000h 39.3.6/ 943 4003_8030 channel (n) value (ftm0_c4v) 32 r/w 0000_0000h 39.3.7/ 946 4003_8034 channel (n) status and control (ftm0_c5sc) 32 r/w 0000_0000h 39.3.6/ 943 4003_8038 channel (n) value (ftm0_c5v) 32 r/w 0000_0000h 39.3.7/ 946 4003_803c channel (n) status and control (ftm0_c6sc) 32 r/w 0000_0000h 39.3.6/ 943 table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 4 freescale semiconductor, inc. ftm memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4003_8040 channel (n) value (ftm0_c6v) 32 r/w 0000_0000h 39.3.7/ 946 4003_8044 channel (n) status and control (ftm0_c7sc) 32 r/w 0000_0000h 39.3.6/ 943 4003_8048 channel (n) value (ftm0_c7v) 32 r/w 0000_0000h 39.3.7/ 946 4003_804c counter initial value (ftm0_cntin) 32 r/w 0000_0000h 39.3.8/ 947 4003_8050 capture and compare status (ftm0_status) 32 r/w 0000_0000h 39.3.9/ 947 4003_8054 features mode selection (ftm0_mode) 32 r/w 0000_0004h 39.3.10/ 950 4003_8058 synchronization (ftm0_sync) 32 r/w 0000_0000h 39.3.11/ 951 4003_805c initial state for channels output (ftm0_outinit) 32 r/w 0000_0000h 39.3.12/ 954 4003_8060 output mask (ftm0_outmask) 32 r/w 0000_0000h 39.3.13/ 955 4003_8064 function for linked channels (ftm0_combine) 32 r/w 0000_0000h 39.3.14/ 957 4003_8068 deadtime insertion control (ftm0_deadtime) 32 r/w 0000_0000h 39.3.15/ 962 4003_806c ftm external trigger (ftm0_exttrig) 32 r/w 0000_0000h 39.3.16/ 963 4003_8070 channels polarity (ftm0_pol) 32 r/w 0000_0000h 39.3.17/ 965 4003_8074 fault mode status (ftm0_fms) 32 r/w 0000_0000h 39.3.18/ 967 4003_8078 input capture filter control (ftm0_filter) 32 r/w 0000_0000h 39.3.19/ 969 4003_807c fault control (ftm0_fltctrl) 32 r/w 0000_0000h 39.3.20/ 971 4003_8080 quadrature decoder control and status (ftm0_qdctrl) 32 r/w 0000_0000h 39.3.21/ 973 4003_8084 configuration (ftm0_conf) 32 r/w 0000_0000h 39.3.22/ 975 4003_8088 ftm fault input polarity (ftm0_fltpol) 32 r/w 0000_0000h 39.3.23/ 976 4003_808c synchronization configuration (ftm0_synconf) 32 r/w 0000_0000h 39.3.24/ 978 table continues on the next page... chapter flextimer ftm 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. ftm memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4003_8090 ftm inverting control (ftm0_invctrl) 32 r/w 0000_0000h 39.3.25/ 980 4003_8094 ftm software output control (ftm0_swoctrl) 32 r/w 0000_0000h 39.3.26/ 981 4003_8098 ftm pwm load (ftm0_pwmload) 32 r/w 0000_0000h 39.3.27/ 983 4003_9000 status and control (ftm1_sc) 32 r/w 0000_0000h 39.3.3/ 940 4003_9004 counter (ftm1_cnt) 32 r/w 0000_0000h 39.3.4/ 941 4003_9008 modulo (ftm1_mod) 32 r/w 0000_0000h 39.3.5/ 942 4003_900c channel (n) status and control (ftm1_c0sc) 32 r/w 0000_0000h 39.3.6/ 943 4003_9010 channel (n) value (ftm1_c0v) 32 r/w 0000_0000h 39.3.7/ 946 4003_9014 channel (n) status and control (ftm1_c1sc) 32 r/w 0000_0000h 39.3.6/ 943 4003_9018 channel (n) value (ftm1_c1v) 32 r/w 0000_0000h 39.3.7/ 946 4003_901c channel (n) status and control (ftm1_c2sc) 32 r/w 0000_0000h 39.3.6/ 943 4003_9020 channel (n) value (ftm1_c2v) 32 r/w 0000_0000h 39.3.7/ 946 4003_9024 channel (n) status and control (ftm1_c3sc) 32 r/w 0000_0000h 39.3.6/ 943 4003_9028 channel (n) value (ftm1_c3v) 32 r/w 0000_0000h 39.3.7/ 946 4003_902c channel (n) status and control (ftm1_c4sc) 32 r/w 0000_0000h 39.3.6/ 943 4003_9030 channel (n) value (ftm1_c4v) 32 r/w 0000_0000h 39.3.7/ 946 4003_9034 channel (n) status and control (ftm1_c5sc) 32 r/w 0000_0000h 39.3.6/ 943 4003_9038 channel (n) value (ftm1_c5v) 32 r/w 0000_0000h 39.3.7/ 946 4003_903c channel (n) status and control (ftm1_c6sc) 32 r/w 0000_0000h 39.3.6/ 943 4003_9040 channel (n) value (ftm1_c6v) 32 r/w 0000_0000h 39.3.7/ 946 table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 6 freescale semiconductor, inc. ftm memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4003_9044 channel (n) status and control (ftm1_c7sc) 32 r/w 0000_0000h 39.3.6/ 943 4003_9048 channel (n) value (ftm1_c7v) 32 r/w 0000_0000h 39.3.7/ 946 4003_904c counter initial value (ftm1_cntin) 32 r/w 0000_0000h 39.3.8/ 947 4003_9050 capture and compare status (ftm1_status) 32 r/w 0000_0000h 39.3.9/ 947 4003_9054 features mode selection (ftm1_mode) 32 r/w 0000_0004h 39.3.10/ 950 4003_9058 synchronization (ftm1_sync) 32 r/w 0000_0000h 39.3.11/ 951 4003_905c initial state for channels output (ftm1_outinit) 32 r/w 0000_0000h 39.3.12/ 954 4003_9060 output mask (ftm1_outmask) 32 r/w 0000_0000h 39.3.13/ 955 4003_9064 function for linked channels (ftm1_combine) 32 r/w 0000_0000h 39.3.14/ 957 4003_9068 deadtime insertion control (ftm1_deadtime) 32 r/w 0000_0000h 39.3.15/ 962 4003_906c ftm external trigger (ftm1_exttrig) 32 r/w 0000_0000h 39.3.16/ 963 4003_9070 channels polarity (ftm1_pol) 32 r/w 0000_0000h 39.3.17/ 965 4003_9074 fault mode status (ftm1_fms) 32 r/w 0000_0000h 39.3.18/ 967 4003_9078 input capture filter control (ftm1_filter) 32 r/w 0000_0000h 39.3.19/ 969 4003_907c fault control (ftm1_fltctrl) 32 r/w 0000_0000h 39.3.20/ 971 4003_9080 quadrature decoder control and status (ftm1_qdctrl) 32 r/w 0000_0000h 39.3.21/ 973 4003_9084 configuration (ftm1_conf) 32 r/w 0000_0000h 39.3.22/ 975 4003_9088 ftm fault input polarity (ftm1_fltpol) 32 r/w 0000_0000h 39.3.23/ 976 4003_908c synchronization configuration (ftm1_synconf) 32 r/w 0000_0000h 39.3.24/ 978 4003_9090 ftm inverting control (ftm1_invctrl) 32 r/w 0000_0000h 39.3.25/ 980 table continues on the next page... chapter flextimer ftm 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 7 ftm memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4003_9094 ftm software output control (ftm1_swoctrl) 32 r/w 0000_0000h 39.3.26/ 981 4003_9098 ftm pwm load (ftm1_pwmload) 32 r/w 0000_0000h 39.3.27/ 983 400b_8000 status and control (ftm2_sc) 32 r/w 0000_0000h 39.3.3/ 940 400b_8004 counter (ftm2_cnt) 32 r/w 0000_0000h 39.3.4/ 941 400b_8008 modulo (ftm2_mod) 32 r/w 0000_0000h 39.3.5/ 942 400b_800c channel (n) status and control (ftm2_c0sc) 32 r/w 0000_0000h 39.3.6/ 943 400b_8010 channel (n) value (ftm2_c0v) 32 r/w 0000_0000h 39.3.7/ 946 400b_8014 channel (n) status and control (ftm2_c1sc) 32 r/w 0000_0000h 39.3.6/ 943 400b_8018 channel (n) value (ftm2_c1v) 32 r/w 0000_0000h 39.3.7/ 946 400b_801c channel (n) status and control (ftm2_c2sc) 32 r/w 0000_0000h 39.3.6/ 943 400b_8020 channel (n) value (ftm2_c2v) 32 r/w 0000_0000h 39.3.7/ 946 400b_8024 channel (n) status and control (ftm2_c3sc) 32 r/w 0000_0000h 39.3.6/ 943 400b_8028 channel (n) value (ftm2_c3v) 32 r/w 0000_0000h 39.3.7/ 946 400b_802c channel (n) status and control (ftm2_c4sc) 32 r/w 0000_0000h 39.3.6/ 943 400b_8030 channel (n) value (ftm2_c4v) 32 r/w 0000_0000h 39.3.7/ 946 400b_8034 channel (n) status and control (ftm2_c5sc) 32 r/w 0000_0000h 39.3.6/ 943 400b_8038 channel (n) value (ftm2_c5v) 32 r/w 0000_0000h 39.3.7/ 946 400b_803c channel (n) status and control (ftm2_c6sc) 32 r/w 0000_0000h 39.3.6/ 943 400b_8040 channel (n) value (ftm2_c6v) 32 r/w 0000_0000h 39.3.7/ 946 400b_8044 channel (n) status and control (ftm2_c7sc) 32 r/w 0000_0000h 39.3.6/ 943 table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 8 freescale semiconductor, inc. ftm memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 400b_8048 channel (n) value (ftm2_c7v) 32 r/w 0000_0000h 39.3.7/ 946 400b_804c counter initial value (ftm2_cntin) 32 r/w 0000_0000h 39.3.8/ 947 400b_8050 capture and compare status (ftm2_status) 32 r/w 0000_0000h 39.3.9/ 947 400b_8054 features mode selection (ftm2_mode) 32 r/w 0000_0004h 39.3.10/ 950 400b_8058 synchronization (ftm2_sync) 32 r/w 0000_0000h 39.3.11/ 951 400b_805c initial state for channels output (ftm2_outinit) 32 r/w 0000_0000h 39.3.12/ 954 400b_8060 output mask (ftm2_outmask) 32 r/w 0000_0000h 39.3.13/ 955 400b_8064 function for linked channels (ftm2_combine) 32 r/w 0000_0000h 39.3.14/ 957 400b_8068 deadtime insertion control (ftm2_deadtime) 32 r/w 0000_0000h 39.3.15/ 962 400b_806c ftm external trigger (ftm2_exttrig) 32 r/w 0000_0000h 39.3.16/ 963 400b_8070 channels polarity (ftm2_pol) 32 r/w 0000_0000h 39.3.17/ 965 400b_8074 fault mode status (ftm2_fms) 32 r/w 0000_0000h 39.3.18/ 967 400b_8078 input capture filter control (ftm2_filter) 32 r/w 0000_0000h 39.3.19/ 969 400b_807c fault control (ftm2_fltctrl) 32 r/w 0000_0000h 39.3.20/ 971 400b_8080 quadrature decoder control and status (ftm2_qdctrl) 32 r/w 0000_0000h 39.3.21/ 973 400b_8084 configuration (ftm2_conf) 32 r/w 0000_0000h 39.3.22/ 975 400b_8088 ftm fault input polarity (ftm2_fltpol) 32 r/w 0000_0000h 39.3.23/ 976 400b_808c synchronization configuration (ftm2_synconf) 32 r/w 0000_0000h 39.3.24/ 978 400b_8090 ftm inverting control (ftm2_invctrl) 32 r/w 0000_0000h 39.3.25/ 980 400b_8094 ftm software output control (ftm2_swoctrl) 32 r/w 0000_0000h 39.3.26/ 981 table continues on the next page... chapter flextimer ftm 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. ftm memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 400b_8098 ftm pwm load (ftm2_pwmload) 32 r/w 0000_0000h 39.3.27/ 983 39.3.3 status and control (ftm x sc contains the overflow status flag and control bits used to configure the interrupt enable, ftm configuration, clock source, and prescaler factor. these controls relate to all channels within this module. addresses: ftm0_sc is 4003_8000h base + 0h offset = 4003_8000h ftm1_sc is 4003_9000h base + 0h offset = 4003_9000h ftm2_sc is 400b_8000h base + 0h offset = 400b_8000h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 tof toie cpwms clks ps w 0 reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ftm x iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero of ier oerlow fla et y harware when the f counter asses the alue in the o reister he of it is cleare y reain the reister while of is set an then writin a to of it ritin a to of has no eect another f oerlow occurs etween the rea an write oerations the write oeration has no eect thereore of reains set inicatin an oerlow has occurre n this case a of interrut request is not lost ue to the clearin sequence or a reious of f counter has not oerlowe f counter has oerlowe o ier oerlow nterrut nale nales f oerlow interruts table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 40 freescale semiconductor, inc. ftm x iel escritions continue fiel escrition isale of interruts use sotware ollin nale of interruts n interrut is enerate when of equals one enteraline elect elects oe his oe coniures the f to oerate in uown countin oe his iel is write rotecte t can e written only when o f counter oerates in u countin oe f counter oerates in uown countin oe l loc ource election elects one o the three f counter cloc sources his iel is write rotecte t can e written only when o o cloc selecte his in eect isales the f counter yste cloc fixe requency cloc xternal cloc rescale factor election elects one o iision actors or the cloc source selecte y l he new rescaler actor aects the cloc source on the next syste cloc cycle ater the new alue is uate into the reister its his iel is write rotecte t can e written only when o iie y iie y iie y iie y iie y iie y iie y iie y ounter f x the cnt register contains the ftm counter value. reset clears the cnt register. writing any value to count updates the counter with its initial value (cntin). when bdm is active, the ftm counter is frozen (this is the value that you may read). chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 941 addresses: ftm0_cnt is 4003_8000h base + 4h offset = 4003_8004h ftm1_cnt is 4003_9000h base + 4h offset = 4003_9004h ftm2_cnt is 400b_8000h base + 4h offset = 400b_8004h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 count w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ftm x iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero ou ounter alue oulo f x o the modulo register contains the modulo value for the ftm counter. after the ftm counter reaches the modulo value, the overflow flag (tof) becomes set at the next clock, and the next value of ftm counter depends on the selected counting method ( counter ). writing to the mod register latches the value into a buffer. the mod register is updated with the value of its write buffer according to registers updated from write buffers . if ftmen = 0, this write coherency mechanism may be manually reset by writing to the sc register (whether bdm is active or not). it is recommended to initialize the ftm counter (write to cnt) before writing to the mod register to avoid confusion about when the first counter overflow will occur. addresses: ftm0_mod is 4003_8000h base + 8h offset = 4003_8008h ftm1_mod is 4003_9000h base + 8h offset = 4003_9008h ftm2_mod is 400b_8000h base + 8h offset = 400b_8008h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r reserved mod w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ftm x o iel escritions fiel escrition resere his iel is resere table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 42 freescale semiconductor, inc. ftm x o iel escritions continue fiel escrition o oulo alue hannel n tatus an ontrol f x cnsc contains the channel-interrupt-status flag and control bits used to configure the interrupt enable, channel configuration, and pin function. table 39-67. mode, edge, and level selection decapen combine cpwms msnb:msna elsnb:elsna mode configuration x x x xx 0 none pin not used for ftm table continues on the next page... chapter flextimer ftm 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 4 table 39-67. mode, edge, and level selection (continued) decapen combine cpwms msnb:msna elsnb:elsna mode configuration 0 0 0 0 1 input capture capture on rising edge only 10 capture on falling edge only 11 capture on rising or falling edge 1 1 output compare toggle output on match 10 clear output on match 11 set output on match 1x 10 edge-aligned pwm high-true pulses (clear output on match) x1 low-true pulses (set output on match) 1 xx 10 center-aligned pwm high-true pulses (clear output on match-up) x1 low-true pulses (set output on match-up) 1 0 xx 10 combine pwm high-true pulses (set on channel (n) match, and clear on channel (n+1) match) x1 low-true pulses (clear on channel (n) match, and set on channel (n +1) match) 1 0 0 x0 see the following table ( table 39-8 ). dual edge capture mode one-shot capture mode x1 continuous capture mode memory map and register definition k60 sub-family reference manual, rev. 6, nov 2011 944 freescale semiconductor, inc. table 39-68. dual edge capture mode ? edge polarity selection elsnb elsna channel port enable detected edges 0 0 disabled no edge 0 1 enabled rising edge 1 0 enabled falling edge 1 1 enabled rising and falling edges addresses: ftm0_c0sc is 4003_8000h base + ch offset = 4003_800ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 chf chie msb msa elsb elsa 0 dma w 0 reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ftm x n iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero hf hannel fla et y harware when an eent occurs on the channel hf is cleare y reain the reister while hnf is set an then writin a to the hf it ritin a to hf has no eect another eent occurs etween the rea an write oerations the write oeration has no eect thereore hf reains set inicatin an eent has occurre n this case a hf interrut request is not lost ue to the clearin sequence or a reious hf o channel eent has occurre channel eent has occurre h hannel nterrut nale nales channel interruts isale channel interruts use sotware ollin nale channel interruts hannel oe elect use or urther selections in the channel loic ts unctionality is eenent on the channel oe ee ale table continues on the next page... chapter flextimer ftm 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 4 ftm x n iel escritions continue fiel escrition his iel is write rotecte t can e written only when o hannel oe elect use or urther selections in the channel loic ts unctionality is eenent on the channel oe ee ale his iel is write rotecte t can e written only when o l e or leel elect he unctionality o l an l eens on the channel oe ee ale his iel is write rotecte t can e written only when o l e or leel elect he unctionality o l an l eens on the channel oe ee ale his iel is write rotecte t can e written only when o resere his reaonly iel is resere an always has the alue ero nale nales transers or the channel isale transers nale transers hannel n alue f x these registers contain the captured ftm counter value for the input modes or the match value for the output modes. in input capture, capture test, and dual edge capture modes, any write to a cnv register is ignored. in output modes, writing to a cnv register latches the value into a buffer. a cnv register is updated with the value of its write buffer according to registers updated from write buffers . if ftmen = 0, this write coherency mechanism may be manually reset by writing to the cnsc register (whether bdm mode is active or not). addresses: ftm0_c0v is 4003_8000h base + 10h offset = 4003_8010h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 val w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 memory map and register definition k60 sub-family reference manual, rev. 6, nov 2011 946 freescale semiconductor, inc. ftm x n iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero l hannel alue ature f counter alue o the inut oes or the atch alue or the outut oes ounter nitial alue f x the counter initial value register contains the initial value for the ftm counter. writing to the cntin register latches the value into a buffer. the cntin register is updated with the value of its write buffer according to registers updated from write buffers . the first time that the ftm clock is selected (first write to change the clks bits to a non-zero value), the ftm counter starts with the value 0x0000. to avoid this behavior, before the first write to select the ftm clock, write the new value to the the cntin register and then initialize the ftm counter (write any value to the cnt register). addresses: ftm0_cntin is 4003_8000h base + 4ch offset = 4003_804ch ftm1_cntin is 4003_9000h base + 4ch offset = 4003_904ch ftm2_cntin is 400b_8000h base + 4ch offset = 400b_804ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r reserved init w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ftm x iel escritions fiel escrition resere his iel is resere nitial alue o the f ounter ature an oare tatus f x u the status register contains a copy of the status flag chnf bit (in cnsc) for each ftm channel for software convenience. chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 947 each chnf bit in status is a mirror of chnf bit in cnsc. all chnf bits can be checked using only one read of status. all chnf bits can be cleared by reading status followed by writing 0x00 to status. hardware sets the individual channel flags when an event occurs on the channel. chf is cleared by reading status while chnf is set and then writing a 0 to the chf bit. writing a 1 to chf has no effect. if another event occurs between the read and write operations, the write operation has no effect; therefore, chf remains set indicating an event has occurred. in this case a chf interrupt request is not lost due to the clearing sequence for a previous chf. note the status register should be used only combine mode. addresses: ftm0_status is 4003_8000h base + 50h offset = 4003_8050h ftm1_status is 4003_9000h base + 50h offset = 4003_9050h ftm2_status is 400b_8000h base + 50h offset = 400b_8050h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 ch7f ch6f ch5f ch4f ch3f ch2f ch1f ch0f w 0 0 0 0 0 0 0 0 reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ftm x u iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero hf hannel fla ee the reister escrition o channel eent has occurre channel eent has occurre hf hannel fla ee the reister escrition o channel eent has occurre channel eent has occurre hf hannel fla ee the reister escrition table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 48 freescale semiconductor, inc. ftm x u iel escritions continue fiel escrition o channel eent has occurre channel eent has occurre hf hannel fla ee the reister escrition o channel eent has occurre channel eent has occurre hf hannel fla ee the reister escrition o channel eent has occurre channel eent has occurre hf hannel fla ee the reister escrition o channel eent has occurre channel eent has occurre hf hannel fla ee the reister escrition o channel eent has occurre channel eent has occurre hf hannel fla ee the reister escrition o channel eent has occurre channel eent has occurre hater flexier f ufaily reerence anual re o freescale eiconuctor nc 39.3.10 features mode selection (ftm x o this register contains the control bits used to configure the fault interrupt and fault control, capture test mode, pwm synchronization, write protection, channel output initialization, and enable the enhanced features of the ftm. these controls relate to all channels within this module. addresses: ftm0_mode is 4003_8000h base + 54h offset = 4003_8054h ftm1_mode is 4003_9000h base + 54h offset = 4003_9054h ftm2_mode is 400b_8000h base + 54h offset = 400b_8054h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 faultie faultm captest pwmsync wpdis init ftmen w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 ftm x o iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero ful fault nterrut nale nales the eneration o an interrut when a ault is etecte y f an the f ault control is enale fault control interrut is isale fault control interrut is enale ful fault ontrol oe eines the f ault control oe his iel is write rotecte t can e written only when o fault control is isale or all channels fault control is enale or een channels only channels an an the selecte oe is the anual ault clearin fault control is enale or all channels an the selecte oe is the anual ault clearin fault control is enale or all channels an the selecte oe is the autoatic ault clearin table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 0 freescale semiconductor, inc. ftm x o iel escritions continue fiel escrition ature est oe nale nales the cature test oe his iel is write rotecte t can e written only when o ature test oe is isale ature test oe is enale ynchroniation oe elects which triers can e use y o n ou an f counter synchroniation ynchroniation he it coniures the synchroniation when o is ero o restrictions otware an harware triers can e use y o n ou an f counter synchroniation otware trier can only e use y o an n synchroniation an harware triers can only e use y ou an f counter synchroniation rite rotection isale hen write rotection is enale write rotecte its can not e written hen write rotection is isale write rotecte its can e written he it is the neation o the it is cleare when is written to is set when it is rea as a an then is written to ritin to has no eect rite rotection is enale rite rotection is isale nitialie the hannels outut hen a is written to it the channels outut is initialie accorin to the state o their corresonin it in the ou reister ritin a to it has no eect he it is always rea as f f nale his iel is write rotecte t can e written only when o only the coatile reisters irst set o reisters can e use without any restriction o not use the fseciic reisters ll reisters incluin the fseciic reisters secon set o reisters are aailale or use with no restrictions ynchroniation f x this register configures the pwm synchronization. a synchronization event can perform the synchronized update of mod, cv, and outmask registers with the value of their write buffer and the ftm counter initialization. chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 951 note the software trigger (swsync bit) and hardware triggers (trig0, trig1, and trig2 bits) have a potential conflict if used together when syncmode = 0. it is recommended using only hardware or software triggers but not both at the same time, otherwise unpredictable behavior is likely to happen. the selection of the loading point (cntmax and cntmin bits) is intended to provide the update of mod, cntin, and cnv registers across all enabled channels simultaneously. the use of the loading point selection together with syncmode = 0 and hardware trigger selection (trig0, trig1, or trig2 bits) is likely to result in unpredictable behavior. the synchronization event selection also depends on the pwmsync (mode register) and syncmode (synconf register) bits. see pwm synchronization . addresses: ftm0_sync is 4003_8000h base + 58h offset = 4003_8058h ftm1_sync is 4003_9000h base + 58h offset = 4003_9058h ftm2_sync is 400b_8000h base + 58h offset = 400b_8058h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 swsync trig2 trig1 trig0 synchom reinit cntmax cntmin w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ftm x iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero ynchroniation otware rier elects the sotware trier as the synchroniation trier he sotware trier haens when a is written to it table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 2 freescale semiconductor, inc. ftm x iel escritions continue fiel escrition otware trier is not selecte otware trier is selecte r ynchroniation harware rier nales harware trier to the synchroniation harware trier haens when a risin ee is etecte at the trier inut sinal rier is isale rier is enale r ynchroniation harware rier nales harware trier to the synchroniation harware trier haens when a risin ee is etecte at the trier inut sinal rier is isale rier is enale r ynchroniation harware rier nales harware trier to the synchroniation harware trier haens when a risin ee is etecte at the trier inut sinal rier is isale rier is enale ho outut as ynchroniation elects when the ou reister is uate with the alue o its uer ou reister is uate with the alue o its uer in all risin ees o the syste cloc ou reister is uate with the alue o its uer only y the synchroniation r f ounter reinitialiation y ynchroniation f ounter ynchroniation eterines i the f counter is reinitialie when the selecte trier or the synchroniation is etecte he r it coniures the synchroniation when o is ero f counter continues to count norally f counter is uate with its initial alue when the selecte trier is etecte axiu loain oint enale elects the axiu loain oint to synchroniation ounary ycle an loain oints is one the selecte loain oint is when the f counter reaches its axiu alue o reister he axiu loain oint is isale he axiu loain oint is enale iniu loain oint enale elects the iniu loain oint to synchroniation ounary ycle an loain oints is one the selecte loain oint is when the f counter reaches its iniu alue reister table continues on the next page... chapter flextimer ftm 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. ftm x iel escritions continue fiel escrition he iniu loain oint is isale he iniu loain oint is enale nitial tate or hannels outut f x ou resses: fou is h ase h oset h fou is h ase h oset h fou is h ase h oset h it r ho ho ho ho ho ho ho ho reset f x ou iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero ho hannel outut nitialiation alue elects the alue that is orce into the channel outut when the initialiation occurs he initialiation alue is he initialiation alue is ho hannel outut nitialiation alue elects the alue that is orce into the channel outut when the initialiation occurs he initialiation alue is he initialiation alue is ho hannel outut nitialiation alue elects the alue that is orce into the channel outut when the initialiation occurs he initialiation alue is he initialiation alue is ho hannel outut nitialiation alue elects the alue that is orce into the channel outut when the initialiation occurs he initialiation alue is he initialiation alue is ho hannel outut nitialiation alue table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 4 freescale semiconductor, inc. ftm x ou iel escritions continue fiel escrition elects the alue that is orce into the channel outut when the initialiation occurs he initialiation alue is he initialiation alue is ho hannel outut nitialiation alue elects the alue that is orce into the channel outut when the initialiation occurs he initialiation alue is he initialiation alue is ho hannel outut nitialiation alue elects the alue that is orce into the channel outut when the initialiation occurs he initialiation alue is he initialiation alue is ho hannel outut nitialiation alue elects the alue that is orce into the channel outut when the initialiation occurs he initialiation alue is he initialiation alue is outut as f x ou this register provides a mask for each ftm channel. the mask of a channel determines if its output responds (that is, it is masked or not) when a match occurs. this feature is used for bldc control where the pwm signal is presented to an electric motor at specific times to provide electronic commutation. any write to the outmask register, stores the value in its write buffer. the register is updated with the value of its write buffer according to pwm synchronization . addresses: ftm0_outmask is 4003_8000h base + 60h offset = 4003_8060h ftm1_outmask is 4003_9000h base + 60h offset = 4003_9060h ftm2_outmask is 400b_8000h base + 60h offset = 400b_8060h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 ch7om ch6om ch5om ch4om ch3om ch2om ch1om ch0om w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 955 ftm x ou iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero ho hannel outut as eines i the channel outut is ase orce to its inactie state or unase it continues to oerate norally hannel outut is not ase t continues to oerate norally hannel outut is ase t is orce to its inactie state ho hannel outut as eines i the channel outut is ase orce to its inactie state or unase it continues to oerate norally hannel outut is not ase t continues to oerate norally hannel outut is ase t is orce to its inactie state ho hannel outut as eines i the channel outut is ase orce to its inactie state or unase it continues to oerate norally hannel outut is not ase t continues to oerate norally hannel outut is ase t is orce to its inactie state ho hannel outut as eines i the channel outut is ase orce to its inactie state or unase it continues to oerate norally hannel outut is not ase t continues to oerate norally hannel outut is ase t is orce to its inactie state ho hannel outut as eines i the channel outut is ase orce to its inactie state or unase it continues to oerate norally hannel outut is not ase t continues to oerate norally hannel outut is ase t is orce to its inactie state ho hannel outut as eines i the channel outut is ase orce to its inactie state or unase it continues to oerate norally hannel outut is not ase t continues to oerate norally hannel outut is ase t is orce to its inactie state ho hannel outut as eines i the channel outut is ase orce to its inactie state or unase it continues to oerate norally hannel outut is not ase t continues to oerate norally hannel outut is ase t is orce to its inactie state table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 6 freescale semiconductor, inc. ftm x ou iel escritions continue fiel escrition ho hannel outut as eines i the channel outut is ase orce to its inactie state or unase it continues to oerate norally hannel outut is not ase t continues to oerate norally hannel outut is ase t is orce to its inactie state function or line hannels f x o this register contains the control bits used to configure the fault control, synchronization, deadtime insertion, dual edge capture mode, complementary, and combine mode for each pair of channels (n) and (n+1), where n equals 0, 2, 4, and 6. addresses: ftm0_combine is 4003_8000h base + 64h offset = 4003_8064h ftm1_combine is 4003_9000h base + 64h offset = 4003_9064h ftm2_combine is 400b_8000h base + 64h offset = 400b_8064h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 faulten3 syncen3 dten3 decap3 decapen3 comp3 combine3 0 faulten2 syncen2 dten2 decap2 decapen2 comp2 combine2 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 faulten1 syncen1 dten1 decap1 decapen1 comp1 combine1 0 faulten0 syncen0 dten0 decap0 decapen0 comp0 combine0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ftm x o iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero ful fault ontrol nale or n nales the ault control in channels n an n his iel is write rotecte t can e written only when o he ault control in this air o channels is isale he ault control in this air o channels is enale table continues on the next page... chapter flextimer ftm 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 7 ftm x o iel escritions continue fiel escrition ynchroniation nale or n nales synchroniation o reisters n an n he synchroniation in this air o channels is isale he synchroniation in this air o channels is enale eatie nale or n nales the eatie insertion in the channels n an n his iel is write rotecte t can e written only when o he eatie insertion in this air o channels is isale he eatie insertion in this air o channels is enale ual e ature oe atures or n nales the cature o the f counter alue accorin to the channel n inut eent an the coniuration o the ual ee cature its his iel alies only when f an it is cleare autoatically y harware i ual ee cature oneshot oe is selecte an when the cature o channel n eent is ae he ual ee catures are inactie he ual ee catures are actie ual e ature oe nale or n nales the ual ee cature oe in the channels n an n his it reconiures the unction o n ln:ln an ln:ln its in ual ee cature oe accorin to ale his iel alies only when f his iel is write rotecte t can e written only when o he ual ee cature oe in this air o channels is isale he ual ee cature oe in this air o channels is enale o oleent o hannel n or n nales coleentary oe or the coine channels n coleentary oe the channel n outut is the inerse o the channel n outut his iel is write rotecte t can e written only when o he channel n outut is the sae as the channel n outut he channel n outut is the coleent o the channel n outut o oine hannels or n nales the coine eature or channels n an n his iel is write rotecte t can e written only when o hannels n an n are ineenent hannels n an n are coine table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 8 freescale semiconductor, inc. ftm x o iel escritions continue fiel escrition resere his reaonly iel is resere an always has the alue ero ful fault ontrol nale or n nales the ault control in channels n an n his iel is write rotecte t can e written only when o he ault control in this air o channels is isale he ault control in this air o channels is enale ynchroniation nale or n nales synchroniation o reisters n an n he synchroniation in this air o channels is isale he synchroniation in this air o channels is enale eatie nale or n nales the eatie insertion in the channels n an n his iel is write rotecte t can e written only when o he eatie insertion in this air o channels is isale he eatie insertion in this air o channels is enale ual e ature oe atures or n nales the cature o the f counter alue accorin to the channel n inut eent an the coniuration o the ual ee cature its his iel alies only when f an it is cleare autoatically y harware i ual ee cature oneshot oe is selecte an when the cature o channel n eent is ae he ual ee catures are inactie he ual ee catures are actie ual e ature oe nale or n nales the ual ee cature oe in the channels n an n his it reconiures the unction o n ln:ln an ln:ln its in ual ee cature oe accorin to ale his iel alies only when f his iel is write rotecte t can e written only when o he ual ee cature oe in this air o channels is isale he ual ee cature oe in this air o channels is enale o oleent o hannel n or n nales coleentary oe or the coine channels n coleentary oe the channel n outut is the inerse o the channel n outut his iel is write rotecte t can e written only when o table continues on the next page... chapter flextimer ftm 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. ftm x o iel escritions continue fiel escrition he channel n outut is the sae as the channel n outut he channel n outut is the coleent o the channel n outut o oine hannels or n nales the coine eature or channels n an n his iel is write rotecte t can e written only when o hannels n an n are ineenent hannels n an n are coine resere his reaonly iel is resere an always has the alue ero ful fault ontrol nale or n nales the ault control in channels n an n his iel is write rotecte t can e written only when o he ault control in this air o channels is isale he ault control in this air o channels is enale ynchroniation nale or n nales synchroniation o reisters n an n he synchroniation in this air o channels is isale he synchroniation in this air o channels is enale eatie nale or n nales the eatie insertion in the channels n an n his iel is write rotecte t can e written only when o he eatie insertion in this air o channels is isale he eatie insertion in this air o channels is enale ual e ature oe atures or n nales the cature o the f counter alue accorin to the channel n inut eent an the coniuration o the ual ee cature its his iel alies only when f an it is cleare autoatically y harware i ual ee cature oneshot oe is selecte an when the cature o channel n eent is ae he ual ee catures are inactie he ual ee catures are actie ual e ature oe nale or n nales the ual ee cature oe in the channels n an n his it reconiures the unction o n ln:ln an ln:ln its in ual ee cature oe accorin to ale his iel alies only when f his iel is write rotecte t can e written only when o table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 60 freescale semiconductor, inc. ftm x o iel escritions continue fiel escrition he ual ee cature oe in this air o channels is isale he ual ee cature oe in this air o channels is enale o oleent o hannel n or n nales coleentary oe or the coine channels n coleentary oe the channel n outut is the inerse o the channel n outut his iel is write rotecte t can e written only when o he channel n outut is the sae as the channel n outut he channel n outut is the coleent o the channel n outut o oine hannels or n nales the coine eature or channels n an n his iel is write rotecte t can e written only when o hannels n an n are ineenent hannels n an n are coine resere his reaonly iel is resere an always has the alue ero ful fault ontrol nale or n nales the ault control in channels n an n his iel is write rotecte t can e written only when o he ault control in this air o channels is isale he ault control in this air o channels is enale ynchroniation nale or n nales synchroniation o reisters n an n he synchroniation in this air o channels is isale he synchroniation in this air o channels is enale eatie nale or n nales the eatie insertion in the channels n an n his iel is write rotecte t can e written only when o he eatie insertion in this air o channels is isale he eatie insertion in this air o channels is enale ual e ature oe atures or n nales the cature o the f counter alue accorin to the channel n inut eent an the coniuration o the ual ee cature its his iel alies only when f an it is cleare autoatically y harware i ual ee cature oneshot oe is selecte an when the cature o channel n eent is ae he ual ee catures are inactie he ual ee catures are actie table continues on the next page... chapter flextimer ftm 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 61 ftm x o iel escritions continue fiel escrition ual e ature oe nale or n nales the ual ee cature oe in the channels n an n his it reconiures the unction o n ln:ln an ln:ln its in ual ee cature oe accorin to ale his iel alies only when f his iel is write rotecte t can e written only when o he ual ee cature oe in this air o channels is isale he ual ee cature oe in this air o channels is enale o oleent o hannel n or n nales coleentary oe or the coine channels n coleentary oe the channel n outut is the inerse o the channel n outut his iel is write rotecte t can e written only when o he channel n outut is the sae as the channel n outut he channel n outut is the coleent o the channel n outut o oine hannels or n nales the coine eature or channels n an n his iel is write rotecte t can e written only when o hannels n an n are ineenent hannels n an n are coine eatie nsertion ontrol f x this register selects the deadtime prescaler factor and deadtime value. all ftm channels use this clock prescaler and this deadtime value for the deadtime insertion. addresses: ftm0_deadtime is 4003_8000h base + 68h offset = 4003_8068h ftm1_deadtime is 4003_9000h base + 68h offset = 4003_9068h ftm2_deadtime is 400b_8000h base + 68h offset = 400b_8068h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 dtps dtval w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ftm x iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 62 freescale semiconductor, inc. ftm x iel escritions continue fiel escrition eatie rescaler alue elects the iision actor o the syste cloc his rescale cloc is use y the eatie counter his iel is write rotecte t can e written only when o x iie the syste cloc y iie the syste cloc y iie the syste cloc y l eatie alue elects the eatie insertion alue or the eatie counter he eatie counter is cloce y a scale ersion o the syste cloc ee the escrition o eatie insert alue l l selects the nuer o eatie counts inserte as ollows: hen l is no counts are inserte hen l is count is inserte hen l is counts are inserte his attern continues u to a ossile counts his iel is write rotecte t can e written only when o f xternal rier f x r this register indicates when a channel trigger was generated, enables the generation of a trigger when the ftm counter is equal to its initial value, and selects which channels are used in the generation of the channel triggers. several channels can be selected to generate multiple triggers in one pwm period. channels 6 and 7 are not used to generate channel triggers. chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 963 addresses: ftm0_exttrig is 4003_8000h base + 6ch offset = 4003_806ch ftm1_exttrig is 4003_9000h base + 6ch offset = 4003_906ch ftm2_exttrig is 400b_8000h base + 6ch offset = 400b_806ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r reserved[bit 8] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r reserved[7:0] trigf inittrigen ch1trig ch0trig ch5trig ch4trig ch3trig ch2trig w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ftm x r iel escritions fiel escrition resere his iel is resere rf hannel rier fla et y harware when a channel trier is enerate lear rf y reain r while rf is set an then writin a to rf ritin a to rf has no eect another channel trier is enerate eore the clearin sequence is colete the sequence is reset so rf reains set ater the clear sequence is colete or the earlier rf o channel trier was enerate channel trier was enerate r nitialiation rier nale nales the eneration o the trier when the f counter is equal to the reister he eneration o initialiation trier is isale he eneration o initialiation trier is enale hr hannel rier nale nale the eneration o the channel trier when the f counter is equal to the n reister he eneration o the channel trier is isale he eneration o the channel trier is enale hr hannel rier nale nale the eneration o the channel trier when the f counter is equal to the n reister he eneration o the channel trier is isale he eneration o the channel trier is enale hr hannel rier nale table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 64 freescale semiconductor, inc. ftm x r iel escritions continue fiel escrition nale the eneration o the channel trier when the f counter is equal to the n reister he eneration o the channel trier is isale he eneration o the channel trier is enale hr hannel rier nale nale the eneration o the channel trier when the f counter is equal to the n reister he eneration o the channel trier is isale he eneration o the channel trier is enale hr hannel rier nale nale the eneration o the channel trier when the f counter is equal to the n reister he eneration o the channel trier is isale he eneration o the channel trier is enale hr hannel rier nale nale the eneration o the channel trier when the f counter is equal to the n reister he eneration o the channel trier is isale he eneration o the channel trier is enale hannels olarity f x ol this register defines the output polarity of the ftm channels. note the safe value that is driven in a channel output when the fault control is enabled and a fault condition is detected is the inactive state of the channel. that is, the safe value of a channel is the value of its pol bit. addresses: ftm0_pol is 4003_8000h base + 70h offset = 4003_8070h ftm1_pol is 4003_9000h base + 70h offset = 4003_9070h ftm2_pol is 400b_8000h base + 70h offset = 400b_8070h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r reserved pol7 pol6 pol5 pol4 pol3 pol2 pol1 pol0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 965 ftm x ol iel escritions fiel escrition resere his iel is resere ol hannel olarity eines the olarity o the channel outut his iel is write rotecte t can e written only when o he channel olarity is actie hih he channel olarity is actie low ol hannel olarity eines the olarity o the channel outut his iel is write rotecte t can e written only when o he channel olarity is actie hih he channel olarity is actie low ol hannel olarity eines the olarity o the channel outut his iel is write rotecte t can e written only when o he channel olarity is actie hih he channel olarity is actie low ol hannel olarity eines the olarity o the channel outut his iel is write rotecte t can e written only when o he channel olarity is actie hih he channel olarity is actie low ol hannel olarity eines the olarity o the channel outut his iel is write rotecte t can e written only when o he channel olarity is actie hih he channel olarity is actie low ol hannel olarity eines the olarity o the channel outut his iel is write rotecte t can e written only when o he channel olarity is actie hih he channel olarity is actie low ol hannel olarity eines the olarity o the channel outut his iel is write rotecte t can e written only when o table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 66 freescale semiconductor, inc. ftm x ol iel escritions continue fiel escrition he channel olarity is actie hih he channel olarity is actie low ol hannel olarity eines the olarity o the channel outut his iel is write rotecte t can e written only when o he channel olarity is actie hih he channel olarity is actie low fault oe tatus f x f this register contains the fault detection flags, write protection enable bit, and the logic or of the enabled fault inputs. addresses: ftm0_fms is 4003_8000h base + 74h offset = 4003_8074h ftm1_fms is 4003_9000h base + 74h offset = 4003_9074h ftm2_fms is 400b_8000h base + 74h offset = 400b_8074h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 faultf wpen faultin 0 faultf3 faultf2 faultf1 faultf0 w 0 0 0 0 0 reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ftm x f iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero table continues on the next page... chapter flextimer ftm 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 67 ftm x f iel escritions continue fiel escrition fulf fault etection fla reresents the loic or o the iniiual fulf its where lear fulf y reain the f reister while fulf is set an then writin a to fulf while there is no existin ault conition at the enale ault inuts ritin a to fulf has no eect another ault conition is etecte in an enale ault inut eore the clearin sequence is colete the sequence is reset so fulf reains set ater the clearin sequence is colete or the earlier ault conition fulf is also cleare when fulf its are cleare iniiually o ault conition was etecte ault conition was etecte rite rotection nale he it is the neation o the it is set when is written to it is cleare when it is rea as a an then is written to ritin to has no eect rite rotection is isale rite rotecte its can e written rite rotection is enale rite rotecte its cannot e written ful fault nuts reresents the loic or o the enale ault inuts ater their ilter i their ilter is enale when ault control is enale he loic or o the enale ault inuts is he loic or o the enale ault inuts is resere his reaonly iel is resere an always has the alue ero fulf fault etection fla et y harware when ault control is enale the corresonin ault inut is enale an a ault conition is etecte at the ault inut lear fulf y reain the f reister while fulf is set an then writin a to fulf while there is no existin ault conition at the the corresonin ault inut ritin a to fulf has no eect fulf it is also cleare when fulf it is cleare another ault conition is etecte at the corresonin ault inut eore the clearin sequence is colete the sequence is reset so fulf reains set ater the clearin sequence is colete or the earlier ault conition o ault conition was etecte at the ault inut ault conition was etecte at the ault inut fulf fault etection fla et y harware when ault control is enale the corresonin ault inut is enale an a ault conition is etecte at the ault inut lear fulf y reain the f reister while fulf is set an then writin a to fulf while there is no existin ault conition at the the corresonin ault inut ritin a to fulf has no eect fulf it is also cleare when fulf it is cleare another ault conition is etecte at the corresonin ault inut eore the clearin sequence is colete the sequence is reset so fulf reains set ater the clearin sequence is colete or the earlier ault conition table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 68 freescale semiconductor, inc. ftm x f iel escritions continue fiel escrition o ault conition was etecte at the ault inut ault conition was etecte at the ault inut fulf fault etection fla et y harware when ault control is enale the corresonin ault inut is enale an a ault conition is etecte at the ault inut lear fulf y reain the f reister while fulf is set an then writin a to fulf while there is no existin ault conition at the the corresonin ault inut ritin a to fulf has no eect fulf it is also cleare when fulf it is cleare another ault conition is etecte at the corresonin ault inut eore the clearin sequence is colete the sequence is reset so fulf reains set ater the clearin sequence is colete or the earlier ault conition o ault conition was etecte at the ault inut ault conition was etecte at the ault inut fulf fault etection fla et y harware when ault control is enale the corresonin ault inut is enale an a ault conition is etecte at the ault inut lear fulf y reain the f reister while fulf is set an then writin a to fulf while there is no existin ault conition at the the corresonin ault inut ritin a to fulf has no eect fulf it is also cleare when fulf it is cleare another ault conition is etecte at the corresonin ault inut eore the clearin sequence is colete the sequence is reset so fulf reains set ater the clearin sequence is colete or the earlier ault conition o ault conition was etecte at the ault inut ault conition was etecte at the ault inut nut ature filter ontrol f x flr this register selects the filter value for the inputs of channels. channels 4, 5, 6 and 7 do not have an input filter. note writing to the filter register has immediate effect and must be done only when the channels 0, 1, 2, and 3 are not in input modes. failure to do this could result in a missing valid signal. chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 969 addresses: ftm0_filter is 4003_8000h base + 78h offset = 4003_8078h ftm1_filter is 4003_9000h base + 78h offset = 4003_9078h ftm2_filter is 400b_8000h base + 78h offset = 400b_8078h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r reserved ch3fval ch2fval ch1fval ch0fval w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ftm x flr iel escritions fiel escrition resere his iel is resere hfl hannel nut filter elects the ilter alue or the channel inut he ilter is isale when the alue is ero hfl hannel nut filter elects the ilter alue or the channel inut he ilter is isale when the alue is ero hfl hannel nut filter elects the ilter alue or the channel inut he ilter is isale when the alue is ero hfl hannel nut filter elects the ilter alue or the channel inut he ilter is isale when the alue is ero eory a an reister einition ufaily reerence anual re o freescale eiconuctor nc 39.3.20 fault control (ftm x flrl this register selects the filter value for the fault inputs, enables the fault inputs and the fault inputs filter. addresses: ftm0_fltctrl is 4003_8000h base + 7ch offset = 4003_807ch ftm1_fltctrl is 4003_9000h base + 7ch offset = 4003_907ch ftm2_fltctrl is 400b_8000h base + 7ch offset = 400b_807ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 ffval ffltr3en ffltr2en ffltr1en ffltr0en fault3en fault2en fault1en fault0en w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ftm x flrl iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero ffl fault nut filter elects the ilter alue or the ault inuts he ault ilter is isale when the alue is ero o: ritin to this iel has ieiate eect an ust e one only when the ault control or all ault inuts are isale failure to o this coul result in a issin ault etection fflr fault nut filter nale nales the ilter or the ault inut his iel is write rotecte t can e written only when o fault inut ilter is isale fault inut ilter is enale fflr fault nut filter nale nales the ilter or the ault inut his iel is write rotecte t can e written only when o fault inut ilter is isale fault inut ilter is enale table continues on the next page... chapter flextimer ftm 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 71 ftm x flrl iel escritions continue fiel escrition fflr fault nut filter nale nales the ilter or the ault inut his iel is write rotecte t can e written only when o fault inut ilter is isale fault inut ilter is enale fflr fault nut filter nale nales the ilter or the ault inut his iel is write rotecte t can e written only when o fault inut ilter is isale fault inut ilter is enale ful fault nut nale nales the ault inut his iel is write rotecte t can e written only when o fault inut is isale fault inut is enale ful fault nut nale nales the ault inut his iel is write rotecte t can e written only when o fault inut is isale fault inut is enale ful fault nut nale nales the ault inut his iel is write rotecte t can e written only when o fault inut is isale fault inut is enale ful fault nut nale nales the ault inut his iel is write rotecte t can e written only when o fault inut is isale fault inut is enale eory a an reister einition ufaily reerence anual re o freescale eiconuctor nc 39.3.21 quadrature decoder control and status (ftm x rl this register has the control and status bits for the quadrature decoder mode. addresses: ftm0_qdctrl is 4003_8000h base + 80h offset = 4003_8080h ftm1_qdctrl is 4003_9000h base + 80h offset = 4003_9080h ftm2_qdctrl is 400b_8000h base + 80h offset = 400b_8080h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 phafltren phbfltren phapol phbpol quadmode quadir tofdir quaden w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ftm x rl iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero hflr hase nut filter nale nales the ilter or the quarature ecoer hase inut he ilter alue or the hase inut is eine y the hfl iel o flr he hase ilter is also isale when hfl is ero hase inut ilter is isale hase inut ilter is enale hflr hase nut filter nale nales the ilter or the quarature ecoer hase inut he ilter alue or the hase inut is eine y the hfl iel o flr he hase ilter is also isale when hfl is ero hase inut ilter is isale hase inut ilter is enale hol hase nut olarity elects the olarity or the quarature ecoer hase inut table continues on the next page... chapter flextimer ftm 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 7 ftm x rl iel escritions continue fiel escrition oral olarity hase inut sinal is not inerte eore ientiyin the risin an allin ees o this sinal nerte olarity hase inut sinal is inerte eore ientiyin the risin an allin ees o this sinal hol hase nut olarity elects the olarity or the quarature ecoer hase inut oral olarity hase inut sinal is not inerte eore ientiyin the risin an allin ees o this sinal nerte olarity hase inut sinal is inerte eore ientiyin the risin an allin ees o this sinal uo uarature ecoer oe elects the encoin oe use in the quarature ecoer oe hase an hase encoin oe ount an irection encoin oe ur f ounter irection in uarature ecoer oe nicates the countin irection ountin irection is ecreasin f counter ecreent ountin irection is increasin f counter increent ofr ier oerlow irection in uarature ecoer oe nicates i the of it was set on the to or the otto o countin of it was set on the otto o countin here was an f counter ecreent an f counter chanes ro its iniu alue reister to its axiu alue o reister of it was set on the to o countin here was an f counter increent an f counter chanes ro its axiu alue o reister to its iniu alue reister u uarature ecoer oe nale nales the quarature ecoer oe n this oe the hase an inut sinals control the f counter irection he quarature ecoer oe has receence oer the other oes ee ale his iel is write rotecte t can e written only when o uarature ecoer oe is isale uarature ecoer oe is enale eory a an reister einition ufaily reerence anual re o freescale eiconuctor nc 39.3.22 configuration (ftm x of this register selects the number of times that the ftm counter overflow should occur before the tof bit to be set, the ftm behavior in bdm modes, the use of an external global time base, and the global time base signal generation. addresses: ftm0_conf is 4003_8000h base + 84h offset = 4003_8084h ftm1_conf is 4003_9000h base + 84h offset = 4003_9084h ftm2_conf is 400b_8000h base + 84h offset = 400b_8084h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 gtbeout gtbeen 0 bdmmode 0 numtof w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ftm x of iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero ou loal tie ase outut nales the loal tie ase sinal eneration to other fs loal tie ase sinal eneration is isale loal tie ase sinal eneration is enale loal tie ase enale oniures the f to use an external loal tie ase sinal that is enerate y another f use o an external loal tie ase is isale use o an external loal tie ase is enale resere his reaonly iel is resere an always has the alue ero o oe elects the f ehaior in oe ee oe resere his reaonly iel is resere an always has the alue ero table continues on the next page... chapter flextimer ftm 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 7 ftm x of iel escritions continue fiel escrition uof of frequency elects the ratio etween the nuer o counter oerlows to the nuer o ties the of it is set uof : he of it is set or each counter oerlow uof : he of it is set or the irst counter oerlow ut not or the next oerlow uof : he of it is set or the irst counter oerlow ut not or the next oerlows uof : he of it is set or the irst counter oerlow ut not or the next oerlows his attern continues u to a axiu o f fault nut olarity f x flol this register defines the fault inputs polarity. addresses: ftm0_fltpol is 4003_8000h base + 88h offset = 4003_8088h ftm1_fltpol is 4003_9000h base + 88h offset = 4003_9088h ftm2_fltpol is 400b_8000h base + 88h offset = 400b_8088h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 flt3pol flt2pol flt1pol flt0pol w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ftm x flol iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero flol fault nut olarity eines the olarity o the ault inut his iel is write rotecte t can e written only when o he ault inut olarity is actie hih one at the ault inut inicates a ault he ault inut olarity is actie low ero at the ault inut inicates a ault table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 76 freescale semiconductor, inc. ftm x flol iel escritions continue fiel escrition flol fault nut olarity eines the olarity o the ault inut his iel is write rotecte t can e written only when o he ault inut olarity is actie hih one at the ault inut inicates a ault he ault inut olarity is actie low ero at the ault inut inicates a ault flol fault nut olarity eines the olarity o the ault inut his iel is write rotecte t can e written only when o he ault inut olarity is actie hih one at the ault inut inicates a ault he ault inut olarity is actie low ero at the ault inut inicates a ault flol fault nut olarity eines the olarity o the ault inut his iel is write rotecte t can e written only when o he ault inut olarity is actie hih one at the ault inut inicates a ault he ault inut olarity is actie low ero at the ault inut inicates a ault hater flexier f ufaily reerence anual re o freescale eiconuctor nc 39.3.24 synchronization configuration (ftm x of this register selects the pwm synchronization configuration, swoctrl, invctrl and cntin registers synchronization, if ftm clears the trigj bit (where j = 0, 1, 2) when the hardware trigger j is detected. addresses: ftm0_synconf is 4003_8000h base + 8ch offset = 4003_808ch ftm1_synconf is 4003_9000h base + 8ch offset = 4003_908ch ftm2_synconf is 400b_8000h base + 8ch offset = 400b_808ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 hwsoc hwinvc hwom hwwrbuf hwrstcnt w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 swsoc swinvc swom swwrbuf swrstcnt syncmode 0 swoc invc 0 cntinc 0 hwtrigmode w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ftm x of iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero ho otware outut control synchroniation is actiate y a harware trier harware trier oes not actiate the orl reister synchroniation harware trier actiates the orl reister synchroniation h nertin control synchroniation is actiate y a harware trier harware trier oes not actiate the rl reister synchroniation harware trier actiates the rl reister synchroniation ho outut as synchroniation is actiate y a harware trier harware trier oes not actiate the ou reister synchroniation harware trier actiates the ou reister synchroniation hruf o an reisters synchroniation is actiate y a harware trier harware trier oes not actiate o an reisters synchroniation harware trier actiates o an reisters synchroniation table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 78 freescale semiconductor, inc. ftm x of iel escritions continue fiel escrition hr f counter synchroniation is actiate y a harware trier harware trier oes not actiate the f counter synchroniation harware trier actiates the f counter synchroniation resere his reaonly iel is resere an always has the alue ero o otware outut control synchroniation is actiate y the sotware trier he sotware trier oes not actiate the orl reister synchroniation he sotware trier actiates the orl reister synchroniation nertin control synchroniation is actiate y the sotware trier he sotware trier oes not actiate the rl reister synchroniation he sotware trier actiates the rl reister synchroniation o outut as synchroniation is actiate y the sotware trier he sotware trier oes not actiate the ou reister synchroniation he sotware trier actiates the ou reister synchroniation ruf o an reisters synchroniation is actiate y the sotware trier he sotware trier oes not actiate o an reisters synchroniation he sotware trier actiates o an reisters synchroniation r f counter synchroniation is actiate y the sotware trier he sotware trier oes not actiate the f counter synchroniation he sotware trier actiates the f counter synchroniation o ynchroniation oe elects the synchroniation oe leacy synchroniation is selecte nhance synchroniation is selecte resere his reaonly iel is resere an always has the alue ero o orl reister synchroniation orl reister is uate with its uer alue at all risin ees o syste cloc orl reister is uate with its uer alue y the synchroniation rl reister synchroniation rl reister is uate with its uer alue at all risin ees o syste cloc rl reister is uate with its uer alue y the synchroniation resere his reaonly iel is resere an always has the alue ero reister synchroniation table continues on the next page... chapter flextimer ftm 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 7 ftm x of iel escritions continue fiel escrition reister is uate with its uer alue at all risin ees o syste cloc reister is uate with its uer alue y the synchroniation resere his reaonly iel is resere an always has the alue ero hro harware rier oe f clears the r it when the harware trier is etecte f oes not clear the r it when the harware trier is etecte f nertin ontrol f x rl this register controls controls when the channel (n) output becomes the channel (n+1) output, and channel (n+1) output becomes the channel (n) output. each invmen bit enables the inverting operation for the corresponding pair channels m. this register has a write buffer. the invmen bit is updated by the invctrl register synchronization. addresses: ftm0_invctrl is 4003_8000h base + 90h offset = 4003_8090h ftm1_invctrl is 4003_9000h base + 90h offset = 4003_9090h ftm2_invctrl is 400b_8000h base + 90h offset = 400b_8090h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 inv3en inv2en inv1en inv0en w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ftm x rl iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero air hannels nertin nale nertin is isale nertin is enale air hannels nertin nale nertin is isale nertin is enale air hannels nertin nale table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 80 freescale semiconductor, inc. ftm x rl iel escritions continue fiel escrition nertin is isale nertin is enale air hannels nertin nale nertin is isale nertin is enale f otware outut ontrol f x orl this register enables software control of channel (n) output and defines the value forced to the channel (n) output: ? the chnoc bits enable the control of the corresponding channel (n) output by software. ? the chnocv bits select the value that is forced at the corresponding channel (n) output. this register has a write buffer. the fields are updated by the swoctrl register synchronization. addresses: ftm0_swoctrl is 4003_8000h base + 94h offset = 4003_8094h ftm1_swoctrl is 4003_9000h base + 94h offset = 4003_9094h ftm2_swoctrl is 400b_8000h base + 94h offset = 400b_8094h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r ch7ocv ch6ocv ch5ocv ch4ocv ch3ocv ch2ocv ch1ocv ch0ocv ch7oc ch6oc ch5oc ch4oc ch3oc ch2oc ch1oc ch0oc w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ftm x orl iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero table continues on the next page... chapter flextimer ftm 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 81 ftm x orl iel escritions continue fiel escrition ho hannel otware outut ontrol alue he sotware outut control orces to the channel outut he sotware outut control orces to the channel outut ho hannel otware outut ontrol alue he sotware outut control orces to the channel outut he sotware outut control orces to the channel outut ho hannel otware outut ontrol alue he sotware outut control orces to the channel outut he sotware outut control orces to the channel outut ho hannel otware outut ontrol alue he sotware outut control orces to the channel outut he sotware outut control orces to the channel outut ho hannel otware outut ontrol alue he sotware outut control orces to the channel outut he sotware outut control orces to the channel outut ho hannel otware outut ontrol alue he sotware outut control orces to the channel outut he sotware outut control orces to the channel outut ho hannel otware outut ontrol alue he sotware outut control orces to the channel outut he sotware outut control orces to the channel outut ho hannel otware outut ontrol alue he sotware outut control orces to the channel outut he sotware outut control orces to the channel outut ho hannel otware outut ontrol nale he channel outut is not aecte y sotware outut control he channel outut is aecte y sotware outut control ho hannel otware outut ontrol nale he channel outut is not aecte y sotware outut control he channel outut is aecte y sotware outut control ho hannel otware outut ontrol nale he channel outut is not aecte y sotware outut control he channel outut is aecte y sotware outut control ho hannel otware outut ontrol nale table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 82 freescale semiconductor, inc. ftm x orl iel escritions continue fiel escrition he channel outut is not aecte y sotware outut control he channel outut is aecte y sotware outut control ho hannel otware outut ontrol nale he channel outut is not aecte y sotware outut control he channel outut is aecte y sotware outut control ho hannel otware outut ontrol nale he channel outut is not aecte y sotware outut control he channel outut is aecte y sotware outut control ho hannel otware outut ontrol nale he channel outut is not aecte y sotware outut control he channel outut is aecte y sotware outut control ho hannel otware outut ontrol nale he channel outut is not aecte y sotware outut control he channel outut is aecte y sotware outut control f loa f x lo enables the loading of the mod, cntin, c(n)v, and c(n+1)v registers with the values of their write buffers when the ftm counter changes from the mod register value to its next value or when a channel (j) match occurs. a match occurs for the channel (j) when ftm counter = c(j)v. addresses: ftm0_pwmload is 4003_8000h base + 98h offset = 4003_8098h ftm1_pwmload is 4003_9000h base + 98h offset = 4003_9098h ftm2_pwmload is 400b_8000h base + 98h offset = 400b_8098h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 ldok 0 ch7sel ch6sel ch5sel ch4sel ch3sel ch2sel ch1sel ch0sel w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 983 ftm x lo iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero lo loa nale nales the loain o the o an reisters with the alues o their write uers loain uate alues is isale loain uate alues is enale resere his reaonly iel is resere an always has the alue ero hl hannel elect o not inclue the channel in the atchin rocess nclue the channel in the atchin rocess hl hannel elect o not inclue the channel in the atchin rocess nclue the channel in the atchin rocess hl hannel elect o not inclue the channel in the atchin rocess nclue the channel in the atchin rocess hl hannel elect o not inclue the channel in the atchin rocess nclue the channel in the atchin rocess hl hannel elect o not inclue the channel in the atchin rocess nclue the channel in the atchin rocess hl hannel elect o not inclue the channel in the atchin rocess nclue the channel in the atchin rocess hl hannel elect o not inclue the channel in the atchin rocess nclue the channel in the atchin rocess hl hannel elect o not inclue the channel in the atchin rocess nclue the channel in the atchin rocess eory a an reister einition ufaily reerence anual re o freescale eiconuctor nc 39.4 functional description the following sections describe the ftm features. the notation used in this document to represent the counters and the generation of the signals is shown in the following figure. ftm counter 0 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 prescaler counter channel (n) output counter overflow channel (n) match counter overflow channel (n) match channel (n) match counter overflow ftm counting is up. channel (n) is in high-true epwm mode. ps[2:0] = 001 cntin = 0x0000 mod = 0x0004 cnv = 0x0002 figure 39-166. notation used 39.4.1 clock source ftm module has only one clock domain that is the system clock. 39.4.1.1 counter clock source the clks[1:0] bits in the sc register select one of three possible clock sources for the ftm counter or disable the ftm counter. after any mcu reset, clks[1:0] = 0:0 so no clock source is selected. the clks[1:0] bits may be read or written at any time. disabling the ftm counter by writing 0:0 to the clks[1:0] bits does not affect the ftm counter value or other registers. chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 985 the fixed frequency clock is an alternative clock source for the ftm counter that allows the selection of a clock other than the system clock or an external clock. this clock input is defined by chip integration. refer the chip specific documentation for further information. due to ftm hardware implementation limitations, the frequency of the fixed frequency clock must not exceed 1/2 of the system clock frequency. the external clock passes through a synchronizer clocked by the system clock to assure that counter transitions are properly aligned to system clock transitions.therefore, to meet nyquist criteria considering also jitter, the frequency of the external clock source must not exceed 1/4 of the system clock frequency. 39.4.2 prescaler the selected counter clock source passes through a prescaler that is a 7-bit counter. the value of the prescaler is selected by the ps[2:0] bits. the following figure shows an example of the prescaler counter and ftm counter. ftm counter 0 0 0 0 0 0 0 0 00 0 0 1 1 1 2 2 3 3 1 1 1 1 11 1 1 1 selected input clock prescaler counter ftm counting is up. ps[2:0] = 001 cntin = 0x0000 mod = 0x0003 figure 39-167. example of the prescaler counter 39.4.3 counter the ftm has a 16-bit counter that is used by the channels either for input or output modes. the ftm counter clock is the selected clock divided by the prescaler. the ftm counter has these modes of operation: ? up counting (see up counting ) ? up-down counting (see up-down counting ) ? quadrature mode (see quadrature decoder mode ) functional description k60 sub-family reference manual, rev. 6, nov 2011 986 freescale semiconductor, inc. 39.4.3.1 up counting up counting is selected when (quaden = 0) and (cpwms = 0). cntin defines the starting value of the count and mod defines the final value of the count (see the following figure). the value of cntin is loaded into the ftm counter, and the counter increments until the value of mod is reached, at which point the counter is reloaded with the value of cntin. the ftm period when using up counting is (mod C cntin + 0x0001) period of the ftm counter clock. the tof bit is set when the ftm counter changes from mod to cntin. ftm counting is up. ftm counter (in decimal values) period of ftm counter clock mod = 0x0004 tof bit set tof bit set tof bit set tof bit 4 -4 -3 -2 -1 -4 -3 -2 -1 0 1 2 3 4 0 1 2 3 4 -4 -3 cntin = 0xfffc (in two's complement is equal to -4) period of counting = (mod - cntin + 0x0001) x period of ftm counter clock figure 39-168. example of ftm up and signed counting if (cntin = 0x0000), the ftm counting is equivalent to tpm up counting (that is, up and unsigned counting) (see the following figure). if (cntin[15] = 1), then the initial value of the ftm counter is a negative number in two's complement, so the ftm counting is up and signed. conversely if (cntin[15] = 0 and cntin 0x0000), then the initial value of the ftm counter is a positive number, so the ftm counting is up and unsigned. chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 987 cntin = 0x0000 mod = 0x0004 ftm counting is up tof bit 3 4 0 0 1 12 2 3 3 4 4 0 1 2 ftm counter set tof bit period of ftm counter clock period of counting = (mod - cntin + 0x0001) x period of ftm counter clock set tof bit set tof bit = (mod + 0x0001) x period of ftm counter clock figure 39-169. example of ftm up counting with cntin = 0x0000 note ? ftm operation is only valid when the value of the cntin register is less than the value of the mod register (either in the unsigned counting or signed counting). it is the responsibility of the software to ensure that the values in the cntin and mod registers meet this requirement. any values of cntin and mod that do not satisfy this criteria can result in unpredictable behavior. ? mod = cntin is a redundant condition. in this case, the ftm counter is always equal to mod and the tof bit is set in each rising edge of the ftm counter clock. ? when mod = 0x0000, cntin = 0x0000 (for example after reset), and ftmen = 1, the ftm counter remains stopped at 0x0000 until a non-zero value is written into the mod or cntin registers. ? setting cntin to be greater than the value of mod is not recommended as this unusual setting may make the ftm operation difficult to comprehend. however, there is no restriction on this configuration, and an example is shown in the following figure. functional description k60 sub-family reference manual, rev. 6, nov 2011 988 freescale semiconductor, inc. ftm counter ... ... ftm counting is up tof bit 0x0005 0x0015 0x0016 0xfffe 0xffff 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0015 0x0016 mod = 0x0005 cntin = 0x0015 set tof bit set tof bit load of cntin load of cntin figure 39-170. example of up counting when the value of cntin is greater than the value of mod 39.4.3.2 up-down counting up-down counting is selected when (quaden= 0) and (cpwms = 1). cntin defines the starting value of the count and mod defines the final value of the count. the value of cntin is loaded into the ftm counter, and the counter increments until the value of mod is reached, at which point the counter is decremented until it returns to the value of cntin and the up-down counting restarts. the ftm period when using up-down counting is 2 (mod C cntin) period of the ftm counter clock. the tof bit is set when the ftm counter changes from mod to (mod C 1). if (cntin = 0x0000), the ftm counting is equivalent to tpm up-down counting (that is, up-down and unsigned counting) (see the following figure). chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 989 ftm counter 0 0 0 1 1 11 1 2 2 22 23 3 33 34 4 4 ftm counting is up-down tof bit set tof bit set tof bit period of ftm counter clock period of counting = 2 x (mod - cntin) x period of ftm counter clock = 2 x mod x period of ftm counter clock cntin = 0x0000 mod = 0x0004 figure 39-171. example of up-down counting when cntin = 0x0000 note it is expected that the up-down counting be used only with cntin = 0x0000. 39.4.3.3 free running counter if (ftmen = 0) and (mod = 0x0000 or mod = 0xffff), the ftm counter is a free running counter. in this case, the ftm counter runs free from 0x0000 through 0xffff and the tof bit is set when the ftm counter changes from 0xffff to 0x0000 (see the following figure). ftm counter 0x00040x0004 0xfffe 0xffff 0x0003 0x0000 0x0001 0x0002 0x0003 0x0005 0x0006 tof bit ... ... ... ftmen = 0 set tof bit mod = 0x0000 figure 39-172. example when the ftm counter is a free running if (ftmen = 1), (quaden = 0), (cpwms = 0), (cntin = 0x0000), and (mod = 0xffff), the ftm counter is a free running counter. in this case, the ftm counter runs free from 0x0000 through 0xffff and the tof bit is set when the ftm counter changes from 0xffff to 0x0000. functional description k60 sub-family reference manual, rev. 6, nov 2011 990 freescale semiconductor, inc. 39.4.3.4 counter reset any write to cnt resets the ftm counter to the value in the cntin register and the channels output to its initial value (except for channels in output compare mode). the ftm counter synchronization (see ftm counter synchronization ) can also be used to force the value of cntin into the ftm counter and the channels output to its initial value (except for channels in output compare mode). 39.4.3.5 when the tof bit is set the numtof[4:0] bits define the number of times that the ftm counter overflow should occur before the tof bit to be set. if numtof[4:0] = 0x00, then the tof bit is set at each ftm counter overflow. ftm counter numtof[4:0] tof counter set tof bit 0x01 0x02 0x00 0x01 0x02 0x00 0x01 0x02 0x02 figure 39-173. periodic tof when numtof = 0x02 ftm counter numtof[4:0] tof counter set tof bit 0x00 0x00 figure 39-174. periodic tof when numtof = 0x00 39.4.4 input capture mode the input capture mode is selected when (decapen = 0), (combine = 0), (cpwms = 0), (msnb:msna = 0:0), and (elsnb:elsna 0:0). chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 991 when a selected edge occurs on the channel input, the current value of the ftm counter is captured into the cnv register, at the same time the chnf bit is set and the channel interrupt is generated if enabled by chnie = 1 (see the following figure). when a channel is configured for input capture, the ftmxchn pin is an edge-sensitive input. elsnb:elsna control bits determine which edge, falling or rising, triggers input- capture event. note that the maximum frequency for the channel input signal to be detected correctly is system clock divided by 4, which is required to meet nyquist criteria for signal sampling. writes to the cnv register is ignored in input capture mode. while in bdm, the input capture function works as configured. when a selected edge event occurs, the ftm counter value (which is frozen because of bdm) is captured into the cnv register and the chnf bit is set. channel (n) input synchronizer 1 is filter enabled? edge detector was falling edge selected? was rising edge selected? rising edge falling edge 0 1 1 0 0 0 cnv ftm counter d q clk d q clk system clock channel (n) interrupt chnie chnf filter* 0 * filtering function is only available in the inputs of channel 0, 1, 2, and 3 figure 39-175. input capture mode if the channel input does not have a filter enabled, then the input signal is always delayed 3 rising edges of the system clock (two rising edges to the synchronizer plus one more rising edge to the edge detector). in other words, the chnf bit is set on the third rising edge of the system clock after a valid edge occurs on the channel input. note it is expected that the input capture mode be used only with cntin = 0x0000. 39.4.4.1 filter for input capture mode the filter function is only available on channels 0, 1, 2, and 3. functional description k60 sub-family reference manual, rev. 6, nov 2011 992 freescale semiconductor, inc. firstly the input signal is synchronized by the system clock. following synchronization, the input signal enters the filter block (see the following figure). when there is a state change in the input signal, the 5-bit counter is reset and starts counting up. as long as the new state is stable on the input, the counter continues to increment. if the 5-bit counter overflows (the counter exceeds the value of the chnfval[3:0] bits), the state change of the input signal is validated. it is then transmitted as a pulse edge to the edge detector. system clock 5-bit up counter logic to define the filter output filter output divided by 4 channel (n) input after the synchronizer logic to control the filter counter chnfval[3:0] c s q clk figure 39-176. channel input filter if the opposite edge appears on the input signal before validation (counter overflow), the counter is reset. at the next input transition, the counter starts counting again. any pulse that is shorter than the minimum value selected by chnfval[3:0] bits ( 4 system clocks) is regarded as a glitch and is not passed on to the edge detector. a timing diagram of the input filter is shown in the following figure. the filter function is disabled when chnfval[3:0] bits are zero. in this case, the input signal is delayed 3 rising edges of the system clock. if (chnfval[3:0] 0000), then the input signal is delayed by the minimum pulse width (chnfval[3:0] 4 system clocks) plus a further 4 rising edges of the system clock (two rising edges to the synchronizer, one rising edge to the filter output plus one more to the edge detector). in other words, chnf is set (4 + 4 chnfval[3:0]) system clock periods after a valid edge occurs on the channel input. the clock for the 5-bit counter in the channel input filter is the system clock divided by 4. chnfval[3:0] = 0010 (binary value) channel (n) input after the synchronizer 5-bit counter filter output system clock divided by 4 time figure 39-177. channel input filter example chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 993 39.4.5 output compare mode the output compare mode is selected when (decapen = 0), (combine = 0), (cpwms = 0), and (msnb:msna = 0:1). in output compare mode, the ftm can generate timed pulses with programmable position, polarity, duration, and frequency. when the counter matches the value in the cnv register of an output compare channel, the channel (n) output can be set, cleared, or toggled. when a channel is initially configured to toggle mode, the previous value of the channel output is held until the first output compare event occurs. the chnf bit is set and the channel (n) interrupt is generated (if chnie = 1) at the channel (n) match (ftm counter = cnv). tof bit ... ... 0 1 1 1 2 2 3 3 4 45 5 0 0 previous value previous value channel (n) output counter overflow counter overflow counter overflow channel (n) match channel (n) match cnt mod = 0x0005 cnv = 0x0003 chnf bit figure 39-178. example of the output compare mode when the match toggles the channel output tof bit ... ... 0 1 1 1 2 2 3 3 4 45 5 0 0 previous value previous value channel (n) output counter overflow counter overflow counter overflow channel (n) match channel (n) match cnt mod = 0x0005 cnv = 0x0003 chnf bit figure 39-179. example of the output compare mode when the match clears the channel output functional description k60 sub-family reference manual, rev. 6, nov 2011 994 freescale semiconductor, inc. channel (n) output chnf bit tof bit cnt mod = 0x0005 cnv = 0x0003 counter overflow channel (n) match counter overflow channel (n) match counter overflow ... 0 1 2 3 4 5 0 1 2 3 4 5 0 1 ... previous value previous value figure 39-180. example of the output compare mode when the match sets the channel output it is possible to use the output compare mode with (elsnb:elsna = 0:0). in this case, when the counter reaches the value in the cnv register, the chnf bit is set and the channel (n) interrupt is generated (if chnie = 1), however the channel (n) output is not modified and controlled by ftm. note it is expected that the output compare mode be used only with cntin = 0x0000. 39.4.6 edge-aligned pwm (epwm) mode the edge-aligned mode is selected when (quaden = 0), (decapen = 0), (combine = 0), (cpwms = 0), and (msnb = 1). the epwm period is determined by (mod ? cntin + 0x0001) and the pulse width (duty cycle) is determined by (cnv ? cntin). the chnf bit is set and the channel (n) interrupt is generated (if chnie = 1) at the channel (n) match (ftm counter = cnv), that is, at the end of the pulse width. this type of pwm signal is called edge-aligned because the leading edges of all pwm signals are aligned with the beginning of the period, which is the same for all channels within an ftm. period counter overflow counter overflow counter overflow channel (n) output channel (n) match channel (n) match channel (n) match pulse width figure 39-181. epwm period and pulse width with elsnb:elsna = 1:0 chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 995 if (elsnb:elsna = 0:0) when the counter reaches the value in the cnv register, the chnf bit is set and the channel (n) interrupt is generated (if chnie = 1), however the channel (n) output is not controlled by ftm. if (elsnb:elsna = 1:0), then the channel (n) output is forced high at the counter overflow (when the cntin register value is are loaded into the ftm counter), and it is forced low at the channel (n) match (ftm counter = cnv) (see the following figure). tof bit chnf bit cnt channel (n) output mod = 0x0008 cnv = 0x0005 counter overflow channel (n) match counter overflow ... 0 1 2 3 4 5 6 7 8 0 1 2 ... previous value figure 39-182. epwm signal with elsnb:elsna = 1:0 if (elsnb:elsna = x:1), then the channel (n) output is forced low at the counter overflow (when the cntin register value is loaded into the ftm counter), and it is forced high at the channel (n) match (ftm counter = cnv) (see the following figure). tof bit chnf bit cnt channel (n) output mod = 0x0008 cnv = 0x0005 counter overflow channel (n) match counter overflow ... 0 1 2 3 4 5 6 7 8 0 1 2 ... previous value figure 39-183. epwm signal with elsnb:elsna = x:1 if (cnv = 0x0000), then the channel (n) output is a 0% duty cycle epwm signal and chnf bit is not set even when there is the channel (n) match. if (cnv > mod), then the channel (n) output is a 100% duty cycle epwm signal and chnf bit is not set even when there is the channel (n) match. therefore, mod must be less than 0xffff in order to get a 100% duty cycle epwm signal. note it is expected that the epwm mode be used only with cntin = 0x0000. functional description k60 sub-family reference manual, rev. 6, nov 2011 996 freescale semiconductor, inc. 39.4.7 center-aligned pwm (cpwm) mode the center-aligned mode is selected when (quaden = 0), (decapen = 0), (combine = 0), and (cpwms = 1). the cpwm pulse width (duty cycle) is determined by 2 (cnv ? cntin) and the period is determined by 2 (mod ? cntin)(see the following figure). mod must be kept in the range of 0x0001 to 0x7fff because values outside this range can produce ambiguous results. in the cpwm mode, the ftm counter counts up until it reaches mod and then counts down until it reaches cntin. the chnf bit is set and channel (n) interrupt is generated (if chnie = 1) at the channel (n) match (ftm counter = cnv) when the ftm counting is down (at the begin of the pulse width) and when the ftm counting is up (at the end of the pulse width). this type of pwm signal is called center-aligned because the pulse width centers for all channels are aligned with the value of cntin. the other channel modes are not compatible with the up-down counter (cpwms = 1). therefore, all ftm channels must be used in cpwm mode when (cpwms = 1). pulse width counter overflow ftm counter = mod period 2 x (cnv - cntin) 2 x (mod - cntincntin) ftm counter = cntin channel (n) match (ftm counting is down) channel (n) match (ftm counting is up) counter overflow ftm counter = mod channel (n) output figure 39-184. cpwm period and pulse width with elsnb:elsna = 1:0 if (elsnb:elsna = 0:0) when the ftm counter reaches the value in the cnv register, the chnf bit is set and the channel (n) interrupt is generated (if chnie = 1), however the channel (n) output is not controlled by ftm. if (elsnb:elsna = 1:0), then the channel (n) output is forced high at the channel (n) match (ftm counter = cnv) when counting down, and it is forced low at the channel (n) match when counting up (see the following figure). chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 997 tof bit ... 7 8 8 7 7 7 6 6 6 5 5 5 4 43 3 2 21 0 1 ... previous value cnt channel (n) output counter overflow channel (n) match in down counting channel (n) match in up counting channel (n) match in down counting counter overflow chnf bit mod = 0x0008 cnv = 0x0005 figure 39-185. cpwm signal with elsnb:elsna = 1:0 if (elsnb:elsna = x:1), then the channel (n) output is forced low at the channel (n) match (ftm counter = cnv) when counting down, and it is forced high at the channel (n) match when counting up (see the following figure). tof bit ... 7 8 8 7 7 7 6 6 6 5 5 5 4 43 3 2 21 0 1 ... previous value cnt channel (n) output counter overflow channel (n) match in down counting channel (n) match in up counting channel (n) match in down counting counter overflow chnf bit mod = 0x0008 cnv = 0x0005 figure 39-186. cpwm signal with elsnb:elsna = x:1 if (cnv = 0x0000) or (cnv is a negative value, that is, cnv[15] = 1) then the channel (n) output is a 0% duty cycle cpwm signal and chnf bit is not set even when there is the channel (n) match. if (cnv is a positive value, that is, cnv[15] = 0), (cnv mod), and (mod 0x0000), then the channel (n) output is a 100% duty cycle cpwm signal and chnf bit is not set even when there is the channel (n) match. this implies that the usable range of periods set by mod is 0x0001 through 0x7ffe (0x7fff if you do not need to generate a 100% duty cycle cpwm signal). this is not a significant limitation because the resulting period is much longer than required for normal applications. the cpwm mode must not be used when the ftm counter is a free running counter. note it is expected that the cpwm mode be used only with cntin = 0x0000. functional description k60 sub-family reference manual, rev. 6, nov 2011 998 freescale semiconductor, inc. 39.4.8 combine mode the combine mode is selected when (ftmen = 1), (quaden = 0), (decapen = 0), (combine = 1), and (cpwms = 0). in combine mode, the channel (n) (an even channel) and channel (n+1) (the adjacent odd channel) are combined to generate a pwm signal in the channel (n) output. in the combine mode, the pwm period is determined by (mod ? cntin + 0x0001) and the pwm pulse width (duty cycle) is determined by (|c(n+1)v ? c(n)v|). the chnf bit is set and the channel (n) interrupt is generated (if chnie = 1) at the channel (n) match (ftm counter = c(n)v). the ch(n+1)f bit is set and the channel (n +1) interrupt is generated (if ch(n+1)ie = 1) at the channel (n+1) match (ftm counter = c(n+1)v). if (elsnb:elsna = 1:0), then the channel (n) output is forced low at the beginning of the period (ftm counter = cntin) and at the channel (n+1) match (ftm counter = c(n +1)v). it is forced high at the channel (n) match (ftm counter = c(n)v)(see the following figure). if (elsnb:elsna = x:1), then the channel (n) output is forced high at the beginning of the period (ftm counter = cntin) and at the channel (n+1) match (ftm counter = c(n +1)v). it is forced low at the channel (n) match (ftm counter = c(n)v)(see the following figure). in combine mode, the els(n+1)b and els(n+1)a bits are not used in the generation of the channels (n) and (n+1) output. however, if (elsnb:elsna = 0:0) then the channel (n) output is not controlled by ftm, and if (els(n+1)b:els(n+1)a = 0:0) then the channel (n+1) output is not controlled by ftm. ftm counter channel (n) match channel (n+1) match channel (n) output with elsnb:elsna = x:1 with elsnb:elsna = 1:0 channel (n) output figure 39-187. combine mode the following figures illustrate the pwm signals generation using combine mode. chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 999 ftm counter channel (n) output with elsnb:elsna = 1:0 channel (n) output with elsnb:elsna = x:1 mod c(n)v cntin c(n+1)v figure 39-188. channel (n) output if (cntin < c(n)v < mod) and (cntin < c(n+1)v < mod) and (c(n)v < c(n+1)v) ftm counter channel (n) output with elsnb:elsna = 1:0 channel (n) output with elsnb:elsna = x:1 mod = c(n+1)v c(n)v cntin figure 39-189. channel (n) output if (cntin < c(n)v < mod) and (c(n+1)v = mod) ftm counter c(n+1)v channel (n) output with elsnb:elsna = 1:0 channel (n) output with elsnb:elsna = x:1 mod c(n)v = cntin figure 39-190. channel (n) output if (c(n)v = cntin) and (cntin < c(n+1)v < mod) functional description k60 sub-family reference manual, rev. 6, nov 2011 1000 freescale semiconductor, inc. ftm counter not fully 100% duty cycle channel (n) output with elsnb:elsna = 1:0 not fully 0% duty cycle channel (n) output with elsnb:elsna = x:1 mod = c(n+1)v c(n)v cntin figure 39-191. channel (n) output if (cntin < c(n)v < mod) and (c(n)v is almost equal to cntin) and (c(n+1)v = mod) ftm counter not fully 100% duty cycle channel (n) output with elsnb:elsna = 1:0 channel (n) output with elsnb:elsna = x:1 not fully 0% duty cycle mod c(n)v = cntin c(n+1)v figure 39-192. channel (n) output if (c(n)v = cntin) and (cntin < c(n+1)v < mod) and (c(n+1)v is almost equal to mod) chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1001 ftm counter 0% duty cycle channel (n) output with elsnb:elsna = 1:0 100% duty cycle channel (n) output with elsnb:elsna = x:1 c(n)v mod cntin c(n+1)v figure 39-193. channel (n) output if c(n)v and c(n+1)v are not between cntin and mod ftm counter 0% duty cycle channel (n) output with elsnb:elsna = 1:0 channel (n) output with elsnb:elsna = x:1 100% duty cycle mod cntin c(n+1)v = c(n)v figure 39-194. channel (n) output if (cntin < c(n)v < mod) and (cntin < c(n+1)v < mod) and (c(n)v = c(n+1)v) functional description k60 sub-family reference manual, rev. 6, nov 2011 1002 freescale semiconductor, inc. ftm counter c(n)v = c(n+1)v = cntin channel (n) output with elsnb:elsna = 1:0 channel (n) output with elsnb:elsna = x:1 100% duty cycle 0% duty cycle mod figure 39-195. channel (n) output if (c(n)v = c(n+1)v = cntin) ftm counter cntin channel (n) output with elsnb:elsna = 1:0 channel (n) output with elsnb:elsna = x:1 100% duty cycle 0% duty cycle mod = c(n+1)v = c(n)v figure 39-196. channel (n) output if (c(n)v = c(n+1)v = mod) channel (n) match is ignored ftm counter channel (n) output with elsnb:elsna = 1:0 channel (n) output with elsnb:elsna = x:1 100% duty cycle 0% duty cycle mod c(n)v cntin c(n+1)v figure 39-197. channel (n) output if (cntin < c(n)v < mod) and (cntin < c(n+1)v < mod) and (c(n)v > c(n+1)v) chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1003 ftm counter c(n)v channel (n) output with elsnb:elsna = 1:0 channel (n) output with elsnb:elsna = x:1 0% duty cycle 100% duty cycle mod c(n+1)v cntin figure 39-198. channel (n) output if (c(n)v < cntin) and (cntin < c(n+1)v < mod) c(n+1)v channel (n) output with elsnb:elsna = x:1 ftm counter cntin channel (n) output with elsnb:elsna = 1:0 c(n)v mod figure 39-199. channel (n) output if (c(n+1)v < cntin) and (cntin < c(n)v < mod) functional description k60 sub-family reference manual, rev. 6, nov 2011 1004 freescale semiconductor, inc. ftm counter channel (n) output with elsnb:elsna = 1:0 channel (n) output with elsnb:elsna = x:1 100% duty cycle 0% duty cycle mod c(n)v c(n+1)v cntin figure 39-200. channel (n) output if (c(n)v > mod) and (cntin < c(n+1)v < mod) c(n)v cntin channel (n) output with elsnb:elsna = x:1 channel (n) output with elsnb:elsna = 1:0 ftm counter c(n+1)v mod figure 39-201. channel (n) output if (c(n+1)v > mod) and (cntin < c(n)v < mod) chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1005 ftm counter cntin c(n+1)v not fully 0% duty cycle channel (n) output with elsnb:elsna = 1:0 not fully 100% duty cycle channel (n) output with elsnb:elsna = x:1 mod = c(n)v figure 39-202. channel (n) output if (c(n+1)v > mod) and (cntin < c(n)v = mod) 39.4.8.1 asymmetrical pwm in combine mode, the control of the pwm signal first edge (when the channel (n) match occurs, that is, ftm counter = c(n)v) is independent of the control of the pwm signal second edge (when the channel (n+1) match occurs, that is, ftm counter = c(n+1)v). so, combine mode allows the generation of asymmetrical pwm signals. 39.4.9 complementary mode the complementary mode is selected when (ftmen = 1), (quaden = 0), (decapen = 0), (combine = 1), (cpwms = 0), and (comp = 1). in complementary mode the channel (n+1) output is the inverse of the channel (n) output. if (ftmen = 1), (quaden = 0), (decapen = 0), (combine = 1), (cpwms = 0), and (comp = 0), then the channel (n+1) output is the same as the channel (n) output. functional description k60 sub-family reference manual, rev. 6, nov 2011 1006 freescale semiconductor, inc. ftm counter channel (n+1) match channel (n+1) output with comp = 1 channel (n+1) output with comp = 0 channel (n) output with elsnb:elsna = 1:0 channel (n) match figure 39-203. channel (n+1) output in complementary mode with (elsnb:elsna = 1:0) ftm counter channel (n+1) match channel (n+1) output with comp = 1 channel (n+1) output with comp = 0 channel (n) output with elsnb:elsna = x:1 channel (n) match figure 39-204. channel (n+1) output in complementary mode with (elsnb:elsna = x:1) 39.4.10 registers updated from write buffers 39.4.10.1 cntin register update if (clks[1:0] = 0:0) then cntin register is updated when cntin register is written (independent of ftmen bit). if (ftmen = 0) or (cntinc = 0) then cntin register is updated at the next system clock after cntin was written. if (ftmen = 1), (syncmode = 1) and (cntinc = 1) then cntin register is updated by the cntin register synchronization ( cntin register synchronization ). 39.4.10.2 mod register update if (clks[1:0] = 0:0) then mod register is updated when mod register is written (independent of ftmen bit). chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1007 if (clks[1:0] 0:0 and ftmen = 0), then mod register is updated according to the cpwms bit, that is: ? if the selected mode is not cpwm then mod register is updated after mod register was written and the ftm counter changes from mod to cntin. if the ftm counter is at free-running counter mode then this update occurs when the ftm counter changes from 0xffff to 0x0000. ? if the selected mode is cpwm then mod register is updated after mod register was written and the ftm counter changes from mod to (mod C 0x0001). if (clks[1:0] 0:0 and ftmen = 1) then mod register is updated by the mod register synchronization ( mod register synchronization ). 39.4.10.3 cnv register update if (clks[1:0] = 0:0) then cnv register is updated when cnv register is written (independent of ftmen bit). if (clks[1:0] 0:0 and ftmen = 0), then cnv register is updated according to the selected mode, that is: ? if the selected mode is output compare then cnv register is updated on the next ftm counter change (end of the prescaler counting) after cnv register was written. ? if the selected mode is epwm then cnv register is updated after cnv register was written and the ftm counter changes from mod to cntin. if the ftm counter is at free-running counter mode then this update occurs when the ftm counter changes from 0xffff to 0x0000. ? if the selected mode is cpwm then cnv register is updated after cnv register was written and the ftm counter changes from mod to (mod C 0x0001). if (clks[1:0] 0:0 and ftmen = 1) then cnv register is updated according to the selected mode, that is:. functional description k60 sub-family reference manual, rev. 6, nov 2011 1008 freescale semiconductor, inc. ? if the selected mode is output compare then cnv register is updated according to the syncen bit. if (syncen = 0) then cnv register is updated after cnv register was written at the next change of the ftm counter (end of the prescaler counting). if (syncen = 1) then cnv register is updated by the cnv register synchronization ( c(n)v and c(n+1)v register synchronization ). ? if the selected mode is not output compare and (syncen = 1) then cnv register is updated by the cnv register synchronization ( c(n)v and c(n+1)v register synchronization ). 39.4.11 pwm synchronization the pwm synchronization provides an opportunity to update the mod, cntin, cnv, outmask, invctrl and swoctrl registers with their buffered value and force the ftm counter to the cntin register value. note ? it is expected that the pwm synchronization be used only in combine mode. ? the legacy pwm synchronization (syncmode = 0) is a subset of the enhanced pwm synchronization (syncmode = 1). thus, it is expected that only the enhanced pwm synchronization be used. 39.4.11.1 hardware trigger three hardware trigger signal inputs of the ftm module are enabled when trign = 1 (where n = 0, 1 or 2 corresponding to each one of the input signals, respectively). the hardware trigger input n is synchronized by the system clock. the pwm synchronization with hardware trigger is initiated when a rising edge is detected at the enabled hardware trigger inputs. if (hwtrigmode = 0) then the trign bit is cleared when 0 is written to it or when the trigger n event is detected. in this case if two or more hardware triggers are enabled (for example, trig0 and trig1 = 1) and only trigger 1 event occurs then only trig1 bit is cleared. if a trigger n event occurs together with a write setting trign bit then the synchronization is initiated, but trign bit remains set due to the write operation. chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1009 write 1 to trig0 bit system clock synchronized trigger_0 trigger 0 event note trig0 bit trigger_0 input by system clock all hardware trigger inputs have the same behavior. figure 39-205. hardware trigger event with hwtrigmode = 0 if hwtrigmode = 1 then the trign bit is only cleared when 0 is written to it. note it is expected that the hwtrigmode bit be 1 only with enhanced pwm synchronization (syncmode = 1). 39.4.11.2 software trigger a software trigger event occurs when 1 is written to the sync[swsync] bit. the swsync bit is cleared when 0 is written to it or when the pwm synchronization (initiated by the software event) is completed. if a new software trigger event occurs (write 1 to swsync bit) together with the end of the previous synchronization (also initiated by the software trigger event) then this new synchronization is started and swsync bit remains equal to 1. if syncmode = 0 then the swsync bit is also cleared by ftm according to pwmsync and reinit bits. in this case if (pwmsync = 1) or (pwmsync = 0 and reinit = 0) then swsync bit is cleared at the next selected loading point ( boundary cycle and loading points ) after that the software trigger event occurred (see the following figure). if (pwmsync = 0) and (reinit = 1) then swsync bit is cleared when the software trigger event occurs. if syncmode = 1 then the swsync bit is also cleared by ftm according to the swrstcnt bit. if swrstcnt = 0 then swsync bit is cleared at the next selected loading point after that the software trigger event occurred (see the following figure). if swrstcnt = 1 then swsync bit is cleared when the software trigger event occurs. functional description k60 sub-family reference manual, rev. 6, nov 2011 1010 freescale semiconductor, inc. swsync bit system clock software trigger event write 1 to swsync bit selected loading point pwm synchronization swsync bit system clock software trigger event write 1 to swsync bit pwm synchronization figure 39-206. software trigger event 39.4.11.3 boundary cycle and loading points the boundary cycle definition is important for the loading points for the registers mod, cntin and c(n)v. in up counting mode ( up counting ) the boundary cycle is defined as when the counter wraps to its initial value (cntin). if in up-down counting mode ( up-down counting ) then the boundary cycle is defined as when the counter turns from down to up counting and when from up to down counting. the following figure shows the boundary cycles and the loading points. in the up counting mode, the loading points are enabled if one of cntmin or ctmax bits are 1. in the up-down counting mode, the loading points are selected by cntmin and cntmax bits, as indicated in the figure. these loading points are safe places for register updates thus allowing a smooth transitions in pwm waveform generation. for both counting modes if neither cntmin nor cntmax are 1 then the boundary cycles are not used as loading points for registers updates. see the register synchronization descriptions in the following sections for details. chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1011 cnt = (mod - 0x0001) -> mod cnt = (cntin + 0x0001) -> cntin loading points if cntmin = 1 loading points if cntmax = 1 up-down counting mode cnt = mod -> cntin loading points if cntmax = 1 or cntmin = 1 up counting mode figure 39-207. boundary cycles and loading points 39.4.11.4 mod register synchronization the mod register synchronization updates the mod register with its buffer value. this synchronization is enabled if (ftmen = 1). the mod register synchronization can be done by either the enhanced pwm synchronization (syncmode = 1) or the legacy pwm synchronization (syncmode = 0). however, it is expected that the mod register be synchronized only by the enhanced pwm synchronization. in the case of enhanced pwm synchronization, the mod register synchronization depends on swwrbuf, swrstcnt, hwwrbuf and hwrstcnt bits according to this flowchart: functional description k60 sub-family reference manual, rev. 6, nov 2011 1012 freescale semiconductor, inc. legacy pwm synchronization end = 0 enhanced pwm synchronization begin = 1 syncmode bit ? = 0 end end end end end = 1 = 1 0 = = 1 = 0 = 1 0 = = 1 = 1 = 1 = 0 = 0 = 0 mod register is updated by software trigger mod register is updated by hardware trigger software trigger hardware trigger ftm counter is reset by software trigger ftm counter is reset by hardware trigger swwrbuf bit ? hwwrbuf bit ? swsync bit ? swrstcnt bit ? wait the next selected loading point update mod with its buffer value clear swsync bit clear swsync bit update mod with its buffer value trign bit ? wait hardware trigger n hwtrigmode bit ? clear trign bit wait the next selected loading point update mod with its buffer value update mod with its buffer value hwrstcnt bit ? figure 39-208. mod register synchronization flowchart in the case of legacy pwm synchronization, the mod register synchronization depends on pwmsync and reinit bits according to the following description. if (syncmode = 0), (pwmsync = 0) and (reinit = 0) then this synchronization is made on the next selected loading point after an enabled trigger event takes place. if the trigger event was a software trigger then the swsync bit is cleared on the next selected chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1013 loading point. if the trigger event was a hardware trigger then the trigger enable bit (trign) is cleared according to hardware trigger . examples with software and hardware triggers follow. system clock selected loading point mod register is updated write 1 to swsync bit swsync bit software trigger event figure 39-209. mod synchronization with (syncmode = 0), (pwmsync = 0), (reinit = 0), and (software trigger was used) system clock selected loading point mod register is updated write 1 to trig0 bit trig0 bit trigger 0 event figure 39-210. mod synchronization with (syncmode = 0), (hwtrigmode = 0), (pwmsync = 0), (reinit = 0), and (a hardware trigger was used) if (syncmode = 0), (pwmsync = 0) and (reinit = 1) then this synchronization is made on the next enabled trigger event. if the trigger event was a software trigger then the swsync bit is cleared according to the following example. if the trigger event was a hardware trigger then the trign bit is cleared according to hardware trigger . examples with software and hardware triggers follow. functional description k60 sub-family reference manual, rev. 6, nov 2011 1014 freescale semiconductor, inc. system clock mod register is updated write 1 to swsync bit swsync bit software trigger event figure 39-211. mod synchronization with (syncmode = 0), (pwmsync = 0), (reinit = 1), and (software trigger was used) system clock mod register is updated write 1 to trig0 bit trig0 bit trigger 0 event figure 39-212. mod synchronization with (syncmode = 0), (hwtrigmode = 0), (pwmsync = 0), (reinit = 1), and (a hardware trigger was used) if (syncmode = 0) and (pwmsync = 1) then this synchronization is made on the next selected loading point after the software trigger event takes place. the swsync bit is cleared on the next selected loading point: system clock selected loading point mod register is updated write 1 to swsync bit swsync bit software trigger event figure 39-213. mod synchronization with (syncmode = 0) and (pwmsync = 1) chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1015 39.4.11.5 cntin register synchronization the cntin register synchronization updates the cntin register with its buffer value. this synchronization is enabled if (ftmen = 1), (syncmode = 1) and (cntinc = 1). the cntin register synchronization can be done only by the enhanced pwm synchronization (syncmode = 1). the synchronization mechanism is the same as the mod register synchronization done by the enhanced pwm synchronization ( mod register synchronization ). 39.4.11.6 c(n)v and c(n+1)v register synchronization the c(n)v and c(n+1)v registers synchronization updates the c(n)v and c(n+1)v registers with their buffer values. this synchronization is enabled if (ftmen = 1) and (syncen = 1). the synchronization mechanism is the same as the mod register synchronization ( mod register synchronization ). however, it is expected that the c(n)v and c(n+1)v registers be synchronized only by the enhanced pwm synchronization (syncmode = 1). 39.4.11.7 outmask register synchronization the outmask register synchronization updates the outmask register with its buffer value. the outmask register can be updated at each rising edge of system clock (synchom = 0), by the enhanced pwm synchronization (synchom = 1 and syncmode = 1) or by the legacy pwm synchronization (synchom = 1 and syncmode = 0). however, it is expected that the outmask register be synchronized only by the enhanced pwm synchronization. in the case of enhanced pwm synchronization, the outmask register synchronization depends on swom and hwom bits. see the following flowchart: functional description k60 sub-family reference manual, rev. 6, nov 2011 1016 freescale semiconductor, inc. end = 0 update outmask register at each rising edge of system clock begin software trigger end end end end = 0 = 0 = 1 = 1 = 1 = 1 = 0 = 1 0 = 0 = 1 = 1 = 0 = legacy pwm synchronization synchom bit ? update outmask register by pwm synchronization update outmask with its buffer value syncmode bit ? clear trign bit hwtrigmode bit ? update outmask with its buffer value wait hardware trigger n trign bit ? hwom bit ? swom bit ? swsync bit ? rising edge of system clock ? update outmask with its buffer value hardware trigger outmask is updated by software trigger outmask is updated by hardware trigger enhanced pwm synchronization = yes no = figure 39-214. outmask register synchronization flowchart in the case of legacy pwm synchronization, the outmask register synchronization depends on pwmsync bit according to the following description. chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1017 if (syncmode = 0), (synchom = 1) and (pwmsync = 0) then this synchronization is done on the next enabled trigger event. if the trigger event was a software trigger then the swsync bit is cleared on the next selected loading point. if the trigger event was a hardware trigger then the trign bit is cleared according to hardware trigger . examples with software and hardware triggers follow. system clock outmask register is updated selected loading point swsync bit is cleared write 1 to swsync bit swsync bit software trigger event figure 39-215. outmask synchronization with (syncmode = 0), (synchom = 1), (pwmsync = 0) and (software trigger was used) system clock write 1 to trig0 bit trig0 bit trigger 0 event outmask register is updated and trig0 bit is cleared figure 39-216. outmask synchronization with (syncmode = 0), (hwtrigmode = 0), (synchom = 1), (pwmsync = 0), and (a hardware trigger was used) if (syncmode = 0), (synchom = 1) and (pwmsync = 1) then this synchronization is made on the next enabled hardware trigger. the trign bit is cleared according to hardware trigger . an example with a hardware trigger follows. functional description k60 sub-family reference manual, rev. 6, nov 2011 1018 freescale semiconductor, inc. system clock outmask register is updated and trig0 bit is cleared write 1 to trig0 bit trig0 bit trigger 0 event figure 39-217. outmask synchronization with (syncmode = 0), (hwtrigmode = 0), (synchom = 1), (pwmsync = 1), and (a hardware trigger was used) 39.4.11.8 invctrl register synchronization the invctrl register synchronization updates the invctrl register with its buffer value. the invctrl register can be updated at each rising edge of system clock (invc = 0) or by the enhanced pwm synchronization (invc = 1 and syncmode = 1) according to the following flowchart. in the case of enhanced pwm synchronization, the invctrl register synchronization depends on swinvc and hwinvc bits. chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1019 end begin = 1 = 0 end end end end end = 1 = 0 = 1 = 1 = 0 = 0 = 1 invctrl is updated by software trigger software trigger hardware trigger invctrl is updated by hardware trigger enhanced pwm synchronization update invctrl register by pwm synchronization update invctrl register at each rising edge of system clock = yes 0 = 1 = 0 = 0 = no = 1 = invc bit ? syncmode bit ? rising edge of system clock ? update invctrl with its buffer value update invctrl with its buffer value hwinvc bit ? trign bit ? wait hardware trigger n update invctrl with its buffer value hwtrigmode bit ? clear trign bit swinvc bit ? swsync bit ? figure 39-218. invctrl register synchronization flowchart 39.4.11.9 swoctrl register synchronization the swoctrl register synchronization updates the swoctrl register with its buffer value. functional description k60 sub-family reference manual, rev. 6, nov 2011 1020 freescale semiconductor, inc. the swoctrl register can be updated at each rising edge of system clock (swoc = 0) or by the enhanced pwm synchronization (swoc = 1 and syncmode = 1) according to the following flowchart. in the case of enhanced pwm synchronization, the swoctrl register synchronization depends on swsoc and hwsoc bits. end begin = 1 = 0 end end end end end = 1 = 0 = 1 = 1 = 0 = 0 = 1 swoctrl is updated by software trigger software trigger hardware trigger swoctrl is updated by hardware trigger enhanced pwm synchronization update swoctrl register by pwm synchronization update swoctrl register at each rising edge of system clock = yes 0 = 1 = 0 = 0 = no = 1 = swoc bit ? syncmode bit ? rising edge of system clock ? update swoctrl with its buffer value update swoctrl with its buffer value hwsoc bit ? trign bit ? wait hardware trigger n update swoctrl with its buffer value hwtrigmode bit ? clear trign bit swsoc bit ? swsync bit ? figure 39-219. swoctrl register synchronization flowchart chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1021 39.4.11.10 ftm counter synchronization the ftm counter synchronization is a mechanism that allows the ftm to re-start the pwm generation at a certain point in the pwm period. the channels outputs are forced to their initial value (except for channels in output compare mode) and the ftm counter is forced to its initial counting value defined by cntin register. the following figure shows the ftm counter synchronization. note that after the synchronization event had occurred the channel (n) is set to its initial value and the channel (n+1) is not set to its initial value due to a specific timing of this figure in which the deadtime insertion prevents this channel output from transitioning to 1. if no deadtime insertion is selected then the channel (n+1) transitions to logical value 1 immediately after the synchronization event had occurred. synchronization event channel (n+1) match ftm counter channel (n) match channel (n) output (after deadtime insertion) channel (n+1) output (after deadtime insertion) figure 39-220. ftm counter synchronization the ftm counter synchronization can be done by either the enhanced pwm synchronization (syncmode = 1) or the legacy pwm synchronization (syncmode = 0). however, it is expected that the ftm counter be synchronized only by the enhanced pwm synchronization. in the case of enhanced pwm synchronization, the ftm counter synchronization depends on swrstcnt and hwrstcnt bits according to the following flowchart. functional description k60 sub-family reference manual, rev. 6, nov 2011 1022 freescale semiconductor, inc. update ftm counter with cntin register value update the channels outputs with their initial value clear swsync bit end ftm counter is reset by software trigger legacy pwm synchronization end clear trign bit hwtrigmode bit ? = 1 = 0 update the channels outputs with their initial value update ftm counter with cntin register value wait hardware trigger n enhanced pwm synchronization ftm counter is reset by hardware trigger begin = 1 = 1 = 1 = 1 end end hwrstcnt bit ? swrstcnt bit ? swsync bit ? software trigger syncmode bit ? hardware trigger trign bit ? = 0 = 0 = 0 = 0 = 0 1 = figure 39-221. ftm counter synchronization flowchart in the case of legacy pwm synchronization, the ftm counter synchronization depends on reinit and pwmsync bits according to the following description. if (syncmode = 0), (reinit = 1) and (pwmsync = 0) then this synchronization is made on the next enabled trigger event. if the trigger event was a software trigger then the swsync bit is cleared according to the following example. if the trigger event was a hardware trigger then the trign bit is cleared according to hardware trigger . examples with software and hardware triggers follow. chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1023 system clock ftm counter is updated with the cntin register value and channel outputs are forced to their initial value write 1 to swsync bit swsync bit software trigger event figure 39-222. ftm counter synchronization with (syncmode = 0), (reinit = 1), (pwmsync = 0), and (software trigger was used) system clock write 1 to trig0 bit trig0 bit trigger 0 event ftm counter is updated with the cntin register value and channel outputs are forced to their initial value figure 39-223. ftm counter synchronization with (syncmode = 0), (hwtrigmode = 0), (reinit = 1), (pwmsync = 0), and (a hardware trigger was used) if (syncmode = 0), (reinit = 1) and (pwmsync = 1) then this synchronization is made on the next enabled hardware trigger. the trign bit is cleared according to hardware trigger . system clock write 1 to trig0 bit trig0 bit trigger 0 event ftm counter is updated with the cntin register value and channel outputs are forced to their initial value figure 39-224. ftm counter synchronization with (syncmode = 0), (hwtrigmode = 0), (reinit = 1), (pwmsync = 1), and (a hardware trigger was used) functional description k60 sub-family reference manual, rev. 6, nov 2011 1024 freescale semiconductor, inc. 39.4.12 inverting the invert functionality swaps the signals between channel (n) and channel (n+1) outputs. the inverting operation is selected when (ftmen = 1), (quaden = 0), (decapen = 0), (combine = 1), (comp = 1), (cpwms = 0), and (invm = 1), where m represents a channel pair. the invm bit in invctrl register is updated with its buffer value according to invctrl register synchronization in high-true (elsnb:elsna = 1:0) combine mode, the channel (n) output is forced low at the beginning of the period (ftm counter = cntin), forced high at the channel (n) match and forced low at the channel (n+1) match. if the inverting is selected, the channel (n) output behavior is changed to force high at the beginning of the pwm period, force low at the channel (n) match and force high at the channel (n+1) match. see the following figure. note channel (n+1) match ftm counter channel (n) match channel (n+1) output before the inverting write 1 to inv(m) bit inv(m) bit buffer invctrl register synchronization inv(m) bit channel (n) output after the inverting channel (n+1) output after the inverting inv(m) bit selects the inverting to the pair channels (n) and (n+1). channel (n) output before the inverting figure 39-225. channels (n) and (n+1) outputs after the inverting in high-true (elsnb:elsna = 1:0) combine mode note that the elsnb:elsna bits value should be consider since that they define the active state of the channels outputs. in low-true (elsnb:elsna = x:1) combine mode, the channel (n) output is forced high at the beginning of the period, forced low at the channel (n) match and forced high at the channel (n+1) match. in the case the inverting is selected the channels (n) and (n+1) present waveforms as shown in the following figure. chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1025 note channel (n+1) match ftm counter channel (n) match channel (n+1) output before the inverting write 1 to inv(m) bit inv(m) bit buffer invctrl register synchronization inv(m) bit channel (n) output after the inverting channel (n+1) output after the inverting inv(m) bit selects the inverting to the pair channels (n) and (n+1). channel (n) output before the inverting figure 39-226. channels (n) and (n+1) outputs after the inverting in low-true (elsnb:elsna = x:1) combine mode note it is expected that the inverting feature be used only in combine mode. 39.4.13 software output control the software output control forces the channel output according to software defined values at a specific time in the pwm generation. the software output control is selected when (ftmen = 1), (quaden = 0), (decapen = 0), (combine = 1), (cpwms = 0), and (chnoc = 1). the chnoc bit enables the software output control for a specific channel output and the chnocv selects the value that is forced to this channel output. both chnoc and chnocv bits in swoctrl register are buffered and updated with their buffer value according to swoctrl register synchronization . the following figure shows the channels (n) and (n+1) outputs signals when the software output control is used. in this case the channels (n) and (n+1) are set to combine and complementary mode. functional description k60 sub-family reference manual, rev. 6, nov 2011 1026 freescale semiconductor, inc. channel (n+1) match ftm counter channel (n) match channel (n) output after the software output control channel (n+1) output after the software output control ch(n)oc buffer ch(n+1)oc buffer ch(n)oc bit ch(n+1)oc bit note ch(n)ocv = 1 and ch(n+1)ocv = 0. swoctrl register synchronization swoctrl register synchronization write to swoctrl register write to swoctrl register figure 39-227. example of software output control in combine and complementary mode software output control forces the following values on channels (n) and (n+1) when the comp bit is zero. table 39-242. software ouput control behavior when (comp = 0) ch(n)oc ch(n+1)oc ch(n)ocv ch(n+1)ocv channel (n) output channel (n+1) output 0 0 x x is not modified by swoc is not modified by swoc 1 1 0 0 is forced to zero is forced to zero 1 1 0 1 is forced to zero is forced to one 1 1 1 0 is forced to one is forced to zero 1 1 1 1 is forced to one is forced to one software output control forces the following values on channels (n) and (n+1) when the comp bit is one. table 39-243. software ouput control behavior when (comp = 1) ch(n)oc ch(n+1)oc ch(n)ocv ch(n+1)ocv channel (n) output channel (n+1) output 0 0 x x is not modified by swoc is not modified by swoc 1 1 0 0 is forced to zero is forced to zero 1 1 0 1 is forced to zero is forced to one 1 1 1 0 is forced to one is forced to zero 1 1 1 1 is forced to one is forced to zero chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1027 note ? it is expected that the software output control feature be used only in combine mode. ? the ch(n)oc and ch(n+1)oc bits should be equal. ? the comp bit should not be modified when software output control is enabled, that is, ch(n)oc = 1 and/or ch(n+1)oc = 1. ? software output control has the same behavior with disabled or enabled ftm counter (see the clks bitfield description in the status and control register). 39.4.14 deadtime insertion the deadtime insertion is enabled when (dten = 1) and (dtval[5:0] is non- zero). deadtime register defines the deadtime delay that can be used for all ftm channels. the dtps[1:0] bits define the prescaler for the system clock and the dtval[5:0] bits define the deadtime modulo (number of the deadtime prescaler clocks). the deadtime delay insertion ensures that no two complementary signals (channels (n) and (n+1)) drive the active state at the same time. if pol(n) = 0, pol(n+1) = 0, and the deadtime is enabled, then when the channel (n) match (ftm counter = c(n)v) occurs, the channel (n) output remains at the low value until the end of the deadtime delay when the channel (n) output is set. similarly, when the channel (n+1) match (ftm counter = c(n+1)v) occurs, the channel (n+1) output remains at the low value until the end of the deadtime delay when the channel (n+1) output is set. see the following figures. if pol(n) = 1, pol(n+1) = 1, and the deadtime is enabled, then when the channel (n) match (ftm counter = c(n)v) occurs, the channel (n) output remains at the high value until the end of the deadtime delay when the channel (n) output is cleared. similarly, when the channel (n+1) match (ftm counter = c(n+1)v) occurs, the channel (n+1) output remains at the high value until the end of the deadtime delay when the channel (n +1) output is cleared. functional description k60 sub-family reference manual, rev. 6, nov 2011 1028 freescale semiconductor, inc. ftm counter channel (n+1) match channel (n) match channel (n) output (before deadtime insertion) channel (n+1) output (before deadtime insertion) channel (n) output (after deadtime insertion) channel (n+1) output (after deadtime insertion) figure 39-228. deadtime insertion with elsnb:elsna = 1:0, pol(n) = 0, and pol(n+1) = 0 ftm counter channel (n+1) match channel (n) output (before deadtime insertion) channel (n+1) output (before deadtime insertion) channel (n) output (after deadtime insertion) channel (n+1) output (after deadtime insertion) channel (n) match figure 39-229. deadtime insertion with elsnb:elsna = x:1, pol(n) = 0, and pol(n+1) = 0 note it is expected that the deadtime feature be used only in combine and complementary modes. 39.4.14.1 deadtime insertion corner cases if (ps[2:0] is cleared), (dtps[1:0] = 0:0 or dtps[1:0] = 0:1): chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1029 ? and the deadtime delay is greater than or equal to the channel (n) duty cycle ((c(n +1)v C c(n)v) system clock), then the channel (n) output is always the inactive value (pol(n) bit value). ? and the deadtime delay is greater than or equal to the channel (n+1) duty cycle ((mod C cntin + 1 C (c(n+1)v C c(n)v) ) system clock), then the channel (n+1) output is always the inactive value (pol(n+1) bit value). although, in most cases the deadtime delay is not comparable to channels (n) and (n+1) duty cycle, the following figures show examples where the deadtime delay is comparable to the duty cycle. ftm counter channel (n+1) match channel (n) match channel (n) output (before deadtime insertion) channel (n) output (after deadtime insertion) channel (n+1) output (before deadtime insertion) channel (n+1) output (after deadtime insertion) figure 39-230. example of the deadtime insertion (elsnb:elsna = 1:0, pol(n) = 0, and pol(n+1) = 0) when the deadtime delay is comparable to channel (n+1) duty cycle ftm counter channel (n+1) match channel (n) match channel (n) output (before deadtime insertion) channel (n) output (after deadtime insertion) channel (n+1) output (before deadtime insertion) channel (n+1) output (after deadtime insertion) figure 39-231. example of the deadtime insertion (elsnb:elsna = 1:0, pol(n) = 0, and pol(n+1) = 0) when the deadtime delay is comparable to channels (n) and (n+1) duty cycle functional description k60 sub-family reference manual, rev. 6, nov 2011 1030 freescale semiconductor, inc. 39.4.15 output mask the output mask can be used to force channels output to their inactive state through software (for example: to control a bldc motor). any write to the outmask register updates its write buffer. the outmask register is updated with its buffer value by pwm synchronization ( outmask register synchronization ). if chnom = 1, then the channel (n) output is forced to its inactive state (poln bit value). if chnom = 0, then the channel (n) output is unaffected by the output mask (see the following figure). ftm counter channel (n) output (before output mask) chnom bit channel (n) output (after output mask) the beginning of new pwm cycles configured pwm signal starts to be available in the channel (n) output channel (n) output is disabled figure 39-232. output mask with poln = 0 the following table shows the output mask result before the polarity control. table 39-244. output mask result for channel (n) (before the polarity control) chnom output mask input output mask result 0 inactive state inactive state active state active state 1 inactive state inactive state active state chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1031 note it is expected the output mask feature be used only in combine mode. 39.4.16 fault control the fault control is enabled if (ftmen = 1) and (faultm[1:0] 0:0). ftm can have up to four fault inputs. faultnen bit (where n = 0, 1, 2, 3) enables the fault input n and ffltrnen bit enables the fault input n filter. ffval[3:0] bits select the value of the enabled filter in each enabled fault input. first each fault input signal is synchronized by the system clock (see the synchronizer block in the following figure). following synchronization, the fault input n signal enters the filter block. when there is a state change in the fault input n signal, the 5-bit counter is reset and starts counting up. as long as the new state is stable on the fault input n, the counter continues to increment. if the 5-bit counter overflows (the counter exceeds the value of the ffval[3:0] bits), the new fault input n value is validated. it is then transmitted as a pulse edge to the edge detector. if the opposite edge appears on the fault input n signal before validation (counter overflow), the counter is reset. at the next input transition, the counter starts counting again. any pulse that is shorter than the minimum value selected by ffval[3:0] bits ( system clock) is regarded as a glitch and is not passed on to the edge detector. the fault input n filter is disabled when the ffval[3:0] bits are zero or when faultnen = 0. in this case the fault input n signal is delayed 2 rising edges of the system clock and the faultfn bit is set on 3th rising edge of the system clock after a rising edge occurs on the fault input n. if ffval[3:0] 0000 and faultnen = 1, then the fault input n signal is delayed (3 + ffval[3:0]) rising edges of the system clock, that is, the faultfn bit is set (4 + ffval[3:0]) rising edges of the system clock after a rising edge occurs on the fault input n. functional description k60 sub-family reference manual, rev. 6, nov 2011 1032 freescale semiconductor, inc. fault input n* system clock * where n = 3, 2, 1, 0 synchronizer fault input n* value faultfn* 0000) and (ffltrnen*) 0 1 rising edge detector fault input polarity control fault filter (5-bit counter) clk clk d d q q fltnpol (ffval[3:0] figure 39-233. fault input n control block diagram if the fault control and fault input n are enabled and a rising edge at the fault input n signal is detected, then the faultfn bit is set. the faultf bit is the logic or of faultfn[3:0] bits (see the following figure). fault interrupt faultie faultin fault input 0 value fault input 1 value fault input 2 value fault input 3 value faultf faultf0 faultf1 faultf2 faultf3 figure 39-234. faultf and faultin bits and fault interrupt if the fault control is enabled (faultm[1:0] 0:0), a fault condition has occurred (rising edge at the logic or of the enabled fault inputs) and (faulten = 1), then channels (n) and (n+1) output are forced to their safe value (the channel (n) output is forced to the value of pol(n) and the channel (n+1) is forced to the value of pol(n+1)). the fault interrupt is generated when (faultf = 1) and (faultie = 1). this interrupt request remains set until: ? software clears the faultf bit (by reading faultf bit as 1 and writing 0 to it) ? software clears the faultie bit ? a reset occurs note it is expected that the fault control be used only in combine mode. chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1033 39.4.16.1 automatic fault clearing if the automatic fault clearing is selected (faultm[1:0] = 1:1), then the channels output disabled by fault control is again enabled when the fault input signal (faultin) returns to zero and a new pwm cycle begins (see the following figure). ftm counter channel (n) output (before fault control) faultin bit channel (n) output (after fault control with automatic fault clearing and poln=0) the beginning of new pwm cycles faultf bit faultf bit is cleared the channel (n) output is after the fault control with automatic fault clearing and poln = 0. note figure 39-235. fault control with automatic fault clearing 39.4.16.2 manual fault clearing if the manual fault clearing is selected (faultm[1:0] = 0:1 or 1:0), then the channels output disabled by fault control is again enabled when the faultf bit is cleared and a new pwm cycle begins (see the following figure). functional description k60 sub-family reference manual, rev. 6, nov 2011 1034 freescale semiconductor, inc. ftm counter channel (n) output (before fault control) faultin bit channel (n) output (after fault control with manual fault clearing and poln=0) the beginning of new pwm cycles faultf bit faultf bit is cleared the channel (n) output is after the fault control with manual fault clearing and poln = 0. note figure 39-236. fault control with manual fault clearing 39.4.16.3 fault inputs polarity control the fltjpol bit selects the fault input j polarity (where j = 0, 1, 2, 3). ? if fltjpol = 0, the fault j input polarity is high, so the logical one at the fault input j indicates a fault. ? if fltjpol = 1, the fault j input polarity is low, so the logical zero at the fault input j indicates a fault. 39.4.17 polarity control the poln bit selects the channel (n) output polarity. ? if poln = 0, the channel (n) output polarity is high, so the logical one is the active state and the logical zero is the inactive state. ? if poln = 1, the channel (n) output polarity is low, so the logical zero is the active state and the logical one is the inactive state. chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1035 note it is expected that the polarity control be used only in combine mode. 39.4.18 initialization the initialization forces the chnoi bit value to the channel (n) output when a one is written to the init bit. the initialization depends on comp and dten bits. the following table shows the values that channels (n) and (n+1) are forced by initialization when the comp and dten bits are zero. table 39-245. initialization behavior when (comp = 0 and dten = 0) ch(n)oi ch(n+1)oi channel (n) output channel (n+1) output 0 0 is forced to zero is forced to zero 0 1 is forced to zero is forced to one 1 0 is forced to one is forced to zero 1 1 is forced to one is forced to one the following table shows the values that channels (n) and (n+1) are forced by initialization when (comp = 1) or (dten = 1). table 39-246. initialization behavior when (comp = 1 or dten = 1) ch(n)oi ch(n+1)oi channel (n) output channel (n+1) output 0 x is forced to zero is forced to one 1 x is forced to one is forced to zero note it is expected that the initialization feature be used only in combine mode and with disabled ftm counter (see the description of the clks field in the status and control register). 39.4.19 features priority the following figure shows the priority of the features used at the generation of channels (n) and (n+1) outputs signals. functional description k60 sub-family reference manual, rev. 6, nov 2011 1036 freescale semiconductor, inc. note the channels (n) and (n+1) are in output compare, epwm, cpwm or combine modes. pair channels (m) - channels (n) and (n+1) initialization complementary mode inverting software output control deadtime insertion output mask fault control polarity control ftm counter quaden decapen combine(m) cpwms c(n)v ms(n)b ms(n)a els(n)b els(n)a generation of channel (n) output signal generation of channel (n+1) output signal c(n+1)v ms(n+1)b ms(n+1)a els(n+1)b els(n+1)a channel (n) output signal channel (n+1) output signal ch(n)oi ch(n+1)oi comp(m) inv(m)en ch(n)oc ch(n)ocv ch(n+1)oc ch(n+1)ocv dten(m) ch(n)om ch(n+1)om faulten(m) pol(n) pol(n+1) figure 39-237. priority of the features used at the generation of channels (n) and (n+1) outputs signals note it is expected that the initialization feature ( initialization ) is not used with inverting ( inverting ) and software output control ( software output control ) features. 39.4.20 channel trigger output if chjtrig = 1 (where j = 0, 1, 2, 3, 4, or 5), then the ftm generates a trigger when the channel (j) match occurs (ftm counter = c(j)v). the channel trigger output provides a trigger signal that is used for on-chip modules. chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1037 the ftm is able to generate multiple triggers in one pwm period. since each trigger is generated for a specific channel, several channels are required to implement this functionality. this behavior is described in the following figure. note (a) ch0trig = 0, ch1trig = 0, ch2trig = 0, ch3trig = 0, ch4trig = 0, ch5trig = 0 (b) ch0trig = 1, ch1trig = 0, ch2trig = 0, ch3trig = 0, ch4trig = 0, ch5trig = 0 (c) ch0trig = 0, ch1trig = 0, ch2trig = 0, ch3trig = 1, ch4trig = 1, ch5trig = 1 (d) ch0trig = 1, ch1trig = 1, ch2trig = 1, ch3trig = 1, ch4trig = 1, ch5trig = 1 the beginning of new pwm cycles mod ftm counter = c5v ftm counter = c4v ftm counter = c3v ftm counter = c2v ftm counter = c1v ftm counter = c0v cntin (a) (b) (c) (d) figure 39-238. channel match trigger note it is expected that the channel match trigger be used only in combine mode. 39.4.21 initialization trigger if inittrigen = 1, then the ftm generates a trigger when the ftm counter is updated with the cntin register value in the following cases. ? the ftm counter is automatically updated with the cntin register value by the selected counting mode. functional description k60 sub-family reference manual, rev. 6, nov 2011 1038 freescale semiconductor, inc. ? when there is a write to cnt register ? when there is the ftm counter synchronization ( ftm counter synchronization ) ? if (cnt = cntin), (clks[1:0] = 0:0), and a value different from zero is written to clks[1:0] bits the following figures show the cases. cpwms = 0 0x0c 0x0d 0x0e 0x0f 0x00 0x01 0x02 0x03 0x04 0x05 initialization trigger ftm counter system clock cntin = 0x0000 mod = 0x000f figure 39-239. initialization trigger is generated when the ftm counting achieves the cntin register value cpwms = 0 0x04 0x05 0x06 0x00 0x01 0x02 0x03 0x04 0x05 0x06 initialization trigger write to cnt ftm counter system clock cntin = 0x0000 mod = 0x000f figure 39-240. initialization trigger is generated when there is a write to cnt register cpwms = 0 0x04 0x05 0x06 0x07 0x00 0x01 0x02 0x03 0x04 0x05 initialization trigger trigger event synchronization ftm counter system clock cntin = 0x0000 mod = 0x000f figure 39-241. initialization trigger is generated when there is the ftm counter synchronization chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1039 cpwms = 0 0x00 00 01 0x01 0x02 0x03 0x04 0x05 initialization trigger clks[1:0] bits ftm counter system clock cntin = 0x0000 mod = 0x000f figure 39-242. initialization trigger is generated if (cnt = cntin), (clks[1:0] = 0:0), and a value different from zero is written to clks[1:0] bits the initialization trigger output provides a trigger signal that is used for on-chip modules. note it is expected that the initialization trigger be used only in combine mode. 39.4.22 capture test mode the capture test mode allows to test the cnv registers, the ftm counter and the interconnection logic between the ftm counter and cnv registers. in this test mode, all channels must be configured for input capture mode ( input capture mode ) and ftm counter must be configured to the up counting ( up counting ). when the capture test mode is enabled (captest = 1), the ftm counter is frozen and any write to cnt register updates directly the ftm counter (see the following figure). after it was written, all cnv registers are updated with the written value to cnt register and chnf bits are set. therefore, the ftm counter is updated with its next value according to its configuration (its next value depends on cntin, mod, and the written value to ftm counter). the next reads of cnv registers return the written value to the ftm counter and the next reads of cnt register return ftm counter next value. functional description k60 sub-family reference manual, rev. 6, nov 2011 1040 freescale semiconductor, inc. note ftm counter clock write to mode captest bit ftm counter write to cnt chnf bit cnv - ftm counter configuration: (ftmen = 1), (quaden = 0), (captest = 1), (cpwms = 0), (cntin = 0x0000), and (mod = 0xffff) - ftm channel n configuration: input capture mode - (decapen = 0), (combine = 0), and (msnb:msna = 0:0) 0x0300 0x78ac set captest clear captest write 0x78ac 0x1056 0x1053 0x1055 0x1054 0x78ac 0x78ad 0x78ae 0x78af 0x78b0 figure 39-243. capture test mode 39.4.23 dma the channel generates a dma transfer request according to dma and chnie bits (see the following table). table 39-247. channel dma transfer request dma chnie channel dma transfer request channel interrupt 0 0 the channel dma transfer request is not generated. the channel interrupt is not generated. 0 1 the channel dma transfer request is not generated. the channel interrupt is generated if (chnf = 1). 1 0 the channel dma transfer request is not generated. the channel interrupt is not generated. 1 1 the channel dma transfer request is generated if (chnf = 1). the channel interrupt is not generated. if dma = 1, the chnf bit is cleared either by channel dma transfer done or reading cnsc while chnf is set and then writing a zero to chnf bit according to chnie bit (see the following table). chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1041 table 39-248. clear chnf bit when dma = 1 chnie how chnf bit can be cleared 0 chnf bit is cleared either when the channel dma transfer is done or by reading cnsc while chnf is set and then writing a 0 to chnf bit. 1 chnf bit is cleared when the channel dma transfer is done. 39.4.24 dual edge capture mode the dual edge capture mode is selected if ftmen = 1 and decapen = 1. this mode allows to measure a pulse width or period of the signal on the input of channel (n) of a channel pair. the channel (n) filter can be active in this mode when n is 0 or 2. channel (n) input system clock synchronizer filter* dual edge capture mode logic is filter enabled? ftm counter * filtering function for dual edge capture mode is only available in the channels 0 and 2 channel (n) interrupt channel (n+1) interrupt c(n+1)v[15:0] c(n)v[15:0] ch(n+1)ie ch(n+1)f ch(n)ie ch(n)f ftmen decapen decap ms(n)a els(n)b:els(n)a els(n+1)b:els(n+1)a clk clk d q d q 0 1 figure 39-244. dual edge capture mode block diagram the ms(n)a bit defines if the dual edge capture mode is one-shot or continuous. the els(n)b:els(n)a bits select the edge that is captured by channel (n), and els(n +1)b:els(n+1)a bits select the edge that is captured by channel (n+1). if both els(n)b:els(n)a and els(n+1)b:els(n+1)a bits select the same edge, then it is the period measurement. if these bits select different edges, then it is a pulse width measurement. in the dual edge capture mode, only channel (n) input is used and channel (n+1) input is ignored. if the selected edge by channel (n) bits is detected at channel (n) input, then ch(n)f bit is set and the channel (n) interrupt is generated (if ch(n)ie = 1). if the selected edge by channel (n+1) bits is detected at channel (n) input and (ch(n)f = 1), then ch(n+1)f bit is set and the channel (n+1) interrupt is generated (if ch(n+1)ie = 1). functional description k60 sub-family reference manual, rev. 6, nov 2011 1042 freescale semiconductor, inc. the c(n)v register stores the value of ftm counter when the selected edge by channel (n) is detected at channel (n) input. the c(n+1)v register stores the value of ftm counter when the selected edge by channel (n+1) is detected at channel (n) input. in this mode, the pair channels coherency mechanism ensures coherent data when the c(n)v and c(n+1)v registers are read. the only requirement is that c(n)v must be read before c(n+1)v. note ? the ch(n)f, ch(n)ie, ms(n)a, els(n)b, and els(n)a bits are channel (n) bits. ? the ch(n+1)f, ch(n+1)ie, ms(n+1)a, els(n+1)b, and els(n+1)a bits are channel (n+1) bits. ? it is expected that the dual edge capture mode be used with els(n)b:els(n)a = 0:1 or 1:0, els(n+1)b:els(n+1)a = 0:1 or 1:0 and the ftm counter in free running counter mode ( free running counter ). 39.4.24.1 one-shot capture mode the one-shot capture mode is selected when (ftmen = 1), (decapen = 1), and (ms(n)a = 0). in this capture mode, only one pair of edges at the channel (n) input is captured. the els(n)b:els(n)a bits select the first edge to be captured, and els(n +1)b:els(n+1)a bits select the second edge to be captured. the edge captures are enabled while decap bit is set. for each new measurement in one-shot capture mode, first the ch(n)f and ch(n+1) bits must be cleared, and then the decap bit must be set. in this mode, the decap bit is automatically cleared by ftm when the edge selected by channel (n+1) is captured. therefore, while decap bit is set, the one-shot capture is in process. when this bit is cleared, both edges were captured and the captured values are ready for reading in the c(n)v and c(n+1)v registers. similarly, when the ch(n+1)f bit is set, both edges were captured and the captured values are ready for reading in the c(n)v and c(n+1)v registers. chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1043 39.4.24.2 continuous capture mode the continuous capture mode is selected when (ftmen = 1), (decapen = 1), and (ms(n)a = 1). in this capture mode, the edges at the channel (n) input are captured continuously. the els(n)b:els(n)a bits select the initial edge to be captured, and els(n+1)b:els(n+1)a bits select the final edge to be captured. the edge captures are enabled while decap bit is set. for the initial use, first the ch(n)f and ch(n+1)f bits must be cleared, and then decap bit must be set to start the continuous measurements. when the ch(n+1)f bit is set, both edges were captured and the captured values are ready for reading in the c(n)v and c(n+1)v registers. the latest captured values are always available in these registers even after the decap bit is cleared. in this mode, it is possible to clear only the ch(n+1)f bit. therefore, when the ch(n+1)f bit is set again, the latest captured values are available in c(n)v and c(n+1)v registers. for a new sequence of the measurements in the dual edge capture C continuous mode, it is recommended to clear the ch(n)f and ch(n+1)f bits to start new measurements. 39.4.24.3 pulse width measurement if the channel (n) is configured to capture rising edges (els(n)b:els(n)a = 0:1) and the channel (n+1) to capture falling edges (els(n+1)b:els(n+1)a = 1:0), then the positive polarity pulse width is measured. if the channel (n) is configured to capture falling edges (els(n)b:els(n)a = 1:0) and the channel (n+1) to capture rising edges (els(n +1)b:els(n+1)a = 0:1), then the negative polarity pulse width is measured. the pulse width measurement can be made in one-shot capture mode ( one-shot capture mode ) or continuous capture mode ( continuous capture mode ). the following figure shows an example of the dual edge capture C one-shot mode used to measure the positive polarity pulse width. the decapen bit selects the dual edge capture mode, so it keeps set in all operation mode. the decap bit is set to enable the measurement of next positive polarity pulse width. the ch(n)f bit is set when the first edge of this pulse is detected, that is, the edge selected by els(n)b:els(n)a bits. the ch(n+1)f bit is set and decap bit is cleared when the second edge of this pulse is detected, that is, the edge selected by els(n+1)b:els(n+1)a bits. both decap and ch(n+1)f bits indicate when two edges of the pulse were captured and the c(n)v and c(n+1)v registers are ready for reading. functional description k60 sub-family reference manual, rev. 6, nov 2011 1044 freescale semiconductor, inc. channel (n) input (after the filter decapen bit c(n+1)v ftm counter clear ch(n+1)f problem 1 problem 2 2 1 2 3 channel input) decap bit set decapen set decap 5 6 7 8 10 3 4 6 5 note - the commands set decapen, set decap, clear ch(n)f, and clear ch(n+1)f are made by the user. 4 9 11 12 13 14 9 10 7 8 15 16 17 18 19 20 21 22 23 24 25 26 27 28 15 16 19 20 22 24 - problem 1: channel (n) input = 1, set decap, not clear ch(n)f, and clear ch(n+1)f. - problem 2: channel (n) input = 1, set decap, not clear ch(n)f, and not clear ch(n+1)f. c(n)v ch(n+1)f bit ch(n)f bit clear ch(n)f 1 figure 39-245. dual edge capture one-shot mode for positive polarity pulse width measurement the following figure shows an example of the dual edge capture C continuous mode used to measure the positive polarity pulse width. the decapen bit selects the dual edge capture mode, so it keeps set in all operation mode. while the decap bit is set the configured measurements are made. the ch(n)f bit is set when the first edge of the positive polarity pulse is detected, that is, the edge selected by els(n)b:els(n)a bits. the ch(n+1)f bit is set when the second edge of this pulse is detected, that is, the edge selected by els(n+1)b:els(n+1)a bits. the ch(n+1)f bit indicates when two edges of the pulse were captured and the c(n)v and c(n+1)v registers are ready for reading. chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1045 channel (n) input (after the filter decapen bit c(n+1)v ftm counter clear ch(n+1)f 2 1 2 3 channel input) decap bit set decapen set decap 5 6 7 8 10 3 4 6 5 note - the commands set decapen, set decap, clear ch(n)f, and clear ch(n+1)f are made by the user. 4 9 11 12 13 14 9 10 7 15 16 17 18 19 20 21 22 23 24 25 26 27 28 15 16 20 c(n)v ch(n+1)f bit ch(n)f bit clear ch(n)f 1 8 12 22 24 11 19 21 23 figure 39-246. dual edge capture continuous mode for positive polarity pulse width measurement 39.4.24.4 period measurement if the channels (n) and (n+1) are configured to capture consecutive edges of the same polarity, then the period of the channel (n) input signal is measured. if both channels (n) and (n+1) are configured to capture rising edges (els(n)b:els(n)a = 0:1 and els(n +1)b:els(n+1)a = 0:1), then the period between two consecutive rising edges is measured. if both channels (n) and (n+1) are configured to capture falling edges (els(n)b:els(n)a = 1:0 and els(n+1)b:els(n+1)a = 1:0), then the period between two consecutive falling edges is measured. the period measurement can be made in one-shot capture mode ( one-shot capture mode ) or continuous capture mode ( continuous capture mode ). functional description k60 sub-family reference manual, rev. 6, nov 2011 1046 freescale semiconductor, inc. the following figure shows an example of the dual edge capture C one-shot mode used to measure the period between two consecutive rising edges. the decapen bit selects the dual edge capture mode, so it keeps set in all operation mode. the decap bit is set to enable the measurement of next period. the ch(n)f bit is set when the first rising edge is detected, that is, the edge selected by els(n)b:els(n)a bits. the ch(n+1)f bit is set and decap bit is cleared when the second rising edge is detected, that is, the edge selected by els(n+1)b:els(n+1)a bits. both decap and ch(n+1)f bits indicate when two selected edges were captured and the c(n)v and c(n+1)v registers are ready for reading. channel (n) input (after the filter decapen bit c(n+1)v ftm counter clear ch(n+1)f problem 2 2 1 2 3 channel input) decap bit set decapen set decap 5 6 7 8 10 3 4 6 5 note - the commands set decapen, set decap, clear ch(n)f, and clear ch(n+1)f are made by the user. 4 9 11 12 13 14 6 15 16 17 18 19 20 21 22 23 24 25 26 27 28 17 20 15 20 23 c(n)v ch(n+1)f bit ch(n)f bit clear ch(n)f 1 - problem 1: channel (n) input = 0, set decap, not clear ch(n)f, and not clear ch(n+1)f. - problem 2: channel (n) input = 1, set decap, not clear ch(n)f, and clear ch(n+1)f. - problem 3: channel (n) input = 1, set decap, not clear ch(n)f, and not clear ch(n+1)f. problem 3 problem 1 7 9 18 26 18 14 27 7 figure 39-247. dual edge capture ? one-shot mode to measure of the period between two consecutive rising edges the following figure shows an example of the dual edge capture C continuous mode used to measure the period between two consecutive rising edges. the decapen bit selects the dual edge capture mode, so it keeps set in all operation mode. while the decap bit is set the configured measurements are made. the ch(n)f bit is set when the first rising chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1047 edge is detected, that is, the edge selected by els(n)b:els(n)a bits. the ch(n+1)f bit is set when the second rising edge is detected, that is, the edge selected by els(n +1)b:els(n+1)a bits. the ch(n+1)f bit indicates when two edges of the period were captured and the c(n)v and c(n+1)v registers are ready for reading. channel (n) input (after the filter decapen bit c(n+1)v ftm counter clear ch(n+1)f 2 1 2 3 channel input) decap bit set decapen set decap 5 6 7 8 10 3 4 6 5 note - the commands set decapen, set decap, clear ch(n)f, and clear ch(n+1)f are made by the user. 4 9 11 12 13 14 9 10 7 15 16 17 18 19 20 22 23 24 26 27 28 15 16 21 c(n)v ch(n+1)f bit ch(n)f bit clear ch(n)f 1 8 12 22 24 11 19 21 23 25 27 23 20 19 17 7 9 11 13 15 6 8 10 12 16 14 24 22 20 18 26 25 21 figure 39-248. dual edge capture ? continuous mode to measure of the period between two consecutive rising edges 39.4.24.5 read coherency mechanism the dual edge capture mode implements a read coherency mechanism between the ftm counter value captured in c(n)v and c(n+1)v registers. the read coherency mechanism is illustrated in the following figure. in this example, the channels (n) and (n+1) are in dual edge capture C continuous mode for positive polarity pulse width measurement. thus, the channel (n) is configured to capture the ftm counter value when there is a rising edge at channel (n) input signal, and channel (n+1) to capture the ftm counter value when there is a falling edge at channel (n) input signal. functional description k60 sub-family reference manual, rev. 6, nov 2011 1048 freescale semiconductor, inc. when a rising edge occurs in the channel (n) input signal, the ftm counter value is captured into channel (n) capture buffer. the channel (n) capture buffer value is transferred to c(n)v register when a falling edge occurs in the channel (n) input signal. c(n)v register has the ftm counter value when the previous rising edge occurred, and the channel (n) capture buffer has the ftm counter value when the last rising edge occurred. when a falling edge occurs in the channel (n) input signal, the ftm counter value is captured into channel (n+1) capture buffer. the channel (n+1) capture buffer value is transferred to c(n+1)v register when the c(n)v register is read. in the following figure, the read of c(n)v returns the ftm counter value when the event 1 occurred and the read of c(n+1)v returns the ftm counter value when the event 2 occurred. c(n)v register must be read prior to c(n+1)v register in dual edge capture one-shot and continuous modes for the read coherency mechanism works properly. read c(n+1)v ftm counter channel (n) input (after the filter channel input) channel (n) capture buffer c(n)v c(n+1)v channel (n+1) capture buffer event 1 event 2 event 3 event 4 event 5 event 6 event 7 event 8 event 9 1 2 3 4 5 6 7 8 9 9 1 3 7 5 6 8 4 2 2 1 3 5 7 read c(n)v figure 39-249. dual edge capture mode read coherency mechanism 39.4.25 quadrature decoder mode the quadrature decoder mode is selected if (ftmen = 1) and (quaden = 1). the quadrature decoder mode uses the input signals phase a and b to control the ftm counter increment and decrement. the following figure shows the quadrature decoder block diagram. each one of input signals phase a and b has a filter that is equivalent to the filter used in the channels input ( filter for input capture mode ). the phase a input filter is enabled by phafltren bit and this filters value is defined by ch0fval[3:0] bits chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1049 (ch(n)fval[3:0] bits in filter0 register). the phase b input filter is enabled by phbfltren bit and this filters value is defined by ch1fval[3:0] bits (ch(n +1)fval[3:0] bits in filter0 register). except for ch0fval[3:0] and ch1fval[3:0] bits, no channel logic is used in quadrature decoder mode. phase a input system clock phase b input synchronizer ch0fval[3:0] phafltren filtered phase a signal phapol phbpol filtered phase b signal phbfltren ch1fval[3:0] synchronizer filter clk d q clk d q clk d q clk d q filter filter ftm counter direction ftm counter enable up/down cntin mod tofdir quadir 0 1 0 1 figure 39-250. quadrature decoder block diagram note it is important to notice that the ftm counter is clocked by the phase a and b input signals when quadrature decoder mode is selected. therefore it is expected that the quadrature decoder be used only with the ftm channels in input capture or output compare modes. the phapol bit selects the polarity of the phase a input, and the phbpol bit selects the polarity of the phase b input. the quadmode selects the encoding mode used in the quadrature decoder mode. if quadmode = 1, then the count and direction encoding mode (see the following figure) is enabled. in this mode, the phase b input value indicates the counting direction (ftm counter increment or decrement), and the phase a input defines the counting rate (ftm counter is updated when there is a rising edge at phase a input signal). functional description k60 sub-family reference manual, rev. 6, nov 2011 1050 freescale semiconductor, inc. phase b (counting direction) phase a (counting rate) ftm counter increment/decrement ftm counter mod cntin 0x0000 time +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 figure 39-251. quadrature decoder count and direction encoding mode if quadmode = 0, then the phase a and phase b encoding mode (see the following figure) is enabled. in this mode, the relationship between phase a and b signals indicates the counting direction, and phase a and b signals define the counting rate (ftm counter is updated when there is an edge either at the phase a or phase b signals). if phapol = 0 and phbpol = 0, then the ftm counter increment happens when: ? there is a rising edge at phase a signal and phase b signal is at logic zero; ? there is a rising edge at phase b signal and phase a signal is at logic one; ? there is a falling edge at phase b signal and phase a signal is at logic zero; ? there is a falling edge at phase a signal and phase b signal is at logic one; and the ftm counter decrement happens when: ? there is a falling edge at phase a signal and phase b signal is at logic zero; ? there is a falling edge at phase b signal and phase a signal is at logic one; ? there is a rising edge at phase b signal and phase a signal is at logic zero; ? there is a rising edge at phase a signal and phase b signal is at logic one. chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1051 phase a phase b ftm counter increment/decrement ftm counter mod cntin 0x0000 time +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 figure 39-252. quadrature decoder phase a and phase b encoding mode the following figure shows the ftm counter overflow in up counting. in this case, when the ftm counter changes from mod to cntin, tof and tofdir bits are set. tof bit indicates the ftm counter overflow occurred. tofdir indicates the counting was up when the ftm counter overflow occurred. phase a phase b ftm counter increment/decrement ftm counter mod cntin 0x0000 time +1 +1 +1 +1 +1 +1 +1 set tof set tofdir set tof set tofdir +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 figure 39-253. ftm counter overflow in up counting for quadrature decoder mode the following figure shows the ftm counter overflow in down counting. in this case, when the ftm counter changes from cntin to mod, tof bit is set and tofdir bit is cleared. tof bit indicates the ftm counter overflow occurred. tofdir indicates the counting was down when the ftm counter overflow occurred. functional description k60 sub-family reference manual, rev. 6, nov 2011 1052 freescale semiconductor, inc. phase a phase b ftm counter increment/decrement ftm counter mod cntin 0x0000 time set tof clear tofdir -1 set tof clear tofdir -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 figure 39-254. ftm counter overflow in down counting for quadrature decoder mode 39.4.25.1 quadrature decoder boundary conditions the following figures are examples of motor jittering which causes the ftm counter transitions as indicated by these figures. it is expected to observe these behaviors in motor position control applications. phase a phase b ftm counter mod cntin 0x0000 time figure 39-255. motor position jittering in a mid count value chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1053 the following figure shows motor jittering produced by the phase b and a pulses respectively. the first highlighted transition causes a jitter on the ftm counter value near the maximum count value (mod). the second indicated transition occurs on phase a and causes the ftm counter transition between the maximum and minimum count values which are defined by mod and cntin registers. phase a phase b ftm counter mod cntin 0x0000 time figure 39-256. motor position jittering near maximum and minimum count value the appropriate settings of the phase a and phase b input filters are important to avoid glitches that may cause oscillation on the ftm counter value. the preceding figures show examples of oscillations that can be caused by poor input filter setup. thus, it is important to guarantee a minimum pulse width to avoid these oscillations. 39.4.26 bdm mode when the chip is in bdm mode, the bdmode[1:0] bits select the behavior of the ftm counter, the ch(n)f bit, the channels output, and the writes to the mod, cntin, and c(n)v registers according to the following table. table 39-249. ftm behavior when the chip is in bdm mode bdmmode ftm counter ch(n)f bit ftm channels output writes to mod, cntin, and c(n)v registers 00 stopped can be set functional mode writes to these registers bypass the registers buffers 01 stopped is not set the channels outputs are forced to their safe value according to poln bit writes to these registers bypass the registers buffers table continues on the next page... functional description 60 sub-family reference manual, rev. 6, nov 2011 104 freescale semiconductor, inc. table 39-249. ftm behavior when the chip is in bdm mode (continued) bdmmode ftm counter ch(n)f bit ftm channels output writes to mod, cntin, and c(n)v registers 10 stopped is not set the channels outputs are frozen when the chip enters in bdm mode writes to these registers bypass the registers buffers 11 functional mode can be set functional mode functional mode note that if bdmmode[1:0] = 2b00 then the channels outputs remain at the value when the chip enters in bdm mode, since the ftm counter is stopped. however, the following situations modify the channels outputs in this bdm mode. ? write any value to cnt register ( counter reset ). in this case, the ftm counter is updated with the cntin register value and the channels outputs are updated to the initial value C except for those channels set to output compare mode. ? ftm counter is reset by pwm synchronization mode ( ftm counter synchronization ). in this case, the ftm counter is updated with the cntin register value and the channels outputs are updated to the initial value C except for channels in output compare mode. ? in the channels outputs initialization ( initialization ), the channel (n) output is forced to the ch(n)oi bit value when the value 1 is written to init bit. note it is expected that the bdmmode[1:0] = 2b00 is not used with the fault control ( fault control ). even if the fault control is enabled and a fault condition exists, the channels outputs values are as defined above. 39.4.27 intermediate load the pwmload register allows software to update the mod, cntin, and c(n)v registers with the content of the register buffer at a defined load point. in this case it is not required to use the pwm synchronization control. a possible loading point is when the ftm counter wraps from mod value to cntin value. this loading point is always enabled. another possible loading point is at the channel (j) match (ftm counter = c(j)v). this loading point is enabled when chjsel = 1. the following figure shows some examples of enabled loading points. chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1055 after enabling the loading points, the ldok bit needs to be set for the load to occur. in this case the load occurs at the next enabled loading point according to the following conditions: ? if a new value was written to the mod register, then the mod register is updated with its write buffer value. ? if a new value was written to the cntin register and cntinc = 1, then the cntin register is updated with its write buffer value. ? if a new value was written to the c(n)v register and syncenm = 1 C where m indicates the pair channels (n) and (n+1), then the c(n)v register is updated with its write buffer value. ? if a new value was written to the c(n+1)v register and syncenm = 1 C where m indicates the pair channels (n) and (n+1), then the c(n+1)v register is updates with its write buffer value. note (c) (a) ldok = 0, ch0sel = 0, ch1sel = 0, ch2sel = 0, ch3sel = 0, ch4sel = 0, ch5sel = 0, ch6sel = 0, ch7sel = 0 (b) ldok = 1, ch0sel = 0, ch1sel = 0, ch2sel = 0, ch3sel = 0, ch4sel = 0, ch5sel = 0, ch6sel = 0, ch7sel = 0 (c) ldok = 0, ch0sel = 0, ch1sel = 0, ch2sel = 0, ch3sel = 1, ch4sel = 0, ch5sel = 0, ch6sel = 0, ch7sel = 0 (d) ldok = 1, ch0sel = 0, ch1sel = 0, ch2sel = 0, ch3sel = 0, ch4sel = 0, ch5sel = 0, ch6sel = 1, ch7sel = 0 (e) ldok = 1, ch0sel = 1, ch1sel = 0, ch2sel = 1, ch3sel = 0, ch4sel = 1, ch5sel = 0, ch6sel = 1, ch7sel = 0 (f) ldok = 1, ch0sel = 1, ch1sel = 1, ch2sel = 1, ch3sel = 1, ch4sel = 1, ch5sel = 1, ch6sel = 1, ch7sel = 1 (d) (e) (f) (b) (a) ftm counter = mod ftm counter = c7v ftm counter = c6v ftm counter = c5v ftm counter = c4v ftm counter = c3v ftm counter = c2v ftm counter = c1v ftm counter = c0v figure 39-257. loading points for intermediate load functional description k60 sub-family reference manual, rev. 6, nov 2011 1056 freescale semiconductor, inc. note ? if elsjb and elsja bits are different from zero, then the channel (j) output signal is generated according to the configured output mode. if elsjb and elsja bits are zero, then the generated signal is not available on channel (j) output. ? if chjie = 1, then the channel (j) interrupt is generated when the channel (j) match occurs. ? at the intermediate load neither the channels outputs nor the ftm counter are changed. software must set the intermediate load at a safe point in time. ? it is expected that the intermediate load feature be used only in combine mode. 39.4.28 global time base (gtb) the global time base (gtb) is a ftm function that allows the synchronization of multiple ftm modules on a chip. the following figure shows an example of the gtb feature used to synchronize two ftm modules. in this case, the ftm a and b channels can behave as if just one ftm module was used, that is, a global time base. gtbeout bit gtb_in gtb_out gtb_in example glue logic ftm module b ftm module a gtbeen bit ftm counter enable logic ftm counter enable gtb_out figure 39-258. global time base (gtb) block diagram the gtb functionality is implemented by the gtbeen and gtbeout bits in the conf register, the internal input signal gtb_in and the internal output signal gtb_out . the gtbeen bit enables gtb_in to control the ftm counter enable signal: ? if gtbeen = 0, each one of ftm modules works independently according to their configured mode. ? if gtbeen = 1, the ftm counter update is enabled only when gtb_in is 1. chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1057 in the configuration described in the preceding figure, ftm modules a and b have their ftm counters enabled if at least one of the gtb_out signals from one of the ftm modules is 1. there are several possible configurations for the interconnection of the gtb_in and gtb_out signals (represented by the example glue logic shown in the figure). note that these configurations are chip-dependent and implemented outside of the ftm modules. see the chip configuration details for the chip's specific implementation. note ? in order to use the internal gtb signals to synchronize the ftm counter of different ftm modules, the configuration of each ftm module should guarantee that its ftm counter starts counting as soon as the gtb_in signal is 1. ? the gtb feature does not provide continuous synchronization of ftm counters, meaning that the ftm counters may lose synchronization during ftm operation. the gtb feature only allows the ftm counters to start their operation synchronously. 39.4.28.1 enabling the global time base (gtb) to enable the gtb feature, follow these steps for each participating ftm module: 1. stop the ftm counter: write 00b to sc[clks]. 2. program the ftm module to the intended configuration. (the operation mode needs to be consistent across all participating modules.) 3. write 1 to conf[gtbeen] and write 0 to conf[gtbeout] at the same time. 4. select the intended ftm counter clock source in sc[clks]. (the clock source needs to be consistent across all participating modules.) 5. reset the ftm counter: write any value to the cnt register. to initiate the gtb feature, follow these steps for the ftm module used as the time base: 1. write 1 to conf[gtbeout]. 2. if needed, configure the gtb glue logic connecting the ftm modules within the chip. some chips do not require configuration of glue logic. see the chip configuration details for the chip's specific implementation. 39.5 reset overview the ftm is reset whenever any chip reset occurs. reset overview k60 sub-family reference manual, rev. 6, nov 2011 1058 freescale semiconductor, inc. when the ftm exits from reset: ? the ftm counter and the prescaler counter are zero and are stopped (clks[1:0] = 00b); ? the timer overflow interrupt is zero ( timer overflow interrupt ); ? the channels interrupts are zero ( channel (n) interrupt ); ? the fault interrupt is zero ( fault interrupt ); ? the channels are in input capture mode ( input capture mode ); ? the channels outputs are zero; ? the channels pins are not controlled by ftm (els(n)b:els(n)a = 0:0) (). the following figure shows the ftm behavior after the reset. at the reset (item 1), the ftm counter is disabled (see the description of the clks field in the status and control register), its value is updated to zero and the pins are not controlled by ftm (). after the reset, the ftm should be configurated (item 2). it is necessary to define the ftm counter mode, the ftm counting limits (mod and cntin registers value), the channels mode and cnv registers value according to the channels mode. thus, it is recommended to write any value to cnt register (item 3). this write updates the ftm counter with the cntin register value and the channels output with its initial value (except for channels in output compare mode) ( counter reset ). the next step is to select the ftm counter clock by the clks[1:0] bits (item 4). it is important to highlight that the pins are only controlled by ftm when clks[1:0] bits are different from zero (). (1) ftm reset 0x0016 0x0015 0x0014 0x0013 0x0011 . . . 0x0010 0x0018 0x0017 xxxx 0x0000 0x0012 ftm counter clks[1:0] channel (n) output (4) write 1 to sc[clks] (3) write any value to cnt register (2) ftm configuration channel (n) pin is controlled by ftm notes: ? cntin = 0x0010 ? channel (n) is in low-true combine mode with cntin < c(n)v < c(n+1)v < mod ? c(n)v = 0x0015 00 xx 01 figure 39-259. ftm behavior after reset when the channel (n) is in combine mode chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1059 the following figure shows an example when the channel (n) is in output compare mode and the channel (n) output is toggled when there is a match. in the output compare mode, the channel output is not updated to its initial value when there is a write to cnt register (item 3). in this case, it is recommended to use the software output control ( software output control ) or the initialization ( initialization ) to update the channel output to the selected value (item 4). (1) ftm reset 0x0015 0x0014 0x0013 0x0012 . . . 0x0010 0x0017 0x0016 xxxx 0x0000 0x0011 ftm counter clks[1:0] channel (n) output (5) write 1 to sc[clks] (3) write any value to cnt register (2) ftm configuration channel (n) pin is controlled by ftm notes: ? cntin = 0x0010 ? channel (n) is in output compare and the channel (n) output is toggled when there is a match ? c(n)v = 0x0014 00 xx 01 (4) use of software output control or initialization to update the channel output to the zero figure 39-260. ftm behavior after reset when the channel (n) is in output compare mode 39.6 ftm interrupts this section describes ftm interrupts. 39.6.1 timer overflow interrupt the timer overflow interrupt is generated when (toie = 1) and (tof = 1). 39.6.2 channel (n) interrupt the channel (n) interrupt is generated when (chnie = 1) and (chnf = 1). ftm interrupts k60 sub-family reference manual, rev. 6, nov 2011 1060 freescale semiconductor, inc. 39.6.3 fault interrupt the fault interrupt is generated when (faultie = 1) and (faultf = 1). chapter 39 flextimer (ftm) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1061 ftm interrupts k60 sub-family reference manual, rev. 6, nov 2011 1062 freescale semiconductor, inc. chapter 40 periodic interrupt timer (pit) 40.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the pit timer module is an array of timers that can be used to raise interrupts and trigger dma channels. 40.1.1 block diagram the following figure shows the pit block diagram. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1063 timer n timer 1 pit registers peripheral load_value pit triggers bus clock bus peripheral iinterrupts figure 40-1. block diagram of the pit note refer to the chip configuration information for the number of pit channels used in this mcu. 40.1.2 features the main features of this block are: ? timers can generate dma trigger pulses ? timers can generate interrupts ? all interrupts are maskable ? independent timeout periods for each timer 40.2 signal description the pit module has no external pins. signal description k60 sub-family reference manual, rev. 6, nov 2011 1064 freescale semiconductor, inc. 40.3 memory map/register description this section provides a detailed description of all registers accessible in the pit module. note reserved registers will read as 0, writes will have no effect. note refer to the chip configuration information for the number of pit channels used in this mcu. pit memory map absolute address (hex) register name width (in bits) access reset value section/ page 4003_7000 pit module control register (pit_mcr) 32 r/w 0000_0002h 40.3.1/ 1066 4003_7100 timer load value register (pit_ldval0) 32 r/w 0000_0000h 40.3.2/ 1067 4003_7104 current timer value register (pit_cval0) 32 r/w 0000_0000h 40.3.3/ 1067 4003_7108 timer control register (pit_tctrl0) 32 r/w 0000_0000h 40.3.4/ 1068 4003_710c timer flag register (pit_tflg0) 32 r/w 0000_0000h 40.3.5/ 1068 4003_7110 timer load value register (pit_ldval1) 32 r/w 0000_0000h 40.3.2/ 1067 4003_7114 current timer value register (pit_cval1) 32 r/w 0000_0000h 40.3.3/ 1067 4003_7118 timer control register (pit_tctrl1) 32 r/w 0000_0000h 40.3.4/ 1068 4003_711c timer flag register (pit_tflg1) 32 r/w 0000_0000h 40.3.5/ 1068 4003_7120 timer load value register (pit_ldval2) 32 r/w 0000_0000h 40.3.2/ 1067 4003_7124 current timer value register (pit_cval2) 32 r/w 0000_0000h 40.3.3/ 1067 4003_7128 timer control register (pit_tctrl2) 32 r/w 0000_0000h 40.3.4/ 1068 4003_712c timer flag register (pit_tflg2) 32 r/w 0000_0000h 40.3.5/ 1068 table continues on the next page... chapter 40 periodic interrupt timer pit 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 106 pit memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4003_7130 timer load value register (pit_ldval3) 32 r/w 0000_0000h 40.3.2/ 1067 4003_7134 current timer value register (pit_cval3) 32 r/w 0000_0000h 40.3.3/ 1067 4003_7138 timer control register (pit_tctrl3) 32 r/w 0000_0000h 40.3.4/ 1068 4003_713c timer flag register (pit_tflg3) 32 r/w 0000_0000h 40.3.5/ 1068 40.3.1 pit module control register (pit_mcr) this register controls whether the timer clocks should be enabled and whether the timers should run in debug mode. address: pit_mcr is 4003_7000h base + 0h offset = 4003_7000h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 mdis frz w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 pit_mcr field descriptions field description 31?2 reserved this read-only field is reserved and always has the value zero. 1 mdis module disable this is used to disable the module clock. this bit must be enabled before any other setup is done. 0 clock for pit timers is enabled. 1 clock for pit timers is disabled. 0 frz freeze allows the timers to be stopped when the device enters debug mode. 0 timers continue to run in debug mode. 1 timers are stopped in debug mode. memory map/register description k60 sub-family reference manual, rev. 6, nov 2011 1066 freescale semiconductor, inc. 40.3.2 timer load value register (pit_ldval n these registers select the timeout period for the timer interrupts. addresses: pit_ldval0 is 4003_7000h base + 100h offset = 4003_7100h pit_ldval1 is 4003_7000h base + 110h offset = 4003_7110h pit_ldval2 is 4003_7000h base + 120h offset = 4003_7120h pit_ldval3 is 4003_7000h base + 130h offset = 4003_7130h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r tsv w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pit_ldval n iel escritions fiel escrition ier tart alue its hese its set the tier start alue he tier will count own until it reaches then it will enerate an interrut an loa this reister alue aain ritin a new alue to this reister will not restart the tier instea the alue will e loae once the tier exires o aort the current cycle an start a tier erio with the new alue the tier ust e isale an enale aain urrent ier alue reister l n these registers indicate the current timer position. addresses: pit_cval0 is 4003_7000h base + 104h offset = 4003_7104h pit_cval1 is 4003_7000h base + 114h offset = 4003_7114h pit_cval2 is 4003_7000h base + 124h offset = 4003_7124h pit_cval3 is 4003_7000h base + 134h offset = 4003_7134h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r tvl w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pit_cval n iel escritions fiel escrition l urrent ier alue the tier is enale these its reresent the current tier alue the tier is isale o not use this iel as its alue is unreliale o: he tier uses a owncounter he tier alues are roen in eu oe i the rfr it is set hater erioic nterrut ier ufaily reerence anual re o freescale eiconuctor nc 40.3.4 timer control register (pit_tctrl n these register contain the control bits for each timer. addresses: pit_tctrl0 is 4003_7000h base + 108h offset = 4003_7108h pit_tctrl1 is 4003_7000h base + 118h offset = 4003_7118h pit_tctrl2 is 4003_7000h base + 128h offset = 4003_7128h pit_tctrl3 is 4003_7000h base + 138h offset = 4003_7138h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 tie ten w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pit_tctrl n iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero ier nterrut nale it hen an interrut is enin f set enalin the interrut will ieiately cause an interrut eent o aoi this the associate f la ust e cleare irst nterrut requests ro ier n are isale nterrut will e requeste wheneer f is set ier nale it his it enales or isales the tier ier n is isale ier n is actie ier fla reister fl n these registers hold the pit interrupt flags. addresses: pit_tflg0 is 4003_7000h base + 10ch offset = 4003_710ch pit_tflg1 is 4003_7000h base + 11ch offset = 4003_711ch pit_tflg2 is 4003_7000h base + 12ch offset = 4003_712ch pit_tflg3 is 4003_7000h base + 13ch offset = 4003_713ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 tif w w1c reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 memory map/register description k60 sub-family reference manual, rev. 6, nov 2011 1068 freescale semiconductor, inc. pit_tflg n iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero f ier nterrut fla f is set to at the en o the tier erio his la can e cleare only y writin it with ritin has no eect enale f causes an interrut request ieout has not yet occurre ieout has occurre functional escrition this section provides the functional description of the module. 40.4.1 general this section gives detailed information on the internal operation of the module. each timer can be used to generate trigger pulses as well as to generate interrupts. each interrupt is available on a separate interrupt line. 40.4.1.1 timers the timers generate triggers at periodic intervals, when enabled. they load their start values, as specified in their ldval registers, then count down until they reach 0. then they load their respective start value again. each time a timer reaches 0, it will generate a trigger pulse and set the interrupt flag. all interrupts can be enabled or masked (by setting the tie bits in the tctrl registers). a new interrupt can be generated only after the previous one is cleared. if desired, the current counter value of the timer can be read via the cval registers. the counter period can be restarted, by first disabling, then enabling the timer with the ten bit (see the following figure). chapter 40 periodic interrupt timer (pit) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1069 p1 timer enabled disable timer p1 p1 re-enable timer start value = p1 trigger event p1 figure 40-23. stopping and starting a timer the counter period of a running timer can be modified, by first disabling the timer, setting a new load value and then enabling the timer again (see the following figure). timer enabled disable timer, p1 p1 re-enable timer start value = p1 trigger event set new load value p2 p2 p2 figure 40-24. modifying running timer period it is also possible to change the counter period without restarting the timer by writing the ldval register with the new load value. this value will then be loaded after the next trigger event (see the following figure). timer enabled p1 p1 start value = p1 trigger event p2 p2 p1 new start value p2 set figure 40-25. dynamically setting a new load value 40.4.1.2 debug mode in debug mode, the timers will be frozen based on frz bit in pit module control register. this is intended to aid software development, allowing the developer to halt the processor, investigate the current state of the system (for example, the timer values) and then continue the operation. functional description k60 sub-family reference manual, rev. 6, nov 2011 1070 freescale semiconductor, inc. 40.4.2 interrupts all of the timers support interrupt generation. refer to the mcu specification for related vector addresses and priorities. timer interrupts can be enabled by setting the tie bits. the timer interrupt flags (tif) are set to 1 when a timeout occurs on the associated timer, and are cleared to 0 by writing a 1 to that tif bit. 40.5 initialization and application information in the example configuration: ? the pit clock has a frequency of 50 mhz. ? timer 1 creates an interrupt every 5.12 ms. ? timer 3 creates a trigger event every 30 ms. first the pit module must be activated by writing a 0 to the mdis bit in the mcr. the 50 mhz clock frequency equates to a clock period of 20 ns. timer 1 needs to trigger every 5.12 ms/20 ns = 256000 cycles and timer 3 every 30 ms/20 ns = 1500000 cycles. the value for the ldval register trigger is calculated as: ldval trigger = (period / clock period) -1 this means ldval1 should be written with 0x0003e7ff, and ldval3 should be written with 0x0016e35f. the interrupt for timer 1 is enabled by setting tie in the tctrl1 register. the timer is started by writing 1 to bit ten in the tctrl1 register. timer 3 shall be used only for triggering. therefore timer 3 is started by writing a 1 to bit ten in the tctrl3 register, bit tie stays at 0. the following example code matches the described setup: // turn on pit pit_mcr = 0x00; // timer 1 pit_ldval1 = 0x0003e7ff; // setup timer 1 for 256000 cycles pit_tctrl1 = tie; // enable timer 1 interrupts pit_tctrl1 |= ten; // start timer 1 // timer 3 chapter 40 periodic interrupt timer (pit) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1071 pit_ldval3 = 0x0016e35f; // setup timer 3for 1500000 cycles pit_tctrl3 |= ten; // start timer 3 initialization and application information k60 sub-family reference manual, rev. 6, nov 2011 1072 freescale semiconductor, inc. chapter 41 low power timer (lptmr) 41.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the low power timer (lptmr) can be configured to operate as a time counter (with optional prescaler) or as a pulse counter (with optional glitch filter) across all power modes, including the low leakage modes. it can also continue operating through most system reset events, allowing it to be used as a time of day counter. 41.1.1 features the lptmr module's features include: ? 16-bit time counter or pulse counter with compare ? optional interrupt can generate asynchronous wakeup from any low power mode ? hardware trigger output ? counter supports free-running mode or reset on compare ? configurable clock source for prescaler/glitch filter ? configurable input source for pulse counter ? rising edge or falling edge 41.1.2 modes of operation 41.1.2.1 run mode in run mode, the lptmr operates normally. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1073 41.1.2.2 wait mode in wait mode, the lptmr continues to operate normally and may be configured to exit the low power mode by generating an interrupt request. 41.1.2.3 stop mode in stop mode, the lptmr continues to operate normally and may be configured to exit the low power mode by generating an interrupt request. 41.1.2.4 low leakage modes in low leakage modes, the lptmr continues to operate normally and may be configured to exit the low power mode by generating an interrupt request. 41.1.2.5 debug modes in debug mode, the lptmr operates normally. 41.2 lptmr signal descriptions table 41-1. lptmr signal descriptions signal description i/o lptmr_alt n pulse counter input pin i ptmr signal descriptions 60 sub-family reference manual, rev. 6, nov 2011 1074 freescale semiconductor, inc. 41.2.1 detailed signal descriptions table 41-2. lptmr interface-detailed signal descriptions signal i/o description lptmr_alt n i pulse counter input. the ptmr can select one of the input pins to be used in pulse counter mode. state meaning assertion-if configured for pulse counter mode with active high input then assertion causes the ptmr counter register to increment. negation-if configured for pulse counter mode with active low input then negation cause the ptmr counter register to increment. timing assertion or negation may occur at any time input may assert asynchronously to the bus cloc. 41. memory map and register definition nte the lptmr registers are reset only on a por or lvd event. see lptmr power and reset for more details. lptmr memory map absolute address (hex) register name width (in bits) access reset value section/ page 4004_0000 low power timer control status register (lptmr0_csr) 32 r/w 0000_0000h 41.3.1/ 1076 4004_0004 low power timer prescale register (lptmr0_psr) 32 r/w 0000_0000h 41.3.2/ 1077 4004_0008 low power timer compare register (lptmr0_cmr) 32 r/w 0000_0000h 41.3.3/ 1079 4004_000c low power timer counter register (lptmr0_cnr) 32 r 0000_0000h 41.3.4/ 1079 chapter 41 low power timer (lptmr) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1075 41.3.1 low power timer control status register (lptmr x r resses: lrr is h ase h oset h it r reset it r f f wc reset lr x r iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero f ier oare fla he tier coare la is set when the lr is enale an the lr ounter reister equals the lr oare reister an increents his ier oare fla is cleare when the lr is isale or a loic one is written to the ier oare fla lr ounter reister has not equale the lr oare reister an increente lr ounter reister has equale the lr oare reister an increente ier nterrut nale hen the ier nterrut nale is set the lr nterrut is enerate wheneer the ier oare fla is also set ier nterrut isale ier nterrut nale ier in elect he ier in elect coniures the inut source to e use in ulse ounter oe he ier in elect shoul only e altere when the lr is isale he inut connections ary y eice ee the hi oniuration etails or inoration on the connections to these inuts ulse counter inut is selecte ulse counter inut is selecte ulse counter inut is selecte ulse counter inut is selecte ier in olarity table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 1076 freescale semiconductor, inc. lptmr x r iel escritions continue fiel escrition he ier in olarity coniures the olarity o the inut source in ulse ounter oe he ier in olarity shoul only e chane when the lr is isale ulse ounter inut source is actie hih an lr ounter reister will increent on the risin ee ulse ounter inut source is actie low an lr ounter reister will increent on the allin ee f ier free runnin ounter hen clear the ier free runnin ounter coniures the lr ounter reister to reset wheneer the ier oare fla is set hen set the ier free runnin ounter coniures the lr ounter reister to reset on oerlow he ier free runnin ounter shoul only e altere when the lr is isale lr ounter reister is reset wheneer the ier oare fla is set lr ounter reister is reset on oerlow ier oe elect he ier oe elect coniures the oe o the lr he ier oe elect shoul only e altere when the lr is isale ie ounter oe ulse ounter oe ier nale hen the ier nale it is clear it resets the lr internal loic incluin the lr ounter reister an ier oare fla hen the ier nale it is set the lr is enale hen writin to this it its lrr: shoul not e altere lr is isale an internal loic is reset lr is enale low ower ier rescale reister lr x r resses: lrr is h ase h oset h it r rl reset lr x r iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero table continues on the next page... chapter 41 ow power timer ptmr 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1077 lptmr x r iel escritions continue fiel escrition rl rescale alue he rescaler alue reister iel coniures the sie o the rescaler in ie ounter oe or with o the litch filter in ulse ounter oe he rescale alue shoul only e altere when the lr is isale rescaler iies the rescaler cloc y litch filter oes not suort this coniuration rescaler iies the rescaler cloc y litch filter reconies chane on inut in ater risin cloc ees rescaler iies the rescaler cloc y litch filter reconies chane on inut in ater risin cloc ees rescaler iies the rescaler cloc y litch filter reconies chane on inut in ater risin cloc ees rescaler iies the rescaler cloc y litch filter reconies chane on inut in ater risin cloc ees rescaler iies the rescaler cloc y litch filter reconies chane on inut in ater risin cloc ees rescaler iies the rescaler cloc y litch filter reconies chane on inut in ater risin cloc ees rescaler iies the rescaler cloc y litch filter reconies chane on inut in ater risin cloc ees rescaler iies the rescaler cloc y litch filter reconies chane on inut in ater risin cloc ees rescaler iies the rescaler cloc y litch filter reconies chane on inut in ater risin cloc ees rescaler iies the rescaler cloc y litch filter reconies chane on inut in ater risin cloc ees rescaler iies the rescaler cloc y litch filter reconies chane on inut in ater risin cloc ees rescaler iies the rescaler cloc y litch filter reconies chane on inut in ater risin cloc ees rescaler iies the rescaler cloc y litch filter reconies chane on inut in ater risin cloc ees rescaler iies the rescaler cloc y litch filter reconies chane on inut in ater risin cloc ees rescaler iies the rescaler cloc y litch filter reconies chane on inut in ater risin cloc ees rescaler yass hen the rescaler yass is set the selecte rescaler cloc in ie ounter oe or selecte inut source in ulse ounter oe irectly clocs the lr ounter reister hen the rescaler yass is clear the lr ounter reister is cloce y the outut o the rescalerlitch ilter he rescaler yass shoul only e altere when the lr is isale rescalerlitch filter is enale rescalerlitch filter is yasse rescaler loc elect he rescaler loc elect selects the cloc to e use y the lr rescalerlitch ilter he rescaler loc elect shoul only e altere when the lr is isale he cloc connections ary y eice ee the hi oniuration etails or inoration on the connections to these inuts table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 1078 freescale semiconductor, inc. lptmr x r iel escritions continue fiel escrition rescalerlitch ilter cloc selecte rescalerlitch ilter cloc selecte rescalerlitch ilter cloc selecte rescalerlitch ilter cloc selecte low ower ier oare reister lr x r resses: lrr is h ase h oset h it r or reset lr x r iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero or oare alue hen the lr is enale an the lr ounter reister equals the alue in the lr oare reister an increents the ier oare fla is set an the harware rier asserts until the next tie the lr ounter reister increents the lr oare reister is ero the harware rier will reain asserte until the lr is isale the lr is enale the lr oare reister shoul only e altere when the ier oare fla is set low ower ier ounter reister lr x r resses: lrr is h ase h oset h it r our reset lr x r iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero table continues on the next page... chapter 41 ow power timer ptmr 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 107 lptmr x r iel escritions continue fiel escrition our ounter alue he lr ounter reister returns the current alue o the lr ounter functional escrition lr ower an reset the lptmr remains powered in all power modes, including low leakage modes. if the lptmr is not required to remain operating during a low power mode, then it should be disabled before entering the mode. the lptmr is reset only on global por or lvd. when configuring the lptmr registers, the control status register should be initially written with the timer disabled, before configuring the lptmr prescale register and compare register. the timer enable should then be set as the last step in the initialization. this ensures the lptmr is configured correctly and the lptmr counter is reset to zero following a warm reset. 41.4.2 lptmr clocking the lptmr prescaler/glitch filter can be clocked by one of four clocks. the clock source should be enabled before the lptmr is enabled. note the clock source selected may need to be configured to remain enabled in low power modes, otherwise the lptmr will not operate during low power modes. in pulse counter mode with the prescaler/glitch filter bypassed, the selected input source directly clocks the lptmr counter register and no other clock source is required. to minimize power in this case, configure the prescaler clock source for a clock that is not toggling. note the clock source or pulse input source selected for the lptmr should not exceed the frequency f lptmr defined in the device datasheet. functional description k60 sub-family reference manual, rev. 6, nov 2011 1080 freescale semiconductor, inc. 41.4.3 lptmr prescaler/glitch filter the lptmr prescaler and glitch filter share the same logic which operates as a prescaler in time counter mode and as a glitch filter in pulse counter mode. the prescaler/glitch filter configuration must not be altered when the lptmr is enabled. 41.4.3.1 prescaler enabled in time counter mode when the prescaler is enabled, the output of the prescaler directly clocks the lptmr counter register. when the lptmr is enabled, the lptmr counter register will increment every 2 2 to 2 16 prescaler clock cycles. after the lptmr is enabled, the first increment of the lptmr counter register will take an additional one or two prescaler clock cycles due to synchronization logic. 41.4.3.2 prescaler bypassed in time counter mode when the prescaler is bypassed, the selected prescaler clock increments the lptmr counter register on every clock cycle. when the lptmr is enabled, the first increment will take an additional one or two prescaler clock cycles due to synchronization logic. 41.4.3.3 glitch filter in pulse counter mode when the glitch filter is enabled, the output of the glitch filter directly clocks the lptmr counter register. when the lptmr is first enabled, the output of the glitch filter is asserted (logic one for active high and logic zero for active low). if the selected input source remains negated for at least 2 1 to 2 15 consecutive prescaler clock rising edges, then the glitch filter output will also negate. if the selected input source remains asserted for at least 2 1 to 2 15 consecutive prescaler clock rising edges, then the glitch filter output will also assert. note that the input is only sampled on the rising clock edge. the lptmr counter register will increment each time the glitch filter output asserts. in pulse counter mode, the maximum rate at which the lptmr counter register can increment is once every 2 2 to 2 16 prescaler clock edges. when first enabled, the glitch filter will wait an additional one or two prescaler clock edges due to synchronization logic. chapter 41 low power timer (lptmr) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1081 41.4.3.4 glitch filter bypassed in pulse counter mode when the glitch filter is bypassed, the selected input source increments the lptmr counter register every time it asserts. before the lptmr is first enabled, the selected input source is forced to asserted. this is to prevent the lptmr counter register from incrementing if the selected input source is already asserted when the lptmr is first enabled. 41.4.4 lptmr compare when the lptmr counter register equals the value of the lptmr compare register and increments, the following events occur: ? timer compare flag is set ? lptmr interrupt is generated if timer interrupt enable is also set ? lptmr hardware trigger is generated ? lptmr counter register is reset if the free running counter bit is clear when the lptmr is enabled, the lptmr compare register can only be altered when the timer compare flag is set. when updating the lptmr compare register, the lptmr compare register must be written and the timer compare flag must be cleared before the lptmr counter has incremented past the new lptmr compare value. 41.4.5 lptmr counter the lptmr counter register increments by one on every: ? prescaler clock (time counter mode with prescaler bypassed) ? prescaler output (time counter mode with prescaler enabled) ? input source assertion (pulse counter mode with glitch filter bypassed) ? glitch filter output (pulse counter mode with glitch filter enabled). the lptmr counter register is reset when the lptmr is disabled or if the counter register overflows. if the csr[tfc] control bit is set then the lptmr counter register is also reset whenever the csr[tcf] status flag is set. the lptmr counter register continues incrementing when the core is halted in debug mode. functional description k60 sub-family reference manual, rev. 6, nov 2011 1082 freescale semiconductor, inc. the lptmr counter register cannot be initialized, but can be read at any time. reading the lptmr counter register at the same time as it is incrementing may return invalid data due to synchronization of the read data bus. if it is necessary for software to read the lptmr counter register, it is recommended that two read accesses are performed and software verifies that the same data was returned for both reads. 41.4.6 lptmr hardware trigger the lptmr hardware trigger asserts at the same time the timer compare flag is set and can be used to trigger hardware events in other peripherals without software intervention. the hardware trigger is always enabled. when the lptmr compare register is set to zero with the free running counter bit clear, the lptmr hardware trigger will assert on the first compare and does not negate. when the lptmr compare register is set to a non-zero value (or if the free running counter bit is set) the lptmr hardware trigger will assert on each compare and negate on the following increment of the lptmr counter register. 41.4.7 lptmr interrupt the lptmr interrupt is generated whenever the csr[tie] and csr[tcf] are set. the csr[tcf] is cleared by disabling the lptmr or by writing a logic one to it. the csr[tie] can be altered and the csr[tcf] can be cleared while the lptmr is enabled. the lptmr interrupt is generated asynchronously to the system clock and can be used to generate a wakeup from any low power mode, including the low leakage modes (provided the lptmr is enabled as a wakeup source). chapter 41 low power timer (lptmr) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1083 functional description k60 sub-family reference manual, rev. 6, nov 2011 1084 freescale semiconductor, inc. chapter 42 carrier modulator transmitter (cmt) 42.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the carrier modulator transmitter (cmt) module provides means to generate the protocol timing and carrier signals for a wide variety of encoding schemes. the cmt incorporates hardware to off-load the critical and/or lengthy timing requirements associated with signal generation from the cpu, releasing much of its bandwidth to handle other tasks such as code data generation, data decompression, or keyboard scanning. the cmt does not include dedicated hardware configurations for specific protocols but is intended to be sufficiently programmable in its function to handle the timing requirements of most protocols with minimal cpu intervention. when the modulator is disabled, certain cmt registers can be used to change the state of the infrared output (cmt_iro) signal directly. this feature allows for the generation of future protocol timing signals not readily producible by the current architecture. 42.2 features the features of this module include: ? four modes of operation ? time; with independent control of high and low times ? baseband ? frequency shift key (fsk) ? direct software control of cmt_iro signal k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1085 ? extended space operation in time, baseband, and fsk modes ? selectable input clock divider ? interrupt on end of cycle ? ability to disable cmt_iro signal and use as timer interrupt 42.3 block diagram the following figure is the cmt block diagram. modulator cmt_iro car r ier gener ator cmt registers clock divider cmt interrupts peripheral bus clock peripheral bus cmt divider_enable figure 42-1. cmt module block diagram block diagram k60 sub-family reference manual, rev. 6, nov 2011 1086 freescale semiconductor, inc. 42.4 modes of operation the cmt module operates in the following modes. ? timewhen operating in time mode, the user independently defines the high and low times of the carrier signal to determine both period and duty cycle. ? basebandwhen msc[base] bit is set, the carrier output (f cg ) to the modulator is held high continuously to allow for the generation of baseband protocols. ? frequency shift key (fsk)this mode allows the carrier generator to alternate between two sets of high and low times . when operating in fsk mode, the generator will toggle between the two sets when instructed by the modulator, allowing the user to dynamically switch between two carrier frequencies without cpu intervention. the following table summarizes the cmt's modes. table 42-1. cmt modes of operation mode msc[mcgen] 1 msc[base] 2 msc[fsk] 2 msc[exspc] comment time 1 0 0 0 f cg controlled by primary high and low registers. f cg transmitted to cmt_iro signal when modulator gate is open. baseband 1 1 x 0 f cg is always high. cmt_iro signal high when modulator gate is open. fsk 1 0 1 0 f cg control alternates between primary high/low registers and secondary high/low registers. f cg transmitted to cmt_iro signal when modulator gate is open. extended space 1 x x 1 setting msc[exspc] bit causes subsequent modulator cycles to be spaces (modulator out not asserted) for the duration of the modulator period (mark and space times). iro latch 0 x x x oc[irol] bit controls state of cmt_iro signal. 1. to prevent spurious operation, initialize all data and control registers before beginning a transmission (msc[mcgen]=1). 2. these bits are not double buffered and should not be changed during a transmission (while msc[mcgen]=1). chapter 42 carrier modulator transmitter (cmt) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1087 note the assignment of module modes to core modes is chip- specific. for module-to-core mode assignments, see the chapter that describes how modules are configured. 42.4.1 wait mode operation during wait mode, the cmt if enabled, will continue to operate normally . however, there is no change in operating modes of cmt while in wait mode, because the cpu is not operating. 42.4.2 stop mode operation this section describes the cmt stop mode operations. 42.4.2.1 normal stop mode operation during normal stop mode, clocks to the cmt module are halted . no registers are affected. because the clocks are halted, the cmt will resume upon exit from normal stop. software should ensure that the normal stop mode is not entered while the modulator is still in operation to prevent the cmt_iro signal from being asserted while in normal stop mode. this may require a time-out period from the time that msc[mcgen] bit is cleared to allow the last modulator cycle to complete. 42.4.2.2 low power stop mode operation during low power stop mode, the cmt module is completely powered off internally and the cmt_iro signal state at the time that low power stop mode is entered is latched and held. to prevent the cmt_iro signal from being asserted while in low power stop mode, software should assure that the signal is not active when entering low power stop mode. upon wake-up from low power stop mode, the cmt module will be in the reset state. modes of operation k60 sub-family reference manual, rev. 6, nov 2011 1088 freescale semiconductor, inc. 42.5 cmt external signal descriptions this table shows the description of the external signal. table 42-2. cmt signal descriptions signal description i/o cmt_iro infrared output o 42.5.1 cmt_iro infrared output this output signal is driven by the modulator output when msc[mcgen] is set and oc[iropen] is set. the cmt_iro signal starts a valid transmission with a delay, after msc[mcgen] bit be asserted to high, that can be calculated based on two register bits. the following table shows how to calculate this delay. if msc[mcgen] bit is cleared and oc[iropen] bit is set, the signal is driven by oc[irol] bit. this enables user software to directly control the state of the cmt_iro signal by writing to oc[irol] bit. if oc[iropen] bit is cleared, the signal is disabled and is not driven by the cmt module. therefore, cmt can be configured as a modulo timer for generating periodic interrupts without causing signal activity. table 42-3. cmt_iro signal delay calculation condition delay (bus clock cycles) msc[cmtdiv] = 0 pps[ppsdiv] + 2 msc[cmtdiv] > 0 (pps{ppsdiv] 2) + 3 42.6 memory map/register definition the following registers control and monitor cmt operation. the address of a register is the sum of a base address and an address offset. the base address is defined at the chip level. the address offset is defined at the module level. chapter 42 carrier modulator transmitter (cmt) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1089 cmt memory map absolute address (hex) register name width (in bits) access reset value section/ page 4006_2000 cmt carrier generator high data register 1 (cmt_cgh1) 8 r/w undefined 42.6.1/ 1090 4006_2001 cmt carrier generator low data register 1 (cmt_cgl1) 8 r/w undefined 42.6.2/ 1091 4006_2002 cmt carrier generator high data register 2 (cmt_cgh2) 8 r/w undefined 42.6.3/ 1092 4006_2003 cmt carrier generator low data register 2 (cmt_cgl2) 8 r/w undefined 42.6.4/ 1092 4006_2004 cmt output control register (cmt_oc) 8 r/w 00h 42.6.5/ 1093 4006_2005 cmt modulator status and control register (cmt_msc) 8 r/w 00h 42.6.6/ 1094 4006_2006 cmt modulator data register mark high (cmt_cmd1) 8 r/w undefined 42.6.7/ 1095 4006_2007 cmt modulator data register mark low (cmt_cmd2) 8 r/w undefined 42.6.8/ 1096 4006_2008 cmt modulator data register space high (cmt_cmd3) 8 r/w undefined 42.6.9/ 1096 4006_2009 cmt modulator data register space low (cmt_cmd4) 8 r/w undefined 42.6.10/ 1097 4006_200a cmt primary prescaler register (cmt_pps) 8 r/w 00h 42.6.11/ 1097 4006_200b cmt direct memory access (cmt_dma) 8 r/w 00h 42.6.12/ 1098 42.6.1 cmt carrier generator high data register 1 (cmt_cgh1) this data register contain the primary high value for generating the carrier output. address: cmt_cgh1 is 4006_2000h base + 0h offset = 4006_2000h bit 7 6 5 4 3 2 1 0 read ph write reset x* x* x* x* x* x* x* x* * notes: x = undefined at reset. memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1090 freescale semiconductor, inc. cmt_cgh1 field descriptions field description 70 ph primary carrier high time data value when selected, these bits contain the number of input clocks required to generate the carrier high time period. when operating in time mode, this register is always selected. when operating in fsk mode, this register and the secondary register pair are alternately selected under control of the modulator. the primary carrier high time value is undefined out of reset. these bits must be written to non-zero values before the carrier generator is enabled to avoid spurious results. 42.6.2 cmt carrier generator low data register 1 (cmt_cgl1) this data register contain the primary low value for generating the carrier output. address: cmt_cgl1 is 4006_2000h base + 1h offset = 4006_2001h bit 7 6 5 4 3 2 1 0 read pl write reset x* x* x* x* x* x* x* x* * notes: x = undefined at reset. cmt_cgl1 field descriptions field description 7?0 pl primary carrier low time data value when selected, these bits contain the number of input clocks required to generate the carrier low time period. when operating in time mode, this register is always selected. when operating in fsk mode, this register and the secondary register pair are alternately selected under control of the modulator. the primary carrier low time value is undefined out of reset. these bits must be written to non-zero values before the carrier generator is enabled to avoid spurious results. chapter 42 carrier modulator transmitter (cmt) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1091 42.6.3 cmt carrier generator high data register 2 (cmt_cgh2) this data register contain the secondary high value for generating the carrier output. address: cmt_cgh2 is 4006_2000h base + 2h offset = 4006_2002h bit 7 6 5 4 3 2 1 0 read sh write reset x* x* x* x* x* x* x* x* * notes: x = undefined at reset. cmt_cgh2 field descriptions field description 7?0 sh secondary carrier high time data value when selected, these bits contain the number of input clocks required to generate the carrier high time period. when operating in time mode, this register is never selected. when operating in fsk mode, this register and the primary register pair are alternately selected under control of the modulator. the secondary carrier high time value is undefined out of reset. these bits must be written to nonzero values before the carrier generator is enabled when operating in fsk mode. 42.6.4 cmt carrier generator low data register 2 (cmt_cgl2) this data register contain the secondary low value for generating the carrier output. address: cmt_cgl2 is 4006_2000h base + 3h offset = 4006_2003h bit 7 6 5 4 3 2 1 0 read sl write reset x* x* x* x* x* x* x* x* * notes: x = undefined at reset. cmt_cgl2 field descriptions field description 7?0 sl secondary carrier low time data value when selected, these bits contain the number of input clocks required to generate the carrier low time period. when operating in time mode, this register is never selected. when operating in fsk mode, this register and the primary register pair are alternately selected under control of the modulator. the secondary carrier low time value is undefined out of reset. these bits must be written to nonzero values before the carrier generator is enabled when operating in fsk mode. memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1092 freescale semiconductor, inc. 42.6.5 cmt output control register (cmt_oc) this register is used to control the iro signal of the cmt module. address: cmt_oc is 4006_2000h base + 4h offset = 4006_2004h bit 7 6 5 4 3 2 1 0 read irol cmtpol iropen 0 write reset 0 0 0 0 0 0 0 0 cmt_oc field descriptions field description 7 irol iro latch control reading irol reads the state of the iro latch. writing to irol changes the state of the cmt_iro signal when msc[mcgen] bit is cleared and the iropen bit is set. 6 cmtpol cmt output polarity the cmtpol bit controls the polarity of the cmt_iro signal of the cmt. 0 cmt_iro signal is active low 1 cmt_iro signal is active high 5 iropen iro pin enable the iropen bit is used to enable and disable the cmt_iro signal. when cmt_iro signal is enabled, it is an output that drives out either the cmt transmitter output or the state of the irol bit depending on whether msc[mcgen] bit is set or not. also, the state of the output is either inverted or not depending on the state of the cmtpol bit. when cmt_iro signal is disabled, it is in a high impedance state so as not to draw any current. this signal is disabled during reset. 0 cmt_iro signal disabled 1 cmt_iro signal enabled as output 4?0 reserved this read-only field is reserved and always has the value zero. chapter 42 carrier modulator transmitter (cmt) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1093 42.6.6 cmt modulator status and control register (cmt_msc) the msc register contains the modulator and carrier generator enable (mcgen), end of cycle interrupt enable (eocie), fsk mode select (fsk), baseband enable (base), extended space (exspc), prescaler (cmtdiv) bits, and the end of cycle (eocf) status bit. address: cmt_msc is 4006_2000h base + 5h offset = 4006_2005h bit 7 6 5 4 3 2 1 0 read eocf cmtdiv exspc base fsk eocie mcgen write reset 0 0 0 0 0 0 0 0 cmt_msc field descriptions field description 7 eocf end of cycle status flag the eocf bit is set when: the modulator is not currently active and the mcgen bit is set to begin the initial cmt transmission. at the end of each modulation cycle while the mcgen bit is set. this is recognized when a match occurs between the contents of the space period register and the down counter. at this time, the counter is initialized with the (possibly new) contents of the mark period buffer, cmt_cmd1 and cmt_cmd2, and the space period register is loaded with the (possibly new) contents of the space period buffer, cmt_cmd3 and cmt_cmd4. this flag is cleared by a read of the msc register followed by an access of cmd2 or cmd4 or by the dma transfer. 0 no end of modulation cycle occurrence since flag last cleared 1 end of modulator cycle has occurred 6?5 cmtdiv cmt clock divide prescaler the secondary prescaler causes the cmt to be clocked at the if signal frequency, or the if frequency divided by 2 ,4, or 8. since these bits are not double buffered, they should not be changed during a transmission. 00 if 1 01 if 2 10 if 4 11 if 8 4 exspc extended space enable the exspc bit enables extended space operation. 0 extended space disabled 1 extended space enabled table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 104 freescale semiconductor, inc. cmt_msc field descriptions (continued) field description 3 base baseband enable when set, the base bit disables the carrier generator and forces the carrier output high for generation of baseband protocols. when base is cleared, the carrier generator is enabled and the carrier output toggles at the frequency determined by values stored in the carrier data registers. this bit is cleared by reset. this bit is not double buffered and should not be written to during a transmission. 0 baseband mode disabled 1 baseband mode enabled 2 fsk fsk mode select the fsk bit enables fsk operation. 0 cmt operates in time or baseband mode 1 cmt operates in fsk mode 1 eocie end of cycle interrupt enable a cpu interrupt will be requested when eocf is set if eocie is high. 0 cpu interrupt disabled 1 cpu interrupt enabled 0 mcgen modulator and carrier generator enable setting mcgen will initialize the carrier generator and modulator and will enable all clocks. once enabled, the carrier generator and modulator will function continuously. when mcgen is cleared, the current modulator cycle will be allowed to expire before all carrier and modulator clocks are disabled (to save power) and the modulator output is forced low. to prevent spurious operation, the user should initialize all data and control registers before enabling the system. 0 modulator and carrier generator disabled 1 modulator and carrier generator enabled 42.6.7 cmt modulator data register mark high (cmt_cmd1) the contents of this register are transferred to the modulator down counter upon the completion of a modulation period. address: cmt_cmd1 is 4006_2000h base + 6h offset = 4006_2006h bit 7 6 5 4 3 2 1 0 read mb[15:8] write reset x* x* x* x* x* x* x* x* * notes: x = undefined at reset. chapter 42 carrier modulator transmitter (cmt) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1095 cmt_cmd1 field descriptions field description 70 mb[15:8] these bits control the upper mark periods of the modulator for all modes. 42.6.8 cmt modulator data register mark low (cmt_cmd2) the contents of this register are transferred to the modulator down counter upon the completion of a modulation period. address: cmt_cmd2 is 4006_2000h base + 7h offset = 4006_2007h bit 7 6 5 4 3 2 1 0 read mb[7:0] write reset x* x* x* x* x* x* x* x* * notes: x = undefined at reset. cmt_cmd2 field descriptions field description 7?0 mb[7:0] these bits control the lower mark periods of the modulator for all modes. 42.6.9 cmt modulator data register space high (cmt_cmd3) the contents of this register are transferred to the space period register upon the completion of a modulation period. address: cmt_cmd3 is 4006_2000h base + 8h offset = 4006_2008h bit 7 6 5 4 3 2 1 0 read sb[15:8] write reset x* x* x* x* x* x* x* x* * notes: x = undefined at reset. memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1096 freescale semiconductor, inc. cmt_cmd3 field descriptions field description 70 sb[15:8] these bits control the upper space periods of the modulator for all modes. 42.6.10 cmt modulator data register space low (cmt_cmd4) the contents of this register are transferred to the space period register upon the completion of a modulation period. address: cmt_cmd4 is 4006_2000h base + 9h offset = 4006_2009h bit 7 6 5 4 3 2 1 0 read sb[7:0] write reset x* x* x* x* x* x* x* x* * notes: x = undefined at reset. cmt_cmd4 field descriptions field description 7?0 sb[7:0] these bits control the lower space periods of the modulator for all modes. 42.6.11 cmt primary prescaler register (cmt_pps) this register is used to set the primary prescaler bits (ppsdiv). address: cmt_pps is 4006_2000h base + ah offset = 4006_200ah bit 7 6 5 4 3 2 1 0 read 0 ppsdiv write reset 0 0 0 0 0 0 0 0 cmt_pps field descriptions field description 7?4 reserved this read-only field is reserved and always has the value zero. 3?0 ppsdiv primary prescaler divider table continues on the next page... chapter 42 carrier modulator transmitter cmt 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 107 cmt_pps field descriptions (continued) field description the primary prescaler divides the cmt clock to generate the intermediate frequency clock enable to the secondary prescaler. 0000 bus clock 1 0001 bus clock 2 0010 bus clock 3 0011 bus clock 4 0100 bus clock 5 0101 bus clock 6 0110 bus clock 7 0111 bus clock 8 1000 bus clock 9 1001 bus clock 10 1010 bus clock 11 1011 bus clock 12 1100 bus clock 13 1101 bus clock 14 1110 bus clock 15 1111 bus clock 16 42.6.12 cmt direct memory access (cmt_dma) this register is used to enable/disable direct memory access (dma). address: cmt_dma is 4006_2000h base + bh offset = 4006_200bh bit 7 6 5 4 3 2 1 0 read 0 dma write reset 0 0 0 0 0 0 0 0 cmt_dma field descriptions field description 7?1 reserved this read-only field is reserved and always has the value zero. 0 dma dma enable this bit enables the dma protocol. table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 108 freescale semiconductor, inc. cmt_dma field descriptions (continued) field description 0 dma transfer request and done are disabled 1 dma transfer request and done are enabled 42.7 functional description the cmt module consists primarily of clock divider, carrier generator and modulator. 42.7.1 clock divider the cmt was originally designed to be based on 8 mhz bus clock that could be divided by 1, 2, 4 or 8 times accordingly with the specification. to be compatible with higher bus frequency, the primary prescaler (pps) was developed to receive a higher frequency and generate a clock enable signal called intermediate frequency (if). this if should be approximately equal to 8 mhz and will work as a clock enable to the secondary prescaler. the following figure shows the clock divider block diagram. primary prescaler if_clk_enable divider_enable bus clock secondary prescaler figure 42-14. clock divider block diagram for compatibility with previous versions of cmt, when bus clock = 8 mhz, the pps should be configured to zero. the pps counter is selected according to the bus clock to generate an intermediate frequency approximately equal to 8 mhz. 42.7.2 carrier generator the carrier generator resolution is 125 ns when operating with an 8 mhz intermediate frequency signal and the secondary prescaler is set to divide by 1 (msc[cmtdiv] = 00). the carrier generator can generate signals with periods between 250 ns (4 mhz) and 127.5 s (7.84 khz) in steps of 125 ns. the following table shows the relationship between the clock divide bits and the carrier generator resolution, minimum carrier generator period, and minimum modulator period. chapter 42 carrier modulator transmitter (cmt) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1099 table 42-17. clock divider bus clock (mhz) msc[cmtdiv] carrier generator resolution (s) min. carrier generator period ( ( the possible duty cycle options depend upon the number of counts required to complete the carrier period. for example, 1.6 mhz signal has a period of 625 ns and will therefore require 5 x 125 ns counts to generate. these counts may be split between high and low times, so the duty cycles available will be 20% (one high, four low), 40% (two high, three low), 60% (three high, two low) and 80% (four high, one low). for lower frequency signals with larger periods, higher resolution (as a percentage of the total period) duty cycles are possible. the carrier signal is generated by counting a register-selected number of input clocks (125 ns for an 8 mhz bus) for both the carrier high time and the carrier low time. the period is determined by the total number of clocks counted. the duty cycle is determined by the ratio of high time clocks to total clocks counted. the high and low time values are user programmable and are held in two registers. an alternate set of high/low count values is held in another set of registers to allow the generation of dual frequency fsk (frequency shift keying) protocols without cpu intervention. note only non-zero data values are allowed. the carrier generator will not work if any of the count values are equal to zero. msc[mcgen] bit must be set and msc[base] bit must be cleared to enable carrier generator clocks. when msc[base] bit is set, the carrier output to the modulator is held high continuously. following figure represents the block diagram of the clock generator. functional description k60 sub-family reference manual, rev. 6, nov 2011 1100 freescale semiconductor, inc. c l o c k a n d o u t p u t c o n t r o l = ? = ? the high/low time counter is an 8-bit up counter. after each increment, the contents of the counter are compared with the appropriate high or low count value register. when the compare value is reached, the counter is reset to a value of 0x01, and the compare is redirected to the other count value register. assuming that the high time count compare register is currently active, a valid compare will cause the carrier output to be driven low. the counter will continue to increment (starting at reset value of 0x01). when the value stored in the selected low count value register is reached, the counter will again be reset and the carrier output will be driven high. the cycle repeats, automatically generating a periodic signal which is directed to the modulator . the lowest frequency (maximum period) and highest frequency (minimum period) which can be generated are defined as: f max = f cmtclk (2 x 1) hz f min = f cmtclk (2 x (2 8 ? 1)) hz in the general case, the carrier generator output frequency is: f cg = f cmtclk (highcount + lowcount) hz where: 0 < highcount < 256 and 0 < lowcount < 256 chapter 42 carrier modulator transmitter (cmt) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1101 the duty cycle of the carrier signal is controlled by varying the ratio of high time to low + high time. as the input clock period is fixed, the duty cycle resolution will be proportional to the number of counts required to generate the desired carrier period. 42.7.3 modulator the modulator block controls the state of the infrared out signal (iro) . the modulator output is gated on to the iro signal when the modulator/carrier generator is enabled . when the modulator/carrier generator is disabled, the iro signal is controlled by the state of the iro latch. oc[cmtpol] enables the iro signal to be active high or active low. in cmt modes, the modulator functions as givenbelow: ? in time mode, the modulator can gate the carrier onto the modulator output. ? in baseband mode, the modulator can control the logic level of the modulator output. ? in fsk mode, the modulator can count carrier periods and instruct the carrier generator to alternate between two carrier frequencies whenever a modulation period (mark + space counts) expires. the modulator provides a simple method to control protocol timing. the modulator has a minimum resolution of 1.0 s with an 8 mhz . it can count bus clocks (to provide real- time control) or it can count carrier clocks (for self-clocked protocols). the modulator includes a 17-bit down counter with underflow detection. the counter is loaded from the 16-bit modulation mark period buffer registers, cmd1 and cmd2. the most significant bit is loaded with a logic zero and serves as a sign bit. when the counter holds a positive value, the modulator gate is open and the carrier signal is driven to the transmitter block. when the counter underflows, the modulator gate is closed and a 16-bit comparator is enabled which compares the logical complement of the value of the down counter with the contents of the modulation space period register which has been loaded from the registers, cmd3 and cmd4. when a match is obtained, the cycle repeats by opening the modulator gate, reloading the counter with the contents of cmd1 and cmd2, and reloading the modulation space period register with the contents of cmd3 and cmd4. functional description k60 sub-family reference manual, rev. 6, nov 2011 1102 freescale semiconductor, inc. the activation of modulation space period is done when the carrier signal is low to prohibit cutting off the high pulse of a carrier signal. if the carrier signal is high, the modulator extends the mark period until the carrier signal become low. to de-assert the space period and assert the mark period, the carrier signal must have gone low to assure that a space period is not erroneously shortened. should the contents of the modulation space period register be all zeroes, the match will be immediate and no space period will be generated (for instance, for fsk protocols that require successive bursts of different frequencies). msc[mcgen] must be set to enable the modulator timer. m s b i t 1 6 b i t s m o d e l o a d f s k b a s e e x s p c e o c i e 1 6 b i t s 1 6 c o u n t e r p r i m a r y / s e c o n d a r y s e l e c t 0 1 6 1 7 - b i t d o wn counter * cmtcmd1:cmtcmd2 c l o c k c o n t r ol c a r r i e r o u t ( f c g ) m o d u l a t or out m o d u l a t o r g a te e o c f l a g set m o d u l e i n t e r r u p t r e q uest s y s t e m c o n t r ol cmtclock s p a ce period register * cmtcmd3:cmtcmd4 * d e n o tes hidden register when the modulator operates in time mode (msc[mcgen] bit is set, msc[base] and msc[fsk] bits are cleared), the modulation mark period consists of an integer number of cmtclk 8 clock periods. the modulation space period consists of zero or an integer number of cmtclk 8 clock periods. with an 8 mhz if and msc[cmtdiv] = 00, the modulator resolution is 1 s and has a maximum mark and space period of about 65.535 ms each . see the following figure for an example of the time mode and baseband mode outputs. the mark and space time equations for time and baseband mode are: chapter 42 carrier modulator transmitter (cmt) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1103 t mark = (cmd1:cmd2 + 1) (f cmtclk 8) t space = cmd3:cmd4 (f cmtclk 8) where cmd1:cmd2 and cmd3:cmd4 are the decimal values of the concatenated registers. c a r r i e r o u t ( f c g ) m o d u l a t o r g a t e i r o signal (time mode) i r o signal (baseband mode) mark s p a ce mark baseband mode (msc[mcgen] and msc[base] bits are set) is a derivative of time mode, where the mark and space period is based on (cmtclk 8) counts. the mark and space calculations are the same as in time mode. in this mode, the modulator output will be at a logic 1 for the duration of the mark period and at a logic 0 for the duration of a space period. see figure 42-17 for an example of the output for both baseband and time modes. in the example, the carrier out frequency (f cg ) is generated with a high count of 0x01 and a low count of 0x02 that results in a divide of 3 of cmtclk with a 33% duty cycle. the modulator down counter was loaded with the value 0x0003 and the space period register with 0x0002. functional description k60 sub-family reference manual, rev. 6, nov 2011 1104 freescale semiconductor, inc. note the waveforms in figure 42-17 and figure 42-18 are for the purpose of conceptual illustration and are not meant to represent precise timing relationships between the signals shown. 42.7.3.3 fsk mode when the modulator operates in fsk mode (msc[mcgen] and msc[fsk] bits are set, and msc[base] bit is cleared), the modulation mark and space periods consist of an integer number of carrier clocks (space period can be zero). when the mark period expires, the space period is transparently started (as in time mode). the carrier generator toggles between primary and secondary data register values whenever the modulator space period expires. the space period provides an interpulse gap (no carrier). if cmd3:cmd4 = 0x0000, then the modulator and carrier generator will switch between carrier frequencies without a gap or any carrier glitches (zero space). using timing data for carrier burst and interpulse gap length calculated by the cpu, fsk mode can automatically generate a phase-coherent, dual-frequency fsk signal with programmable burst and interburst gaps. the mark and space time equations for fsk mode are: t mark = (cmd1:cmd2 + 1) f cg t space = cmd3:cmd4 f cg where f cg is the frequency output from the carrier generator. the example in figure below shows what the iro signal looks like in fsk mode with the following values: cmd1:cmd2 = 0x0003, cmd3:cmd4 = 0x0002, primary carrier high count = 0x01, primary carrier low count = 0x02, secondary carrier high count = 0x03, and secondary carrier low count = 0x01. chapter 42 carrier modulator transmitter (cmt) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1105 i r o signal m o d u l a t o r g a te c a r r i e r o u t ( f c g ) in either time, baseband or fsk mode, the space period can be made longer than the maximum possible value of the space period register . setting msc[exspc] bit will force the modulator to treat the next modulation period (beginning with the next load of the counter and space period register) as a space period equal in length to the mark and space counts combined . subsequent modulation periods will consist entirely of these extended space periods with no mark periods . clearing msc[exspc] will return the modulator to standard operation at the beginning of the next modulation period . 42.7.4.1 exspc operation in time mode to calculate the length of an extended space in time or baseband mode, add the mark and space times and multiply by the number of modulation periods when msc[exspc] is set. t exspace = (t mark + t space ) x (number of modulation periods) for an example of extended space operation, see the following figure. note the extended space enable feature can be used to emulate a zero mark event. functional description k60 sub-family reference manual, rev. 6, nov 2011 1106 freescale semiconductor, inc. s e t e x s p c c l e a r e x s p c in fsk mode, the modulator continues to count carrier out clocks, alternating between the primary and secondary registers at the end of each modulation period. to calculate the length of an extended space in fsk mode, one needs to know whether msc[exspc] bit was set on a primary or secondary modulation period, as well as the total number of both primary and secondary modulation periods completed while msc[exspc] bit is high. a status bit for the current modulation is not accessible to the cpu. if necessary, software should maintain tracking of the current modulation cycle (primary or secondary). the extended space period ends at the completion of the space period time of the modulation period during which msc[exspc] bit is cleared. if msc[exspc] bit was set during a primary modulation cycle, use the equation: t exspace = (t space ) p + (t mark + t space ) s + (t mark + t space ) p +... where the subscripts p and s refer to mark and space times for the primary and secondary modulation cycles. if msc[exspc] bit was set during a secondary modulation cycle, use the equation: t exspace = (t space ) s + (t mark + t space ) p + (t mark + t space ) s +... 42.8 cmt interrupts and dma the cmt generates an interrupt request or a dma transfer request according to msc[eocie], msc[eocf], dma[dma] bits. table 42-18. dma transfer request x cmt interrupt request msc[eocf] dma[dma] msc[eocie] dma transfer request cmt interrupt request 0 x x 0 0 1 x 0 0 0 1 0 1 0 1 1 1 1 1 0 chapter 42 carrier modulator transmitter (cmt) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1107 msc[eocf] is set when: ? the modulator is not currently active and msc[mcgen] bit is set to begin the initial cmt transmission ? at the end of each modulation cycle (when the counter is reloaded from cmd1:cmd2) while msc[mcgen] bit is set in the case where msc[mcgen] bit is cleared and then set before the end of the modulation cycle, msc[eocf] bit will not be set when msc[mcgen] is set, but will become set at the end of the current modulation cycle. when msc[mcgen] becomes disabled, the cmt module does not set the eoc flag at the end of the last modulation cycle. if msc[eocie] bit is high when msc[eocf] bit is set, the cmt module will generate an interrupt request or a dma transfer request. msc[eocf] bit must be cleared to prevent from being generated another event (interrupt or dma request) after exiting the service routine. see following table. table 42-19. how to clear msc[eocf] bit dma[dm a] msc[eocie] description 0 x msc[eocf] bit is cleared by reading the cmt modulator status and control register msc followed by an access of cmd2 or cmd4. 1 x msc[eocf] bit is cleared by the cmt dma transfer done. the eoc interrupt is coincident with loading the down-counter with the contents of cmd1:cmd2 and loading the space period register with the contents of cmd3:cmd4. the eoc interrupt provides a means for the user to reload new mark/space values into the modulator data registers. modulator data register updates will take effect at the end of the current modulation cycle. note that the down-counter and space period register are updated at the end of every modulation cycle, irrespective of interrupt handling and the state of the eocf flag. cmt interrupts and dma k60 sub-family reference manual, rev. 6, nov 2011 1108 freescale semiconductor, inc. chapter 43 real time clock (rtc) 43.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. 43.1.1 features the rtc module features include: ? independent power supply, por and 32 khz crystal oscillator ? 32-bit seconds counter with roll-over protection and 32-bit alarm ? 16-bit prescaler with compensation that can correct errors between 0.12 ppm and 3906 ppm ? register write protection ? lock register requires vbat por or software reset to enable write access ? access control registers require system reset to enable read and/or write access ? 1 hz square wave output 43.1.2 modes of operation the rtc operates in one of two modes of operation, chip power-up and chip power- down. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1109 during chip power-down, rtc is powered from the backup power supply (vbat) and is electrically isolated from the rest of the chip but continues to increment the time counter (if enabled) and retain the state of the rtc registers. the rtc registers are not accessible. during chip power-up, rtc remains powered from the backup power supply (vbat). all rtc registers are accessible by software and all functions are operational. if enabled, the 32.768 khz clock can be supplied to the rest of the chip. 43.1.3 rtc signal descriptions table 43-1. rtc signal descriptions signal description i/o extal32 32.768 khz oscillator input i xtal32 32.768 khz oscillator output o rtc_clkout 1hz square-wave output o rtc_wakeup wakeup for external device o 43.1.3.1 rtc clock output the clock to the seconds counter is available on the rtc_clkout signal. it is a 1hz square wave output. 43.1.3.2 rtc wakeup pin the rtc wakeup pin is an open drain, active low, output that allows the rtc to wakeup the chip via an external component. the wakeup pin asserts when the wakeup pin enable is set, the rtc interrupt is asserted and the chip is powered down. the wakeup pin does not assert from the rtc seconds interrupt. the wakeup pin is optional and may not be implemented on all devices. 43.2 register definition all registers must be accessed using 32-bit writes and all register accesses incur three wait states. register definition k60 sub-family reference manual, rev. 6, nov 2011 1110 freescale semiconductor, inc. write accesses to any register by non-supervisor mode software, when the supervisor access bit in the control register is clear, will terminate with a bus error. read accesses by non-supervisor mode software complete as normal. writing to a register protected by the write access register or lock register does not generate a bus error, but the write will not complete. reading a register protected by the read access register does not generate a bus error, but the register will read zero. rtc memory map absolute address (hex) register name width (in bits) access reset value section/ page 4003_d000 rtc time seconds register (rtc_tsr) 32 r/w 0000_0000h 43.2.1/ 1111 4003_d004 rtc time prescaler register (rtc_tpr) 32 r/w 0000_0000h 43.2.2/ 1112 4003_d008 rtc time alarm register (rtc_tar) 32 r/w 0000_0000h 43.2.3/ 1112 4003_d00c rtc time compensation register (rtc_tcr) 32 r/w 0000_0000h 43.2.4/ 1113 4003_d010 rtc control register (rtc_cr) 32 r/w 0000_0000h 43.2.5/ 1114 4003_d014 rtc status register (rtc_sr) 32 r/w 0000_0001h 43.2.6/ 1116 4003_d018 rtc lock register (rtc_lr) 32 r/w 0000_00ffh 43.2.7/ 1117 4003_d01c rtc interrupt enable register (rtc_ier) 32 r/w 0000_0007h 43.2.8/ 1118 4003_d800 rtc write access register (rtc_war) 32 r/w 0000_00ffh 43.2.9/ 1119 4003_d804 rtc read access register (rtc_rar) 32 r/w 0000_00ffh 43.2.10/ 1120 43.2.1 rtc time seconds register (rtc_tsr) address: rtc_tsr is 4003_d000h base + 0h offset = 4003_d000h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r tsr w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 chapter 43 real time clock (rtc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1111 rtc_tsr field descriptions field description 310 tsr time seconds register when the time counter is enabled, the tsr is read only and increments once a second provided sr[tof] or sr[tif] are not set. the time counter will read as zero when sr[tof] or sr[tif] are set. when the time counter is disabled, the tsr can be read or written. writing to the tsr when the time counter is disabled will clear the sr[tof] and/or the sr[tif]. writing to the tsr register with zero is supported, but not recommended since tsr will read as zero when sr[tif] or sr[tof] are set (indicating the time is invalid). 43.2.2 rtc time prescaler register (rtc_tpr) address: rtc_tpr is 4003_d000h base + 4h offset = 4003_d004h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 tpr w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rtc_tpr field descriptions field description 3116 reserved this read-only field is reserved and always has the value zero. 150 tpr time prescaler register when the time counter is enabled, the tpr is read only and increments every 32.768 khz clock cycle. the time counter will read as zero when sr[tof] or sr[tif] are set. when the time counter is disabled, the tpr can be read or written. the tsr[tsr] increments when bit 14 of the tpr transitions from a logic one to a logic zero. 43.2.3 rtc time alarm register (rtc_tar) address: rtc_tar is 4003_d000h base + 8h offset = 4003_d008h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r tar w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rtc_tar field descriptions field description 310 tar time alarm register register definition k60 sub-family reference manual, rev. 6, nov 2011 1112 freescale semiconductor, inc. rtc_tar field descriptions (continued) field description when the time counter is enabled, the sr[taf] is set whenever the tar[tar] equals the tsr[tsr] and the tsr[tsr] increments. writing to the tar clears the sr[taf]. 43.2.4 rtc time compensation register (rtc_tcr) address: rtc_tcr is 4003_d000h base + ch offset = 4003_d00ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r cic tcv cir tcr w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rtc_tcr field descriptions field description 3124 cic compensation interval counter current value of the compensation interval counter. if the compensation interval counter equals zero then it is loaded with the contents of the cir. if the cic does not equal zero then it is decremented once a second. 2316 tcv time compensation value current value used by the compensation logic for the present second interval. updated once a second if the cic equals 0 with the contents of the tcr field. if the cic does not equal zero then it is loaded with zero (compensation is not enabled for that second increment). 158 cir compensation interval register configures the compensation interval in seconds from 1 to 256 to control how frequently the tcr should adjust the number of 32.768 khz cycles in each second. the value written should be one less than the number of seconds (for example, write zero to configure for a compensation interval of one second). this register is double buffered and writes do not take affect until the end of the current compensation interval. 70 tcr time compensation register configures the number of 32.768 khz clock cycles in each second. this register is double buffered and writes do not take affect until the end of the current compensation interval. 80h time prescaler register overflows every 32896 clock cycles. ... ... ffh time prescaler register overflows every 32769 clock cycles. 00h time prescaler register overflows every 32768 clock cycles. 01h time prescaler register overflows every 32767 clock cycles. ... ... 7fh time prescaler register overflows every 32641 clock cycles. chapter 43 real time clock (rtc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1113 43.2.5 rtc control register (rtc_cr) address: rtc_cr is 4003_d000h base + 10h offset = 4003_d010h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 reserved sc2p sc4p sc8p sc16p clko osce 0 um sup wpe swr w 0 reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rtc_cr field descriptions field description 3115 reserved this read-only field is reserved and always has the value zero. 14 reserved this field is reserved. it must always be written to 0. 13 sc2p oscillator 2pf load configure 0 disable the load. 1 enable the additional load. 12 sc4p oscillator 4pf load configure 0 disable the load. 1 enable the additional load. 11 sc8p oscillator 8pf load configure 0 disable the load. 1 enable the additional load. 10 sc16p oscillator 16pf load configure 0 disable the load. 1 enable the additional load. table continues on the next page... register definition 60 sub-family reference manual, rev. 6, nov 2011 1114 freescale semiconductor, inc. rtc_cr field descriptions (continued) field description 9 clko clock output 0 the 32khz clock is output to other peripherals 1 the 32khz clock is not output to other peripherals 8 osce oscillator enable 0 32.768 khz oscillator is disabled. 1 32.768 khz oscillator is enabled. after setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 khz clock time to stabilize. 74 reserved this read-only field is reserved and always has the value zero. 3 um update mode allows the sr[tce] to be written even when the status register is locked. when set, the sr[tce] can always be written if the sr[tif] or sr[tof] are set or if the sr[tce] is clear. 0 registers cannot be written when locked. 1 registers can be written when locked under limited conditions. 2 sup supervisor access 0 non-supervisor mode write accesses are not supported and generate a bus error. 1 non-supervisor mode write accesses are supported. 1 wpe wakeup pin enable the wakeup pin is optional and not available on all devices. 0 wakeup pin is disabled. 1 wakeup pin is enabled and wakeup pin asserts if the rtc interrupt asserts and the chip is powered down. 0 swr software reset 0 no effect 1 resets all rtc registers except for the swr bit and the rtc_war and rtc_rar registers. the swr bit is cleared after vbat por and by software explicitly clearing it. chapter 43 real time clock (rtc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1115 43.2.6 rtc status register (rtc_sr) address: rtc_sr is 4003_d000h base + 14h offset = 4003_d014h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 tce 0 taf tof tif w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 rtc_sr field descriptions field description 315 reserved this read-only field is reserved and always has the value zero. 4 tce time counter enable when time counter is disabled the tsr register and tpr register are writeable, but do not increment. when time counter is enabled the tsr register and tpr register are not writeable, but increment. 0 time counter is disabled. 1 time counter is enabled. 3 reserved this read-only field is reserved and always has the value zero. 2 taf time alarm flag time alarm flag is set when the tar[tar] equals the tsr[tsr] and the tsr[tsr] increments. this bit is cleared by writing the tar register. 0 time alarm has not occurred. 1 time alarm has occurred. 1 tof time overflow flag time overflow flag is set when the time counter is enabled and overflows. the tsr and tpr do not increment and read as zero when this bit is set. this bit is cleared by writing the tsr register when the time counter is disabled. 0 time overflow has not occurred. 1 time overflow has occurred and time counter is read as zero. 0 tif time invalid flag the time invalid flag is set on vbat por or software reset. the tsr and tpr do not increment and read as zero when this bit is set. this bit is cleared by writing the tsr register when the time counter is disabled. 0 time is valid. 1 time is invalid and time counter is read as zero. register definition k60 sub-family reference manual, rev. 6, nov 2011 1116 freescale semiconductor, inc. 43.2.7 rtc lock register (rtc_lr) address: rtc_lr is 4003_d000h base + 18h offset = 4003_d018h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 1 lrl srl crl tcl 1 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 rtc_lr field descriptions field description 318 reserved this read-only field is reserved and always has the value zero. 7 reserved this read-only field is reserved and always has the value one. 6 lrl lock register lock once cleared, this bit can only be set by vbat por or software reset. 0 lock register is locked and writes are ignored. 1 lock register is not locked and writes complete as normal. 5 srl status register lock once cleared, this bit can only be set by vbat por or software reset. 0 status register is locked and writes are ignored. 1 status register is not locked and writes complete as normal. 4 crl control register lock once cleared, this bit can only be set by vbat por. 0 control register is locked and writes are ignored. 1 control register is not locked and writes complete as normal. 3 tcl time compensation lock once cleared, this bit can only be set by vbat por or software reset. 0 time compensation register is locked and writes are ignored. 1 time compensation register is not locked and writes complete as normal. 20 reserved this read-only field is reserved and always has the value one. chapter 43 real time clock (rtc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1117 43.2.8 rtc interrupt enable register (rtc_ier) address: rtc_ier is 4003_d000h base + 1ch offset = 4003_d01ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 reserved reserved reserved taie toie tiie w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 rtc_ier field descriptions field description 318 reserved this read-only field is reserved and always has the value zero. 75 reserved this field is reserved. 4 reserved this field is reserved. 3 reserved this field is reserved. 2 taie time alarm interrupt enable 0 time alarm flag does not generate an interrupt. 1 time alarm flag does generate an interrupt. 1 toie time overflow interrupt enable 0 time overflow flag does not generate an interrupt. 1 time overflow flag does generate an interrupt. 0 tiie time invalid interrupt enable 0 time invalid flag does not generate an interrupt. 1 time invalid flag does generate an interrupt. register definition k60 sub-family reference manual, rev. 6, nov 2011 1118 freescale semiconductor, inc. 43.2.9 rtc write access register (rtc_war) address: rtc_war is 4003_d000h base + 800h offset = 4003_d800h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 ierw lrw srw crw tcrw tarw tprw tsrw w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 rtc_war field descriptions field description 318 reserved this read-only field is reserved and always has the value zero. 7 ierw interrupt enable register write once cleared, this bit is only set by system reset. it is not affected by vbat por or software reset. 0 writes to the interupt enable register are ignored. 1 writes to the interrupt enable register complete as normal. 6 lrw lock register write once cleared, this bit is only set by system reset. it is not affected by vbat por or software reset. 0 writes to the lock register are ignored. 1 writes to the lock register complete as normal. 5 srw status register write once cleared, this bit is only set by system reset. it is not affected by vbat por or software reset. 0 writes to the status register are ignored. 1 writes to the status register complete as normal. 4 crw control register write once cleared, this bit is only set by system reset. it is not affected by vbat por or software reset. 0 writes to the control register are ignored. 1 writes to the control register complete as normal. 3 tcrw time compensation register write once cleared, this bit is only set by system reset. it is not affected by vbat por or software reset. 0 writes to the time compensation register are ignored. 1 writes to the time compensation register complete as normal. 2 tarw time alarm register write once cleared, this bit is only set by system reset. it is not affected by vbat por or software reset. 0 writes to the time alarm register are ignored. 1 writes to the time alarm register complete as normal. table continues on the next page... chapter 4 real time cloc rtc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 111 rtc_war field descriptions (continued) field description 1 tprw time prescaler register write once cleared, this bit is only set by system reset. it is not affected by vbat por or software reset. 0 writes to the time prescaler register are ignored. 1 writes to the time prescaler register complete as normal. 0 tsrw time seconds register write once cleared, this bit is only set by system reset. it is not affected by vbat por or software reset. 0 writes to the time seconds register are ignored. 1 writes to the time seconds register complete as normal. 43.2.10 rtc read access register (rtc_rar) address: rtc_rar is 4003_d000h base + 804h offset = 4003_d804h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 ierr lrr srr crr tcrr tarr tprr tsrr w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 rtc_rar field descriptions field description 318 reserved this read-only field is reserved and always has the value zero. 7 ierr interrupt enable register read once cleared, this bit is only set by system reset. it is not affected by vbat por or software reset. 0 reads to the interrupt enable register are ignored. 1 reads to the interrupt enable register complete as normal. 6 lrr lock register read once cleared, this bit is only set by system reset. it is not affected by vbat por or software reset. 0 reads to the lock register are ignored. 1 reads to the lock register complete as normal. 5 srr status register read once cleared, this bit is only set by system reset. it is not affected by vbat por or software reset. 0 reads to the status register are ignored. 1 reads to the status register complete as normal. table continues on the next page... register definition 60 sub-family reference manual, rev. 6, nov 2011 1120 freescale semiconductor, inc. rtc_rar field descriptions (continued) field description 4 crr control register read once cleared, this bit is only set by system reset. it is not affected by vbat por or software reset. 0 reads to the control register are ignored. 1 reads to the control register complete as normal. 3 tcrr time compensation register read once cleared, this bit is only set by system reset. it is not affected by vbat por or software reset 0 reads to the time compensation register are ignored. 1 reads to the time compensation register complete as normal. 2 tarr time alarm register read once cleared, this bit is only set by system reset. it is not affected by vbat por or software reset. 0 reads to the time alarm register are ignored. 1 reads to the time alarm register complete as normal. 1 tprr time prescaler register read once cleared, this bit is only set by system reset. it is not affected by vbat por or software reset. 0 reads to the time prescaler register are ignored. 1 reads to the time prescaler register complete as normal. 0 tsrr time seconds register read once cleared, this bit is only set by system reset. it is not affected by vbat por or software reset. 0 reads to the time seconds register are ignored. 1 reads to the time seconds register complete as normal. 43.3 functional description 43.3.1 power, clocking and reset the rtc is an always powered block that is powered by the battery power supply (vbat). the battery power supply ensures that the rtc registers retain their state during chip power-down and that the rtc time counter remains operational. the time counter within the rtc is clocked by a 32.768 khz clock and can supply this clock to other peripherals. the 32.768 khz clock can only be sourced from an external crystal using the oscillator that is part of the rtc module. chapter 43 real time clock (rtc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1121 the rtc includes its own analog por block, which generates a power-on-reset signal whenever the rtc module is powered up and initializes all rtc registers to their default state. a software reset bit can also initialize all rtc registers. the rtc also monitors the chip power supply and electrically isolates itself when the rest of the chip is powered down. any attempt to access an rtc register (except the access control registers) when vbat is powered down, when the rtc is electrically isolated, or when vbat por is asserted, will result in a bus error. 43.3.1.1 oscillator control the 32.768 khz crystal oscillator is disabled at vbat por and must be enabled by software. after enabling the cystal oscillator, wait the oscillator startup time before setting the sr[tce] bit or using the oscillator clock external to the rtc. the crystal oscillator includes tunable capacitors that can be configured by software. do not change the capacitance unless the oscillator is disabled. 43.3.1.2 software reset writing one to the cr[swr] forces the equivalent of a vbat por to the rest of the rtc module. the cr[swr] is not affected by the software reset and must be cleared by software. the access control registers are not affected by either vbat por or the software reset; they are reset by the chip reset. 43.3.1.3 supervisor access when the supervisor access control bit is clear, only supervisor mode software can write to the rtc registers, non-supervisor mode software will generate a bus error. both supervisor and non-supervisor mode software can always read the rtc registers. 43.3.2 time counter the time counter consists of a 32-bit seconds counter that increments once every second and a 16-bit prescaler register that increments once every 32.768 khz clock cycle. functional description k60 sub-family reference manual, rev. 6, nov 2011 1122 freescale semiconductor, inc. the time seconds register and time prescaler register can only be written when the sr[tce] bit is clear. always write to the prescaler register before writing to the seconds register, since the seconds register increments on the falling edge of bit 14 of the prescaler register. the time prescaler register increments provided the sr[tce] bit is set, the sr[tif] is clear, the sr[tof] is clear and the 32.768 khz clock source is present. after enabling the oscillator, wait the oscillator startup time before setting the sr[tce] bit to allow time for the oscillator clock output to stabilize. if the time seconds register overflows then the sr[tof] will set and the time prescaler register will stop incrementing. clear the sr[tof] by initializing the time seconds register. the time seconds register and time prescaler register read as zero whenever the sr[tof] is set. the sr[tif] is set on vbat por and software reset and is cleared by initializing the time seconds register. the time seconds register and time prescaler register read as zero whenever the sr[tif] is set. 43.3.3 compensation the compensation logic provides an accurate and wide compensation range and can correct errors as high as 3906 ppm and as low as 0.12 ppm. note that the compensation factor must be calculated externally to the rtc and supplied by software to the compensation register. the rtc itself does not calculate the amount of compensation that is required, although the 1 hz clock is output to an external pin in support of external calibration logic. crystal compensation can be supported by using firmware and crystal characteristics to determine the compensation amount. temperature compensation can be supported by firmware that periodically measures the external temperature (via adc) and updates the compensation register based on a look-up table that specifies the change in crystal frequency over temperature. the compensation logic alters the number of 32.768 khz clock cycles it takes for the prescaler register to overflow and increment the time seconds counter. the time compensation value is used to adjust the number of clock cycles between -127 and +128. cycles are added or subtracted from the prescaler register when the prescaler register equals 0x3fff and then increments. the compensation interval is used to adjust the frequency at which the time compensation value is used (from once a second to once every 256 seconds). chapter 43 real time clock (rtc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1123 updates to the time compensation register will not take effect until the next time the time seconds register increments and provided the previous compensation interval has expired. when the compensation interval is set to other than once a second then the compensation is applied in the first second interval and the remaining second intervals receive no compensation. compensation is disabled by configuring the time compensation register to zero. 43.3.4 time alarm the time alarm register, sr[taf] and ier[taie] allow the rtc to generate an interrupt at a predefined time. the 32-bit time alarm register is compared with the 32-bit time seconds register each time it increments. the sr[taf] will set when the time alarm register equals the time seconds register and the time seconds register increments. the time alarm flag is cleared by writing the time alarm register. this will usually be the next alarm value, although writing a value that is less than the time seconds register (such as zero) will prevent the time alarm flag from setting again. the time alarm flag cannot otherwise be disabled, although the interrupt it generates is enabled or disabled by ier[taie]. 43.3.5 update mode the update mode bit (cr[um]) in the control register configures software write access to the time counter enable (sr[tce]) bit. when cr[um] is clear, sr[tce] can only be written when the lr[srl] bit is set. when cr[um] is set, the sr[tce] can also be written when sr[tce] is clear or when sr[tif] or sr[tof] are set. this allows the time seconds and prescaler registers to be initialized whenever time is invalidated, while preventing the time seconds and prescaler registers from being changed on the fly. when lr[srl] is set, the cr[um] bit has no effect on sr[tce]. 43.3.6 register lock the lock register can be used to block write accesses to certain registers until the next vbat por or software reset. locking the control register will disable the software reset. locking the lock register will block future updates to the lock register. write accesses to a locked register are ignored and do not generate a bus error. functional description k60 sub-family reference manual, rev. 6, nov 2011 1124 freescale semiconductor, inc. 43.3.7 access control the read access and write access registers are implemented in the chip power domain and reset on the chip reset (they are not affected by the vbat por or the software reset). they are used to block read or write accesses to each register until the next chip system reset. when accesses are blocked the bus access is not seen in the vbat power supply and does not generate a bus error. 43.3.8 interrupt the rtc interrupt is asserted whenever a status flag and the corresponding interrupt enable bit are both set. it is always asserted on vbat por, software reset and when the vbat power supply is powered down. the rtc interrupt is enabled at the chip level by enabling the chip-specific rtc clock gate control bit. the rtc interrupt can be used to wakeup the chip from any low power mode. the optional rtc seconds interrupt is an edge-sensitive interrupt with a dedicated interrupt vector that is generated once a second and requires no software overhead (there is no corresponding status flag to clear). it is enabled in the rtc by the time seconds interrupt enable bit and enabled at the chip level by setting the chip-specific rtc clock gate control bit. the rtc seconds interrupt does not cause the rtc wakeup pin to assert. this interrupt is optional and may not be implemented on all devices. chapter 43 real time clock (rtc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1125 functional description k60 sub-family reference manual, rev. 6, nov 2011 1126 freescale semiconductor, inc. chapter 44 10/100-mbps ethernet mac (enet) 44.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the mac-net core, in conjunction with a 10/100 mac, implements layer 3 network acceleration functions. these functions are designed to accelerate the processing of various common networking protocols, such as ip, tcp, udp and icmp, providing wire speed services to client applications. 44.1.1 overview the core implements a dual speed 10/100 mbps ethernet mac compliant with the ieee802.3-2002 standard. the mac layer provides compatibility with half- or full- duplex 10/100mbps ethernet lans. the mac operation is fully programmable and can be used in nic (network interface card), bridging, or switching applications. the core implements the remote network monitoring (rmon) counters according to ietf rfc 2819. the core also implements a hardware acceleration block to optimize the performance of network controllers providing ip and tcp, udp, icmp protocol services. the acceleration block performs critical functions in hardware, which are typically implemented with large software overhead. the core implements programmable embedded fifos that can provide buffering on the receive path for loss-less flow control advanced power management features are available with magic packet detection and programmable power-down modes. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1127 for industrial automation application, the ieee 1588 standard is becoming the main technology for precise time synchronization on ethernet networks. this provides accurate clock synchronization for distributed control nodes to overcome one of the drawbacks of ethernet. the programmable 10/100 ethernet mac with ieee 1588 integrates a standard ieee 802.3 ethernet mac with a time-stamping module. 44.1.2 features the mac-net core includes the following features. 44.1.2.1 ethernet mac features ? implements the full 802.3 specification with preamble/sfd generation, frame padding generation, crc generation and checking ? dynamically configurable to support 10/100 mbps operation ? supports 10/100 mbps full duplex and configurable half duplex operation ? compliant with the amd magic packet detection with interrupt for node remote power management ? seamless interface to commercial ethernet phy device via: ? a 4-bit medium independent interface (mii) operating at 25 mhz, or ? a 2-bit reduced mii (rmii) operating at 50 mhz. ? simple 64-bit fifo interface to user application ? crc-32 checking at full speed with optional forwarding of the frame check sequence (fcs) field to the client ? crc-32 generation and append on transmit or forwarding of user application provided fcs selectable on a per-frame basis ? when operating in full duplex mode ? implements automated pause frame (802.3 x31a) generation and termination providing flow control without user application intervention ? pause quanta used to form pause frames, dynamically programmable ? pause frame generation additionally controllable by user application offering flexible traffic flow control ? optional forwarding of received pause frames to the user application ? implements standard flow-control mechanism ? in half-duplex mode, provides full collision support, including jamming, backoff, and automatic retransmission ? support for vlan-tagged frames according to ieee 802.1q ? programmable mac address: insertion on transmit; discards frames with mismatching destination address on receive (except broadcast and pause frames) introduction k60 sub-family reference manual, rev. 6, nov 2011 1128 freescale semiconductor, inc. ? programmable promiscuous mode support to omit mac destination address checking on receive ? multicast and unicast address filtering on receive based on 64 entries hash table reducing higher layer processing load ? programmable frame maximum length providing support for any standard or proprietary frame length ? statistics indicators for frame traffic and errors (alignment, crc, length) and pause frames providing for ieee 802.3 basic and mandatory management information database (mib) package and remote network monitoring (rfc 2819) ? simple handshake user application fifo interface with fully programmable depth and threshold levels ? separate status word available for each received frame on the user interface providing information such as frame length, frame type, vlan tag, and error information ? multiple internal loopback options ? mdio master interface for phy device configuration and management with two programmable mdio base addresses ? supports legacy fec buffer descriptors 44.1.2.2 ip protocol performance optimization features ? operates on tcp/ip and udp/ip and icmp/ip protocol data or ip header only ? enables wire-speed processing ? ipv4 and ipv6 support ? transparent passing of frames of other types and protocols ? support for vlan tagged frames according to ieee 802.1q with transparent forwarding of vlan tag and control field ? automatic ip-header and payload (protocol specific) checksum calculation and verification on receive ? automatic ip-header and payload (protocol specific) checksum generation and automatic insertion on transmit configurable on a per-frame basis ? support for ip and tcp, udp, icmp data for checksum generation and checking ? full header options support for ipv4 and tcp protocol headers ? ipv6 support limited to datagrams with base header only. datagrams with extension headers are passed transparently unmodifed/unchecked. chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1129 ? statistics information for received ip and protocol errors ? configurable automatic discard of erroneous frames ? configurable automatic host-to-network (rx) and network-to-host (tx) byte order conversion for ip and tcp/udp/icmp headers within the frame ? configurable padding remove for short ip datagrams on receive ? configurable ethernet payload alignment to allow for 32-bit word aligned header and payload processing ? programmable store-and-forward operation with clock and rate decoupling fifos 44.1.2.3 ieee 1588 features ? support for all ieee 1588 frames ? reference clock can be chosen independently of the network speed ? software-programmable precise time-stamping of ingress and egress frames ? timer monitoring capabilities for system calibration and timing accuracy management ? precise time-stamping of external events with programmable interrupt generation ? programmable event and interrupt generation for external system control ? hardware- and software-controllable timer synchronization ? 4 channel ieee 1588 timer, each with support for input capture and output compare using the 1588 counter introduction k60 sub-family reference manual, rev. 6, nov 2011 1130 freescale semiconductor, inc. 44.1.3 block diagram rx control pause frame terminate receive fifo tcp offload engine (toe) functions tx control pause frame generate check transmit fifo configuration statistics mdio master register interface management transmit application interface mii/rmii mii/rmii phy interface transmit interface interface receive crc generate crc tcp/ip performance optimization mac tcp/ip performance optimization receive application interface figure 44-1. 10/100 ethernet mac-net core block diagram 44.2 external signal description mii rmii description i/o mii_col asserted upon detection of a collision and remains asserted while the collision persists. this signal is not defined for full-duplex mode. i mii_crs carrier sense. when asserted, indicates transmit or receive medium is not idle. in rmii mode, this signal is present on the rmii_crs_dv pin. i mii_mdc rmii_mdc output clock provides a timing reference to the phy for data transfers on the mdio signal. o table continues on the next page... chapter 44 10100-mbps ethernet mac enet 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 111 mii rmii description i/o mii_mdio rmii_mdio transfers control information between the external phy and the media-access controller. data is synchronous to mdc. this signal is an input after reset. i/o mii_rxclk in mii mode, provides a timing reference for rxdv, rxd[3:0], and rxer. i mii_rxdv rmii_crs_dv asserting this input indicates the phy has valid nibbles present on the mii. rxdv must remain asserted from the first recovered nibble of the frame through to the last nibble. asserting rxdv must start no later than the sfd and exclude any eof. in rmii mode, this pin also generates the crs signal. i mii_rxd[3:0] rmii_rxd[1:0] contains the ethernet input data transferred from the phy to the media-access controller when rxdv is asserted. i mii_rxer rmii_rxer when asserted with rxdv, indicates the phy detects an error in the current frame. i mii_txclk input clock which provides a timing reference for txen, txd[3:0], and txer. i mii_txd[3:0] rmii_txd[1:0] the serial output ethernet data and only valid during the assertion of txen. o mii_txen rmii_txen indicates when valid nibbles are present on the mii. this signal is asserted with the first nibble of a preamble and is negated before the first txclk following the final nibble of the frame. o mii_txer when asserted for one or more clock cycles while txen is also asserted, phy sends one or more illegal symbols. o rmii_ref_clk in rmii mode, this signal is the reference clock for receive, transmit, and the control interface. i table continues on the next page... external signal description 60 sub-family reference manual, rev. 6, nov 2011 112 freescale semiconductor, inc. mii rmii description i/o 1588_tmr n 188_tmr n capturecompare bloc input output event bus. when configured for capture and a rising edge is detected, the current timer value is latched and transferred into the corresponding enet_tccr n register for inspection by software. when configured for compare, the corresponding signal 188_tmr n is asserted for one cycle when the timer reaches the compare value programmed in register enet_tccr n . an interrupt or dma reuest can be triggered if the corresponding bit in enet_tcsr n tie or enet_tcsr n tdre is set. i enet_188_cin enet_188_cin alternate ieee 188 ethernet cloc input i 44. memory mapregister definition reserved bits should be written with 0 and ignored on read to allow future extension. unused registers read zero and a write has no effect. the following table summarizes the ethernet registers. table 44-1. register map summary offset address section description 0x000 configuration core control and status registers 0x200 statistics counters mib block counters. see statistic event counters . 0x400 1588 control 1588 adjustable timer (tsm) and 1588 frame control 0x600 capture/compare block registers for the capture/compare block chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1133 enet memory map absolute address (hex) register name width (in bits) access reset value section/ page 400c_0004 interrupt event register (enet_eir) 32 w1c 0000_0000h 44.3.1/ 1136 400c_0008 interrupt mask register (enet_eimr) 32 r/w 0000_0000h 44.3.2/ 1138 400c_0010 receive descriptor active register (enet_rdar) 32 r/w 0000_0000h 44.3.3/ 1141 400c_0014 transmit descriptor active register (enet_tdar) 32 r/w 0000_0000h 44.3.4/ 1142 400c_0024 ethernet control register (enet_ecr) 32 r/w f000_0000h 44.3.5/ 1143 400c_0040 mii management frame register (enet_mmfr) 32 r/w 0000_0000h 44.3.6/ 1144 400c_0044 mii speed control register (enet_mscr) 32 r/w 0000_0000h 44.3.7/ 1145 400c_0064 mib control register (enet_mibc) 32 r/w c000_0000h 44.3.8/ 1147 400c_0084 receive control register (enet_rcr) 32 r/w 05ee_0001h 44.3.9/ 1148 400c_00c4 transmit control register (enet_tcr) 32 r/w 0000_0000h 44.3.10/ 1150 400c_00e4 physical address lower register (enet_palr) 32 r/w 0000_0000h 44.3.11/ 1152 400c_00e8 physical address upper register (enet_paur) 32 r/w 0000_8808h 44.3.12/ 1152 400c_00ec opcode/pause duration register (enet_opd) 32 r/w 0001_0000h 44.3.13/ 1153 400c_0118 descriptor individual upper address register (enet_iaur) 32 r/w 0000_0000h 44.3.14/ 1153 400c_011c descriptor individual lower address register (enet_ialr) 32 r/w 0000_0000h 44.3.15/ 1154 400c_0120 descriptor group upper address register (enet_gaur) 32 r/w 0000_0000h 44.3.16/ 1154 400c_0124 descriptor group lower address register (enet_galr) 32 r/w 0000_0000h 44.3.17/ 1155 400c_0144 transmit fifo watermark register (enet_tfwr) 32 r/w 0000_0000h 44.3.18/ 1155 400c_0180 receive descriptor ring start register (enet_rdsr) 32 r/w 0000_0000h 44.3.19/ 1156 400c_0184 transmit buffer descriptor ring start register (enet_tdsr) 32 r/w 0000_0000h 44.3.20/ 1157 table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 114 freescale semiconductor, inc. enet memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 400c_0188 maximum receive buffer size register (enet_mrbr) 32 r/w 0000_0000h 44.3.21/ 1157 400c_0190 receive fifo section full threshold (enet_rsfl) 32 r/w 0000_0000h 44.3.22/ 1158 400c_0194 receive fifo section empty threshold (enet_rsem) 32 r/w 0000_0000h 44.3.23/ 1158 400c_0198 receive fifo almost empty threshold (enet_raem) 32 r/w 0000_0004h 44.3.24/ 1159 400c_019c receive fifo almost full threshold (enet_rafl) 32 r/w 0000_0004h 44.3.25/ 1159 400c_01a0 transmit fifo section empty threshold (enet_tsem) 32 r/w 0000_0000h 44.3.26/ 1160 400c_01a4 transmit fifo almost empty threshold (enet_taem) 32 r/w 0000_0004h 44.3.27/ 1160 400c_01a8 transmit fifo almost full threshold (enet_tafl) 32 r/w 0000_0008h 44.3.28/ 1161 400c_01ac transmit inter-packet gap (enet_tipg) 32 r/w 0000_000ch 44.3.29/ 1161 400c_01b0 frame truncation length (enet_ftrl) 32 r/w 0000_07ffh 44.3.30/ 1162 400c_01c0 transmit accelerator function configuration (enet_tacc) 32 r/w 0000_0000h 44.3.31/ 1162 400c_01c4 receive accelerator function configuration (enet_racc) 32 r/w 0000_0000h 44.3.32/ 1163 400c_0400 timer control register (enet_atcr) 32 r/w 0000_0000h 44.3.33/ 1165 400c_0404 timer value register (enet_atvr) 32 r/w 0000_0000h 44.3.34/ 1166 400c_0408 timer offset register (enet_atoff) 32 r/w 0000_0000h 44.3.35/ 1167 400c_040c timer period register (enet_atper) 32 r/w 3b9a_ ca00h 44.3.36/ 1167 400c_0410 timer correction register (enet_atcor) 32 r/w 0000_0000h 44.3.37/ 1168 400c_0414 time-stamping clock period register (enet_atinc) 32 r/w 0000_0000h 44.3.38/ 1168 400c_0418 timestamp of last transmitted frame (enet_atstmp) 32 r 0000_0000h 44.3.39/ 1169 400c_0604 timer global status register (enet_tgsr) 32 r/w 0000_0000h 44.3.40/ 1169 table continues on the next page... chapter 44 10100-mbps ethernet mac enet 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 11 enet memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 400c_0608 timer control status register (enet_tcsr0) 32 r/w 0000_0000h 44.3.41/ 1170 400c_060c timer compare capture register (enet_tccr0) 32 r/w 0000_0000h 44.3.42/ 1171 400c_0610 timer control status register (enet_tcsr1) 32 r/w 0000_0000h 44.3.41/ 1170 400c_0614 timer compare capture register (enet_tccr1) 32 r/w 0000_0000h 44.3.42/ 1171 400c_0618 timer control status register (enet_tcsr2) 32 r/w 0000_0000h 44.3.41/ 1170 400c_061c timer compare capture register (enet_tccr2) 32 r/w 0000_0000h 44.3.42/ 1171 400c_0620 timer control status register (enet_tcsr3) 32 r/w 0000_0000h 44.3.41/ 1170 400c_0624 timer compare capture register (enet_tccr3) 32 r/w 0000_0000h 44.3.42/ 1171 44.3.1 interrupt event register (enet_eir) when an event occurs that sets a bit in eir, an interrupt occurs if the corresponding bit in the interrupt mask register (eimr) is also set. writing a 1 to an eir bit clears it; writing 0 has no effect. this register is cleared upon hardware reset. address: enet_eir is 400c_0000h base + 4h offset = 400c_0004h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 babr babt gra txf txb rxf rxb mii eberr lc rl un plr wakeup ts_avail w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r ts_timer 0 w w1c reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1136 freescale semiconductor, inc. enet_eir field descriptions field description 31 reserved this read-only field is reserved and always has the value zero. 30 babr babbling receive error indicates a frame was received with length in excess of rcr[max_fl] bytes. 29 babt babbling transmit error indicates the transmitted frame length exceeds rcr[max_fl] bytes. usually this condition is caused when a frame that is too long is placed into the transmit data buffer(s). truncation does not occur. 28 gra graceful stop complete this interrupt is asserted after the transmitter is put into a pause state after completion of the frame currently being transmitted. see graceful transmit stop (gts) for conditions that lead to graceful stop. note: the gra interrupt is asserted only when the tx transitions into the stopped state. if this bit is cleared (by writing 1) and the tx is still stopped, the bit is not set again. 27 txf transmit frame interrupt indicates a frame has been transmitted and the last corresponding buffer descriptor has been updated. 26 txb transmit buffer interrupt indicates a transmit buffer descriptor has been updated. 25 rxf receive frame interrupt indicates a frame has been received and the last corresponding buffer descriptor has been updated. 24 rxb receive buffer interrupt. indicates a receive buffer descriptor not the last in the frame has been updated. 23 mii mii interrupt. indicates the mii has completed the data transfer requested. 22 eberr ethernet bus error indicates a system bus error occurred when a udma transaction is underway. (when this bit is set, ecr[ether_en] is cleared, halting frame processing by the mac. when this occurs, software must ensure proper actions (possibly resetting the system) to resume normal operation. 21 lc late collision indicates a collision occurred beyond the collision window (slot time) in half-duplex mode. the frame truncates with a bad crc and the remainder of the frame is discarded. 20 rl collision retry limit. indicates a collision occurred on each of 16 successive attempts to transmit the frame. the frame is discarded without being transmitted and transmission of the next frame commences. this error can only occur in half duplex mode. 19 un transmit fifo underrun indicates the transmit fifo became empty before the complete frame was transmitted. a bad crc is appended to the frame fragment and the remainder of the frame is discarded. table continues on the next page... chapter 44 10100-mbps ethernet mac enet 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 117 enet_eir field descriptions (continued) field description 18 plr payload receive error indicates a frame was received with a payload length error. see frame length/type verification: payload length check for more information. 17 wakeup node wake-up request indication read-only status bit to indicate that a magic packet has been detected. will act only if ecr[magicen] is set. 16 ts_avail transmit timestamp available indicates that the timestamp of the last transmitted timing frame is available in the atstmp register. 15 ts_timer timestamp timer the adjustable timer reached the period event. a period event interrupt can be generated if atcr[peren] is set and the timer wraps according to the periodic setting in the atper register. set the timer period value before setting atcr[peren]. 140 reserved this read-only field is reserved and always has the value zero. 44.3.2 interrupt mask register (enet_eimr) eimr controls which interrupt events are allowed to generate actual interrupts. a hardware reset clears this register. if the corresponding bits in the eir and eimr registers are set, an interrupt is generated. the interrupt signal remains asserted until a 1 is written to the eir bit (write 1 to clear) or a 0 is written to the eimr bit. address: enet_eimr is 400c_0000h base + 8h offset = 400c_0008h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 babr babt gra txf txb rxf rxb mii eberr lc rl un plr wakeup ts_avail w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r ts_timer 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1138 freescale semiconductor, inc. enet_eimr field descriptions field description 31 reserved this read-only field is reserved and always has the value zero. 30 babr babr interrupt mask corresponds to interrupt source babr defined by the eir register and determines whether an interrupt condition can generate an interrupt. at every module clock, the eir samples the signal generated by the interrupting source. the corresponding eir babr bit reflects the state of the interrupt signal even if the corresponding eimr bit is cleared. 0 the corresponding interrupt source is masked. 1 the corresponding interrupt source is not masked. 29 babt babt interrupt mask corresponds to interrupt source babt defined by the eir register and determines whether an interrupt condition can generate an interrupt. at every module clock, the eir samples the signal generated by the interrupting source. the corresponding eir babt bit reflects the state of the interrupt signal even if the corresponding eimr bit is cleared. 0 the corresponding interrupt source is masked. 1 the corresponding interrupt source is not masked. 28 gra gra interrupt mask corresponds to interrupt source gra defined by the eir register and determines whether an interrupt condition can generate an interrupt. at every module clock, the eir samples the signal generated by the interrupting source. the corresponding eir gra bit reflects the state of the interrupt signal even if the corresponding eimr bit is cleared. 0 the corresponding interrupt source is masked. 1 the corresponding interrupt source is not masked. 27 txf txf interrupt mask corresponds to interrupt source txf defined by the eir register and determines whether an interrupt condition can generate an interrupt. at every module clock, the eir samples the signal generated by the interrupting source. the corresponding eir txf bit reflects the state of the interrupt signal even if the corresponding eimr bit is cleared. 0 the corresponding interrupt source is masked. 1 the corresponding interrupt source is not masked. 26 txb txb interrupt mask corresponds to interrupt source txb defined by the eir register and determines whether an interrupt condition can generate an interrupt. at every module clock, the eir samples the signal generated by the interrupting source. the corresponding eir txf bit reflects the state of the interrupt signal even if the corresponding eimr bit is cleared. 0 the corresponding interrupt source is masked. 1 the corresponding interrupt source is not masked. 25 rxf rxf interrupt mask corresponds to interrupt source rxf defined by the eir register and determines whether an interrupt condition can generate an interrupt. at every module clock, the eir samples the signal generated by the table continues on the next page... chapter 44 10100-mbps ethernet mac enet 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 11 enet_eimr field descriptions (continued) field description interrupting source. the corresponding eir rxf bit reflects the state of the interrupt signal even if the corresponding eimr bit is cleared. 24 rxb rxb interrupt mask corresponds to interrupt source rxb defined by the eir register and determines whether an interrupt condition can generate an interrupt. at every module clock, the eir samples the signal generated by the interrupting source. the corresponding eir rxb bit reflects the state of the interrupt signal even if the corresponding eimr bit is cleared. 23 mii mii interrupt mask corresponds to interrupt source mii defined by the eir register and determines whether an interrupt condition can generate an interrupt. at every module clock, the eir samples the signal generated by the interrupting source. the corresponding eir mii bit reflects the state of the interrupt signal even if the corresponding eimr bit is cleared. 22 eberr eberr interrupt mask corresponds to interrupt source eberr defined by the eir register and determines whether an interrupt condition can generate an interrupt. at every module clock, the eir samples the signal generated by the interrupting source. the corresponding eir eberr bit reflects the state of the interrupt signal even if the corresponding eimr bit is cleared. 21 lc lc interrupt mask corresponds to interrupt source lc defined by the eir register and determines whether an interrupt condition can generate an interrupt. at every module clock, the eir samples the signal generated by the interrupting source. the corresponding eir lc bit reflects the state of the interrupt signal even if the corresponding eimr bit is cleared. 20 rl rl interrupt mask corresponds to interrupt source rl defined by the eir register and determines whether an interrupt condition can generate an interrupt. at every module clock, the eir samples the signal generated by the interrupting source. the corresponding eir rl bit reflects the state of the interrupt signal even if the corresponding eimr bit is cleared. 19 un un interrupt mask corresponds to interrupt source un defined by the eir register and determines whether an interrupt condition can generate an interrupt. at every module clock, the eir samples the signal generated by the interrupting source. the corresponding eir un bit reflects the state of the interrupt signal even if the corresponding eimr bit is cleared. 18 plr plr interrupt mask corresponds to interrupt source plr defined by the eir register and determines whether an interrupt condition can generate an interrupt. at every module clock, the eir samples the signal generated by the interrupting source. the corresponding eir plr bit reflects the state of the interrupt signal even if the corresponding eimr bit is cleared. 17 wakeup wakeup interrupt mask corresponds to interrupt source wakeup defined by the eir register and determines whether an interrupt condition can generate an interrupt. at every module clock, the eir samples the signal generated by the interrupting source. the corresponding eir wakeup bit reflects the state of the interrupt signal even if the corresponding eimr bit is cleared. table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 1140 freescale semiconductor, inc. enet_eimr field descriptions (continued) field description 16 ts_avail ts_avail interrupt mask corresponds to interrupt source ts_avail defined by the eir register and determines whether an interrupt condition can generate an interrupt. at every module clock, the eir samples the signal generated by the interrupting source. the corresponding eir ts_avail bit reflects the state of the interrupt signal even if the corresponding eimr bit is cleared. 15 ts_timer ts_timer interrupt mask corresponds to interrupt source ts_timer defined by the eir register and determines whether an interrupt condition can generate an interrupt. at every module clock, the eir samples the signal generated by the interrupting source. the corresponding eir ts_timer bit reflects the state of the interrupt signal even if the corresponding eimr bit is cleared. 140 reserved this read-only field is reserved and always has the value zero. 44.3.3 receive descriptor active register (enet_rdar) rdar is a command register, written by the user, indicating the receive descriptor ring has been updated (the driver produced empty receive buffers with the empty bit set). when the register is written, the rdar bit is set. this is independent of the data actually written by the user. when set, the mac polls the receive descriptor ring and processes receive frames (provided ecr[ether_en] is also set). after the mac polls a receive descriptor whose empty bit is not set, mac clears rdar and ceases receive descriptor ring polling until the user sets the bit again, signifying that additional descriptors have been placed into the receive descriptor ring. the rdar register is cleared at reset and when ecr[ether_en] transitions from set to cleared or when ecr[reset] is set. address: enet_rdar is 400c_0000h base + 10h offset = 400c_0010h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 rdar 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enet_rdar field descriptions field description 31?25 reserved this read-only field is reserved and always has the value zero. table continues on the next page... chapter 44 10100-mbps ethernet mac enet 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1141 enet_rdar field descriptions (continued) field description 24 rdar receive descriptor active set to 1 when this register is written, regardless of the value written. this bit is cleared by the mac device when no additional empty descriptors remain in the receive ring. it is also cleared when ecr[ether_en] transitions from set to cleared or when ecr[reset] is set. 230 reserved this read-only field is reserved and always has the value zero. 44.3.4 transmit descriptor active register (enet_tdar) the tdar is a command register that the user writes to indicate that the transmit descriptor ring has been updated (transmit buffers have been produced by the driver with the ready bit set in the buffer descriptor). when the register is written, the tdar bit is set. this value is independent of the data actually written by the user. when set, the mac polls the transmit descriptor ring and processes transmit frames (provided ecr[ether_en] is also set). after the mac polls a transmit descriptor that contains a ready bit that is not set, the mac clears tdar and ceases transmit descriptor ring polling until the user sets the bit again, signifying additional descriptors have been placed into the transmit descriptor ring. the tdar register is cleared at reset, when ecr[ether_en] transitions from set to cleared, or when ecr[reset] is set. address: enet_tdar is 400c_0000h base + 14h offset = 400c_0014h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 tdar 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enet_tdar field descriptions field description 31?25 reserved this read-only field is reserved and always has the value zero. 24 tdar transmit descriptor active set to 1 when this register is written, regardless of the value written. this bit is cleared by the mac device when no additional ready descriptors remain in the transmit ring. also cleared when ecr[ether_en] transitions from set to cleared or when ecr[reset] is set. 23?0 reserved this read-only field is reserved and always has the value zero. memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1142 freescale semiconductor, inc. 44.3.5 ethernet control register (enet_ecr) ecr is a read/write user register, though hardware may alter fields in this register as well. it controls many of the high level features of the ethernet mac, including legacy fec support through the en1588 bit. address: enet_ecr is 400c_0000h base + 24h offset = 400c_0024h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 1 0 w reset 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 stopen dbgen 0 en1588 sleep magicen etheren reset w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enet_ecr field descriptions field description 31?28 reserved this read-only field is reserved and always has the value one. 27?8 reserved this read-only field is reserved and always has the value zero. 7 stopen stopen signal control controls device behavior in doze mode. in doze mode, if this bit is set then all the clocks of the enet assembly are disabled (except the rmii/mii clock). doze mode is like a conditional stop mode entry for the enet assembly depending on ecr[stopen]. note: if module clocks are gated in this mode, the module can still wake the system after receiving a magic packet in stop mode. magicen must be set prior to entering sleep/stop mode. 6 dbgen debug enable enables the mac to enter hardware freeze mode when the device enters debug mode. 0 mac continues operation in debug mode. 1 mac enters hardware freeze mode when the processor is in debug mode. 5 reserved this read-only field is reserved and always has the value zero. 4 en1588 en1588 enable enables enhanced functionality of the mac. table continues on the next page... chapter 44 10100-mbps ethernet mac enet 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 114 enet_ecr field descriptions (continued) field description 0 legacy fec buffer descriptors and functions enabled. 1 enhanced frame time-stamping functions enabled. 3 sleep sleep mode enable 0 normal operating mode. 1 sleep mode. 2 magicen magic packet detection enable enables/disables magic packet detection. note: magicen is relevant only if the sleep bit is set. if magicen is set, changing the sleep bit enables/disables sleep mode and magic packet detection. 0 magic detection logic disabled 1 the mac core detects magic packets and asserts eir[wakeup] when a frame is detected. 1 etheren ethernet enable enables/disables the ethernet mac. when the mac is disabled, the buffer descriptors for an aborted transmit frame are not updated. the udma, buffer descriptor, and fifo control logic are reset, including the buffer descriptor and fifo pointers. hardware clears this bit under the following conditions: ? reset is set by software ? an error condition causes the eberr bit to set. 0 reception immediately stops and transmission stops after a bad crc is appended to any currently transmitted frame. 1 mac is enabled, and reception and transmission are possible. 0 reset ethernet mac reset when this bit is set, it clears the ether_en bit. 44.3.6 mii management frame register (enet_mmfr) performing a write to mmfr triggers a management frame transaction to the phy device unless mscr is programmed to zero. if mscr is changed from zero to non-zero during a write to mmfr, an mii frame is generated with the data previously written to the mmfr. this allows mmfr and mscr to be programmed in either order if mscr is currently zero. if the mmfr register is written while frame generation is in progress, the frame contents are altered. software must use the eir[mii] interrupt indication to avoid writing to the mmfr register while frame generation is in progress. memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1144 freescale semiconductor, inc. address: enet_mmfr is 400c_0000h base + 40h offset = 400c_0040h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r st op pa ra ta data w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enet_mmfr field descriptions field description 3130 st start of frame delimiter these bits must be programmed to 01 for a valid mii management frame. 2928 op operation code determines the frame operation. 00 write frame operation, but not mii compliant. 01 write frame operation for a valid mii management frame. 10 read frame operation for a valid mii management frame. 11 read frame operation, but not mii compliant. 2723 pa phy address phy address. specifies one of up to 32 attached phy devices. 2218 ra register address specifies one of up to 32 registers within the specified phy device. 1716 ta turn around this field must be programmed to 10 to generate a valid mii management frame. 150 data management frame data this is the field for data to be written to or read from the phy register. 44.3.7 mii speed control register (enet_mscr) mscr provides control of the mii clock (mdc pin) frequency and allows a preamble drop on the mii management frame. the mii_speed field must be programmed with a value to provide an mdc frequency of less than or equal to 2.5 mhz to be compliant with the ieee 802.3 mii specification. the mii_speed must be set to a non-zero value to source a read or write management frame. after the management frame is complete, the mscr register may optionally be cleared to turn off mdc. the mdc signal generated has a 50% duty cycle except when mii_speed changes during operation (change takes effect following a rising or falling edge of mdc). chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1145 if the internal module clock is 25 mhz, programming this register to 0x0000_0004 results in an mdc as stated the equation below. 25 mhz / ((4 + 1) x 2) = 2.5 mhz the following table shows the optimum values for mii_speed as a function of internal module clock frequency. table 44-10. programming examples for mscr internal mac clock frequency mscr [mii_speed] mdc frequency 25 mhz 0x4 2.50 mhz 33 mhz 0x6 2.36 mhz 40 mhz 0x7 2.50 mhz 50 mhz 0x9 2.50 mhz 66 mhz 0xd 2.36 mhz address: enet_mscr is 400c_0000h base + 44h offset = 400c_0044h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 holdtime dis_pre mii_speed 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enet_mscr field descriptions field description 31?11 reserved this read-only field is reserved and always has the value zero. 10?8 holdtime holdtime on mdio output ieee802.3 clause 22 defines a minimum of 10 ns for the holdtime on the mdio output. depending on the host bus frequency the setting may need to be increased. 000 1 internal module clock cycle 001 2 internal module clock cycles 010 3 internal module clock cycles 111 8 internal module clock cycles 7 dis_pre disable preamble table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 1146 freescale semiconductor, inc. enet_mscr field descriptions (continued) field description enables/disables prepending a preamble to the mii management frame. the mii standard allows the preamble to be dropped if the attached phy devices do not require it. 0 preamble enabled. 1 preamble (32 ones) is not prepended to the mii management frame. 61 mii_speed mii speed controls the frequency of the mii management interface clock (mdc) relative to the internal module clock. a value of 0 in this field turns off mdc and leaves it in low voltage state. any non-zero value results in the mdc frequency of: 1/((mii_speed + 1) x 2) of the internal module clock frequency 0 reserved this read-only field is reserved and always has the value zero. 44.3.8 mib control register (enet_mibc) mibc is a read/write register controlling and observing the state of the mib block. access this register to disable the mib block operation or clear the mib counters. the mib_dis bit resets to 1. address: enet_mibc is 400c_0000h base + 64h offset = 400c_0064h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r mib_dis mib_ idle mib_clear 0 w reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enet_mibc field descriptions field description 31 mib_dis disable mib logic if this control bit is set, the mib logic halts and does not update any mib counters. 30 mib_idle mib idle if this status bit is set, the mib block is not currently updating any mib counters. table continues on the next page... chapter 44 10100-mbps ethernet mac enet 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1147 enet_mibc field descriptions (continued) field description 29 mib_clear mib clear if set, all statistics counters are reset to 0. note: this bit is not self-clearing. to clear the mib counters set and then clear the bit. 280 reserved this read-only field is reserved and always has the value zero. 44.3.9 receive control register (enet_rcr) address: enet_rcr is 400c_0000h base + 84h offset = 400c_0084h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r grs nlc max_fl w reset 0 0 0 0 0 1 0 1 1 1 1 0 1 1 1 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r cfen crcfwd paufwd paden 0 rmii_10t rmii_mode 0 0 fce bc_ rej prom mii_mode drt loop w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 enet_rcr field descriptions field description 31 grs graceful receive stopped read-only status indicating that the mac receive datapath is stopped. 30 nlc payload length check disable enables/disables a payload length check. 0 the payload length check is disabled 1 the core checks the frames payload length with the frame length/type field. errors are indicated in the eir[plc] bit. 2916 max_fl maximum frame length resets to decimal 1518. length is measured starting at da and includes the crc at the end of the frame. transmit frames longer than max_fl cause the babt interrupt to occur. receive frames longer than max_fl cause the babr interrupt to occur and set the lg bit in the end of frame receive buffer descriptor. the recommended default value to be programmed is 1518 or 1522 if vlan tags are supported. table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 1148 freescale semiconductor, inc. enet_rcr field descriptions (continued) field description 15 cfen mac control frame enable enables/disables the mac control frame. 0 mac control frames with any opcode other than 0x0001 are accepted and forwarded to the client interface. 1 mac control frames with any opcode other than 0x0001 (pause frame) are silently discarded. 14 crcfwd terminate/forward received crc specifies whether the crc field of received frames is transmitted or stripped. note: if padding function is enabled (paden = 1), crcfwd is ignored and the crc field is checked and always terminated and removed. 0 the crc field of received frames is transmitted to the user application. 1 the crc field is stripped from the frame. 13 paufwd terminate/forward pause frames. specifies whether pause frames are terminated or forwarded. 0 pause frames are terminated and discarded in the mac. 1 pause frames are forwarded to the user application. 12 paden enable frame padding remove on receive specifies whether the mac removes padding from received frames. 0 no padding is removed on receive by the mac. 1 padding is removed from received frames. 1110 reserved this read-only field is reserved and always has the value zero. 9 rmii_10t enables 10-mbps mode of the rmii. 0 100 mbps operation 1 10 mbps operation 8 rmii_mode rmii mode enable specifies whether the mac is configured for mii mode or rmii operation. 0 mac configured for mii mode. 1 mac configured for rmii operation. 7 reserved this read-only field is reserved and always has the value zero. 6 reserved this read-only field is reserved and always has the value zero. 5 fce flow control enable if set, the receiver detects pause frames. upon pause frame detection, the transmitter stops transmitting data frames for a given duration. 4 bc_rej broadcast frame reject table continues on the next page... chapter 44 10100-mbps ethernet mac enet 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 114 enet_rcr field descriptions (continued) field description if set, frames with da (destination address) equal to 0xffff_ffff_ffff are rejected unless the prom bit is set. if bc_rej and prom are set, frames with broadcast da are accepted and the m (miss) is set in the receive buffer descriptor. 3 prom promiscuous mode. all frames are accepted regardless of address matching. 0 disabled 1 enabled 2 mii_mode media independent interface mode this bit must always be set. 0 reserved. 1 mii or rmii mode, as indicated by the rmii_mode bit 1 drt disable receive on transmit 0 receive path operates independently of transmit (use for full duplex or to monitor transmit activity in half duplex mode). 1 disable reception of frames while transmitting (normally used for half duplex mode). 0 loop internal loopback 0 loopback disabled. 1 transmitted frames are looped back internal to the device and transmit mii output signals are not asserted. drt must be cleared. . 44.3.10 transmit control register (enet_tcr) tcr is read/write and configures the transmit block. this register is cleared at system reset. fden can only be modified when ecr[ether_en] is cleared. address: enet_tcr is 400c_0000h base + c4h offset = 400c_00c4h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 crcfwd addins addsel rfc_ pause tfc_pause fden 0 gts w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1150 freescale semiconductor, inc. enet_tcr field descriptions field description 3110 reserved this read-only field is reserved and always has the value zero. 9 crcfwd forward frame from application with crc 0 txbd[tc] controls whether the frame has a crc from the application 1 the transmitter does not append any crc to transmitted frames as it is expecting a frame with crc from the application. 8 addins set mac address on transmit 0 the source mac address is not modified by the mac. 1 the mac overwrites the source mac address with the programmed mac address according to addsel. 75 addsel source mac address select on transmit if addins is set, indicates the mac address that overwrites the source mac address. 000 node mac address programmed on paddr1/2 registers. 100 reserved 101 reserved 110 reserved 4 rfc_pause receive frame control pause this status bit is set when a full duplex flow control pause frame is received and the transmitter pauses for the duration defined in this pause frame. this bit automatically clears when the pause duration is complete. 3 tfc_pause transmit frame control pause pauses frame transmission. when this bit is set, eir[gra] is set. with transmission of data frames stopped, the mac transmits a mac control pause frame. next, the mac clears tfc_pause and resumes transmitting data frames. if the transmitter pauses due to user assertion of gts or reception of a pause frame, the mac may continue transmitting a mac control pause frame. 0 no pause frame transmitted. 1 the mac stops transmission of data frames after the current transmission is complete. 2 fden full duplex enable if this bit set, frames transmit independent of carrier sense and collision inputs. only modify this bit when ecr[ether_en] is cleared. 1 reserved this read-only field is reserved and always has the value zero. 0 gts graceful transmit stop when this bit is set, mac stops transmission after any frame currently transmitted is complete and eir[gra] is set. if frame transmission is not currently underway, the gra interrupt is asserted immediately. after transmission finishes, clear gts to restart. the next frame in the transmit fifo is then transmitted. if an early collision occurs during transmission when gts is set, transmission stops after the collision. the frame is transmitted again after gts is cleared. there may be old frames in the transmit fifo that transmit when gts is reasserted. to avoid this, clear ecr[ether_en] following the gra interrupt. chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1151 44.3.11 physical address lower register (enet_palr) palr contains the lower 32 bits (bytes 0,1,2,3) of the 48-bit address used in the address recognition process to compare with the da (destination address) field of receive frames with an individual da. in addition, this register is used in bytes 0 through 3 of the six- byte source address field when transmitting pause frames. this register is not reset and you must initialize it. address: enet_palr is 400c_0000h base + e4h offset = 400c_00e4h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r paddr1 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enet_palr field descriptions field description 31?0 paddr1 pause address bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the 6-byte individual address are used for exact match and the source address field in pause frames. 44.3.12 physical address upper register (enet_paur) paur contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in the address recognition process to compare with the da (destination address) field of receive frames with an individual da. in addition, this register is used in bytes 4 and 5 of the six-byte source address field when transmitting pause frames. bits 15:0 of paur contain a constant type field (0x8808) for transmission of pause frames. the upper 16 bits of this register are not reset and you must initialize it. address: enet_paur is 400c_0000h base + e8h offset = 400c_00e8h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r paddr2 type w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 enet_paur field descriptions field description 31?16 paddr2 bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match, and the source address field in pause frames. table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 112 freescale semiconductor, inc. enet_paur field descriptions (continued) field description 150 type type field in pause frames. these bits have a constant value of 0x8808. 44.3.13 opcode/pause duration register (enet_opd) opd is read/write accessible. this register contains the 16-bit opcode and 16-bit pause duration fields used in transmission of a pause frame. the opcode field is a constant value, 0x0001. when another node detects a pause frame, that node pauses transmission for the duration specified in the pause duration field. the lower 16 bits of this register are not reset and you must initialize them. address: enet_opd is 400c_0000h base + ech offset = 400c_00ech bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r opcode pause_dur w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enet_opd field descriptions field description 31?16 opcode opcode field in pause frames these bits have a constant value of 0x0001. 15?0 pause_dur pause duration pause duration field used in pause frames. 44.3.14 descriptor individual upper address register (enet_iaur) iaur contains the upper 32 bits of the 64-bit individual address hash table. the address recognition process uses this table to check for a possible match with the destination address (da) field of receive frames with an individual da. this register is not reset and you must initialize it. address: enet_iaur is 400c_0000h base + 118h offset = 400c_0118h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r iaddr1 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1153 enet_iaur field descriptions field description 310 iaddr1 the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address. bit 31 of iaddr1 contains hash index bit 63. bit 0 of iaddr1 contains hash index bit 32. 44.3.15 descriptor individual lower address register (enet_ialr) ialr contains the lower 32 bits of the 64-bit individual address hash table. the address recognition process uses this table to check for a possible match with the da field of receive frames with an individual da. this register is not reset and you must initialize it. address: enet_ialr is 400c_0000h base + 11ch offset = 400c_011ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r iaddr2 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enet_ialr field descriptions field description 31?0 iaddr2 the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address. bit 31 of iaddr2 contains hash index bit 31. bit 0 of iaddr2 contains hash index bit 0. 44.3.16 descriptor group upper address register (enet_gaur) gaur contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. you must initialize this register. address: enet_gaur is 400c_0000h base + 120h offset = 400c_0120h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r gaddr1 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enet_gaur field descriptions field description 31?0 gaddr1 contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. bit 31 of gaddr1 contains hash index bit 63. bit 0 of gaddr1 contains hash index bit 32. memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1154 freescale semiconductor, inc. 44.3.17 descriptor group lower address register (enet_galr) galr contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. you must initialize this register. address: enet_galr is 400c_0000h base + 124h offset = 400c_0124h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r gaddr2 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enet_galr field descriptions field description 31?0 gaddr2 contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. bit 31 of gaddr2 contains hash index bit 31. bit 0 of gaddr2 contains hash index bit 0. 44.3.18 transmit fifo watermark register (enet_tfwr) if tfr[strfwd] is cleared, tfwr[tfwr] controls the amount of data required in the transmit fifo before transmission of a frame can begin. this allows you to minimize transmit latency (tfwr = 00 or 01) or allow for larger bus access latency (tfwr = 11) due to contention for the system bus. setting the watermark to a high value minimizes the risk of transmit fifo underrun due to contention for the system bus. the byte counts associated with the tfwr field may need to be modified to match a given system requirement (worst case bus access latency by the transmit data dma channel). address: enet_tfwr is 400c_0000h base + 144h offset = 400c_0144h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 strfwd 0 tfwr w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1155 enet_tfwr field descriptions field description 319 reserved this read-only field is reserved and always has the value zero. 8 strfwd store and forward enable 0 disabled, the transmission start threshold is programmed in tfwr. 1 enabled. 76 reserved this read-only field is reserved and always has the value zero. 50 tfwr transmit fifo write if strfwd is cleared, indicates the number of bytes written to the transmit fifo before transmission of a frame begins. note: if a frame with less than the threshold is written,it is still sent, independently of this threshold setting. the threshold is only relevant if the frame is larger than the threshold given. 000000 64 bytes written 000001 64 bytes written 000010 128 bytes written 000011 192 bytes written 111111 4032 bytes written 44.3.19 receive descriptor ring start register (enet_rdsr) rdsr points to the start of the circular receive buffer descriptor queue in external memory. this pointer must be 64-bit aligned (bits 2C0 must be zero); however, it is recommended to be 128-bit aligned (evenly divisible by 16). this register is not reset and must be initialized prior to operation. address: enet_rdsr is 400c_0000h base + 180h offset = 400c_0180h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r_des_start 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enet_rdsr field descriptions field description 31?3 r_des_start pointer to the start of the receive buffer descriptor queue. 2?0 reserved this read-only field is reserved and always has the value zero. memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1156 freescale semiconductor, inc. 44.3.20 transmit buffer descriptor ring start register (enet_tdsr) tdsr provides a pointer to the start of the circular transmit buffer descriptor queue in external memory. this pointer must be 64-bit aligned (bits 2C0 must be zero); however, it is recommended to be 128-bit aligned (evenly divisible by 16). this register is undefined at reset and must be initialized prior to operation. address: enet_tdsr is 400c_0000h base + 184h offset = 400c_0184h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r x_des_start 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enet_tdsr field descriptions field description 31?3 x_des_start pointer to the start of the transmit buffer descriptor queue. 2?0 reserved this read-only field is reserved and always has the value zero. 44.3.21 maximum receive buffer size register (enet_mrbr) the mrbr is a user-programmable register that dictates the maximum size of all receive buffers. this value should take into consideration that the receive crc is always written into the last receive buffer. to allow one maximum size frame per buffer, mrbr must be set to rcr[max_fl] or larger. to properly align the buffer, mrbr must be evenly divisible by 16. to ensure this, bits 3C0 are forced low. to minimize bus utilization (descriptor fetches), set mrbr greater than or equal to 256 bytes. the mrbr register is undefined at reset and must be initialized by the user. address: enet_mrbr is 400c_0000h base + 188h offset = 400c_0188h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 r_buf_size 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1157 enet_mrbr field descriptions field description 3114 reserved this read-only field is reserved and always has the value zero. 134 r_buf_size receive buffer size in bytes. 30 reserved this read-only field is reserved and always has the value zero. 44.3.22 receive fifo section full threshold (enet_rsfl) address: enet_rsfl is 400c_0000h base + 190h offset = 400c_0190h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 rx_section_full w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enet_rsfl field descriptions field description 318 reserved this read-only field is reserved and always has the value zero. 70 rx_section_ full value of receive fifo section full threshold value, in 64-bit words, of the receive fifo section full threshold. clear this field to enable store and forward on the rx fifo. when programming a value greater than 0 (cut-through operation), it must be greater than raem[rx_almost_empty]. 44.3.23 receive fifo section empty threshold (enet_rsem) address: enet_rsem is 400c_0000h base + 194h offset = 400c_0194h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 rx_section_empty w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enet_rsem field descriptions field description 318 reserved this read-only field is reserved and always has the value zero. table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 118 freescale semiconductor, inc. enet_rsem field descriptions (continued) field description 70 rx_section_ empty value of the receive fifo section empty threshold value, in 64-bit words, of the receive fifo section empty threshold. 44.3.24 receive fifo almost empty threshold (enet_raem) address: enet_raem is 400c_0000h base + 198h offset = 400c_0198h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 rx_almost_empty w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 enet_raem field descriptions field description 318 reserved this read-only field is reserved and always has the value zero. 70 rx_almost_ empty value of the receive fifo almost empty threshold value, in 64-bit words, of the receive fifo almost empty threshold. 44.3.25 receive fifo almost full threshold (enet_rafl) address: enet_rafl is 400c_0000h base + 19ch offset = 400c_019ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 rx_almost_full w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 enet_rafl field descriptions field description 318 reserved this read-only field is reserved and always has the value zero. 70 rx_almost_ full value of the receive fifo almost full threshold value, in 64-bit words, of the receive fifo almost full threshold. chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1159 44.3.26 transmit fifo section empty threshold (enet_tsem) address: enet_tsem is 400c_0000h base + 1a0h offset = 400c_01a0h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 tx_section_empty w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enet_tsem field descriptions field description 318 reserved this read-only field is reserved and always has the value zero. 70 tx_section_ empty value of the transmit fifo section empty threshold value, in 64-bit words, of the transmit fifo section empty threshold. 44.3.27 transmit fifo almost empty threshold (enet_taem) address: enet_taem is 400c_0000h base + 1a4h offset = 400c_01a4h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 tx_almost_empty w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 enet_taem field descriptions field description 318 reserved this read-only field is reserved and always has the value zero. 70 tx_almost_ empty value of transmit fifo almost empty threshold value, in 64-bit words, of the transmit fifo almost empty threshold. memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1160 freescale semiconductor, inc. 44.3.28 transmit fifo almost full threshold (enet_tafl) address: enet_tafl is 400c_0000h base + 1a8h offset = 400c_01a8h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 tx_almost_full w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 enet_tafl field descriptions field description 318 reserved this read-only field is reserved and always has the value zero. 70 tx_almost_ full value of the transmit fifo almost full threshold value, in 64-bit words, of the transmit fifo almost full threshold. a minimum value of six is required a recommended value of at least 8 should be set allowing a latency of two clock cycles to the application. if more latency is required the value can be increased as necessary (latency = tafl - 5). note: a fifo overflow is a fatal error and requires a global reset on the transmit datapath or at least deassertion of ether_en. 44.3.29 transmit inter-packet gap (enet_tipg) address: enet_tipg is 400c_0000h base + 1ach offset = 400c_01ach bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 ipg w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 enet_tipg field descriptions field description 315 reserved this read-only field is reserved and always has the value zero. 40 ipg transmit inter-packet gap indicates the ipg, in bytes, between transmitted frames. can be set between 8 and 27. if set to less than 8, the ipg is 8. if set to greater than 27, the ipg is 27. chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1161 44.3.30 frame truncation length (enet_ftrl) address: enet_ftrl is 400c_0000h base + 1b0h offset = 400c_01b0h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 trunc_fl w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 enet_ftrl field descriptions field description 3114 reserved this read-only field is reserved and always has the value zero. 130 trunc_fl frame truncation length indicates the value a receive frame is truncated, if it is greater than this value. should be greater than or equal to rcr[max_fl]. note: truncation happens at trunc_fl. however, when truncation occurs, the application (fifo) may receive less data, guaranteeing that it never receives more than the set limit. 44.3.31 transmit accelerator function configuration (enet_tacc) tacc controls accelerator actions when sending frames. the register can be changed before or after each frame, but it must remain unmodified during frame writes into the transmit fifo. the tfwr[strfwd] bit must be set to use the checksum feature. address: enet_tacc is 400c_0000h base + 1c0h offset = 400c_01c0h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 prochk ipchk 0 shift16 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1162 freescale semiconductor, inc. enet_tacc field descriptions field description 315 reserved this read-only field is reserved and always has the value zero. 4 prochk enables insertion of protocol checksum. 0 checksum not inserted. 1 if an ip frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. the checksum field must be cleared. the other frames are not modified. 3 ipchk enables insertion of ip header checksum. 0 checksum is not inserted. 1 if an ip frame is transmitted, the checksum is inserted automatically. the ip header checksum field must be cleared. if a non-ip frame is transmitted the frame is not modified. 21 reserved this read-only field is reserved and always has the value zero. 0 shift16 tx fifo shift-16 0 disabled. 1 indicates to the transmit data fifo, that the written frames contain two additional octets before the frame data. this means the actual frame starts at bit 16 of the first word written into the fifo. this function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte ethernet header is extended to a 16-byte header. 44.3.32 receive accelerator function configuration (enet_racc) address: enet_racc is 400c_0000h base + 1c4h offset = 400c_01c4h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 shift16 linedis 0 prodis ipdis padrem w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enet_racc field descriptions field description 318 reserved this read-only field is reserved and always has the value zero. table continues on the next page... chapter 44 10100-mbps ethernet mac enet 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 116 enet_racc field descriptions (continued) field description 7 shift16 rx fifo shift-16 when this bit is set, the actual frame data starts at bit 16 of the first word read from the rx fifo aligning the ethernet payload on a 32-bit boundary. note: this function only affects the fifo storage and has no influence on the statistics, which use the actual length of the frame received. 0 disabled. 1 instructs the mac to write two additional bytes in front of each frame received into the rx fifo. 6 linedis enable discard of frames with mac layer errors 0 frames with errors are not discarded. 1 any frame received with a crc, length, or phy error is automatically discarded and not forwarded to the user application interface. 53 reserved this read-only field is reserved and always has the value zero. 2 prodis enable discard of frames with wrong protocol checksum 0 frames with wrong checksum are not discarded. 1 if a tcp/ip, udp/ip, or icmp/ip frame is received that has a wrong tcp, udp, or icmp checksum, the frame is discarded. discarding is only available when the rx fifo operates in store and forward mode (rsfl cleared). 1 ipdis enable discard of frames with wrong ipv4 header checksum. 0 frames with wrong ipv4 header checksum are not discarded. 1 if an ipv4 frame is received with a mismatching header checksum, the frame is discarded. ipv6 has no header checksum and is not affected by this setting. discarding is only available when the rx fifo operates in store and forward mode (rsfl cleared). 0 padrem enable padding removal for short ip frames. 0 padding not removed. 1 any bytes following the ip payload section of the frame are removed from the frame. memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1164 freescale semiconductor, inc. 44.3.33 timer control register (enet_atcr) atcr command bits can trigger the corresponding events directly. it is not necessary to preserve any of the configuration bits when a command bit is set in the register (no read- modify-write is required). the bits are automatically cleared after the command completes. address: enet_atcr is 400c_0000h base + 400h offset = 400c_0400h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 slave 0 capture 0 restart 0 pinper 0 peren offrst offen 0 en w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enet_atcr field descriptions field description 31?14 reserved this read-only field is reserved and always has the value zero. 13 slave enable timer slave mode 0 the timer is active and all configuration bits in this register are relevant. 1 the internal timer is disabled and the externally provided timer value is used. all other bits, except capture, in this register have no effect. capture can still be used to capture the current timer value. 12 reserved this read-only field is reserved and always has the value zero. 11 capture capture timer value 0 no effect. 1 the current time is captured and can be read from the atvr register. 10 reserved this read-only field is reserved and always has the value zero. 9 restart reset timer resets the timer to zero. this has no effect on the counter enable. if the counter is enabled when this bit is set, the timer is reset to zero and starts counting from there. when set, all other bits are ignored during a write. table continues on the next page... chapter 44 10100-mbps ethernet mac enet 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 116 enet_atcr field descriptions (continued) field description 8 reserved this read-only field is reserved and always has the value zero. 7 pinper enables event signal output assertion on period event. note: not all devices contain the event signal output. see the chip configuration details. 0 disable. 1 enable. 65 reserved this read-only field is reserved and always has the value zero. 4 peren enable periodical event 0 disable. 1 a period event interrupt can be generated (eir[ts_timer]) and the event signal output is asserted when the timer wraps around according to the periodic setting atper. set the timer period value before setting this bit. note: not all devices contain the event signal output. see the chip configuration details. 3 offrst reset timer on offset event 0 the timer is not affected and no action occurs (besides clearing offen) when the offset is reached. 1 if offen is set, the timer resets to zero when the offset setting is reached. the offset event does not cause a timer interrupt. 2 offen enable one-shot offset event 0 disable. 1 the timer can be reset to zero when the given offset time is reached (offset event). the bit is cleared when the offset event is reached, so no further event occurs until the bit is set again. set the timer offset value before setting this bit. 1 reserved this read-only field is reserved and always has the value zero. 0 en enable timer 0 the timer stops at the current value. 1 the timer starts incrementing. 44.3.34 timer value register (enet_atvr) address: enet_atvr is 400c_0000h base + 404h offset = 400c_0404h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r atime w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1166 freescale semiconductor, inc. enet_atvr field descriptions field description 310 atime a write sets the timer. a read returns the last captured value. to read the current value, issue a capture command (set atcr[capture]) prior to reading this register. 44.3.35 timer offset register (enet_atoff) address: enet_atoff is 400c_0000h base + 408h offset = 400c_0408h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r offset w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enet_atoff field descriptions field description 310 offset offset value for one-shot event generation. when the timer reaches the value an event can be generated to reset the counter. if the increment value in atinc is given in true nanoseconds, this value is also given in true nanoseconds. 44.3.36 timer period register (enet_atper) address: enet_atper is 400c_0000h base + 40ch offset = 400c_040ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r period w reset 0 0 1 1 1 0 1 1 1 0 0 1 1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 enet_atper field descriptions field description 310 period value for generating periodic events. each instance the timer reaches this value, the period event occurs and the timer restarts. if the increment value in atinc is given in true nanoseconds, this value is also given in true nanoseconds. the value should be initialized to 1,000,000,000 (1 x 10 9 ) to represent a timer wrap around of one second. the increment value set in atinc should be set to the true nanoseconds of the period of clock ts_clk, hence implementing a true 1 second counter. chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1167 44.3.37 timer correction register (enet_atcor) address: enet_atcor is 400c_0000h base + 410h offset = 400c_0410h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 cor w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enet_atcor field descriptions field description 31 reserved this read-only field is reserved and always has the value zero. 300 cor correction counter wrap-around value defines after how many timer clock cycles (ts_clk) the correction counter should be reset and trigger a correction increment on the timer. the amount of correction is defined in atinc[inc_corr]. a value of 0 disables the correction counter and no corrections occur. note: this value is given in clock cycles, not in nanoseconds as all other values. 44.3.38 time-stamping clock period register (enet_atinc) address: enet_atinc is 400c_0000h base + 414h offset = 400c_0414h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 inc_corr 0 inc w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enet_atinc field descriptions field description 3115 reserved this read-only field is reserved and always has the value zero. 148 inc_corr correction increment value this value is added every time the correction timer expires (every clock cycle given in atcor). a value smaller than inc slows the timer, while a value larger than inc speeds the timer. 7 reserved this read-only field is reserved and always has the value zero. 60 inc clock period of the timestamping clock (ts_clk) in nanoseconds the timer increments by this amount each clock cycle. for example, set to 10 for 100 mhz, 8 for 125 mhz, 5 for 200 mhz. note: for highest precision, use a value that is an integer fraction of the period set in atper. memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1168 freescale semiconductor, inc. 44.3.39 timestamp of last transmitted frame (enet_atstmp) address: enet_atstmp is 400c_0000h base + 418h offset = 400c_0418h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r timestamp w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enet_atstmp field descriptions field description 310 timestamp timestamp of the last frame transmitted by the core that had txbd[ts] set. this register is only valid when eir[ts_avail] is set. 44.3.40 timer global status register (enet_tgsr) address: enet_tgsr is 400c_0000h base + 604h offset = 400c_0604h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 tf3 tf2 tf1 tf0 w w1c w1c w1c w1c reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enet_tgsr field descriptions field description 314 reserved this read-only field is reserved and always has the value zero. 3 tf3 copy of timer flag for channel 3 0 timer flag for channel 3 is clear 1 timer flag for channel 3 is set 2 tf2 copy of timer flag for channel 2 0 timer flag for channel 2 is clear 1 timer flag for channel 2 is set 1 tf1 copy of timer flag for channel 1 table continues on the next page... chapter 44 10100-mbps ethernet mac enet 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 116 enet_tgsr field descriptions (continued) field description 0 timer flag for channel 1 is clear 1 timer flag for channel 1 is set 0 tf0 copy of timer flag for channel 0 0 timer flag for channel 0 is clear 1 timer flag for channel 0 is set 44.3.41 timer control status register (enet_tcsr n resses: r is h ase h oset h r is h ase h oset h r is h ase h oset h r is h ase h oset h it r reset it r f o r wc reset r n iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero f ier fla ets when inut cature or outut coare occurs his la is oule uere etween the oule cloc an cloc oains lear the la y writin a loic one to this it when it is set nut ature or outut oare has not occurre nut ature or outut oare has occurre ier interrut enale nterrut is isale nterrut is enale table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 1170 freescale semiconductor, inc. enet_tcsr n iel escritions continue fiel escrition o ier oe uatin the ier oe iel taes a ew cycles to reister since it is synchronie to the cloc he ersion o ier oe returne on a rea is ro the cloc oain hen chanin ier oe always isale the channel an rea this reister to eriy the channel is isale irst ier hannel is isale ier hannel is coniure or nut ature on risin ee ier hannel is coniure or nut ature on allin ee ier hannel is coniure or nut ature on oth ees ier hannel is coniure or outut oare sotware only ier hannel is coniure or outut oare tole outut on coare ier hannel is coniure or outut oare clear outut on coare ier hannel is coniure or outut oare set outut on coare resere ier hannel is coniure or outut oare clear outut on coare set outut on oerlow x ier hannel is coniure or outut oare set outut on coare clear outut on oerlow resere ier hannel is coniure or outut oare ulse outut low on coare or one cloc cycle ier hannel is coniure or outut oare ulse outut hih on coare or one cloc cycle resere his reaonly iel is resere an always has the alue ero r ier request nale request is isale request is enale ier oare ature reister r n resses: r is h ase h oset h r is h ase h oset h r is h ase h oset h r is h ase h oset h it r reset hater s thernet ufaily reerence anual re o freescale eiconuctor nc enet_tccr n iel escritions fiel escrition ier ature oare his reister is oule uere etween the oule cloc an cloc oains hen coniure or coare cloc oain uates with the alue in the oule cloc oain wheneer the ier hannel is irst enale an on each susequent coare rite to this reister with the irst coare alue eore enalin the ier hannel hen the ier hannel is enale write the secon coare alue either ieiately or at least eore the irst coare occurs ter each coare write the next coare alue eore the reious coare occurs an eore clearin the ier fla he coare occurs one cloc cycle ater the ounter increents ast the coare alue in the cloc oain the coare alue is less than the alue o the ounter when the ier hannel is irst enale then the coare oes not occur until ollowin the next oerlow o the ounter the coare alue is reater than the ounter when the ounter oerlows or the coare alue is less than the alue o the ounter ater the oerlow then the coare occurs one cloc cycle ollowin the oerlow hen coniure or ature the alue o the ounter is cature into the cloc oain an then uate into the oule cloc oain roie the ier fla is clear lways rea the cature alue eore clearin the ier fla tatistic ent ounters the following table shows the locations of the statistic event counters in the module's memory map. definitions of these registers can be found in ietf rfc 2819, remote network monitoring management information base . note all counters are 32-bit wide with the top 16 bits reserved/ ignored except for the following: ? rmon_t_octets ? ieee_t_octets_ok ? rmon_r_octets ? ieee_r_octets_ok table 44-54. statistic event counters memory map address offset from enet base address register 0x200 count of frames not counted correctly (rmon_t_drop). note: counter not implemented (read 0 always) as not applicable. 0x204 rmon tx packet count (rmon_t_packets) 0x208 rmon tx broadcast packets (rmon_t_bc_pkt) 0x20c rmon tx multicast packets (rmon_t_mc_pkt) table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 1172 freescale semiconductor, inc. table 44-54. statistic event counters memory map (continued) address offset from enet base address register 0x210 rmon tx packets w crc/align error (rmon_t_crc_align) 0x214 rmon tx packets < 64 bytes, good crc (rmon_t_undersize) 0x218 rmon tx packets > max_fl bytes, good crc (rmon_t_oversize) 0x21c rmon tx packets < 64 bytes, bad crc (rmon_t_frag) 0x220 rmon tx packets > max_fl bytes, bad crc (rmon_t_jab) 0x224 rmon tx collision count (rmon_t_col) 0x228 rmon tx 64 byte packets (rmon_t_p64) 0x22c rmon tx 65 to 127 byte packets (rmon_t_p65to127n) 0x230 rmon tx 128 to 255 byte packets (rmon_t_p128to255n) 0x234 rmon tx 256 to 511 byte packets (rmon_t_p256to511) 0x238 rmon tx 512 to 1023 byte packets (rmon_t_p512to1023) 0x23c rmon tx 1024 to 2047 byte packets (rmon_t_p1024to2047) 0x240 rmon tx packets w > 2048 bytes (rmon_t_p_gte2048) 0x244 rmon tx octets (rmon_t_octets) 0x248 count of frames not counted correctly (ieee_t_drop). note: counter not implemented (read 0 always) as not applicable. 0x24c frames transmitted ok (ieee_t_frame_ok) 0x250 frames transmitted with single collision (ieee_t_1col) 0x254 frames transmitted with multiple collisions (ieee_t_mcol) 0x258 frames transmitted after deferral delay (ieee_t_def) 0x25c frames transmitted with late collision (ieee_t_lcol) 0x260 frames transmitted with excessive collisions (ieee_t_excol) 0x264 frames transmitted with tx fifo underrun (ieee_t_macerr) 0x268 frames transmitted with carrier sense error (ieee_t_cserr) 0x26c frames transmitted with sqe error (ieee_t_sqe). note: counter not implemented (read 0 always) as no sqe information is available. 0x270 flow control pause frames transmitted (ieee_t_fdxfc) table continues on the next page... chapter 44 10100-mbps ethernet mac enet 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 117 table 44-54. statistic event counters memory map (continued) address offset from enet base address register 0x274 octet count for frames transmitted w/o error (ieee_t_octets_ok). note: counts total octets (includes header and fcs fields). 0x284 rmon rx packet count (rmon_r_packets) 0x288 rmon rx broadcast packets (rmon_r_bc_pkt) 0x28c rmon rx multicast packets (rmon_r_mc_pkt) 0x290 rmon rx packets w crc/align error (rmon_r_crc_align) 0x294 rmon rx packets < 64 bytes, good crc (rmon_r_undersize) 0x298 rmon rx packets > max_fl, good crc (rmon_r_oversize) 0x29c rmon rx packets < 64 bytes, bad crc (rmon_r_frag) 0x2a0 rmon rx packets > max_fl bytes, bad crc (rmon_r_jab) 0x2a4 reserved (rmon_r_resvd_0) 0x2a8 rmon rx 64 byte packets (rmon_r_p64) 0x2ac rmon rx 65 to 127 byte packets (rmon_r_p65to127) 0x2b0 rmon rx 128 to 255 byte packets (rmon_r_p128to255) 0x2b4 rmon rx 256 to 511 byte packets (rmon_r_p256to511) 0x2b8 rmon rx 512 to 1023 byte packets (rmon_r_p512to1023) 0x2bc rmon rx 1024 to 2047 byte packets (rmon_r_p1024to2047) 0x2c0 rmon rx packets w > 2048 bytes (rmon_r_p_gte2048) 0x2c4 rmon rx octets (rmon_r_octets) 0x2c8 count of frames not counted correctly (ieee_r_drop). note: counter increments if a frame with invalid/missing sfd character is detected and has been dropped. none of the other counters increments if this counter increments. 0x2cc frames received ok (ieee_r_frame_ok) 0x2d0 frames received with crc error (ieee_r_crc) 0x2d4 frames received with alignment error (ieee_r_align) 0x2d7 receive fifo overflow count (ieee_r_macerr) 0x2dc flow control pause frames received (ieee_r_fdxfc) table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 1174 freescale semiconductor, inc. table 44-54. statistic event counters memory map (continued) address offset from enet base address register 0x2e0 octet count for frames rcvd w/o error (ieee_r_octets_ok). counts total octets (includes header and fcs fields) 44.4 functional description the following sections describe functional details of the mac-net core. 44.4.1 ethernet mac frame formats the ieee 802.3 standard defines the ethernet frame format as follows: ? minimum length of 64 bytes ? maximum length of 1518 bytes, excluding the preamble and the sfd bytes an ethernet frame consists of the following fields: ? seven bytes preamble ? start frame delimiter (sfd) ? two address fields ? length or type field ? data field ? frame check sequence (crc value) frame check sequence (fcs) payload length frame length preamble 1 octet destination address source address length/type payload data 0?46 octets 4 octets pad 0?1500/9000 octets 2 octets 7 octets sfd 6 octets 6 octets figure 44-52. mac frame format overview chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1175 optionally, mac frames can be vlan-tagged with an additional four-byte field inserted between the mac source address and the type/length field. vlan tagging is defined by the ieee p802.1q specification. vlan-tagged frames have a maximum length of 1522 bytes, excluding the preamble and the sfd bytes. frame check sequence (fcs) payload length frame length preamble 1 octet destination address source address length/type payload data 4 octets pad 0?1500/9000 octets 2 octets 7 octets sfd 6 octets 6 octets 0?42 octets 2 octets 2 octets vlan tag (0x8100) vlan info figure 44-53. vlan-tagged mac frame format overview table 44-55. mac frame definition term description frame length defines the length, in octets, of the complete frame without preamble and sfd. a frame has a valid length if it contains at least 64 octets and does not exceed the programmed maximum length (typical 1518). payload length the length/type field indicates the length of the frame's payload section. the most significant byte is sent/received first. if the length/type field is set to a value less than 46, the payload is padded so that the minimum frame length requirement (64 bytes) is met. for vlan-tagged frames, a value less than 42 indicates a padded frame. if the length/type field is set to a value larger than the programmed frame maximum length (e.g. 1518) it is interpreted as a type field. destination and source address 48-bit mac addresses. the least significant byte is sent/received first and the first two least significant bits of the mac address distinguish mac frames as detailed in mac address check . note although the ieee specification defines a maximum frame length, the mac core provides the flexibility to program any value for the frame maximum length. 44.4.1.1 pause frames the receiving device generates a pause frame to indicate a congestion to the emitting device, which should stop sending data. functional description k60 sub-family reference manual, rev. 6, nov 2011 1176 freescale semiconductor, inc. pause frames are indicated by the length/type set to 0x8808. the two first bytes of a pause frame following the type, defines a 16-bit opcode field set to 0x0001 always. a 16- bit pause quanta is defined in the frame payload bytes 2 (p1) and 3 (p2) as defined in the following table. the p1 pause quanta byte is the most significant. table 44-56. pause frame format (values in hex) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 55 55 55 55 55 55 55 d5 01 80 c2 00 00 01 preamble sfd multicast destination address 15 16 17 18 19 20 21 22 23 24 25 26 27 ?68 00 00 00 00 00 00 88 08 00 01 hi lo 00 source address type opcode p1 p2 pad (42) 69 70 71 72 26 6b ae 0a crc-32 there is no payload length field found within a pause frame and a pause frame is always padded with 42 bytes (0x00). if a pause frame with a pause value greater zero (xoff condition) is received, the mac stops transmitting data as soon the current frame transfer is completed. the mac stops transmitting data for the value defined in pause quanta. one pause quanta fraction refers to 512 bit times. if a pause frame with a pause value of zero (xon condition) is received, the transmitter is allowed to send data immediately (see full duplex flow control operation for details). 44.4.1.2 magic packets a magic packet is a unicast, multicast, or broadcast packet, which carries a defined sequence in the payload section. magic packets are received and inspected only under specific conditions as described in magic packet detection . the defined sequence to decode a magic packet is formed with a synchronization stream (six consecutive 0xff bytes) followed by sequence of six consecutive unicast mac addresses of the node to be awakened. the sequence can be located anywhere in the magic packet payload and the magic packet is formed with standard ethernet header and optional padding and crc. chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1177 44.4.2 ip and higher layers frame format the following sections use the term datagram to describe the protocol specific data unit that is found within the payload section of its container entity. for example, an ip datagram specifies the payload section of an ethernet frame. a tcp datagram specifies the payload section within an ip datagram. 44.4.2.1 ethernet types ip datagrams are carried in the payload section of an ethernet frame. the ethernet frame type/length field discriminates several datagram types. the following table lists the types of interest: table 44-57. ethernet type value examples type description 0x8100 vlan-tagged frame. the actual type is found 4 octets later in the frame 0x0800 ip 0x0806 arp 0x86dd ipv6 44.4.2.2 ipv4 datagram format the following figure shows the ip version 4 (ipv4) header, which is located at the beginning of an ip datagram. it is organized in 32-bit words. the first byte sent/received is the leftmost byte of the first word (i.e. version/ihl field). the ip header can contain further options, which are always padded if necessary to guarantee the payload following the header is aligned to a 32-bit boundary. the ip header is followed by the payload immediately, which can contain further protocol headers (e.g., tcp or udp as indicated by the protocol field value). the complete ip datagram is transported in the payload section of an ethernet frame. table 44-58. ipv4 header format 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 version ihl tos length table continues on the next page... functional description 60 sub-family reference manual, rev. 6, nov 2011 1178 freescale semiconductor, inc. table 44-58. ipv4 header format (continued) fragment id flags fragment offset ttl protocol header checksum source address destination address options table 44-59. ipv4 header fields field name description version 4-bit ip version information. 0x4 for ipv4 frames. ihl 4-bit internet header length information. determines number of 32-bit words found within the ip header. if no options are present, the default value is 0x5. tos type of service/diffserv field length total length of the datagram in bytes, including all octets of header and payload fragment id, flags, fragment offset fields used for ip fragmentation ttl time-to-live. if zero, datagram must be discarded protocol protocol identifier of protocol that follows in the datagram header checksum checksum over all ip header fields source address source ip address destination address destination ip address 44.4.2.3 ipv6 datagram format the following figure shows the ip version 6 (ipv6) header, which is located at the beginning of an ip datagram. it is organized in 32-bit words and has a fixed length of ten words (40 bytes). the next header field identifies the type of the header to follow the ipv6 header. it is defined identical to the protocol identifier within ipv4 with new definitions for identifying extension headers, which can be inserted between the ipv6 header and the protocol header, shifting the protocol header accordingly. the accelerator currently only supports ipv6 without extension headers (i.e. next header identifies tcp, udp, or icmp protocol). the first byte sent/received is the leftmost byte of the first word (i.e. version/traffic class fields). chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1179 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 version traffic class flow label payload length next header hop limit source address destination address start of next header/payload figure 44-54. ipv6 header format table 44-60. ipv6 header fields field name description version 4-bit ip version information. 0x6 for all ipv6 frames traffic class 8-bit field defining the traffic class flow label 20-bit flow label identifying frames of the same flow payload length 16-bit length of the datagram payload in bytes. it includes all octets following the ipv6 header. next header identifies the header that follows the ipv6 header. this can be the protocol header or any ipv6 defined extension header. hop limit hop counter, decremented by one by each station that forwards the frame. if hop limit is 0 the frame must be discarded. source address 128-bit ipv6 source address destination address 128-bit ipv6 destination address 44.4.2.4 internet control message protocol (icmp) datagram format following the ip header, an internet control message protocol (icmp) datagram is found when the protocol identifier is 1. the icmp datagram has a four octet header followed by additional message data. table 44-61. icmp header format 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 type code checksum icmp message data table 44-62. ip header fields field name description type 8-bit type information table continues on the next page... functional description 60 sub-family reference manual, rev. 6, nov 2011 1180 freescale semiconductor, inc. table 44-62. ip header fields (continued) field name description code 8-bit code that is related to the message type checksum 16-bit ones complement checksum over the complete icmp datagram 44.4.2.5 user datagram protocol (udp) datagram format following the ip header, a user datagram protocol header is found when the protocol identifier is 17. following the udp header is the payload of the datagram. the header byte order follows the conventions given for the ip header above. table 44-63. udp header format 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 source port destination port length checksum table 44-64. udp header fields field name description source port source application port destination port destination application port length length of user data which follows immediately the header including the udp header. that is, the minimum value is 8. checksum checksum over the complete datagram and some ip header information 44.4.2.6 tcp datagram format following the ip header, a tcp header is found when the protocol identifier has a value of 6. the tcp payload immediately follows the tcp header. table 44-65. tcp header format 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 source port destination port table continues on the next page... chapter 44 10100-mbps ethernet mac enet 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1181 table 44-65. tcp header format (continued) sequence number acknowledgement number offset flags window checksum urgent pointer options table 44-66. tcp header fields field name description source port source application port destination port destination application port sequence number transmit sequence number ack. number receive sequence number offset data offset. number of 32-bit words within the tcp header. if no options, a value of 5. flags urg, ack, psh, rst, syn, fin flags window tcp receive window size information checksum checksum over the complete datagram (tcp header and data) and ip header information options additional 32-bit words for protocol options 44.4.3 ieee 1588 message formats the following sections describe the ieee 1588 message formats. 44.4.3.1 transport encapsulation the precision time protocol (ptp) datagrams are encapsulated in ethernet frames using the udp/ip transport mechanism, or optionally, with the newer 1588v2 directly in ethernet frames (layer 2). typically, multicast addresses are used to allow efficient distribution of the synchronization messages. 44.4.3.1.1 udp/ip the 1588 messages (v1 and v2) can be transported using udp/ip multicast messages. functional description k60 sub-family reference manual, rev. 6, nov 2011 1182 freescale semiconductor, inc. the following ip multicast groups are defined for ptp. the table also shows their respective mac layer multicast address mapping according to rfc 1112 (last three octets of ip follow the fixed value of 01-00-5e). table 44-67. udp/ip multicast domains name ip address mac address mapping defaultptpdomain 224.0.1.129 01-00-5e-00-01-81 alternateptpdomain1 224.0.1.130 01-00-5e-00-01-82 alternateptpdomain2 224.0.1.131 01-00-5e-00-01-83 alternateptpdomain3 224.0.1.132 01-00-5e-00-01-84 table 44-68. udp port numbers message type udp port note event 319 used for sync and delay_request messages general 320 all other messages (e.g., follow-up, delay-response) 44.4.3.1.2 native ethernet (ptpv2) in addition to using udp/ip frames, ieee 1588v2 defines a native ethernet frame format that uses ethertype = 0x88f7. the payload of the ethernet frame immediately contains the ptp datagram, starting with the ptpv2 header. besides others, version 2 adds a peer delay mechanism to allow delay measurements between individual point-to-point links along a path over multiple nodes. the following multicast domains are additionally defined in ptpv2. table 44-69. ptpv2 multicast domains name mac address normal messages 01-1b-19-00-00-00 peer delay messages 01-80-c2-00-00-0e 44.4.3.2 ptp header all ptp frames contain a common header, which determines the protocol version and the type of message, which defines the further content of the message. all multi-octet fields are transmitted in big-endian order (the most significant byte is transmitted/received first). chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1183 the version field's (versionptp) last four bits are at the same position (i.e. second byte) for ptpv1 and ptpv2 headers, allowing a correct identification by inspecting the first two bytes of the message. 44.4.3.2.1 ptpv1 header table 44-70. common ptpv1 message header offset octets bits 7 6 5 4 3 2 1 0 0 2 versionptp = 0x0001 2 2 versionnetwork 4 16 subdomain 20 1 messagetype 21 1 sourcecommunicationtechnology 22 6 sourceuuid 28 2 sourceportid 30 2 sequenceid 32 1 control 33 1 0x00 34 2 flags 36 4 reserved the type of message is encoded in the messagetype and control fields as follows: table 44-71. ptpv1 message type identification messagetype control message name message 0x01 0x0 sync event message 0x01 0x1 delay_req event message 0x02 0x2 follow_up general message 0x02 0x3 delay_resp general message 0x02 0x4 management general message other other reserved the field sequenceid is used to non-ambiguously identify a message. functional description k60 sub-family reference manual, rev. 6, nov 2011 1184 freescale semiconductor, inc. 44.4.3.2.2 ptpv2 header table 44-72. common ptpv2 message header offset octets bits 7 6 5 4 3 2 1 0 0 1 transportspecific messageid 1 1 reserved versionptp = 0x2 2 2 messagelength 4 1 domainnumber 5 1 reserved 6 2 flags 8 8 correctionfield 16 4 reserved 20 10 sourceportidentity 30 2 sequenceid 32 1 control 33 1 logmeanmessageinterval the type of message is encoded in the field messageid as follows: table 44-73. ptpv2 message type identification messageid message name message 0x0 sync event message 0x1 delay_req event message 0x2 path_delay_req event message 0x3 path_delay_resp event message 0x4?0x7 reserved 0x8 follow_up general message 0x9 delay_resp general message 0xa path_delay_follow_up general message 0xb announce general message 0xc signaling general message 0xd management general message the ptpv2 flags field contains further details on the type of message, especially if one- step or two-step implementations are used. the flags field consists of two octets with the following meanings for the bits. reserved bits are cleared (false). chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1185 table 44-74. ptpv2 message flags field definitions bit name description 0 alternate_master see ieee 1588 clause 17.4 1 two_step 1 two-step clock 0 one-step clock 2 unicast 1 transport layer address uses a unicast destination address 0 multicast is used 3 reserved 4 reserved 5 profile specific 6 profile specific 7 reserved 44.4.4 mac receive the mac receive engine performs the following tasks: ? check frame framing ? remove frame preamble and frame sfd field ? frame discarding based on frame destination address field ? terminate pause frames ? check frame length ? remove payload padding if it exists ? calculate and verify crc-32 ? write received frames in the core receive fifo if the mac is programmed to operate in half duplex mode, the mac performs the following additional action: ? check if the frame is received with a collision functional description k60 sub-family reference manual, rev. 6, nov 2011 1186 freescale semiconductor, inc. discard discard discard discard detect preamble collision compare destination address with local/multicast/broadcast discriminate length/type information receive payload remove padding verify crc verify frame length write data fifo and frame status half duplex only figure 44-55. mac receive flow 44.4.4.1 collision detection in half duplex mode if the packet is received with a collision detected during reception of the first 64 bytes, the packet is discarded (if frame size was less than ~14 octets) or transmitted to the user application with an error and rxbd[ce] set. 44.4.4.2 preamble processing the ieee 802.3 standard allows a maximum size of 56 bits (seven bytes) for the preamble, while the mac core allows any arbitrary preamble length. the mac core checks for the start frame delimiter (sfd) byte. if the next byte of the preamble, which is different from 0x55, is not 0xd5, the frame is discarded. although the ieee specification specifies that frames should be separated by at least 96 bits (inter-packet gap), the mac core is designed to accept frames only separated by 64 mii (10/100 mbps operation) bits. the mac core removes the preamble and sfd bytes. chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1187 44.4.4.3 mac address check the destination address bit 0 differentiates between multicast and unicast addresses. ? if bit 0 is 0, the mac address is an individual (unicast) address ? if bit 0 is 1, the mac address defines a group (multicast) address ? if all 48 bits of the mac address are set, it indicates a broadcast address 44.4.4.3.1 unicast address check if a unicast address is received, the destination mac address is compared to the node mac address programmed by the host in the paddr1/2 registers. if the destination address matches any of the programmed mac addresses, the frame is accepted. if promiscuous mode is enabled (rcr[prom] = 1) no address checking is performed and all unicast frames are accepted. 44.4.4.3.2 multicast and unicast address resolution the hash table algorithm used in the group and individual hash filtering operates as follows. the 48-bit destination address is mapped into one of 64 bits, represented by 64 bits in enet n _gaur/galr (group address hash match) or enet n _iaur/ialr (individual address hash match). this mapping is performed by passing the 48-bit address through the on-chip 32-bit crc generator and selecting the six most significant bits of the crc-encoded result to generate a number between 0 and 63. the msb of the crc result selects enet n _gaur (msb = 1) or enet n _galr (msb = 0). the five lsbs of the hash result select the bit within the selected register. if the crc generator selects a bit set in the hash table, the frame is accepted; else, it is rejected. for example, if eight group addresses are stored in the hash table and random group addresses are received, the hash table prevents roughly 56/64 (or 87.5%) of the group address frames from reaching memory. those that do reach memory must be further filtered by the processor to determine if they truly contain one of the eight desired addresses. the effectiveness of the hash table declines as the number of addresses increases. the user must initialize the hash table registers. use this crc32 polynomial to compute the hash: ? fcs(x) = x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x 1 + 1 functional description k60 sub-family reference manual, rev. 6, nov 2011 1188 freescale semiconductor, inc. if promiscuous mode is enabled (enet n _rcr[prom] = 1) all unicast and multicast frames are accepted regardless of enet n _gaur/galr and enet n _iaur/ialr settings. 44.4.4.3.3 broadcast address reject all broadcast frames are accepted if bc_rej is cleared or enet n _rcr[prom] is set. if prom is cleared when enet n _rcr[bc_rej] is set, all broadcast frames are rejected. table 44-75. broadcast address reject programming prom bc_rej broadcast frames 0 0 accepted 0 1 rejected 1 0 accepted 1 1 accepted 44.4.4.3.4 miss-bit implementation for higher layer filtering purposes, rxbd[m] indicates an address miss when the mac operates in promiscuous mode and accepted a frame that would otherwise be rejected. if a group/individual hash or exact match does not occur and promiscuous mode is enabled (rcr[prom] = 1), the frame is accepted and the m bit is set in the buffer descriptor; otherwise, the frame is rejected. this means the status bit is set in any of the following conditions during promiscuous mode: ? a broadcast frame is received when bc_rej is set. ? a unicast is received that does not match either of: ? node address (palr[paddr1] and paur[paddr2]) ? hash table for unicast (iaur[iaddr1] and ialr[iaddr2]) ? a multicast is received that does not match the gaur[gaddr1] and galr[gaddr2] hash table entries chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1189 44.4.4.4 frame length/type verification: payload length check if the length/type is less than 0x600 and nlc is set, the mac checks the payload length and reports any error in the frame status word and interrupt bit plr. if the length/type is greater than or equal to 0x600, the mac interprets the field as a type and no payload length check is performed. the length check is performed on vlan and stacked vlan frames. if a padded frame is received, no length check can be performed due to the extended frame payload (i.e. padded frames can never have a payload length error). 44.4.4.5 frame length/type verification: frame length check when the receive frame length exceeds max_fl bytes, the babr interrupt is generated and the rxbd[lg] bit is set. the frame is not truncated unless the frame length exceeds the value programmed in enet n _ftrl[trunc_fl]. if the frame is truncated, rxbd[tr] is set. in addition, a truncated frame always has the crc error indication set (rxbd[cr]). 44.4.4.6 vlan frames processing vlan frames have a length/type field set to 0x8100 immediately followed by a 16-bit vlan control information field. vlan-tagged frames are received as normal frames (the vlan tag is not interpreted by the mac function) and are completely (including the vlan tag) pushed to the user application. if the length/type field of the vlan-tagged frame, which is found four octets later in the frame, is less than 42, the padding is removed. in addition, the frame status word (rxbd[no]) indicates that the current frame is vlan tagged. 44.4.4.7 pause frame termination the receive engine terminates pause frames and they are not transferred to the receive fifo. the quanta is extracted and sent to the mac transmit path via a small internal clock rate decoupling asynchronous fifo. the quanta is written only if a correct crc and frame length are detected by the control state machine. if not, the quanta is discarded and the mac transmit path is not paused. functional description k60 sub-family reference manual, rev. 6, nov 2011 1190 freescale semiconductor, inc. good pause frames are ignored if enet n _rcr[fce] is cleared and are forwarded to the client interface when enet n _rcr[paufwd] is set. 44.4.4.8 crc check the crc-32 field is checked and forwarded to the core fifo interface if enet n _rcr[crcfwd] is cleared and enet n _rcr[paden] is set. when crcfwd is set (regardless of paden), the crc-32 field is checked and terminated (not transmitted to the fifo). the crc polynomial, as specified in the 802.3 standard, is: ? fcs(x) = x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x 1 + 1 the 32 bits of the crc value are placed in the frame check sequence (fcs) field with the x 31 term as right-most bit of the first octet. the crc bits are thus received in the following order: x 31 , x 30 ,..., x 1 , x 0 . if a crc error is detected, the frame is marked invalid and rxbd[cr] is set. 44.4.4.9 frame padding removal when a frame is received with a payload length field set to less than 46 (42 for vlan- tagged frames and 38 for frames with stacked vlans), the zero padding can be removed before the frame is written into the data fifo depending on the setting of enet n _rcr[paden]. note if a frame is received with excess padding (i.e. the length field is set as mentioned above, but the frame has more than 64 octets) and padding removal is enabled, the padding is removed as normal and no error is reported if the frame is otherwise correct (e.g. good crc, less than maximum length, and no other error). 44.4.5 mac transmit frame transmission starts when the transmit fifo holds enough data. once a transfer starts, the mac transmit function performs the following tasks: chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1191 ? generates preamble and sfd field before frame transmission ? generates xoff pause frames if the receive fifo reports a congestion or if enet n _tcr[tfc_pause] is set with enet n _opd[pause_dur] set to a non- zero value ? generates xon pause frames if the receive fifo congestion condition is cleared or if tfc_pause is set with pause_dur cleared ? suspends ethernet frame transfer (xoff) if a non-zero pause quanta is received from the mac receive path ? adds padding to the frame if required ? calculates and appends crc-32 to the transmitted frame ? send frame with correct inter-packet gap (ipg) (deferring) when the mac is configured to operate in half duplex mode, the following additional tasks are performed: ? collision detection ? frame retransmit after back-off timer expires send preamble send destination address send local mac address send payload (overwrite fifo data) send padding (if necessary) send crc figure 44-56. frame transmit overview 44.4.5.1 frame payload padding the ieee specification defines a minimum frame length of 64 bytes. functional description k60 sub-family reference manual, rev. 6, nov 2011 1192 freescale semiconductor, inc. if the frame sent to the mac from the user application has a size smaller than 60 bytes, the mac automatically adds padding bytes (0x00) to comply with the ethernet minimum frame length specification. transmit padding is always performed and cannot be disabled. if the mac is not allowed to append a crc (txbd[tc] = 1), the user application is responsible for providing frames with a minimum length of 64 octets. 44.4.5.2 mac address insertion on each frame received from the core transmit fifo interface, the source mac address is either: ? replaced by the address programmed in the paddr1/2 fields (enet n _tcr[addins] = 1) ? transparently forwarded to the ethernet line (enet n _tcr[addins] = 0) 44.4.5.3 crc-32 generation the crc-32 field is optionally generated and appended at the end of a frame. the crc polynomial, as specified in the 802.3 standard, is: ? fcs(x) = x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x 1 + 1 the 32 bits of the crc value are placed in the fcs field so that the x 31 term is the right- most bit of the first octet. the crc bits are thus transmitted in the following order: x 31 , x 30 ,..., x 1 , x 0 . 44.4.5.4 inter-packet gap in full duplex mode, after frame transmission and before transmission of a new frame, an inter-packet gap (programmed in enet n _tipg) is maintained. the minimum ipg can be programmed between 8 and 27 byte-times (64 and 216 bit-times). in half duplex mode, the core constantly monitors the line. actual transmission of the data onto the network occurs only if it has been idle for a 96-bit time period and any back-off time requirements have been satisfied. in accordance with the standard, the core begins to measure the ipg from mii_crs de-assertion. chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1193 44.4.5.5 collision detection and handling ? half duplex operation only a collision occurs on a half-duplex network when concurrent transmissions from two or more nodes take place. during transmission, the core monitors the line condition and detects a collision when the phy device asserts mii_col. when the core detects a collision while transmitting, it stops transmission of the data and transmits a 32-bit jam pattern. if the collision is detected during the preamble or the sfd transmission, the jam pattern is transmitted after completing the sfd, which results in a minimum 96-bit fragment. the jam pattern is a fixed pattern that is not compared to the actual frame crc and has a very low probability (0.532) of having a jam pattern identical to the crc. if a collision occurs before transmission of 64 bytes (including preamble and sfd), the mac core waits for the back-off period and retransmits the packet data (stored in a 64- byte re-transmit buffer) already sent on the line. the backoff period is generated from a pseudo-random process (truncated binary exponential backoff). if a collision occurs after transmission of 64 bytes (including preamble and sfd), the mac discards the remainder of the frame, optionally sets the lc interrupt bit, and sets txbd[lce]. buffer retransmit 64x8 buffer transmit fifo interface retransmit control read address write address frame discard period backoff control mac transmit datapath mac transmit phy control mac tx engine enable phy interface mac fifo figure 44-57. packet re-transmit overview functional description k60 sub-family reference manual, rev. 6, nov 2011 1194 freescale semiconductor, inc. the back-off time is represented by an integer multiple of slot times (one slot is equal to a 512-bit time period). the number of the delay slot times, before the n th re-transmission attempt, is chosen as a uniformly-distributed random integer in the range: ? 0 < r < 2 k ? k = min( n , n); where n is the number of retransmissions and n = 10 for example, after the first collision, the backoff period is 0 or 1 slot time. if a collision occurs on the first retransmission, the backoff period is 0, 1, 2, or 3 and so on. the maximum backoff time (in 512-bit time slots) is limited by n = 10 as specified in the ieee 802.3 standard. if a collision occurs after 16 consecutive retransmissions, the core reports an excessive collision condition (enet n _eir[rl] interrupt bit and txbd[ee]) and discards the current packet from the fifo. in networks violating the standard requirements, a collision may occur after transmission of the first 64 bytes. in this case, the core stops the current packet transmission and discards the rest of the packet from the transmit fifo. the core resumes transmission with the next packet available in the core transmit fifo. 44.4.6 full duplex flow control operation three conditions are handled by the core's flow control engine: ? remote device congestion the remote device connected to the same ethernet segment as the core reports a congestion requesting the core to stop sending data ? core fifo congestion when the core's receive fifo reaches a user- programmable threshold (rx section empty), the core sends a pause frame back to the remote device requesting the data transfer to stop ? local device congestion any device connected to the core can request (typically, via the host processor) the remote device to stop transmitting data 44.4.6.1 remote device congestion when the mac transmit control gets a valid pause quanta from the receive path and if enet n _rcr[fce] is set, the mac transmit logic: ? completes the transfer of the current frame chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1195 ? stops sending data for the amount of time specified by the pause quanta in 512 bit time increments ? sets enet n _tcr[rfc_pause] frame transfer resumes when the time specified by the quanta expireds and if no new quanta value is received or if a new pause frame with a quanta value set to 0x0000 is received. the mac also resets rfc_pause to zero. if enet n _rcr[fce] cleared, the mac ignores received pause frames. optionally and independent of enet n _rcr[fce], pause frames are forwarded to the client interface if paufwd is set. 44.4.6.2 local device/fifo congestion the mac transmit engine generates pause frames when the local receive fifo is not able to receive more than a pre-defined number of words (fifo programmable threshold) or when pause frame generation is requested by the local host processor. ? to generate a pause frame, the host processor sets enet n _tcr[tfc_pause]. a single pause frame is generated when the current frame transfer is completed and tfc_pause is automatically cleared. optionally, an interrupt is generated. ? a xoff pause frame is generated when the receive fifo asserts its section empty flag (internal). a xoff pause frame is generated automatically, when the current frame transfer completes. ? a xon pause frame is generated when the receive fifo deasserts its section empty flag (internal). a xon pause frame is generated automatically, when the current frame transfer completes. when a xoff pause frame is generated, the pause quanta (payload byte p1 and p2) is filled with the value programmed in enet n _opd[pause_dur]. functional description k60 sub-family reference manual, rev. 6, nov 2011 1196 freescale semiconductor, inc. pause frame generation pause_dur from ethernet line programmable threshold to ethernet line tfc_pause figure 44-58. pause frame generation overview note although the flow control mechanism should prevent any fifo overflow on the mac core receive path, the core receive fifo is protected. when an overflow is detected on the receive fifo, the current frame is truncated with an error indication set in the frame status word. the frame should subsequently be discarded by the user application. 44.4.7 magic packet detection magic packet detection wakes a node that is put is power-down mode by the node management agent. magic packet detection is supported only if the mac is configured in sleep mode. 44.4.7.1 sleep mode to put the mac in sleep mode, set enet n _ecr[sleep]. at the same time enet n _ecr[magicen] should be set to enable magic packet detection. in addition, when the processor is in stop mode, sleep mode is entered, without affecting the enet n _ecr register bits. when the core is in sleep mode: ? the mac transmit logic is disabled chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1197 ? the core fifo receive/transmit functions are disabled ? the mac receive logic is kept in normal mode, but it ignores all traffic from the line except magic packets. they are detected so that a remote agent can wake the node. 44.4.7.2 magic packet detection the core is designed to detect magic packets (see magic packets ) with the destination address set to: ? any multicast address ? the broadcast address ? the unicast address programmed in paddr1/2 when a magic packet is detected, eir[wakeup] is set and none of the statistic registers are incremented. 44.4.7.3 wake-up when a magic packet is detected, indicated by enet n _eir[wakeup], enet n _ecr[sleep] should be cleared to resume normal operation of the mac. clearing the sleep bit automatically masks enet n _ecr[magicen], disabling magic packet detection. 44.4.8 ip accelerator functions the following sections describe the ip accelerator functions. 44.4.8.1 checksum calculation the ip and icmp, tcp, udp checksums are calculated with one's complement arithmetic summing up 16-bit values. functional description k60 sub-family reference manual, rev. 6, nov 2011 1198 freescale semiconductor, inc. ? for icmp the checksum is calculated over the complete icmp datagram (i.e. without ip header). ? for tcp and udp the checksums contain the header and data sections and values from the ip header, which can be seen as a pseudo header that is not actually present in the datastream. table 44-76. ipv4 pseudo header for checksum calculation 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 source address destination address zero protocol tcp/udp length table 44-77. ipv6 pseudo header for checksum calculation 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 source address destination address tcp/udp length zero next header the tcp/udp length value is the length of the tcp or udp datagram, which is equal to the payload of an ip datagram. it is derived by subtracting the ip header length from the complete ip datagram length that is given in the ip header (ipv4) or directly taken from the ip header (ipv6). the protocol field is the corresponding value from the ip header and zero is filled with zeroes. for ipv6 the complete 128-bit addresses are considered. the next header value identifies the upper layer protocol (tcp or udp) and may differ from the ipv6 header's actual next header value if extension headers are inserted before the protocol header. the checksum calculation uses 16-bit words in network byte order: the first byte sent/ received is the msb, and the second byte sent/received is the lsb of the 16-bit value to add to the checksum. if the frame ends on an odd number of bytes, a zero byte is appended for checksum calculation only (not actually transmitted). 44.4.8.2 additional padding processing according to ieee 802.3, any ethernet frame must have a minimum length of 64 octets. chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1199 the mac usually removes padding on receive when a frame with length information is received. as ip frames have a type value instead of length, the mac does not remove padding for short ip frames, as it is not aware of the frame contents. the ip accelerator function can be configured to remove the ethernet padding bytes that might follow the ip datagram. on transmit, the mac automatically adds padding as necessary to fill any frame to a 64- byte length. 44.4.8.3 32-bit ethernet payload alignment the data fifos allow inserting two additional arbitrary bytes in front of a frame. this extends the 14-byte ethernet header to a 16-byte header, which leads to alignment of the ethernet payload, following the ethernet header, on a 32-bit boundary. this function can be enabled for transmit and receive independently with the corresponding shift16 bits in the enet n _tacc and enet n _racc registers. when enabled, the valid frame data is arranged as shown in this table. table 44-78. 64-bit interface data structure with shift16 enabled 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 any value any value byte 13 byte 12 byte 11 byte 10 byte 9 byte 8 byte 7 byte 6 ... 44.4.8.3.1 receive processing when enet n _racc[shift16] is set, each frame is received with two additional bytes in front of the frame. the user application must ignore these first two bytes and find the first byte of the frame in bits 23C16 of the first word from the rx fifo. note shift16 must be set during initialization and kept set during the complete operation, as it influences the fifo write behavior. functional description k60 sub-family reference manual, rev. 6, nov 2011 1200 freescale semiconductor, inc. 44.4.8.3.2 transmit processing when enet n _tacc[shift16] is set, the first two bytes of the first word written (bits 15C0) are discarded immediately by the fifo write logic. the shift16 bit can be enabled/disabled for each frame individually if required, but can be changed only between frames. 44.4.8.4 received frame discard as the receive fifo must be operated in store and forward mode (enet n _rsfl cleared), received frames can be discarded based on the following errors: ? the mac function receives the frame with an error: ? the frame has an invalid payload length ? frame length is greater than max_fl ? frame received with a crc-32 error ? frame truncated due to receive fifo overflow ? frame is corrupted as phy signaled an error (mii_rx_err asserted during reception) ? an ip frame is detected and the ip header checksum is wrong ? an ip frame with a valid ip header and a valid ip header checksum is detected, the protocol is known but the protocol specific checksum is wrong if one of the errors occurs and the ip accelerator function is configured to discard frames (enet n _racc), the frame is automatically discarded. statistics are maintained normally and are not affected by this discard function. 44.4.8.5 ipv4 fragments when an ip (ipv4) fragment frame is received only the ip header is inspected and its checksum verified. 32-bit alignment operates on fragments as on normal ip frames, as specified above. the ip fragment frame payload is not inspected for any protocol headers. as such, a protocol header would only exist in the very first fragment. to assist in protocol-specific checksum verification, the one's-complement sum is calculated on the ip payload (all bytes following the ip header) and provided with the frame status word. chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1201 the frame fragment status bit, rxbd[frag], is set to indicate a fragment reception and the one's-complement sum of the ip payload is available in rxbd[payload checksum]. note the application software can take advantage of the payload checksum delivered with the frame's status word to calculate the protocol-specific checksum of the datagram after all fragments have been received and reassembled. for example, if a tcp payload is delivered by multiple ip fragments, the application software can calculate the pseudo-header checksum value from the first fragment and add the payload checksums delivered with the status for all fragments to verify the tcp datagram checksum. 44.4.8.6 ipv6 support the following sections describe the ipv6 support. 44.4.8.6.1 receive processing an ethernet frame of type 0x86dd identifies an ip version 6 frame (ipv6) frame. if an ipv6 frame is received, the first ip header is inspected (first ten words) which is available in every ipv6 frame. if the receive shift16 function is enabled, the ip header is aligned on a 32-bit boundary allowing more efficient processing (see 32-bit ethernet payload alignment ). for tcp and udp datagrams the pseudo-header checksum calculation is performed and verified. to assist in protocol-specific checksum verification, the one's-complement sum is always calculated on the ip payload (all bytes following the ip header) and provided with the frame status word. for example, if extension headers were present, their sums can be subtracted in software from the checksum to isolate the tcp/udp datagram checksum, if required. 44.4.8.6.2 transmit processing for ipv6 transmission the shift16 function is supported to process 32-bit aligned datagrams. ipv6 has no ip header checksum; therefore, the ip checksum insertion configuration is ignored. functional description k60 sub-family reference manual, rev. 6, nov 2011 1202 freescale semiconductor, inc. the protocol checksum is inserted only if the next header of the ip header is a known protocol (tcp, udp, or icmp). if a known protocol is detected, the checksum over all bytes following the ip header is calculated and inserted in the correct position. the pseudo-header checksum calculation is performed for tcp and udp datagrams accordingly. 44.4.9 resets and stop controls the following sections describe the resets and stop controls. 44.4.9.1 hardware reset to reset the ethernet module, set enet n _ecr[reset]. 44.4.9.2 soft reset when enet n _ecr[ether_en] is cleared during operation, the following occurs: ? dma, buffer descriptor, and fifo control logic are reset, including the buffer descriptor and fifo pointers ? a currently ongoing transmit is terminated by asserting mii_txer to the phy ? a currently ongoing transmit fifo write from the application is terminated by stopping the write to the fifo, and all further data from the application is ignored. all subsequent writes are ignored until reenabled. ? a currently ongoing receive fifo read is terminated. the rxbd has arbitrary values in this case. 44.4.9.3 hardware freeze when the processor enters debug mode and ecr[dbgen] is set , the mac enters a freeze state where it stops all transmit and receive activities gracefully. the following happens when the mac enters hardware freeze: ? a currently ongoing receive transaction on the receive application interface is completed as normal. no further frames are read from the fifo. chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1203 ? a currently ongoing transmit transaction on the transmit application interface is completed as normal (i.e. until writing end-of-packet (eop)). ? a currently ongoing mii frame receive is completed normally. after that, no further frames are accepted from the mii. ? a currently ongoing mii frame transmit is completed normally. after that, no further frames are transmitted. 44.4.9.4 graceful stop during a graceful stop any currently ongoing transactions are completed normally and no further frames are accepted. the mac can resume from a graceful stop without the need for a reset (e.g. clearing ether_en is not required). the following conditions lead to a graceful stop of the mac transmit or receive datapaths. 44.4.9.4.1 graceful transmit stop (gts) when gracefully stopped, the mac is no longer reading frame data from the transmit fifo and has completed any ongoing transmission. in any of the following conditions, the transmit datapath stops after an ongoing frame transmission has been completed normally. ? enet n _tcr[gts] is set by software ? enet n _tcr[tfc_pause] is set by software requesting a pause frame transmission. the status (and register bit) is cleared after the pause frame has been sent. ? a pause frame was received stopping the transmitter. the stopped situation is terminated when the pause timer expires or a pause frame with zero quanta is received. ? mac is placed in sleep mode by software or the processor entering stop mode (see sleep mode ). ? the mac is in hardware freeze mode when the transmitter has reached its stopped state, the following events occur: functional description k60 sub-family reference manual, rev. 6, nov 2011 1204 freescale semiconductor, inc. ? the gra interrupt is asserted, when transitioned into stopped ? in hardware freeze mode, the gra interrupt does not wait for the application write completion and asserts when the transmit state machine (line side of tx fifo) reaches its stopped state. 44.4.9.4.2 graceful receive stop (grs) when gracefully stopped, the mac is no longer writing frames into the receive fifo. the receive datapath stops after any ongoing frame reception has been completed normally, if any of the following conditions occur: ? mac is placed in sleep mode (by software or the processor is in stop mode). the mac continues to receive frames and hunt for magic packets if enabled (see magic packet detection ). however, no frames are written into the receive fifo, and therefore are not forwarded to the application. ? the mac is in hardware freeze mode. the mac does not accept any frames from the mii. when the receive datapath is stopped the following events occur: ? if the rx is in the stopped state, rcr[grs] is set ? the gra interrupt is asserted when the transmitter and receiver are stopped ? any ongoing receive transaction to the application (rx fifo read) continues normally until the frame is completed (end of packet (eop)). after this, the following occurs: ? when sleep mode is active, all further frames are discarded, flushing the rx fifo ? in hardware freeze mode, no further frames are delivered to the application and they stay in the receive fifo. note the assertion of grs does not wait for an ongoing transaction on the application side of the fifo (fifo read). 44.4.9.4.3 graceful stop interrupt (gra) the graceful stopped interrupt (gra) is asserted for the following conditions: chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1205 ? in sleep mode, the interrupt asserts only after both tx and rx datapaths are stopped ? in hardware freeze mode, the interrupt asserts only after both tx and rx datapaths are stopped ? the mac transmit datapath is stopped for any other condition (gts, tfc_pause, pause received) the gra interrupt is triggered only once when the stopped state is entered. if the interrupt is cleared while the stop condition persists, no further interrupt is triggered. 44.4.10 ieee 1588 functions to allow for ieee 1588 or similar time synchronization protocol implementations, the mac is combined with a time-stamping module to support precise time stamping of incoming and outgoing frames. set enet n _ecr[1588en] to enable 1588 support. adjustable timer module events generator user application controldata 10/100 mac mac with 1588 phy control/status frame data 1pps control/status timing figure 44-59. ieee 1588 functions overview 44.4.10.1 adjustable timer module the adjustable timer module (tsm) implements the free running counter (frc), which generates the timestamps. the frc operates with the time-stamping clock, which can be set to any value depending on your system requirements. however, choose a period which is an integer value (e.g. 5ns, 6ns, 8ns) to implement a precise timer. functional description k60 sub-family reference manual, rev. 6, nov 2011 1206 freescale semiconductor, inc. through dedicated correction logic, the timer can be adjusted to allow synchronization to a remote master and provide a synchronized timing reference to the local system. the timer can be configured to cause an interrupt after a fixed time period to allow synchronization of software timers or perform other synchronized system functions. the timer is usually used to implement a period of one second; hence, its value ranges from 0 to (1 10 9 )-1. the period event can trigger an interrupt and software can maintain the seconds and hours time values as necessary. 44.4.10.1.1 adjustable timer implementation the adjustable timer consists of a programmable counter/accumulator and a correction counter. the periods of both counters and its increment rate are freely configurable allowing very fine tuning of the timer. mod counter correction counter [inc_corr] [inc] [slave] adjustable timer external free-running counter enet_atper enet_atcor enet_atcr enet_atinc enet_atinc to mac figure 44-60. adjustable timer implementation detail the counter produces the current time. during each time-stamping clock cycle a constant value is added to the current time as programmed in enet n _atinc. the value depends on the chosen time-stamping clock frequency. for example, if it operates at 125 mhz setting the increment to eight represents 8 ns. the period, configured in enet n _atper, defines the modulo when the counter wraps. in a typical implementation the period is set to 1 10 9 so the counter wraps every second, and hence all timestamps represent the absolute nanoseconds within the one second period. when the period is reached, the counter wraps to start again respecting the period modulo. this means it does not necessarily start from zero, but instead the counter is loaded with the value (current + inc C(1 10 9 )), assuming the period is set to 1 10 9 . chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1207 the correction counter operates fully independently and increments by one with each time-stamping clock cycle. when it reaches the value configured in enet n _atcor, it restarts and instructs the timer once to increment by the correction value, instead of the normal value. the normal and correction increments are configured in enet n _atinc. to speed up the timer, set the correction increment more than the normal increment value. to slow down the timer, set the correction increment less than the normal increment value. the correction counter only defines the distance of the corrective actions, not the amount. this allows very fine corrections and low jitter (in the range of 1 ns) independent of the chosen clock frequency. by enabling slave mode (enet n _atcr[slave] = 1) the timer is ignored and the current time is externally provided from one of the external modules. see the chip configuration details for which clock source is used. this is useful if multiple modules within the system must operate from a single timer. when slave mode is enabled, you still must set enet n _atinc[inc] to the value of the master, since it is used for internal comparisons. 44.4.10.2 transmit timestamping only 1588 event frames need to be time-stamped on transmit. the client application (e.g. the mac driver) should detect 1588 event frames and set txbd[ts] together with the frame. if txbd[ts] is set, the mac records the timestamp for the frame in enet n _atstmp. enet n _eir[ts_avail] is set to indicate that a new timestamp is available. software implements a handshaking procedure by setting txbd[ts] when it transmits the frame it needs a timestamp for and then waits for enet n _eir[ts_avail] to know when the timestamp is available. it then can read the timestamp from enet n _atstmp. this is done for all event frames. other frames do not use txbd[ts] and, therefore, do not interfere with the timestamp capture. 44.4.10.3 receive timestamping when a frame is received, the mac latches the value of the timer when the frame's sfd (start of frame delimiter) field is detected and provides the captured timestamp on rxbd[1588 timestamp]. this is done for all received frames. functional description k60 sub-family reference manual, rev. 6, nov 2011 1208 freescale semiconductor, inc. 44.4.10.4 time synchronization the adjustable timer module is available to synchronize the local clock of a node to a remote master. it implements a free running 32-bit counter, and also contains an additional correction counter. the correction counter increases or decreases the rate of the free running counter, enabling very fine granular changes of the timer for synchronization, yet adding only very low jitter when performing corrections. the application software implements, in a slave scenario, the required control algorithm setting the correction to compensate for local oscillator drifts and locking the timer to the remote master clock on the network. the timer and all timestamp-related information should be configured to show the true nanoseconds value of a second (i.e. the timer is configured to have a period of one second). hence, the values range from 0 to (1 10 9 )-1. in this application, the seconds counter is implemented in software using an interrupt function that is executed when the nanoseconds counter wraps at 1 10 9 . 44.4.11 fifo thresholds the core fifo thresholds are fully programmable to dynamically change the fifo operation. for example, store and forward transfer can be enabled by a simple change in the fifo threshold registers. the thresholds are defined in 64-bit words. chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1209 44.4.11.1 receive fifo four programmable thresholds are available, which can be set to any value to control the core operation as follows. table 44-79. receive fifo thresholds definition register description enet n _rsf rx_sectin_ fu when the fif level reaches the enet n _rsf value, the mac status signal is asserted to indicate that data is available in the receive fif cut-through operation. nce asserted, if the fif empties below the threshold set with enet n _raem and if the end-of-frame is not yet stored in the fif, the status signal is deasserted again. if a frame has a size smaller than the threshold i.e. an end-of-frame is available for the frame, the status is also asserted. to enable store and forward on the receive path, clear enet n _rsf. the mac status signal is asserted only when a complete frame is stored in the receive fif. when programming a non-zero value to enet n _rsf cut-through operation it should be greater than enet n _raem. enet n _raem rx_amst_e mpt when the fif level reaches the enet n _raem value, and the end-of-frame has not been received, the core receive read control stops the fif read and subseuently stops transferring data to the mac client application. it continues to deliver the frame, if again more data than the threshold or the end-of-frame is available in the fif. set enet n _raem to a minimum of six. enet n _raf rx_amst_f u when the fif level comes close to the maximum, so that there is no more space for at least enet n _raf number of words, the mac control logic stops writing data in the fif and truncates the received frame to avoid fif overflow. the corresponding error status is set when the frame is delivered to the application. set enet n _raf to a minimum of 4. enet n _rsem rx_sectin_ empt when the fif level reaches the enet n _rsem value, an indication is sent to the mac transmit logic, which generates a xff pause frame. this indicates fif congestion to the remote ethernet client. when the fif level goes below the value programmed in enet n _mrbr, an indication is sent to the mac transmit logic, which generates a xn pause frame. this indicates the fif congestion is cleared to the remote ethernet client. clearing enet n _rsem disables any pause frame generation. functional description 60 sub-family reference manual, rev. 6, nov 2011 1210 freescale semiconductor, inc. rsfl - section full (core fifo status) mac receive fifo read control rafl - almost full (fifo write protection) rsem - section empty raem - almost empty (fifo read control) (pause frame generation) figure 44-61. receive fifo overview 44.4.11.2 transmit fifo four programmable thresholds are available which control the core operation as described below. table 44-80. transmit fifo thresholds definition register description enet n _taem tx_amst _empt when the fif level reaches the enet n _taem value and no end-of-frame is available for the frame, the mac transmit logic avoids a fif underflow by stopping fif reads and transmitting the ethernet frame with an mii error indication. set enet n _taem to a minimum of 4. enet n _taf tx_amst _fu when the fif level approaches the maximum, so that there is no more space for at least enet n _taf number of words, the mac deasserts its control signal to the application. if the application does not react on this signal, the fif write control logic avoids fif overflow by truncating the current frame and setting the error status. as a result, the frame is transmitted with an mii error indication. set enet n _taf to a minimum of 4. arger values allow more latency for the application to react on the mac control signal deassertion, before the frame is truncated. a typical setting is 8, which offers 4 cloc cycles of latency to the application to react on the mac control signal deassertion. enet n _tsem tx_sectin _empt when the fif level reaches the enet n _tsem value, a mac status signal is deasserted to indicate that the transmit fif is getting full. this gives the application an indication to slow or stop its write transaction to avoid a buffer overflow. this is a pure indication function to the application. it has no effect within the mac. when enet n _tsem is 0, the signal is never deasserted. table continues on the next page... chapter 44 10100-mbps ethernet mac enet 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1211 table 44-80. transmit fifo thresholds definition (continued) register description enet n _tfwr when the fif level reaches the enet n _tfwr value and when strfwd is cleared, the mac transmit control logic starts frame transmission before the end-of-frame is available in the fif cut-through operation. if a complete frame has a size smaller than the enet n _tfwr threshold, the mac also transmits the frame to the line. to enable store and forward on the transmit path, set strfwd. in this case, the mac starts to transmit data only when a complete frame is stored in the transmit fif. mac transmit fif write control fif write control taf - almost full taem - almost empty tsem - section empty tfwr - section full (mac read control) (core fifo status) (mac transmit start) figure 44-62. transmit fifo overview 44.4.12 loopback options the core implements external and internal loopback options, which are controlled by the following enet n _rcr register bits: table 44-81. loopback options register bit description loop internal mii loopback. the mac transmit is returned to the mac receive. no data is transmitted to the external interfaces. in mii internal loopback, mii_txclk and mii_rxclk must be provided with a clock signal (2.5mhz for 10mbps and 25mhz for 100mbps) functional description k60 sub-family reference manual, rev. 6, nov 2011 1212 freescale semiconductor, inc. line interface mac interface enet n _rcrp, figure 44-6. oopbac ptions 44.4.1 egacy buffer descriptors to support the ethernet controller on previous freescale devices, legacy fec buffer descriptors are available. to enable legacy support, clear enet n _ecr[1588en]. 44.4.13.1 legacy receive buffer descriptor the following figureshows the legacy fec receive buffer descriptor. table 44-85 contains the descriptions for each field. note the following addresses are shown for a big endian implementation. table 44-82. legacy fec receive buffer descriptor (rxbd) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 offset + 0 e ro1 w ro2 l m bc mc lg no cr ov tr offset + 2 data length offset + 4 rx data buffer pointer - a[31:16] offset + 6 rx data buffer pointer - a[15:0] 44.4.13.2 legacy transmit buffer descriptor the following figureshows the legacy fec transmit buffer descriptor. table 44-87 contains the descriptions for each field. chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1213 note the following addresses are shown for a big endian implementation. table 44-83. legacy fec transmit buffer descriptor (txbd) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 offset + 0 r to1 w to2 l tc abc 1 offset + 2 data length offset + 4 tx data buffer pointer - a[31:16] offset + 6 tx data buffer pointer - a[15:0] 1. this bit is not supported by the udma. 44.4.14 enhanced buffer descriptors this section provides a description of the enhanced operation of the driver/dma via the buffer descriptors. it is followed by a detailed description of the receive and transmit descriptor fields. to enable the enhanced features, set enet n _ecr[1588en]. 44.4.14.1 enhanced receive buffer descriptor this section discusses the enhanced udma receive buffer descriptor. note the following addresses are shown for a big endian implementation. table 44-84. enhanced udma receive buffer descriptor (rxbd) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 offset + 0 e ro1 w ro2 l m bc mc lg no cr ov tr offset + 2 data length offset + 4 rx data buffer pointer - a[31:16] offset + 6 rx data buffer pointer - a[15:0] offset + 8 me pe ce uc int offset + a ice pcr vla n ipv6 fra g offset + c header length protocol type offset + e payload checksum offset + 10 bdu table continues on the next page... functional description 60 sub-family reference manual, rev. 6, nov 2011 1214 freescale semiconductor, inc. table 44-84. enhanced udma receive buffer descriptor (rxbd) (continued) offset + 12 offset + 14 1588 timestamp [31:16] offset + 16 1588 timestamp [15:0] offset + 18 offset + 1a offset + 1c offset + 1e table 44-85. receive buffer descriptor field definitions word field description offset + 0 15 e empty. written by the mac (=0) and user (=1). 0 the data buffer associated with this bd is filled with received data, or data reception has aborted due to an error condition. the status and length fields have been updated as required. 1 the data buffer associated with this bd is empty, or reception is currently in progress. offset + 0 14 ro1 receive software ownership. this field is reserved for use by software. this read/write bit is not modified by hardware, nor does its value affect hardware. offset + 0 13 w wrap. written by user. 0 the next buffer descriptor is found in the consecutive location 1 the next buffer descriptor is found at the location defined in enet n _rdsr ffset 0 12 r2 receive software ownership. this field is reserved for use by software. this readwrite bit is not modified by hardware, nor does its value affect hardware. ffset 0 11 ast in frame. written by the udma. 0 the buffer is not the last in a frame. 1 the buffer is the last in a frame. ffset 0 10 reserved, must be cleared. ffset 0 8 m miss. written by the mac. this bit is set by the mac for frames accepted in promiscuous mode, but flagged as a miss by the internal address recognition. therefore, while in promiscuous mode, you can use the m-bit to uicly determine whether the frame was destined to this station. this bit is valid only if the and prm bits are set. 0 the frame was received because of an address recognition hit 1 the frame was received because of promiscuous mode the information needed for this bit comes from the promiscuous_missff_rx_err_stat26 sideband signal. ffset 0 7 bc set if the da is broadcast ffff_ffff_ffff. table continues on the next page... chapter 44 10100-mbps ethernet mac enet 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 121 table 44-85. receive buffer descriptor field definitions (continued) word field description offset + 0 6 mc set if the da is multicast and not bc. offset + 0 5 lg rx frame length violation. written by the mac. a frame length greater than rcr[max_fl] was recognized. this bit is valid only if the l bit is set. the receive data is not altered in any way unless the length exceeds trunc_fl bytes. offset + 0 4 no receive non-octet aligned frame. written by the mac. a frame that contained a number of bits not divisible by 8 was received, and the crc check that occurred at the preceding byte boundary generated an error or a phy error occurred. this bit is valid only if the l bit is set. if this bit is set, the cr bit is not set. offset + 0 3 reserved, must be cleared. offset + 0 2 cr receive crc or frame error. written by the mac. this frame contains a phy or crc error and is an integral number of octets in length. this bit is valid only if the l bit is set. offset + 0 1 ov overrun. written by the mac. a receive fifo overrun occurred during frame reception. if this bit is set, the other status bits, m, lg, no, cr, and cl lose their normal meaning and are zero. this bit is valid only if the l bit is set. offset + 0 0 tr set if the receive frame is truncated (frame length >trunc_fl). if the tr bit is set, the frame must be discarded and the other error bits must be ignored as they may be incorrect. offset + 2 150 data length data length. written by the mac. data length is the number of octets written by the mac into this bds data buffer if l is cleared (the value is equal to emrbr), or the length of the frame including crc if l is set. it is written by the mac once as the bd is closed. 0ffset + 4 150 a[31:16] rx data buffer pointer, bits [31:16] 1 offset + 6 150 a[15:0] rx data buffer pointer, bits [15:0] offset + 8 15 me mac error. this bit is written by the udma. this bit means that the frame stored in the system memory was received with an error (typically, a receive fifo overflow). this bit is only valid when the l bit is set. offset + 8 1411 reserved, must be cleared. offset + 8 10 pe phy error. this bit is written by the udma. set to "1"when the frame was received with an error character on the phy interface. the frame is invalid. this bit is valid only when the l bit is set. offset + 8 9 ce collision. this bit is written by the udma. set when the frame was received with a collision detected during reception. the frame is invalid and sent to the user application. this bit is valid only when the l bit is set. offset + 8 8 uc unicast. this bit is written by the udma. this bit means that the frame is unicast. this bit is valid regardless of if the l bit is set. offset + 8 7 int generate rxb/rxf interrupt. this bit is set by the user. this bit indicates that the udma is to generate an interrupt on the dma_int_rxb dma_int_rxfevent . ffset 8 60 reserved, must be cleared. table continues on the next page... functional description 60 sub-family reference manual, rev. 6, nov 2011 1216 freescale semiconductor, inc. table 44-85. receive buffer descriptor field definitions (continued) word field description offset + a 156 reserved, must be cleared. offset + a 5 ice ip header checksum error. this is an accelerator option. this bit is written by the udma. set when either a non-ip frame is received or the ip header checksum was invalid. an ip frame with less than 3 bytes of payload is considered to be an invalid ip frame. this bit is only valid if the l bit is set. offset + a 4 pcr protocol checksum error. this is an accelerator option. this bit is written by the udma. set when the checksum of the protocol is invalid or an unknown protocol is found and checksumming could not be performed. this bit is only valid if the l bit is set. offset + a 3 reserved, must be cleared. offset + a 2 vlan vlan. this is an accelerator option. this bit is written by the udma. this bit means that the frame has a vlan tag. this bit is valid only if the l bit is set. offset + a 1 ipv6 ipv6 frame. this bit is written by the udma. this bit indicates that the frame has a ipv6 frame type. if this bit is not set it means that an ipv4 or other protocol frame was received. this bit is valid only if the l bit is set. offset + a 0 frag ipv4 fragment.this is an accelerator option.this bit is written by the udma.this bit indicates that the frame is an ipv4 fragment frame. this bit is only valid when the l bit is set. offset + c 1511 header length header length. this is an accelerator option. this field is written by the udma. this field is the sum of 32 bit words found within the ip and its following protocol headers. if an ip datagram with an unknown protocol is found the value is the length of the ip header. if no ip frame or an erroneous ip header is found, the value is 0. the following values are minimum values if no header options exist in the respective headers: ? icmp/ip: 6 (5 ip header, 1 icmp header) ? udp/ip: 7 (5 ip header, 2 udp header) ? tcp/ip: 10 (5 ip header, 5 tcp header) this field is only valid if the l bit is set. offset + c 108 reserved, must be cleared. offset + c 70 protocol type protocol type. this is an accelerator option. the 8-bit protocol field found within the ip header of the frame. only valid if ice is cleared. this bit is only valid if the l bit is set. offset + e 150 payload checksum internet payload checksum. this is an accelerator option. the ones complement sum of the payload section of the ip frame. the sum is calculated over all data following the ip header until the end of the ip payload. this field is valid only when the l bit is set. offset + 10 15 bdu last buffer descriptor update done. indicates that the last bd data has been updated by udma. this bit is written by the user (=0) and udma (=1). offset + 10 140 reserved, must be cleared. offset + 12 150 reserved, must be cleared. offset + 14 150 1588 timestamp this value is written by the udma. it is only valid if the l bit is set. offset + 16 table continues on the next page... chapter 44 10100-mbps ethernet mac enet 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1217 table 44-85. receive buffer descriptor field definitions (continued) word field description offset + 18 offset + 1e 150 reserved, must be cleared. 1. the receive buffer pointer, containing the address of the associated data buffer, must always be evenly divisible by 16. the buffer must reside in memory external to the mac. the ethernet controller never modifies this value. 44.4.14.2 enhanced transmit buffer descriptor this section discusses the enhanced udma transmit buffer descriptor. note the following addresses are shown for a big endian implementation. table 44-86. enhanced transmit buffer descriptor (txbd) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 offset + 0 r to1 w to2 l tc offset + 2 data length offset + 4 tx data buffer pointer - a[31:16] offset + 6 tx data buffer pointer - a[15:0] offset + 8 int ts pin s iins offset + a txe ue ee fe lce oe tse offset + c offset + e offset + 10 bdu offset + 12 offset + 14 1588 timestamp [31:16] offset + 16 1588 timestamp [15:0] offset + 18 offset + 1a offset + 1c offset + 1e functional description k60 sub-family reference manual, rev. 6, nov 2011 1218 freescale semiconductor, inc. table 44-87. enhanced transmit buffer descriptor field definitions word field description offset + 0 15 r ready. written by the mac and you. 0 the data buffer associated with this bd is not ready for transmission. you are free to manipulate this bd or its associated data buffer. the mac clears this bit after the buffer has been transmitted or after an error condition is encountered. 1 the data buffer, prepared for transmission by you, has not been transmitted or currently transmits. you may write no fields of this bd after this bit is set. offset + 0 14 to1 transmit software ownership. this field is reserved for software use. this read/ write bit is not modified by hardware nor does its value affect hardware. offset + 0 13 w wrap. written by user. 0 the next buffer descriptor is found in the consecutive location 1 the next buffer descriptor is found at the location defined in etdsr. offset + 0 12 to2 transmit software ownership. this field is reserved for use by software. this read/write bit is not modified by hardware nor does its value affect hardware. offset + 0 11 l last in frame. written by user. 0 the buffer is not the last in the transmit frame 1 the buffer is the last in the transmit frame offset + 0 10 tc transmit crc. written by user (only valid if l is set). 0 end transmission immediately after the last data byte 1 transmit the crc sequence after the last data byte this bit is valid only when the l bit is set. offset + 0 9 abc append bad crc. note: this bit is not supported by the udma and is ignored. offset + 0 80 reserved, must be cleared. offset + 2 150 data length data length, written by user. data length is the number of octets the mac should transmit from this bds data buffer. it is never modified by the mac. offset + 4 150 a[31:16] tx data buffer pointer, bits [31:16]. the transmit buffer pointer, containing the address of the associated data buffer, must always be evenly divisible by 8. the buffer must reside in memory external to the mac. this value is never modified by the ethernet controller. offset + 6 150 a[15:0] tx data buffer pointer, bits [15:0] offset + 8 15 reserved, must be cleared. offset + 8 14 int generate interrupt. this bit is written by the user. this bit is valid regardless of the l bit and must be the same for all ebd for a given frame. the udma does not update this value. table continues on the next page... chapter 44 10100-mbps ethernet mac enet 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 121 table 44-87. enhanced transmit buffer descriptor field definitions (continued) word field description offset + 8 13 ts timestamp. this bit is written by the user. this indicates that the udma is to generate a timestamp frame to the mac. this bit is valid regardless of the l bit and must be the same for all ebd for the given frame. the udma does not update this value. offset + 8 12 pins insert protocol specific checksum. this bit is written by the user. if set, the macs ip accelerator calculates the protocol checksum and overwrites the corresponding checksum field with the calculated value. the checksum field must be cleared by the application generating the frame. the udma does not update this value. this bit is valid regardless of the l bit and must be the same for all ebd for a given frame. offset + 8 11 iins insert ip header checksum. this bit is written by the user. if set, the macs ip accelerator calculates the ip header checksum and overwrites the corresponding header field with the calculated value. the checksum field must be cleared by the application generating the frame. the udma does not update this value. this bit is valid regardless of the l bit and must be the same for all ebd for a given frame. offset + 8 100 reserved, must be cleared. offset + a 15 txe transmit error occurred. this bit is written by the udma. this bit indicates that there was a transmit error of some sort reported with the frame. effectively this bit is an or of the other error bits including ue, ee, fe, lce, oe, and tse. this bit is only valid when the l bit is set. offset + a 14 reserved, must be cleared. offset + a 13 ue underflow error. this bit is written by the udma. this bit indicates that the mac reported an underflow error on transmit. this bit is only valid when the l bit is set. offset + a 12 ee excess collision error. this bit is written by the udma. this bit indicates that the mac reported an excess collision error on transmit. this bit is only valid when the l bit is set. offset + a 11 fe frame with error. this bit is written by the udma. this bit indicates that the mac reported that the udma reported an error when providing the packet. this bit is only valid when the l bit is set. offset + a 10 lce late collision error. this bit is written by the udma. this bit indicates that the mac reported that there was a late collision on transmit. this bit is only valid when the l bit is set. offset + a 9 oe overflow error. this bit is written by the udma. this bit indicates that the mac reported that there was a fifo overflow condition on transmit. this bit is only valid when the l bit is set. offset + a 8 tse timestamp error. this bit is written by the udma. this bit indicates that the mac reported a different frame type then a timestamp frame. this bit is only valid when the l bit is set. offset + a 70 reserved, must be cleared. offset + c 150 reserved, must be cleared. offset + e 150 reserved, must be cleared. offset + 10 15 bdu last buffer descriptor update done. indicates that the last bd data has been updated by udma. this bit is written by the user (=0) and udma (=1). table continues on the next page... functional description 60 sub-family reference manual, rev. 6, nov 2011 1220 freescale semiconductor, inc. table 44-87. enhanced transmit buffer descriptor field definitions (continued) word field description offset + 10 140 reserved, must be cleared. offset + 12 150 reserved, must be cleared. offset + 14 150 1588 timestamp this value is written by the udma . it is only valid if the l bit is set. offset + 16 offset + 18offset + 1e 150 reserved, must be cleared. 44.4.15 client fifo application interface the fifo interface is completely asynchronous from the ethernet line, and the transmit and receive interface can operate at a different clock rate. all transfers to/from the user application are handled independent of the core operation, and the core provides a simple interface to user applications based on a two-signal handshake. 44.4.15.1 data structure description the data structure defined in the following tables for the fifo interface must be respected to ensure proper data transmission on the ethernet line. byte 0 is sent to and received from the line first. table 44-88. fifo interface data structure 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 word 0 byte 7 byte 6 byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 word 1 byte 15 byte 14 byte 13 byte 12 byte 11 byte 10 byte 9 byte 8 ... ... the size of a frame on the fifo interface may not be a modulo of 64-bit. the user application may not care about the ethernet frame formats in full detail. it needs to provide and receive an ethernet frame with the following structure: ? ethernet mac destination address ? ethernet mac source address ? optional 802.1q vlan tag (vlan type and info field) chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1221 ? ethernet length/type field ? payload frames on the fifo interface do not contain preamble and sfd fields, which are inserted and discarded by the mac on transmit and receive, respectively. ? on receive, crc and frame padding can be stripped or passed through transparently. ? on transmit, padding and crc can be provided by the user application, or appended automatically by the mac independent for each frame. no size restrictions apply. note on transmit, if enet n _tcr[addins] is set, bytes 6C11 of each frame can be set to any value, since the mac overwrites the bytes with the mac address programmed in the enet n _paur and enet n _palr registers. table 44-89. fifo interface frame format byte number field 0?5 destination mac address 6?11 source mac address 12?13 length/type field 14?n payload data vlan-tagged frames are also supported on both transmit and receive and implement additional information (vlan type and info). table 44-90. fifo interface vlan frame format byte number field 0?5 destination mac address 6?11 source mac address 12?15 vlan tag and info 16?17 length/type field 18?n payload data note the standard defines that the lsb of the mac address is sent/ received first, while for all the other header fields (i.e. length/ type, vlan tag, vlan info and pause quanta), the msb is sent/received first. functional description k60 sub-family reference manual, rev. 6, nov 2011 1222 freescale semiconductor, inc. 44.4.15.2 data structure examples bits 07 transmitted first word 0 1 2 3 n destination address source address (cont.) payload (cont.) payload (cont.) payload (last-2) 63 55 47 39 31 23 15 7 source address payload length (low) length (high) unused (0x00) payload (last) payload (last-1) figure 44-64. normal ethernet frame 64-bit mapping example bits 0?7 transmitted first word 0 1 2 3 n destination address source address (cont.) payload payload (cont.) payload (last-2) 63 55 47 39 31 23 15 7 source address length (low) length (high) unused (0x00) payload (last) payload (last-1) vlan tag (0x81) vlan info (low) vlan info (high) vlan tag (0x00) figure 44-65. vlan tagged frame 64-bit mapping example if crc forwarding is enabled (crcfwd = 0), the last four valid octets of the frame contain the fcs field. the non-significant bytes of the last word can have any value. 44.4.15.3 frame status a mac layer status word and an accelerator status word is available in the receive buffer descriptor. see enhanced buffer descriptors for details. the status is available with each frame with the last data of the frame. if the frame status contains a mac layer error (e.g., crc or length error), rxbd[me] is also setwith the last data of the frame. chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1223 44.4.16 fifo protection the following sections describe the fifo protection mechanisms. 44.4.16.1 transmit fifo underflow during a frame transfer, when the transmit fifo reaches the almost empty threshold with no end-of-frame indication stored in the fifo, the mac logic: ? stops reading data from the fifo ? asserts the mii error signal (mii_txer) (1) to indicate that the fragment already transferred is not valid ? deasserts the mii transmit enable signal (mii_txen) to terminate the frame transfer (2) after an underflow, when the application completes the frame transfer (3), the mac transmit logic discards any new data available in the fifo until the end of packet is reached (4) and sets the enhanced txbd[ue] bit. the mac starts to transfer data on the mii interface when the application sends a new frame with a start of frame indication (5). transmit fifo mii transmit 3 4 1 2 5 55 55 tx clk tx ready write enable start of packet end of packet tx data tx error status mii_txclk mii_txen mii_txd[3:0] mii_txer fifo data section empty internal signals external signals figure 44-66. transmit fifo underflow protection functional description k60 sub-family reference manual, rev. 6, nov 2011 1224 freescale semiconductor, inc. 44.4.16.2 transmit fifo overflow on the transmit path, when the fifo reaches the programmable almost full threshold, the internal mac ready signal is deasserted. the application should stop sending new data . however, if the application keeps sending data , the transmit fifo overflows, corrupting previously-stored contents. the core logic sets the enhanced txbd[oe] bit for the next frame transmitted to indicate this overflow occurence. note overflow is a fatal error and must be addressed by resetting the core or clearing enet n _ecr[ether_en] to clear the fifos and prepare for normal operation again. chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1225 44.4.16.3 receive fifo overflow during a frame reception, if the client application is not able to receive data (1), the mac receive control truncates the incoming frame, when the fifo reaches the programmable almost full threshold to avoid an overflow. the frame is subsequently received on the fifo interface with an error indication (enhanced rxbd[me] bit set together with receive end-of-packet) (2) with the truncation error status bit set (3). mii receive mii_rxclk mii_rxd[3:0] mii_rxen mii_rxer receive fifo rx clk rx ready frame available data valid start of packet end of packet rx data rx error rx error status 2 3 1 external signals internal signals figure 44-67. receive fifo overflow protection 44.4.17 phy management interface the mdio interface is a two-wire management interface. the mdio management interface implements a standardized method to access the phy device management registers. the core implements a master mdio interface, which can be connected to up to 32 phy devices. 44.4.17.1 mdio frame format the core mdio master controller communicates with the slave (phy device) using frames that are defined in the following table. functional description k60 sub-family reference manual, rev. 6, nov 2011 1226 freescale semiconductor, inc. a complete frame has a length of 64 bits (optional 32-bit preamble, 14-bit command, 2- bit bus direction change, 16-bit data). each bit is transferred on the rising edge of the mdio clock (mdc signal). the core phy management interface supports the standard mdio specification (ieee803.2 clause 22). table 44-91. mdio frame formats (read/write) type command ta data idle pre st op addr1 addr2 msb lsb read 11 01 10 xxxxx xxxxx z0 xxxxxxxxxxxxxxxx z write 11 01 01 xxxxx xxxxx 10 xxxxxxxxxxxxxxxx z table 44-92. mdio frame field descriptions field description pre preamble. 32 bits of logical ones sent prior to every transaction when enet n _mscrdis_pre is cleared. if dis_pre is set, the preamble is not generated. st start indication, programmed with enet n _mmfrst standard mdi clause 22 01 p pcode defines if a read or write operation is performed, programmed with enet n _mmfrp. 01 write operation 10 read operation addr1 the ph device address, programmed with enet n _mmfrpa. up to 2 devices can be addressed. addr2 register address, programmed with enet n _mmfrra. each ph can implement up to 2 registers. ta turnaround time, programmed with enet n _mmfrta. two bit-times are reserved for read operations to switch the data bus from write to read for read operations. the ph device presents its register contents in the data phase and drives the bus from the second bit of the turnaround phase. data 16 bits of data, set to enet n _mmfrdata, written to or read from the ph idle between frames the mdi data signal is tri-stated. 44.4.17.2 mdi cloc eneration the mdc clock is generated from the internal bus clock divided by the value programmed in enet n _mscr[mii_speed]. chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1227 44.4.17.3 mdio operation to perform a mdio access, set the mdio command register (enet n _mmfr) according to the description provided in mii management frame register (enetn_mmfr). to check when the programmed access completes, read the enet n _eir[mii] bit. start load enet n _mmfr register read enet n _eir mii 1 n figure 44-68. mdi access verview 44.4.18 ethernet interfaces the following ethernet interfaces are implemented: ? fast ethernet mii (medium independent interface) ? rmii 10/100 by way of interface converters/gaskets the following table shows how to configure enet registers to select each interface. mode ecr[speed] rcr[rmii_10t] rcr[rmii_mode] mii - 10mbps 1 0 0 mii - 100mbps 1 0 0 rmii - 10mbps 0 1 1 rmii - 100mbps 0 0 1 1. selecting between 10mbps and 100mbps mii mode is implicitly selected by the mii clock speed. 44.4.18.1 rmii interface in rmii receive mode, for normal reception following assertion of crs_dv, rxd[1:0] is 00b until the receiver determines that the receive event has a proper start of stream delimiter (ssd). functional description k60 sub-family reference manual, rev. 6, nov 2011 1228 freescale semiconductor, inc. the preamble appears (rxd[1:0]=01) and the macs begin capturing data following detection of sfd. /j/ /k / pream bl e sfd d ata rmii_ref_clk rmii_crs_dv 0 0 0 0 0 0 0 0 0 0 0 0 0 1 x x x x x x 0 rmii_rxd1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 x x x x x x 0 rmii_rxd0 figure 44-69. rmii receive operation if a false carrier is detected (bad ssd), then rxd[1:0] is 10b until the end of the receive event. this is a unique pattern since a false carrier can only occur at the beginning of a packet where the preamble is decoded (rxd[1:0] = 01b). rmii_ref_clk rmii_crs_dv 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 rmii_rxd1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rmii_rxd0 false carrier detected figure 44-70. rmii receive operation with false carrier in rmii transmit mode, txd[1:0] provides valid data for each ref_clk period while txen is asserted. pream bl e sfd d ata rmii_ref_clk rmii_txen 0 0 0 0 0 0 0 0 0 0 0 0 0 1 x x x x x x 0 rmii_txd1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 x x x x x x 0 rmii_txd0 figure 44-71. rmii transmit operation chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1229 44.4.18.2 mii interface ? transmit on transmit, all data transfers are synchronous to mii_txclk rising edge. the mii data enable signal mii_txen is asserted to indicate the start of a new frame and remains asserted until the last byte of the frame is present on the mii_txd[3:0] bus. between frames, mii_txen remains deasserted. crc-32 sfd preamble 5 04 05 06 07 08 09 0a 0f 10 11 12 13 14 15 16 17 18 19 1a 1c 1e 1f 20 21 22 23 24 25 26 27 28 29 2b 2e 2f 30 31 32 33 34 35 36 37 38 39 3b 3f 40 99 80 28 mii_txer mii_txclk mii_txd[3:0] mii_txen figure 44-72. mii transmit operation if a frame is received on the fifo interface with an error (e.g., rxbd[me] set) the frame is subsequently transmitted with the mii_txer error signal for one clock cycle at any time during the packet transfer. crc-32 sfd mii_txclk mii_txd[3:0] mii_txen mii_txer preamble 5 figure 44-73. mii transmit operation errored frame functional description k60 sub-family reference manual, rev. 6, nov 2011 1230 freescale semiconductor, inc. 44.4.18.2.1 transmit with collision ? half duplex when a collision is detected during a frame transmission (mii_col asserted), the mac stops the current transmission, sends a 32-bit jam pattern, and re-transmits the current frame. (see collision detection in half duplex mode for details) jam mii_txclk mii_txd[3:0] mii_txen mii_txer mii_crs mii_col 5 figure 44-74. mii transmit operation transmission with collision 44.4.18.3 mii interface receive on receive all signals are sampled on the mii_rxclk rising edge. the mii data enable signal, mii_rxdv, is asserted by the phy to indicate the start of a new frame and remains asserted until the last byte of the frame is present on mii_rxd[3:0] bus. between frames, mii_rxdv remains de-asserted. crc-32 sfd preamble 5 mii_rxer mii_rxclk mii_rxd[3:0] mii_rxdv figure 44-75. mii receive operation chapter 44 10/100-mbps ethernet mac (enet) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1231 if the phy detects an error on the frame received from the line, the phy asserts the mii error signal, mii_rxer, for at least one clock cycle at any time during the packet transfer. crc-32 sfd preamble 5 mii_rxer mii_rxclk mii_rxd[3:0] mii_rxdv figure 44-76. mii receive operation errored frame a frame received on the mii interface with a phy error indication is subsequently transferred on the fifo interface with rxbd[me] set. functional description k60 sub-family reference manual, rev. 6, nov 2011 1232 freescale semiconductor, inc. chapter 45 universal serial bus otg controller (usbotg) 45.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. this section describes the usb. the otg implementation in this module provides limited host functionality as well as device solutions for implementing a usb 2.0 full- speed/low-speed compliant peripheral. the otg implementation supports the on-the- go (otg) addendum to the usb 2.0 specification. only one protocol can be active at any time. a negotiation protocol must be used to switch to a usb host functionality from a usb device. this is known as the master negotiation protocol (mnp). 45.1.1 usb the usb is a cable bus that supports data exchange between a host computer and a wide range of simultaneously accessible peripherals. the attached peripherals share usb bandwidth through a host-scheduled, token-based protocol. the bus allows peripherals to be attached, configured, used, and detached while the host and other peripherals are in operation. usb software provides a uniform view of the system for all application software, hiding implementation details making application software more portable. it manages the dynamic attach and detach of peripherals. there is only one host in any usb system. the usb interface to the host computer system is referred to as the host controller. there may be multiple usb devices in any system such as joysticks, speakers, printers, etc. usb devices present a standard usb interface in terms of comprehension, response, and standard capability. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1233 the host initiates transactions to specific peripherals, while the device responds to control transactions. the device sends and receives data to and from the host using a standard usb data format. usb 2.0 full-speed /low-speed peripherals operate at 12mb/s or 1.5 mb/s. for additional information, refer to the usb 2.0 specification. external hub root hub usb cable usb cable usb cable external hub usb peripherals host pc host software usb cables figure 45-1. example usb 2.0 system configuration 45.1.2 usb on-the-go usb (universal serial bus) is a popular standard for connecting peripherals and portable consumer electronic devices such as digital cameras and hand-held computers to host pcs. the on-the-go (otg) supplement to the usb specification extends usb to peer- to-peer application. using usb otg technology consumer electronics, peripherals and portable devices can connect to each other (for example, a digital camera can connect directly to a printer, or a keyboard can connect to a personal digital assistant) to exchange data. with the usb on-the-go product, you can develop a fully usb-compliant peripheral device that can also assume the role of a usb host. software determines the role of the device based on hardware signals, and then initializes the device in the appropriate mode of operation (host or peripheral) based on how it is connected. after connecting the devices can negotiate using the otg protocols to assume the role of host or peripheral based on the task to be accomplished. for additional information, refer to the on-the-go supplement to the usb 2.0 specification . introduction k60 sub-family reference manual, rev. 6, nov 2011 1234 freescale semiconductor, inc. print photos keyboard input swap songs download songs hot sync figure 45-2. example usb 2.0 on-the-go configurations 45.1.3 usb-fs features ? usb 1.1 and 2.0 compliant full-speed device controller ? 16-bidirectional end points ? dma or fifo data stream interfaces ? low-power consumption ? on-the-go protocol logic 45.2 functional description the usb-fs 2.0 full-speed/low-speed module communicates with the processor core through status registers, control registers, and data structures in memory. chapter 45 universal serial bus otg controller (usbotg) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1235 45.2.1 data structures the function of the device operation is to transfer a request in the memory image to and from the universal serial bus. to efficiently manage usb endpoint communications the usb-fs implements a buffer descriptor table (bdt) in system memory. see figure 45-3 . 45.3 programmers interface this section discusses the major components of the programming model for the usb module. 45.3.1 buffer descriptor table to efficiently manage usb endpoint communications the usb-fs implements a buffer descriptor table (bdt) in system memory. the bdt resides on a 512 byte boundary in system memory and is pointed to by the bdt page registers. every endpoint direction requires two eight-byte buffer descriptor entries. therefore, a system with 16 fully bidirectional endpoints would require 512 bytes of system memory to implement the bdt. the two buffer descriptor (bd) entries allows for an even bd and odd bd entry for each endpoint direction. this allows the microprocessor to process one bd while the usb-fs is processing the other bd. double buffering bds in this way allows the usb-fs to easily transfer data at the maximum throughput provided by usb. the software api intelligently manages buffers for the usb-fs by updating the bdt when needed. this allows the usb-fs to efficiently manage data transmission and reception, while the microprocessor performs communication overhead processing and other function dependent applications. because the buffers are shared between the microprocessor and the usb-fs a simple semaphore mechanism is used to distinguish who is allowed to update the bdt and buffers in system memory. a semaphore bit, the own bit, is cleared to 0 when the bd entry is owned by the microprocessor. the microprocessor is allowed read and write access to the bd entry and the buffer in system memory when the own bit is 0. when the own bit is set to 1, the bd entry and the buffer in system memory are owned by the usb-fs. the usb-fs now has full read and write access and the microprocessor should not modify the bd or its corresponding data buffer. the bd also contains indirect address pointers to where the actual buffer resides in system memory. this indirect address mechanism is shown in the following diagram. programmers interface k60 sub-family reference manual, rev. 6, nov 2011 1236 freescale semiconductor, inc. current endpoint bdt buffer in memory bdt page start of buffer ? 000oddinbdt_page registers end_point ? ? ? ? ? end of buffer system memory figure 45-3. buffer descriptor table 45.3.2 rx vs. tx as a usb target device or usb host the usb-fs core uses software control to switch between two modes of operation: ? usb target device ? usb hosts in either mode, usb host or usb target device, the same data paths and buffer descriptors are used for the transmission and reception of data. for this reason, a usb-fs core centric nomenclature is used to describe the direction of the data transfer between the usb-fs core and the usb: rx (or receive) describes transfers that move data from the usb to memory. tx (or transmit) describes transfers that move data from memory to the usb. the following table shows how the data direction corresponds to the usb token type in host and target device applications. table 45-1. data direction for usb host or usb target rx tx device out or setup in table continues on the next page... chapter 4 universal serial bus t controller usbt 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 127 table 45-1. data direction for usb host or usb target (continued) rx tx host in out or setup 45.3.3 addressing buffer descriptor table entries an understanding of the addressing mechanism of the buffer descriptor table is useful when accessing endpoint data via the usb-fs or microprocessor. some points of interest are: ? the buffer descriptor table occupies up to 512 bytes of system memory. ? 16 bidirectional endpoints can be supported with a full bdt of 512 bytes. ? 16 bytes are needed for each usb endpoint direction. ? applications with less than 16 endpoints require less ram to implement the bdt. ? the bdt page registers point to the starting location of the bdt. ? the bdt must be located on a 512-byte boundary in system memory. ? all enabled tx and rx endpoint bd entries are indexed into the bdt to allow easy access via the usb-fs or mcu core. when a usb token on an enabled endpoint is received, the usb-fs uses its integrated dma controller to interrogate the bdt. the usb-fs reads the corresponding endpoint bd entry to determine if it owns the bd and corresponding buffer in system memory. to compute the entry point in to the bdt, the bdt_page registers is concatenated with the current endpoint and the tx and odd fields to form a 32-bit address. this address mechanism is shown in the following diagrams: table 45-2. bdt address calculation fields field description bdt_page bdt_page registers in the control register block end_point end point field from the usb token tx 1 for an tx transmit transfers and 0 for an rx receive transfers odd this bit is maintained within the usb-fs sie. it corresponds to the buffer currently in use. the buffers are used in a ping-pong fashion. 45.3.4 buffer descriptor formats the buffer descriptors (bd) provide endpoint buffer control information for the usb-fs and microprocessor. the buffer descriptors have different meaning based on whether it is the usb-fs or microprocessor reading the bd in memory. programmers interface k60 sub-family reference manual, rev. 6, nov 2011 1238 freescale semiconductor, inc. the usb-fs controller uses the data stored in the bds to determine: ? who owns the buffer in system memory ? data0 or data1 pid ? release own upon packet completion ? no address increment (fifo mode) ? data toggle synchronization enable ? how much data is to be transmitted or received ? where the buffer resides in system memory while the microprocessor uses the data stored in the bds to determine: ? who owns the buffer in system memory ? data0 or data1 pid ? the received token pid ? how much data was transmitted or received ? where the buffer resides in system memory the format for the bd is shown in the following figure. table 45-3. buffer descriptor byte format 31:26 25:16 15:8 7 6 5 4 3 2 1 0 rsvd bc (10 bits) rsvd own data0/1 keep/ tok_pid[3] ninc/ tok_pid[2] dts/ tok_pid[1] bdt_stall/ tok_pid[0] 0 0 buffer address (32-bits) table 45-4. buffer descriptor byte fields field description 31 ?26 rsvd reserved 25 ?16 bc[9:0] the byte count bits represent the 10-bit byte count. the usb-fs sie changes this field upon the completion of a rx transfer with the byte count of the data received. 15 ?8 rsvd reserved table continues on the next page... chapter 4 universal serial bus t controller usbt 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 12 table 45-4. buffer descriptor byte fields (continued) field description 7 own the own bit determines whether the microprocessor or the usb-fs currently owns the buffer. except when keep=1, the sie writes a 0 to this bit when it has completed a token. this byte of the bd should always be the last byte the microprocessor updates when it initializes a bd. 0 the microprocessor has exclusive access to the bd. the usb-fs ignores all other fields in the bd. 1 usb-fs has exclusive access to the bd. after the bd has been assigned to the usb-fs, the microprocessor should not change it in any way. 6 data0/1 this bit defines if a data0 field (data0/1=0) or a data1 (data0/1=1) field was transmitted or received. it is unchanged by the usb-fs. 5 keep/ tok_pid[3] typically this bit is set (that is, 1) with iso endpoints feeding a fifo. the microprocessor is not informed that a token has been processed, the data is simply transferred to or from the fifo. if keep is set, normally the ninc bit is also set to prevent address increment. 0 bit 3 of the current token pid is written back in to the bd by the usb-fs. allows the usb-fs to release the bd when a token has been processed. 1 this bit is unchanged by the usb-fs. if the own bit also is set, the bd remains owned by the usb-fs forever. 4 ninc/ tok_pid[2] the no increment (ninc) bit disables the dma engine address increment. this forces the dma engine to read or write from the same address. this is useful for endpoints when data needs to be read from or written to a single location such as a fifo. typically this bit is set with the keep bit for iso endpoints that are interfacing to a fifo. 0 the usb-fs writes bit 2 of the current token pid to the bd. 1 this bit is unchanged by the usb-fs. 3 dts/ tok_pid[1] setting this bit enables the usb-fs to perform data toggle synchronization. ? if keep=0, bit 1 of the current token pid is written back to the bd. ? if keep=1, this bit is unchanged by the usb-fs. 0 data toggle synchronization is disabled. 1 enables the usb-fs to perform data toggle synchronization. table continues on the next page... programmers interface 60 sub-family reference manual, rev. 6, nov 2011 1240 freescale semiconductor, inc. table 45-4. buffer descriptor byte fields (continued) field description 2 bdt_stall tok_pid[0] setting this bit causes the usb-fs to issue a stall handshake if a token is received by the sie that would use the bdt in this location. the bdt is not consumed by the sie (the owns bit remains set and the rest of the bdt is unchanged) when a bdt-stall bit is set. ? if keep=0, bit 0 of the current token pid is written back to the bd. ? if keep=1, this bit is unchanged by the usb-fs. 0 no stall issued. 1 the bdt is not consumed by the sie (the own bit remains set and the rest of the bdt is unchanged). tok_pid[n] bits [5:2] can also represent the current token pid. the current token pid is written back in to the bd by the usb-fs when a transfer completes. the values written back are the token pid values from the usb specification: ? 0x1 for an out token. ? 0x9 for an in token. ? 0xd for a setup token. in host mode, this field is used to report the last returned pid or a transfer status indication. the possible values returned are: ? 0x3 data0 ? 0xb data1 ? 0x2 ack ? 0xe stall ? 0xa nak ? 0x0 bus timeout ? 0xf data error 10 reserved reserved, should read as zeroes. addr[31:0] the address bits represent the 32 -bit buffer address in system memory. these bits are unchanged by the usb-fs. 45.3.5 usb transaction when the usb-fs transmits or receives data, it computes the bdt address using the address generation shown in "addressing buffer descriptor entries" table. if own =1, the following process occurs: 1. the usb-fs reads the bdt. 2. the sie transfers the data via the dma to or from the buffer pointed to by the addr field of the bd. 3. when the token is complete, the usb-fs updates the bdt and, if keep=0, changes the own bit to 0. 4. the stat register is updated and the tok_dne interrupt is set. chapter 45 universal serial bus otg controller (usbotg) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1241 5. when the microprocessor processes the tok_dne interrupt, it reads from the status register all the information needed to process the endpoint. 6. at this point, the microprocessor allocates a new bd so additional usb data can be transmitted or received for that endpoint, and then processes the last bd. the following figure shows a timeline of how a typical usb token is processed after the bdt is read and own=1. setup token data ack usb rst sof in token data ack out token data ack usb_rst interrupt generated usb host function tok_dne interrupt generated sof interrupt generated tok_dne interrupt generated tok_dne interrupt generated figure 45-4. usb token transaction the usb has two sources for the dma overrun error: memory latency the memory latency on the bvci initiator interface may be too high and cause the receive fifo to overflow. this is predominantly a hardware performance issue, usually caused by transient memory access issues. oversized packets the packet received may be larger than the negotiated maxpacket size. typically, this is caused by a software bug. for dma overrun errors due to oversized data packets, the usb specification is ambiguous. it assumes correct software drivers on both sides. naking the packet can result in retransmission of the already oversized packet data. therefore, in response to oversized packets, the usb core continues acking the packet for non-isochronous transfers. table 45-5. usb responses to dma overrun errors errors due to memory latency errors due to oversized packets non-acknowledgment (nak) or bus timeout (bto) see bit 4 in "error interrupt status register (err_stat)" as appropriate for the class of transaction. continues acknowledging (acking) the packet for non- isochronous transfers. table continues on the next page... programmers interface 60 sub-family reference manual, rev. 6, nov 2011 1242 freescale semiconductor, inc. table 45-5. usb responses to dma overrun errors (continued) errors due to memory latency errors due to oversized packets the data written to memory is clipped to the maxpacket size so as not to corrupt system memory. the dma_err bit is set in the err_stat register for host and device modes of operation. depending on the values of the int_enb and err_enb register, the core may assert an interrupt to notify the processor of the dma error. asserts the dma_err bit of the err_stat register (which could trigger an interrupt) and a tok_dne interrupt fires. (note: the tok_pid field of the bdt is not 1111 because the dma_err is not due to latency). ? for host mode, the tok_dne interrupt fires and the tok_pid field of the bdt is 1111 to indicate the dma latency error. host mode software can decide to retry or move to next scheduled item. ? in device mode, the bdt is not written back nor is the tok_dne interrupt triggered because it is assumed that a second attempt is queued and will succeed in the future. the packet length field written back to the bdt is the maxpacket value that represents the length of the clipped data actually written to memory. from here, the software can decide an appropriate course of action for future transactions such as stalling the endpoint, canceling the transfer, disabling the endpoint, etc. 45.4 memory map/register definitions this section provides the memory map and detailed descriptions of all usb interface registers. usb memory map absolute address (hex) register name width (in bits) access reset value section/ page 4007_2000 peripheral id register (usb0_perid) 8 r 04h 45.4.1/ 1245 4007_2004 peripheral id complement register (usb0_idcomp) 8 r fbh 45.4.2/ 1246 4007_2008 peripheral revision register (usb0_rev) 8 r 33h 45.4.3/ 1246 4007_200c peripheral additional info register (usb0_addinfo) 8 r 01h 45.4.4/ 1247 4007_2010 otg interrupt status register (usb0_otgistat) 8 r/w 00h 45.4.5/ 1247 4007_2014 otg interrupt control register (usb0_otgicr) 8 r/w 00h 45.4.6/ 1248 4007_2018 otg status register (usb0_otgstat) 8 r/w 00h 45.4.7/ 1249 table continues on the next page... chapter 4 universal serial bus t controller usbt 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 124 usb memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4007_201c otg control register (usb0_otgctl) 8 r/w 00h 45.4.8/ 1250 4007_2080 interrupt status register (usb0_istat) 8 r/w 00h 45.4.9/ 1251 4007_2084 interrupt enable register (usb0_inten) 8 r/w 00h 45.4.10/ 1252 4007_2088 error interrupt status register (usb0_errstat) 8 r/w 00h 45.4.11/ 1253 4007_208c error interrupt enable register (usb0_erren) 8 r/w 00h 45.4.12/ 1254 4007_2090 status register (usb0_stat) 8 r 00h 45.4.13/ 1256 4007_2094 control register (usb0_ctl) 8 r/w 00h 45.4.14/ 1257 4007_2098 address register (usb0_addr) 8 r/w 00h 45.4.15/ 1258 4007_209c bdt page register 1 (usb0_bdtpage1) 8 r/w 00h 45.4.16/ 1259 4007_20a0 frame number register low (usb0_frmnuml) 8 r/w 00h 45.4.17/ 1259 4007_20a4 frame number register high (usb0_frmnumh) 8 r/w 00h 45.4.18/ 1260 4007_20a8 token register (usb0_token) 8 r/w 00h 45.4.19/ 1260 4007_20ac sof threshold register (usb0_softhld) 8 r/w 00h 45.4.20/ 1261 4007_20b0 bdt page register 2 (usb0_bdtpage2) 8 r/w 00h 45.4.21/ 1262 4007_20b4 bdt page register 3 (usb0_bdtpage3) 8 r/w 00h 45.4.22/ 1262 4007_20c0 endpoint control register (usb0_endpt0) 8 r/w 00h 45.4.23/ 1262 4007_20c4 endpoint control register (usb0_endpt1) 8 r/w 00h 45.4.23/ 1262 4007_20c8 endpoint control register (usb0_endpt2) 8 r/w 00h 45.4.23/ 1262 4007_20cc endpoint control register (usb0_endpt3) 8 r/w 00h 45.4.23/ 1262 4007_20d0 endpoint control register (usb0_endpt4) 8 r/w 00h 45.4.23/ 1262 table continues on the next page... memory mapregister definitions 60 sub-family reference manual, rev. 6, nov 2011 1244 freescale semiconductor, inc. usb memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4007_20d4 endpoint control register (usb0_endpt5) 8 r/w 00h 45.4.23/ 1262 4007_20d8 endpoint control register (usb0_endpt6) 8 r/w 00h 45.4.23/ 1262 4007_20dc endpoint control register (usb0_endpt7) 8 r/w 00h 45.4.23/ 1262 4007_20e0 endpoint control register (usb0_endpt8) 8 r/w 00h 45.4.23/ 1262 4007_20e4 endpoint control register (usb0_endpt9) 8 r/w 00h 45.4.23/ 1262 4007_20e8 endpoint control register (usb0_endpt10) 8 r/w 00h 45.4.23/ 1262 4007_20ec endpoint control register (usb0_endpt11) 8 r/w 00h 45.4.23/ 1262 4007_20f0 endpoint control register (usb0_endpt12) 8 r/w 00h 45.4.23/ 1262 4007_20f4 endpoint control register (usb0_endpt13) 8 r/w 00h 45.4.23/ 1262 4007_20f8 endpoint control register (usb0_endpt14) 8 r/w 00h 45.4.23/ 1262 4007_20fc endpoint control register (usb0_endpt15) 8 r/w 00h 45.4.23/ 1262 4007_2100 usb control register (usb0_usbctrl) 8 r/w c0h 45.4.24/ 1264 4007_2104 usb otg observe register (usb0_observe) 8 r 50h 45.4.25/ 1264 4007_2108 usb otg control register (usb0_control) 8 r/w 00h 45.4.26/ 1265 4007_210c usb transceiver control register 0 (usb0_usbtrc0) 8 r/w 00h 45.4.27/ 1266 45.4.1 peripheral id register (usb x r the peripheral id register reads back the value of 0x04. this value is defined for the usb peripheral. addresses: usb0_perid is 4007_2000h base + 0h offset = 4007_2000h bit 7 6 5 4 3 2 1 0 read 0 id write reset 0 0 0 0 0 1 0 0 chapter 45 universal serial bus otg controller (usbotg) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1245 usb x r iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero eriheral ientiication its hese its always rea x eriheral oleent reister u x o the peripheral id complement register reads back the complement of the peripheral id register. for the usb peripheral, this is the value 0xfb. addresses: usb0_idcomp is 4007_2000h base + 4h offset = 4007_2004h bit 7 6 5 4 3 2 1 0 read 1 nid write reset 1 1 1 1 1 0 1 1 usb x o iel escritions fiel escrition resere his reaonly iel is resere an always has the alue one hese its always rea ones ones coleent o eriheral ientiication its eriheral reision reister u x r this register contains the revision number of the usb module. addresses: usb0_rev is 4007_2000h base + 8h offset = 4007_2008h bit 7 6 5 4 3 2 1 0 read rev write reset 0 0 1 1 0 0 1 1 usb x r iel escritions fiel escrition r reision nicate the reision nuer o the u ore eory areister einitions ufaily reerence anual re o freescale eiconuctor nc 45.4.4 peripheral additional info register (usb x fo the peripheral additional info register reads back the value of the fixed interrupt request level (irqnum) along with the host enable bit. if set to 1, the host enable bit indicates the usb peripheral is operating in host mode. addresses: usb0_addinfo is 4007_2000h base + ch offset = 4007_200ch bit 7 6 5 4 3 2 1 0 read irqnum 0 iehost write reset 0 0 0 0 0 0 0 1 usb x fo iel escritions fiel escrition ru ssine nterrut request uer resere his reaonly iel is resere an always has the alue ero ho his it is set i host oe is enale o nterrut tatus reister u x o the otg interrupt status register records changes of the id sense and vbus signals. software can read this register to determine which event has caused an interrupt. only bits that have changed since the last software read are set. writing a one to a bit clears the associated interrupt. addresses: usb0_otgistat is 4007_2000h base + 10h offset = 4007_2010h bit 7 6 5 4 3 2 1 0 read idchg onemsec line_ state_ chg 0 sessvldchg b_sess_chg 0 avbuschg write reset 0 0 0 0 0 0 0 0 usb x o iel escritions fiel escrition h his it is set when a chane in the inal ro the u connector is sense o his it is set when the illisecon tier exires his it stays asserte until cleare y sotware he interrut ust e serice eery illisecon to aoi losin sec counts table continues on the next page... chapter 4 universal serial bus t controller usbt 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1247 usb x o iel escritions continue fiel escrition l h his it is set when the u line state chanes he interrut associate with this it can e use to etect reset resue onnect an ata line ulse sinals resere his reaonly iel is resere an always has the alue ero lh his it is set when a chane in u is etecte inicatin a session ali or a session no loner ali h his it is set when a chane in u is etecte on a eice resere his reaonly iel is resere an always has the alue ero uh his it is set when a chane in u is etecte on an eice o nterrut ontrol reister u x or the otg interrupt control register enables the corresponding interrupt status bits defined in the otg interrupt status register. addresses: usb0_otgicr is 4007_2000h base + 14h offset = 4007_2014h bit 7 6 5 4 3 2 1 0 read iden onemsecen linestateen 0 sessvlden bsessen 0 avbusen write reset 0 0 0 0 0 0 0 0 usb x or iel escritions fiel escrition interrut enale he interrut is isale he interrut is enale o illisecon interrut enale he sec tier interrut is isale he sec tier interrut is enale l line tate chane interrut enale he lh interrut is isale he lh interrut is enale resere his reaonly iel is resere an always has the alue ero table continues on the next page... memory mapregister definitions 60 sub-family reference manual, rev. 6, nov 2011 1248 freescale semiconductor, inc. usb x or iel escritions continue fiel escrition l ession ali interrut enale he lh interrut is isale he lh interrut is enale ession interrut enale he h interrut is isale he h interrut is enale resere his reaonly iel is resere an always has the alue ero u u ali interrut enale he uh interrut is isale he uh interrut is enale o tatus reister u x o the otg status register displays the actual value from the external comparator outputs of the id pin and vbus. addresses: usb0_otgstat is 4007_2000h base + 18h offset = 4007_2018h bit 7 6 5 4 3 2 1 0 read id onemsecen linestatestable 0 sess_vld bsessend 0 avbusvld write reset 0 0 0 0 0 0 0 0 usb x o iel escritions fiel escrition nicates the current state o the in on the u connector nicates a ye cale has een lue into the u connector nicates no cale is attache or a ye cale has een lue into the u connector o his it is resere or the sec count ut it is not useul to sotware ll his it inicates that the internal sinals that control the lh it it o the o reister hae een stale or at least illisecon first rea the lh it an then rea this it this it reas as then the alue o lh can e consiere stale table continues on the next page... chapter 4 universal serial bus t controller usbt 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 124 usb x o iel escritions continue fiel escrition he lh it is not yet stale he lh it has een eounce an is stale resere his reaonly iel is resere an always has the alue ero l ession ali he u oltae is elow the session ali threshol he u oltae is aoe the session ali threshol ession he u oltae is aoe the session n threshol he u oltae is elow the session n threshol resere his reaonly iel is resere an always has the alue ero ul u ali he u oltae is elow the u ali threshol he u oltae is aoe the u ali threshol o ontrol reister u x ol the otg control register controls the operation of vbus and data line termination resistors. addresses: usb0_otgctl is 4007_2000h base + 1ch offset = 4007_201ch bit 7 6 5 4 3 2 1 0 read dphigh 0 dplow dmlow 0 otgen 0 write reset 0 0 0 0 0 0 0 0 usb x ol iel escritions fiel escrition hh ata line ullu resistor enale ullu resistor is not enale ullu resistor is enale resere his reaonly iel is resere an always has the alue ero lo ata line ullown resistor enale his it shoul always e enale toether with it lo table continues on the next page... memory mapregister definitions 60 sub-family reference manual, rev. 6, nov 2011 120 freescale semiconductor, inc. usb x ol iel escritions continue fiel escrition ullown resistor is not enale ullown resistor is enale lo ata line ullown resistor enale ullown resistor is not enale ullown resistor is enale resere his reaonly iel is resere an always has the alue ero o onheo ulluullown resistor enale u is set an hoo is clear in the ontrol reister l then the ata line ull u resistors are enale hoo is set the an ata line ullown resistors are enae he ullu an ullown controls in this reister are use resere his reaonly iel is resere an always has the alue ero nterrut tatus reister u x the interrupt status register contains bits for each of the interrupt sources within the usb module. each of these bits are qualified with their respective interrupt enable bits. all bits of this register are logically or'd together along with the otg interrupt status register (otgstat) to form a single interrupt source for the processor's interrupt controller. after an interrupt bit has been set it may only be cleared by writing a one to the respective interrupt bit. this register contains the value of 0x00 after a reset. addresses: usb0_istat is 4007_2000h base + 80h offset = 4007_2080h bit 7 6 5 4 3 2 1 0 read stall attach resume sleep tokdne softok error usbrst write w1c w1c w1c w1c w1c w1c w1c w1c reset 0 0 0 0 0 0 0 0 usb x iel escritions fiel escrition ll tall nterrut n aret oe this it is asserte when a ll hanshae is sent y the n host oe this it is set when the u oule etects a ll acnowlee urin the hanshae hase o a u transaction his interrut can e use to eterine is the last u transaction was colete successully or i it stalle h ttach nterrut table continues on the next page... chapter 4 universal serial bus t controller usbt 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 121 usb x iel escritions continue fiel escrition his it is set when the u oule etects an attach o a u eice his sinal is only ali i hoo is true his interrut siniies that a eriheral is now resent an ust e coniure ru his it is set eenin uon the sinals an can e use to sinal reote waeu sinalin on the u us hen not in susen oe this interrut shoul e isale l his it is set when the u oule etects a constant ile on the u us or illisecons he slee tier is reset y actiity on the u us o his it is set when the current toen ein rocesse has colete he rocessor shoul ieiately rea the reister to eterine the noint an use or this toen learin this it y writin a one causes the reister to e cleare or the holin reister to e loae into the reister ofo his it is set when the u oule receies a tart o frae of toen n host oe this it is set when the of threshol is reache so that sotware can reare or the next of rror his it is set when any o the error conitions within the rr reister occur he rocessor ust then rea the rr reister to eterine the source o the error ur his it is set when the u oule has ecoe a ali u reset his inors the icrorocessor that it shoul write x into the aress reister an enale enoint ur is set ater a u reset has een etecte or icrosecons t is not asserte aain until the u reset conition has een reoe an then reasserte nterrut nale reister u x the interrupt enable register contains enable bits for each of the interrupt sources within the usb module. setting any of these bits enables the respective interrupt source in the istat register. this register contains the value of 0x00 after a reset. addresses: usb0_inten is 4007_2000h base + 84h offset = 4007_2084h bit 7 6 5 4 3 2 1 0 read stallen attachen resumeen sleepen tokdneen softoken erroren usbrsten write reset 0 0 0 0 0 0 0 0 usb x iel escritions fiel escrition ll ll nterrut nale he ll interrut is not enale he ll interrut is enale h h nterrut nale he h interrut is not enale he h interrut is enale table continues on the next page... memory mapregister definitions 60 sub-family reference manual, rev. 6, nov 2011 122 freescale semiconductor, inc. usb x iel escritions continue fiel escrition ru ru nterrut nale he ru interrut is not enale he ru interrut is enale l l nterrut nale he l interrut is not enale he l interrut is enale o o nterrut nale he o interrut is not enale he o interrut is enale ofo ofo nterrut nale he ofo interrut is not enale he ofo interrut is enale rror rror nterrut nale he rror interrut is not enale he rror interrut is enale ur ur nterrut nale he ur interrut is not enale he ur interrut is enale rror nterrut tatus reister u x rr the error interrupt status register contains enable bits for each of the error sources within the usb module. each of these bits are qualified with their respective error enable bits. all bits of this register are logically or'd together and the result placed in the error bit of the istat register. after an interrupt bit has been set it may only be cleared by writing a one to the respective interrupt bit. each bit is set as soon as the error conditions is detected. therefore, the interrupt does not typically correspond with the end of a token being processed. this register contains the value of 0x00 after a reset. addresses: usb0_errstat is 4007_2000h base + 88h offset = 4007_2088h bit 7 6 5 4 3 2 1 0 read btserr 0 dmaerr btoerr dfn8 crc16 crc5eof piderr write w1c w1c w1c w1c w1c w1c w1c reset 0 0 0 0 0 0 0 0 chapter 45 universal serial bus otg controller (usbotg) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1253 usb x rr iel escritions fiel escrition rr his it is set when a it stu error is etecte set the corresonin acet is reecte ue to the error resere his reaonly iel is resere an always has the alue ero rr his it is set i the u oule has requeste a access to rea a new ut has not een ien the us eore it nees to receie or transit ata rocessin a transer this woul cause a transit ata unerlow conition rocessin a r transer this woul cause a receie ata oerlow conition his interrut is useul when eeloin eice aritration harware or the icrorocessor an the u oule to iniie us request an us rant latency his it is also set i a ata acet to or ro the host is larer than the uer sie allocate in the n this case the ata acet is truncate as it is ut into uer eory orr his it is set when a us turnaroun tieout error occurs he u oule contains a us turnaroun tier that ees trac o the aount o tie elase etween the toen an ata hases o a u or ou o or the ata an hanshae hases o a o ore than it ties are counte ro the reious o eore a transition ro l a us turnaroun tieout error occurs f his it is set i the ata iel receie was not its in lenth u eciication requires that ata iels e an interal nuer o ytes the ata iel was not an interal nuer o ytes this it is set r his it is set when a ata acet is reecte ue to a r error rof his error interrut has two unctions hen the u oule is oeratin in eriheral oe hoo this interrut etects r errors in the toen acets enerate y the host set the toen acet was reecte ue to a r error hen the u oule is oeratin in host oe hoo this interrut etects n o frae of error conitions his occurs when the u oule is transittin or receiin ata an the of counter reaches ero his interrut is useul when eeloin u acet scheulin sotware to ensure that no u transactions cross the start o the next rae rr his it is set when the chec iel ails rror nterrut nale reister u x rr the error interrupt enable register contains enable bits for each of the error interrupt sources within the usb module. setting any of these bits enables the respective interrupt source in the errstat register. each bit is set as soon as the error conditions is detected. therefore, the interrupt does not typically correspond with the end of a token being processed. this register contains the value of 0x00 after a reset. addresses: usb0_erren is 4007_2000h base + 8ch offset = 4007_208ch bit 7 6 5 4 3 2 1 0 read btserren 0 dmaerren btoerren dfn8en crc16en crc5eofen piderren write reset 0 0 0 0 0 0 0 0 memory map/register definitions k60 sub-family reference manual, rev. 6, nov 2011 1254 freescale semiconductor, inc. usb x rr iel escritions fiel escrition rr rr nterrut nale he rr interrut is not enale he rr interrut is enale resere his reaonly iel is resere an always has the alue ero rr rr nterrut nale he rr interrut is not enale he rr interrut is enale orr orr nterrut nale he orr interrut is not enale he orr interrut is enale f f nterrut nale he f interrut is not enale he f interrut is enale r r nterrut nale he r interrut is not enale he r interrut is enale rof rof nterrut nale he rof interrut is not enale he rof interrut is enale rr rr nterrut nale he rr interrut is not enale he rr interrut is enale hater uniersal erial us o ontroller uo ufaily reerence anual re o freescale eiconuctor nc 45.4.13 status register (usb x the status register reports the transaction status within the usb module. when the processor's interrupt controller has received a tokdne interrupt the status register should be read to determine the status of the previous endpoint communication. the data in the status register is valid when the tokdne interrupt bit is asserted. the stat register is actually a read window into a status fifo maintained by the usb module. when the usb module uses a bd, it updates the status register. if another usb transaction is performed before the tokdne interrupt is serviced, the usb module stores the status of the next transaction in the stat fifo. thus the stat register is actually a four byte fifo that allows the processor core to process one transaction while the sie is processing the next transaction. clearing the tokdne bit in the istat register causes the sie to update the stat register with the contents of the next stat value. if the data in the stat holding register is valid, the sie immediately reasserts to tokdne interrupt. addresses: usb0_stat is 4007_2000h base + 90h offset = 4007_2090h bit 7 6 5 4 3 2 1 0 read endp tx odd 0 write reset 0 0 0 0 0 0 0 0 usb x iel escritions fiel escrition his ourit iel encoes the enoint aress that receie or transitte the reious toen his allows the rocessor core to eterine which entry was uate y the last u transaction ransit nicator he ost recent transaction was a receie oeration he ost recent transaction was a ransit oeration o this it is set i the last uer escritor uate was in the o an o the resere his reaonly iel is resere an always has the alue ero eory areister einitions ufaily reerence anual re o freescale eiconuctor nc 45.4.14 control register (usb x l the control register provides various control and configuration information for the usb module. addresses: usb0_ctl is 4007_2000h base + 94h offset = 4007_2094h bit 7 6 5 4 3 2 1 0 read jstate se0 txsuspendtokenbusy reset hostmodeen resume oddrst usbensofen write reset 0 0 0 0 0 0 0 0 usb x l iel escritions fiel escrition lie u ierential receier sinal he olarity o this sinal is aecte y the current state o l lie u inle ne ero sinal uou hen the u oule is in host oe ou is set when the u oule is usy executin a u toen an no ore toen coans shoul e written to the oen reister otware shoul chec this it eore writin any toens to the oen reister to ensure that toen coans are not lost n aret oe u is set when the has isale acet transission an recetion learin this it allows the to continue toen rocessin his it is set y the when a etu oen is receie allowin sotware to equeue any enin acet transactions in the eore resuin toen rocessin r ettin this it enales the u oule to enerate u reset sinalin his allows the u oule to reset u eriherals his control sinal is only ali in host oe hoo otware ust set r to or the require aount o tie an then clear it to to en reset sinalin for ore inoration on r sinalin see ection o the u seciication ersion hoo hen set to this it enales the u oule to oerate in host oe n host oe the u oule erors u transactions uner the rorae control o the host rocessor ru hen set to this it enales the u oule to execute resue sinalin his allows the u oule to eror reote waeu otware ust set ru to or the require aount o tie an then clear it to the hoo it is set the u oule aens a low ee n o acet to the resue sinalin when the ru it is cleare for ore inoration on ru sinalin see ection o the u seciication ersion or ettin this it to resets all the o inon its to which then seciies the an table continues on the next page... chapter 4 universal serial bus t controller usbt 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 127 usb x l iel escritions continue fiel escrition uof u nale ettin this it causes the to reset all o its o its to the s hereore settin this it resets uch o the loic in the hen host oe is enale clearin this it causes the to sto senin of toens he u oule is isale he u oule is enale ress reister u x r the address register holds the unique usb address that the usb module decodes when in peripheral mode (hostmodeen=0). when operating in host mode (hostmodeen=1) the usb module transmits this address with a token packet. this enables the usb module to uniquely address an usb peripheral. in either mode, the usb_en bit within the control register must be set. the address register is reset to 0x00 after the reset input becomes active or the usb module decodes a usb reset signal. this action initializes the address register to decode address 0x00 as required by the usb specification. addresses: usb0_addr is 4007_2000h base + 98h offset = 4007_2098h bit 7 6 5 4 3 2 1 0 read lsen addr write reset 0 0 0 0 0 0 0 0 usb x r iel escritions fiel escrition l low ee nale it his it inors the u oule that the next toen coan written to the toen reister ust e erore at low see his enales the u oule to eror the necessary reale require or lowsee ata transissions r u aress his it alue eines the u aress that the u oule ecoes in eriheral oe or transit when in host oe eory areister einitions ufaily reerence anual re o freescale eiconuctor nc 45.4.16 bdt page register 1 (usb x the buffer descriptor table page register 1 provides address bits 15 through 9 of the base address where the current buffer descriptor table (bdt) resides in system memory. the 32-bit bdt base address is always aligned on 512-byte boundaries, so bits 8 through 0 of the base address are always taken as zero. addresses: usb0_bdtpage1 is 4007_2000h base + 9ch offset = 4007_209ch bit 7 6 5 4 3 2 1 0 read bdtba 0 write reset 0 0 0 0 0 0 0 0 usb x iel escritions fiel escrition his iel roies aress its throuh o the ase aress resere his reaonly iel is resere an always has the alue ero frae uer reister low u x frul the frame number register (low and high) contains an 11-bit value used to compute the address where the current buffer descriptor table (bdt) resides in system memory. addresses: usb0_frmnuml is 4007_2000h base + a0h offset = 4007_20a0h bit 7 6 5 4 3 2 1 0 read frm[7:0] write reset 0 0 0 0 0 0 0 0 usb x frul iel escritions fiel escrition fr: his it iel an the it iel in the frae uer reister hih are use to coute the aress where the current uer escritor ale resies in syste eory hater uniersal erial us o ontroller uo ufaily reerence anual re o freescale eiconuctor nc 45.4.18 frame number register high (usb x fruh the frame number register (low and high) contains an 11-bit value used to compute the address where the current buffer descriptor table (bdt) resides in system memory. addresses: usb0_frmnumh is 4007_2000h base + a4h offset = 4007_20a4h bit 7 6 5 4 3 2 1 0 read 0 frm[10:8] write reset 0 0 0 0 0 0 0 0 usb x fruh iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero fr: his it iel an the it iel in the frae uer reister low are use to coute the aress where the current uer escritor ale resies in syste eory oen reister u x o the token register is used to perform usb transactions when in host mode (hostmodeen=1). when the processor core wishes to execute a usb transaction to a peripheral, it writes the token type and endpoint to this register. after this register has been written, the usb module begins the specified usb transaction to the address contained in the address register. the processor core should always check that the token_busy bit in the control register is not set before performing a write to the token register. this ensures token commands are not overwritten before they can be executed. the address register and endpoint control register 0 are also used when performing a token command and therefore must also be written before the token register. the address register is used to correctly select the usb peripheral address transmitted by the token command. the endpoint control register determines the handshake and retry policies used during the transfer. addresses: usb0_token is 4007_2000h base + a8h offset = 4007_20a8h bit 7 6 5 4 3 2 1 0 read tokenpid tokenendpt write reset 0 0 0 0 0 0 0 0 memory map/register definitions k60 sub-family reference manual, rev. 6, nov 2011 1260 freescale semiconductor, inc. usb x o iel escritions fiel escrition o his it iel contains the toen tye execute y the u oule ou oen u oule erors an ou transaction oen u oule erors an n r transaction u oen u oule erors a u transaction o his it iel hols the noint aress or the toen coan he our it alue written ust e a ali enoint of hreshol reister u x ofhl the sof threshold register is used only in hosts mode (hostmodeen=1). when in host mode, the 14-bit sof counter counts the interval between sof frames. the sof must be transmitted every 1msec so the sof counter is loaded with a value of 12000. when the sof counter reaches zero, a start of frame (sof) token is transmitted. the sof threshold register is used to program the number of usb byte times before the sof to stop initiating token packet transactions. this register must be set to a value that ensures that other packets are not actively being transmitted when the sof time counts to zero. when the sof counter reaches the threshold value, no more tokens are transmitted until after the sof ha been transmitted. the value programmed into the threshold register must reserve enough time to ensure the worst case transaction completes. in general the worst case transaction is a in token followed by a data packet from the target followed by the response from the host. the actual time required is a function of the maximum packet size on the bus. typical values for the sof threshold are: 64-byte packets=74; 32-byte packets=42; 16-byte packets=26; 8-byte packets=18. addresses: usb0_softhld is 4007_2000h base + ach offset = 4007_20ach bit 7 6 5 4 3 2 1 0 read cnt write reset 0 0 0 0 0 0 0 0 usb x ofhl iel escritions fiel escrition his it iel reresents the of count threshol in yte ties hater uniersal erial us o ontroller uo ufaily reerence anual re o freescale eiconuctor nc 45.4.21 bdt page register 2 (usb x the buffer descriptor table page register 2 contains an 8-bit value used to compute the address where the current buffer descriptor table (bdt) resides in system memory. addresses: usb0_bdtpage2 is 4007_2000h base + b0h offset = 4007_20b0h bit 7 6 5 4 3 2 1 0 read bdtba write reset 0 0 0 0 0 0 0 0 usb x iel escritions fiel escrition his it iel roies aress its throuh o the ase aress which eines where the uer escritor ale resies in syste eory ae reister u x the buffer descriptor table page register 3 contains an 8-bit value used to compute the address where the current buffer descriptor table (bdt) resides in system memory. addresses: usb0_bdtpage3 is 4007_2000h base + b4h offset = 4007_20b4h bit 7 6 5 4 3 2 1 0 read bdtba write reset 0 0 0 0 0 0 0 0 usb x iel escritions fiel escrition his it iel roies aress its throuh o the ase aress which eines where the uer escritor ale resies in syste eory noint ontrol reister u x n the endpoint control registers contain the endpoint control bits for each of the 16 endpoints available within the usb module for a decoded address. the format for these registers is shown in the following figure. endpoint 0 (endpt0) is associated with control pipe 0, which is required for all usb functions. therefore, after a usbrst interrupt occurs the processor core should set the endpt0 register to contain 0x0d. memory map/register definitions k60 sub-family reference manual, rev. 6, nov 2011 1262 freescale semiconductor, inc. in host mode endpt0 is used to determine the handshake, retry and low speed characteristics of the host transfer. for host mode control, bulk and interrupt transfers the ephshk bit should be set to 1. for isochronous transfers it should be set to 0. common values to use for endpt0 in host mode are 0x4d for control, bulk, and interrupt transfers, and 0x4c for isochronous transfers. addresses: 4007_2000h base + c0h offset + (4d n , where n 0d to 1d bit 7 6 4 2 1 0 read hstwhub retrdis 0 epctdis eprxen eptxen epsta ephsh write reset 0 0 0 0 0 0 0 0 usb x n iel escritions fiel escrition hoohu his is a host oe only it an is only resent in the control reister or enoint hen set this it allows the host to counicate to a irectly connecte low see eice hen cleare the host rouces the r then switch to low see sinalin when senin a toen to a low see eice as require to counicate with a low see eice throuh a hu rr his is a host oe only it an is only resent in the control reister or enoint hen set this it causes the host to not retry e eatie cnowleeent transactions hen a transaction is e the iel is uate with the an the o interrut is set hen this it is cleare e transactions is retrie in harware his it ust e set when the host is attetin to oll an interrut enoint resere his reaonly iel is resere an always has the alue ero l his it when set isales control u transers hen cleare control transers are enale his alies i an only i the r an its are also set r his it when set enales the enoint or r transers his it when set enales the enoint or transers ll hen set this it inicates that the enoint is calle his it has riority oer all other control its in the noint nale reister ut it is only ali i or r ny access to this enoint causes the u oule to return a ll hanshae ter an enoint is stalle it requires interention ro the host ontroller hh hen set this et enales an enoint to eror hanshain urin a transaction to this enoint his it is enerally set unless the enoint is sochronous hater uniersal erial us o ontroller uo ufaily reerence anual re o freescale eiconuctor nc 45.4.24 usb control register (usb x url resses: uurl is h ase h oset h it rea u rite reset u x url iel escritions fiel escrition u laces the u transceier into the susen state u transceier is not in susen state u transceier is in susen state nales the wea ullowns on the u transceier ea ullowns are isale on an ea ullowns are enale on an resere his reaonly iel is resere an always has the alue ero u o osere reister u x or provides visibility on the state of the pull-ups and pull-downs at the transceiver. useful when interfacing to an external otg control module via a serial interface. addresses: usb0_observe is 4007_2000h base + 104h offset = 4007_2104h bit 7 6 5 4 3 2 1 0 read dppu dppd 0 dmpd 0 0 write reset 0 1 0 1 0 0 0 0 usb x or iel escritions fiel escrition u roies oseraility o the ull u sinal outut ro the u o oule ullu isale ullu enale roies oseraility o the ull own sinal outut ro the u o oule ullown isale ullown enale table continues on the next page... memory mapregister definitions 60 sub-family reference manual, rev. 6, nov 2011 1264 freescale semiconductor, inc. usb x or iel escritions continue fiel escrition resere his reaonly iel is resere an always has the alue ero roies oseraility o the ull own sinal outut ro the u o oule ullown isale ullown enale resere his reaonly iel is resere an always has the alue ero resere his reaonly iel is resere an always has the alue ero u o ontrol reister u x orol resses: uorol is h ase h oset h it rea ulluoo rite reset u x orol iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero ulluoo roies control o the ullu in the u o oule i u is coniure in nono eice oe ull u in nono eice oe is not enale ull u in nono eice oe is enale resere his reaonly iel is resere an always has the alue ero hater uniersal erial us o ontroller uo ufaily reerence anual re o freescale eiconuctor nc 45.4.27 usb transceiver control register 0 (usb x ur resses: uur is h ase h oset h it rea ur u ru rite ur reset u x ur iel escritions fiel escrition ur u reset enerates a har reset to the uo oule ter this it is set an the reset occurs this it is autoatically cleare o: t is always rea as ero oral u oule oeration returns the u oule to its reset state resere his iel is resere o: otware ust set this it to ur synchronous resue nterrut nale his it when set allows the u oule to sen an asynchronous waeu eent to the u uon etection o resue sinalin on the u us he u then reenales clocs to the u oule t is use or lowower susen oe when u oule clocs are stoe or the u transceier is in usen oe sync waeu only wors in eice oe u asynchronous waeu ro susen oe isale u asynchronous waeu ro susen oe enale he asynchronous resue interrut iers ro the synchronous resue interrut in that it asynchronously etects state usin the uniltere state o the an ins his interut shoul only e enale when the ransceier is susene resere his reaonly iel is resere an always has the alue ero ynchronous u nterrut etect ynchronous interrut has not een etecte ynchronous interrut has een etecte uru u synchronous nterrut o interrut was enerate nterrut was enerate ecause o the u asynchronous interrut eory areister einitions ufaily reerence anual re o freescale eiconuctor nc 45.5 otg and host mode operation the host mode logic allows devices such as digital cameras and palmtop computers to function as a usb host controller. the otg logic adds an interface to allow the otg host negotiation and session request protocols (hnp and srp) to be implemented in software. host mode allows a peripheral such as a digital camera to be connected directly to a usb compliant printer. digital photos can then be easily printed without having to upload them to a pc. in the palmtop computer application, a usb compliant keyboard/ mouse can be connected to the palmtop computer with the obvious advantages of easier interaction. host mode is intended for use in handheld-portable devices to allow easy connection to simple hid class devices such as printers and keyboards. it is not intended to perform the functions of a full ohci or uhci compatible host controller found on pc motherboards. the usb-fs is not supported by windows 98 as a usb host controller. host mode allows bulk, isochronous, interrupt and control transfers. bulk data transfers are performed at nearly the full usb bus bandwidth. support is provided for iso transfers, but the number of iso streams that can be practically supported is affected by the interrupt latency of the processor servicing the token during interrupts from the sie. custom drivers must be written to support host mode operation. setting the host_mode_en bit in the ctl register enables host mode. the usb-fs core can only operate as a peripheral device or in host mode. it cannot operate in both modes simultaneously. when host_mode is enabled, only endpoint zero is used. all other endpoints should be disabled by software. 45.6 host mode operation examples the following sections illustrate the steps required to perform usb host functions using the usb-fs core. while it is useful to understand the interaction of the hardware and the software at a detailed level, an understanding of the interactions at this level is not required to write host applications using the api software. to enable host mode and discover a connected device: 1. enable host mode (ctl[host_mode_en]=1). the pull-down resistors are enabled, and pull-up disabled. start of frame (sof) generation begins. sof counter loaded with 12,000. disable sof packet generation to eliminate noise on the usb by writing the usb enable bit to 0 (ctl[usb_en]=0). chapter 45 universal serial bus otg controller (usbotg) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1267 2. enable the attach interrupt (int_enb[attach]=1). 3. wait for attach interrupt (int_stat[attach]). signaled by usb target pull- up resistor changing the state of dplus or dminus from 0 to 1 (se0 to j or k state). 4. check the state of the jstate and se0 bits in the control register. if the connecting device is low speed (jstate bit is 0), set the low-speed bit in the address registers (addr[ls_en]=1) and the host without hub bit in endpoint 0 register control (ep_ctl0[host_wo_hub]=1). 5. enable reset (ctl[reset]=1) for 10 ms. 6. enable sof packet to keep the connected device from going to suspend (ctl[usb_en=1]). 7. start enumeration by sending a sequence of device framework commands, device frame work packets to the default control pipe of the connected device. refer to the universal serial bus revision 2.0 specification, "chapter 9 usb device framework" (http://www.usb.org/developers/docs). to complete a control transaction to a connected device: 1. complete all steps discover a connected device 2. set up the endpoint control register for bidirectional control transfers ep_ctl0[4:0] = 0x0d. 3. place a copy of the device framework setup command in a memory buffer. refer to the universal serial bus revision 2.0 specification, "chapter 9 usb device framework" (http://www.usb.org/developers/docs). 4. initialize current (even or odd) tx ep0 bdt to transfer the 8 bytes of command data for a device framework command (for example, a get device descriptor). ? set the bdt command word to 0x00080080 Cbyte count to 8, own bit to 1. ? set the bdt buffer address field to the start address of the 8 byte command buffer. 5. set the usb device address of the target device in the address register (addr[6:0]). after the usb bus reset, the device usb address is zero. it is set to some other value (usually 1) by the set address device framework command. 6. write the token register with a setup to endpoint 0 the target device default control pipe (token=0xd0). this initiates a setup token on the bus followed by a data packet. the device handshake is returned in the bdt pid field after the packets host mode operation examples k60 sub-family reference manual, rev. 6, nov 2011 1268 freescale semiconductor, inc. complete. when the bdt is written a token done (int_stat[tok_dne]) interrupt is asserted. this completes the setup phase of the setup transaction. refer to the universal serial bus revision 2.0 specification, "chapter 9 usb device framework" (http://www.usb.org/developers/docs). 7. to initiate the data phase of the setup transaction (for example, get the data for the get device descriptor command) set up a buffer in memory for the data to be transferred. 8. initialize the current (even or odd) tx ep0 bdt to transfer the data. ? set the bdt command word to 0x004000c0 Cbyte count to the length of the data buffer in this case 64, own bit to 1, data toggle to data1. ? set the bdt buffer address field to the start address of the data buffer 9. write the token register with a in or out token to endpoint 0 the target device default control pipe, an in token for a get device descriptor command (token=0x90). this initiates an in token on the bus followed by a data packet from the device to the host. when the data packet completes the bdt is written and a token done (int_stat[tok_dne]) interrupt is asserted. for control transfers with a single packet data phase this completes the data phase of the setup transaction. refer to the universal serial bus revision 2.0 specification, "chapter 9 usb device framework" (http://www.usb.org/developers/docs). 10. to initiate the status phase of the setup transaction set up a buffer in memory to receive or send the zero length status phase data packet. 11. initialize the current (even or odd) tx ep0 bdt to transfer the status data. ? set the bdt command word to 0x00000080 Cbyte count to the length of the data buffer in this case 0, own bit to 1, data toggle to data0. ? set the bdt buffer address field to the start address of the data buffer 12. write the token register with a in or out token to endpoint 0 the target device default control pipe, an out token for a get device descriptor command (token=0x10). this initiates an out token on the bus followed by a zero length data packet from the host to the device. when the data packet completes the bdt is written with the handshake form the device and a token done (int_stat[tok_dne]) interrupt is asserted. this completes the data phase of the setup transaction. refer to the universal serial bus revision 2.0 specification, "chapter 9 usb device framework" (http://www.usb.org/developers/docs). to send a full speed bulk data transfer to a target device: chapter 45 universal serial bus otg controller (usbotg) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1269 1. complete all steps discover a connected device and to configure a connected device. write the addr register with the address of the target device. typically, there is only one other device on the usb bus in host mode so it is expected that the address is 0x01 and should remain constant. 2. write the endpt0 to 0x1d register to enable transmit and receive transfers with handshaking enabled. 3. setup the even tx ep0 bdt to transfer up to 64 bytes. 4. set the usb device address of the target device in the address register (addr[6:0]). 5. write the token register with an out token to the desired endpoint. the write to this register triggers the usb-fs transmit state machines to begin transmitting the token and the data. 6. setup the odd tx ep0 bdt to transfer up to 64 bytes. 7. write the token register with an out token as in step 4. two tokens can be queued at a time to allow the packets to be double buffered to achieve maximum throughput. 8. wait for the tok_dne interrupt. this indicates one of the bdts has been released back to the microprocessor and that the transfer has completed. if the target device asserts naks, the usb-fs continues to retry the transfer indefinitely without processor intervention unless the retry_dis retry disable bit is set in the ep0 control register. if the retry disable bit is set, the handshake (ack, nak, stall, or error (0xf)) is returned in the bdt pid field. if a stall interrupt occurs, the pending packet must be dequeued and the error condition in the target device cleared. if a reset interrupt occurs (se0 for more than 2.5us), the target has detached. 9. after the tok_dne interrupt occurs, the bdts can be examined and the next data packet queued by returning to step 2. 45.7 on-the-go operation the usb-otg core provides sensors and controls to enable on-the-go (otg) operation. these sensors are used by the otg api software to implement the host negotiation protocol (hnp) and session request protocol (srp). api calls are provided to give access the otg protocol control signals, and include the otg capabilities in the device application. the following state machines show the otg operations involved with hnp and srp protocols from either end of the usb cable. on-the-go operation k60 sub-family reference manual, rev. 6, nov 2011 1270 freescale semiconductor, inc. 45.7.1 otg dual role a device operation a device is considered the a device because of the type of cable attached. if the usb type a connector or the usb type mini a connector is plugged into the device, he is considered the a device. a dual role a device operates as the following flow diagram and state description table illustrates. a_idle a_wait_vfall a_wait_vrise a_peripheral a_suspend b_idle a_wait_bcon a_host figure 45-91. dual role a device flow diagram table 45-94. state descriptions for the dual role a device flow state action response a_idle if id interrupt. the cable has been un-plugged or a type b cable has been attached. the device now acts as a type b device. go to b_idle if the a application wants to use the bus or if the b device is doing an srp as indicated by an a_sess_vld interrupt or attach or port status change interrupt check data line for 5 ?10 msec pulsing. go to a_wait_vrise turn on drv_vbus a_wait_vrise if id interrupt or if a_vbus_vld is false after 100 msec the cable has been changed or the a device cannot support the current required from the b device. go to a_wait_vfall turn off drv_vbus if a_vbus_vld interrupt go to a_wait_bcon table continues on the next page... chapter 4 universal serial bus t controller usbt 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1271 table 45-94. state descriptions for the dual role a device flow (continued) state action response a_wait_bcon after 200 msec without attach or id interrupt. (this could wait forever if desired.) go to a_wait_fall turn off drv_vbus a_vbus_vld interrupt and b device attaches go to a_host turn on host mode a_host enumerate device determine otg support. if a_vbus_vld/ interrupt or a device is done and doesnt think he wants to do something soon or the b device disconnects go to a_wait_vfall turn off host mode turn off drv_vbus if the a device is finished with session or if the a device wants to allow the b device to take bus. go to a_suspend id interrupt or the b device disconnects go to a_wait_bcon a_suspend if id interrupt, or if 150 msec b disconnect timeout (this timeout value could be longer) or if a_vbus_vld\ interrupt go to a_wait_vfall turn off drv_vbus if hnp enabled, and b disconnects in 150 msec then b device is becoming the host. go to a_peripheral turn off host mode if a wants to start another session go to a_host a_peripheral if id interrupt or if a_vbus_vld interrupt go to a_wait_vfall turn off drv_vbus. if 3 200 msec of bus idle go to a_wait_bcon turn on host mode a_wait_vfall if id interrupt or (a_sess_vld/ & b_conn/) go to a_idle 45.7.2 otg dual role b device operation a device is considered a b device if it connected to the bus with a usb type b cable or a usb type mini b cable. a dual role b device operates as the following flow diagram and state description table illustrates. on-the-go operation k60 sub-family reference manual, rev. 6, nov 2011 1272 freescale semiconductor, inc. b_idle b_host b_srp_init b_wait_acon a_idle b_peripheral figure 45-92. dual role b device flow diagram table 45-95. state descriptions for the dual role b device flow state action response b_idle if id\ interrupt. a type a cable has been plugged in and the device should now respond as a type a device. go to a_idle if b_sess_vld interrupt. the a device has turned on vbus and begins a session. go to b_peripheral turn on dp_high if b application wants the bus and bus is idle for 2 ms and the b_sess_end bit is set, the b device can perform an srp. go to b_srp_init pulse chrg_vbus pulse dp_high 5-10 ms b_srp_init if id\ interrupt or srp done (srp must be done in less than 100 msecs.) go to b_idle b_peripheral if hnp enabled and the bus is suspended and b wants the bus, the b device can become the host. go to b_wait_acon turn off dp_high b_wait_acon if a connects, an attach interrupt is received go to b_host turn on host mode if id\ interrupt or b_sess_vld/ interrupt if the cable changes or if vbus goes away, the host doesnt support us. go to b_idle go to b_idle if 3.125 ms expires or if a resume occurs go to b_peripheral b_host if id\ interrupt or b_sess_vld\ interrupt if the cable changes or if vbus goes away, the host doesnt support us. go to b_idle if b application is done or a disconnects go to b_peripheral chapter 45 universal serial bus otg controller (usbotg) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1273 on-the-go operation k60 sub-family reference manual, rev. 6, nov 2011 1274 freescale semiconductor, inc. chapter 46 usb device charger detection module (usbdcd) 46.1 preface 46.1.1 references the following publications are referenced in this document. for updates to these specifications, see http://www.usb.org. ? usb battery charging specification revision 1.1, usb implementers forum ? universal serial bus specification revision 2.0, usb implementers forum .1.2 acronyms and abbreviations the following table contains acronyms and abbreviations used in this document. table 46-1. acronyms and abbreviated terms term meaning fs full speed (12 mbps) hs high speed (480 mbps) i dev_dchg current drawn when the usb device is connected to a dedicated charging port i dev_hchg_lfs current drawn when the usb device is connected to an fs charging host port i dm_sink current sink for the d- line i dp_src current source for the d+ line i susp current drawn when the usb device is suspended ldo low dropout ls low speed (1.5 mbps) n/a not applicable table continues on the next page... 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 127 table 46-1. acronyms and abbreviated terms (continued) term meaning otg on-the-go r dm_dwn d- pulldown resistance for data pin contact detect v dat_ref data detect reference voltage for the voltage comparator v dp_src voltage source for the d+ line v lgc threshold voltage for logic high 46.1.3 glossary the following table shows a glossary of terms used in this document. table 46-2. glossary of terms term definition transceiver module that implements the physical layer of the usb standard (fs or ls only) phy module that implements the physical layer of the usb standard (hs capable) attached device is physically plugged into usb port but has not enabled either d or d- pullup resistor connected device is physically plugged into usb port and has enabled either d or d- pullup resistor suspended after ms of no bus activity the usb device enters suspend mode. component the hardware and software that mae up a subsystem. 46.2 introduction nte for the chip-specific implementation details of this module's instances see the chip configuration chapter. the usbdcd module works with the usb transceiver to detect if the usb device is attached to a charging port (either a dedicated charging port or a charging host). system software coordinates the detection activites of the module and controls an off-chip integrated circuit that performs the battery charging. 46.2.1 block diagram the following figure is a high level block diagram of the module. introduction k60 sub-family reference manual, rev. 6, nov 2011 1276 freescale semiconductor, inc. digital block analog block voltage comparator control and feedback clk reset bus state of d- state of d+ analog control unit timer unit bus interface & registers current source current sink d+ d- voltage source d- pulldown enable figure 46-1. block diagram the usbdcd module consists of 2 main blocks: ? a digital block provides the programming interface (memory-mapped registers) and includes the timer unit and the analog control unit. ? an analog block provides the circuitry for the physical detection of the charger, including the voltage source, current source, current sink, and voltage comparator circuitry. 46.2.2 features the usbdcd module offers the following features: ? compliant with the latest industry standard specification: usb battery charging specification, revision 1.1 ? programmable timing parameters default to values required by the industry standards: ? having standard default values allows for minimal configuration: set the clock frequency before enabling the module. ? programmability allows for flexibility to meet future udpates to the standards. 46.2.3 modes of operation the usbdcd module operating modes are shown in the following table. chapter 46 usb device charger detection module (usbdcd) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1277 table 46-3. module modes and their conditions module mode description conditions when used enabled the module performs the charger detection sequence. system software should enable the module only when all of the following conditions are true the system uses a rechargeable battery. the device is being used in an fs usb device application. the device has detected that it is attached to the usb cable. disabled the module is not active and is held in a low power state. system software should disable the module when either of the following conditions is true the charger detect seuence is complete. the conditions for being enabled are not met. powered ff the digital supply voltage dvdd is removed. ptionally, the analog supply voltage avdd also may be reduced to as low as 1.7v without causing excess leaage. ow system performance reuirements allow putting the device into a very low-power stop mode. operating mode transitions are shown in the following table. table 46-4. entering and exiting module modes module mode entering exiting mode after exiting enabled set the control[start] bit. set the control[sr] bit. 1 disabled disabled take either of the following actions set the cntrsr bit. 1 reset the module. the module is disabled out of reset by default. set the cntrstart bit. enabled powered ff perform the following actions 1. put the device into very low-power stop mode. 2. adust the supply voltages. perform the following actions 1. restore the supply voltages. 2. tae the device out of very low-power stop mode. disabled 1. the effect of setting the sr bit is immediate that is, the module is disabled even if the seuence has not completed. 46. module signal description this section describes the module signals. module signal description k60 sub-family reference manual, rev. 6, nov 2011 1278 freescale semiconductor, inc. 46.3.1 usb signal descriptions the following table shows a summary of module signals that interface with the device's pins. table 46-5. usb signal descriptions signal description i/o usb_dm usb d- analog data signal. the analog block interfaces directly to the d- signal on the usb bus. i/o usb_dp usb d+ analog data signal. the analog block interfaces directly to the d+ signal on the usb bus. i/o avdd33 1 3.3v regulated analog supply i avss analog ground i dvss digital ground i dvdd 1.2 v digital supply i 1. voltage must be 3.3v +/- 10% for full functionality of the module. that is, the charger detection function does not work when this voltage is below 3.0v, and the control[start] bit should not be set. note the transceiver module also interfaces to usb_dm and usb_dp. both modules and the usb host/hub use these signal as bi- directional, tri-state signals. information about the signal integrity aspects of the lines including shielding, isolated return paths, input or output impedance, packaging, suggested external components, esd, and other protections can be found in the usb 2.0 specification and in application information . 46.4 memory map/register definition this section describes the memory map and registers for the usbdcd module. usbdcd memory map absolute address (hex) register name width (in bits) access reset value section/ page 4003_5000 usbdcd_control 32 r/w 0001_0000h 46.4.1/ 1280 4003_5004 clock register (usbdcd_clock) 32 r/w 0000_00c1h 46.4.2/ 1281 table continues on the next page... chapter 46 usb device charger detection module usbdcd 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 127 usbdcd memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4003_5008 status register (usbdcd_status) 32 r 0000_0000h 46.4.3/ 1282 4003_5010 timer0 register (usbdcd_timer0) 32 r/w 0010_0000h 46.4.4/ 1284 4003_5014 usbdcd_timer1 32 r/w 000a_0028h 46.4.5/ 1285 4003_5018 usbdcd_timer2 32 r/w 0028_0001h 46.4.6/ 1285 46.4.1 control register (usbdcd_control) contains the control and interrupt bit fields. address: usbdcd_control is 4003_5000h base + 0h offset = 4003_5000h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 ie w sr start reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r reserved if 0 0 w iack reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 usbdcd_control field descriptions field description 31?26 reserved this read-only field is reserved and always has the value zero. 25 sr software reset determines whether a software reset is performed. 0 do not perform a software reset. 1 perform a software reset. 24 start start change detection sequence table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 1280 freescale semiconductor, inc. usbdcd_control field descriptions (continued) field description determines whether the charger detection sequence is initiated. 0b0 do not start the sequence. writes of this value have no effect. 0b1 initiate the charger detection sequence. if the sequence is already running, writes of this value have no effect. 2317 reserved this read-only field is reserved and always has the value zero. 16 ie interrupt enable enables/disables interrupts to the system. 0b0 disable interrupts to the system. 0b1 enable interrupts to the system. 159 reserved this field is reserved. 8 if interrupt flag determines whether an interrupt is pending 0b0 no interrupt is pending. 0b1 an interrupt is pending. 71 reserved this read-only field is reserved and always has the value zero. 0 iack interrupt acknowledge determines whether the interrupt is cleared. 0b0 do not clear the interrupt. 0b1 clear the if bit (interrupt flag). 46.4.2 clock register (usbdcd_clock) address: usbdcd_clock is 4003_5000h base + 4h offset = 4003_5004h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 clock_speed 0 clock_ unit w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 chapter 46 usb device charger detection module (usbdcd) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1281 usbdcd_clock field descriptions field description 3112 reserved this read-only field is reserved and always has the value zero. 112 clock_speed numerical value of clock speed in binary the unit of measure is programmed in clock_unit. the valid range is from 1 to 1023 when clock unit is mhz and 4 to 1023 when clock unit is khz. examples with clock_unit = 1: ? for 48 mhz: 0b00_0011_0000 (48) (default) ? for 24 mhz: 0b00_0001_1000 (24) examples with clock_unit = 0: ? for 100 khz: 0b00_0110_0100 (100) ? for 500 khz: 0b01_1111_0100 (500) 1 reserved this read-only field is reserved and always has the value zero. 0 clock_unit unit of measurement encoding for clock speed specifies the unit of measure for the clock speed. 0b0 khz speed (between 1 khz and 1023 khz) 0b1 mhz speed (between 1 mhz and 1023 mhz) 46.4.3 status register (usbdcd_status) the status register provides the current state of the module for system software monitoring. address: usbdcd_status is 4003_5000h base + 8h offset = 4003_5008h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 active to err seq_stat seq_res w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r reserved w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1282 freescale semiconductor, inc. usbdcd_status field descriptions field description 3123 reserved this read-only field is reserved and always has the value zero. 22 active active status indicator indicates whether the sequence is running. 0b0 the sequence is not running. 0b1 the sequence is running. 21 to timeout flag indicates whether the detection sequence has passed the timeout threshhold. 0b0 the detection sequence has not been running for over 1 s. 0b1 it has been over 1 s since the data pin contact was detected and debounced.{ 20 err error flag indicates whether there is an error in the detection sequence. 0b0 no sequence errors. 0b1 error in the detection sequence. see the seq_stat field to determine the phase in which the error occurred. 1918 seq_stat charger detection sequence status indicates the status of the charger detection sequence. 0b00 the module is either not enabled, or the module is enabled but the data pins have not yet been detected. 0b01 data pin contact detection is complete. 0b10 charger detection is complete. 0b11 charger type detection is complete. 1716 seq_res charger detection sequence results reports how charger detection is attached. 0b00 no results to report. 0b01 attached to a standard host. must comply with usb spec 2.0 by drawing only 2.5ma (max) until connected. 0b10 attached to a charging port. the exact meaning depends on bit 18: 0: attached to either a charging host or a dedicated charger (the charger type detection has not completed.) 1: attached to a charging host (the charger type detection has completed.) 0b11 attached to a dedicated charger. 150 reserved this field is reserved. note: bits do not always read as 0. chapter 46 usb device charger detection module (usbdcd) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1283 46.4.4 timer0 register (usbdcd_timer0) timer0 has an tseq_init field that represents the system latency (in ms) measured from the time vbus goes active to the time system software initiates the charger detection sequence in the usbdcd module. when software sets the control[start] bit, the unit connection timer (tunitcon) is initialized with the value of tseq_init. valid values are 0-1023, however the usb battery charging specification requires the entire sequence, including tseq_init, to be completed in 1s or less. address: usbdcd_timer0 is 4003_5000h base + 10h offset = 4003_5010h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 tseq_init 0 tunitcon w reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 usbdcd_timer0 field descriptions field description 31?26 reserved this read-only field is reserved and always has the value zero. 25?16 tseq_init sequence initiation time tseq_init represents the system latency (in ms) measured from the time vbus goes active to the time system software initiates the charger detection sequence in the usbdcd module. when software sets the control[start] bit, the unit connection timer (tunitcon) is initialized with the value of tseq_init. valid values are 0-1023, but the usb battery charging specification requires the entire sequence, including tseq_init, to be completed in 1s or less. 15?12 reserved this read-only field is reserved and always has the value zero. 11?0 tunitcon unit connection timer elapse (in ms) displays the current elapsed time since software set the control[start] bit plus the value of tseq_init. the timer is initially loaded with the value of tseq_init before starting to count. this timer enables compliance with the maximum time allowed to connect (tunit_con) under the usb battery charging specification, v1.1.if the timer reaches the tunit_con one second limit, the module triggers an interrupt and sets the error flag status[err]. the timer continues counting throughout the charger detection sequence, even when control has been passed to software. as long as the module is active, the timer continues to count until it reaches the maximum value of 0xfff (4095 ms). the timer does not rollover to zero. a software reset clears the timer. memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1284 freescale semiconductor, inc. 46.4.5 usbdcd_timer1 address: usbdcd_timer1 is 4003_5000h base + 14h offset = 4003_5014h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 tdcd_dbnc 0 tvdpsrc_on w reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 usbdcd_timer1 field descriptions field description 3126 reserved this read-only field is reserved and always has the value zero. 2516 tdcd_dbnc time period to debounce d+ signal sets the amount of time (in ms) to debounce the d+ signal during the data pin contact detection phase (while idp_src and rdm_dwn are enabled). valid values are 1-1023, but the usb battery charging specification requires a minimum value of 10 ms. 1510 reserved this read-only field is reserved and always has the value zero. 90 tvdpsrc_on time period comparator enabled sets the amount of time (in ms) that vdp_src, idm_sink, and the d-/vdat_ref comparator are enabled and connected to the d+/d- lines during the charging port detection phase of the sequence. valid values are 1-1023, but the usb battery charging specification requires a minimum value of 40 ms. 46.4.6 usbdcd_timer2 timer2 contains timing parameters. note that register values can be written that are not compliant with the usb battery charging specification v1.1, so care should be taken when overwriting the default values. address: usbdcd_timer2 is 4003_5000h base + 18h offset = 4003_5018h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 tvdpsrc_con 0 check_dm w reset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 usbdcd_timer2 field descriptions field description 31?26 reserved this read-only field is reserved and always has the value zero. table continues on the next page... chapter 46 usb device charger detection module usbdcd 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 128 usbdcd_timer2 field descriptions (continued) field description 2516 tvdpsrc_con time period before enabling d+ pullup sets the amount of time (in ms) that the module waits after charging port detection before system software should enable the d+ pullup to connect to the usb host. valid values are 1-1023, but the usb battery charging specification requires a minimum value of 40 ms. 154 reserved this read-only field is reserved and always has the value zero. 30 check_dm time before check of d- line sets the amount of time (in ms) that the module waits after the device connects to the usb bus (software enables the d+ pullup) until checking the state of the d- line to determine the type of charging port. valid values are 1-15ms. 46.5 functional description the sequence of detecting the presence of and type of charging port involves several hardware components, coordinated by system software. this collection of interacting hardware and software is called the usb battery charging subsystem. the following figure shows the usbdcd module as a component of the subsystem. the following table describes the components. usbdcd module control and status system software device control battery charger ic system interrupt connector usb transceiver pullup enable command charge rate comm vbus_detect pulldown enable d usb controller usb bus d vbus standard host port dedicated charger or or charging host port d d pullup enable module figure 46-8. the usb battery charging subsystem functional description 60 sub-family reference manual, rev. 6, nov 2011 1286 freescale semiconductor, inc. table 46-13. usb battery charger subsystem components component description battery charger ic the external battery charger ic regulates the charge rate to the rechargable battery. system software is responsible for communicating the appropriate charge rates. charger maximum current drawn 1 standard host port up to 500 ma charging host port up to 1500 ma dedicated charging port up to 1800 ma 1. if the usb host has suspended the usb device, system software must configure the system to limit the current drawn from the usb bus to 2.5 ma or less. comm module a communications module on the device can be used to control the charge rate of the battery charger ic. system software coordinates the detection activities of the subsystem. usb controller the d+ pullup enable control signal plays a role during the charger type detection phase. system software must issue a command to the usb controller to assert this signal. once this pullup is enabled, the device is considered to be connected to the usb bus. the host then attempts to enumerate it. note that the usb controller must be used only for usb device applications when using the usbdcd module. for usb host applications the usbdcd module must be disabled. usb transceiver the usb transceiver contains the pullup resistor for the usb d signal and the pulldown resistors for the usb d and d- signals. the d pullup and the d- pulldown are both used during the charger detection seuence. the usb transceiver also outputs the digital state of the d and d- signals from the usb bus. the pullup and pulldown enable signals are controlled by other modules during the charger detection seuence the d pullup enable is physically output from the usb controller but is under software control. the usbdcd module controls the d- pulldown enable. usbdcd module detects if the device has been plugged into either a standard host port, a charging host port, or a dedicated charger. vbus_detect this interrupt pin connected to the usb vbus signal detects when the device has been plugged into or unplugged from the usb bus. if the system reuires waing up from a low power mode upon being plugged into the usb port, this interrupt should also be a low power wae up source. if this pin multiplexes other functions, such as pi, the pin should be configured as an interrupt whenever the usb plug or unplug event is reuired to be detected. 1. if the usb host has suspended the usb device, system software must configure the system to limit the current drawn from the usb bus to 2. ma or less. 46..1 the charger detection seuence the following figure illustrates the charger detection sequence in a simplified timing diagram based on the usb battery charging specification v1.1. chapter 46 usb device charger detection module (usbdcd) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1287 vbus detect 1 2 3 4 5 6 = 1 s dev_hchg_lfs d p _ p u l l u p dm_src dp_sink host port charger detection phase t unit_con_elapsed speed portable usb device a t c h a r g i n g h o s t p o r t . c a u s e d + v o l t a g e t o e x c e e d v v dev_dchg v b u s a t p o r t a b l e u s b d e v i ce 0 m a d+ d- c h a r g i n g h o s t : v dat_ref < v d - < v lgc d e d i c a t e d c h a r g i n g p o r t c h a r g i n g h o s t p o r t , f s 1 m s t u n i t _ c o n _ e l a p s e d = t s e q_init t seq_init t dcd_dbnc c h e c k _ d m dedicated charger c h a r g i n g h o s t d e d i c a t e d c h a r g e r c h a r g i n g h o s t t vdpsrc_on t vdpsrc_con t con_idpsnk_dis t vdmsrc_dis s t a n d a r d h o s t : v d - < v dat ref t vdmsrc_en lgc_hi lgc_lo o f f on o f f on lgc_hi lgc_lo o f f on o f f on o f f on i susp i dp_src r d m _ d wn v dp_src i dm_sink the following table provides an overview description of the charger detection sequence shown in the preceding figure. functional description k60 sub-family reference manual, rev. 6, nov 2011 1288 freescale semiconductor, inc. table 46-14. overview of the charger detection sequence phase overview description full description 1 initial conditions initial system conditions that need to be met before initiating the detection sequence initial system conditions 2 vbus detection system software detects contact of the vbus signal with the system interrupt pin vbus_detect. vbus contact detection 3 data pin contact detection the usbdcd module detects that the usb data pins d+ and d have made contact with the usb port. data pin contact detection 4 charging port detection the usbdcd module detects if the port is a standard host or either type of charging port (charging host or dedicated charger). charging port detection 5 charger type detection if attached to a charging port, detect which type. charger type detection 6 sequence timeout the usbdcd module did not finish the detection sequence within the timeout interval. the sequence will continue until halted by software. charger detection sequence timeout timing parameter values used in this module are listed in the following table. table 46-15. timing parameters for the charger detection sequence parameter usb battery charging spec module default module programmable range t dcd_dbnc 1 10 ms min (no max) 10 ms 0 - 1023 ms t vdpsrc_on 1 40 ms min (no max) 40 ms 0 - 1023 ms t vdpsrc_con 1 40 ms min (no max) 40 ms 0 - 1023 ms check_dm n/a 1 ms 0 - 15 ms t seq_init n/a 16 ms 0 - 1023 ms t unit_con 1 1 s n/a n/a t vdmsrc_en 1 1 - 20 ms from the usb host n/a t vdmsrc_dis 1 0 - 20 ms from the usb host n/a t con_idpsink_dis 1 0 - 20 ms from the usb host n/a 1. this parameter is defined by the usb battery charging specification, v1.1 . 46..1.1 initial system conditions before starting the usbdcd module's charger detection sequence, the system must be: ? using a rechargable battery, ? for a fs usb device application (cannot be hs, ls, host, or otg), ? powered-up and in run mode, chapter 46 usb device charger detection module (usbdcd) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1289 ? recently plugged into a usb port, and ? drawing no more than 2.5 ma total system current from the usb bus. there are many allowable precursors to this set of initial conditions. for example, the device could have been powered down and subsequently powered up upon being plugged into the usb bus. alternatively, the device could have been in a low power state that was exited due to the plugin event. or, the device could have been operating in normal run mode, powered by a separate supply or non-rechargable battery. 46.5.1.2 vbus contact detection once the device is plugged into a usb port, the vbus_detect system interrupt is triggered. system software should do the following to initialize the module and start the charger detection sequence: 1. restore power if the module is powered-off. 2. set the control[sr] bit to initiate a software reset. 3. configure the usbdcd module: program the clock register and the timing parameters as needed. 4. set the control[ie] bit to enable interrupts (by default), or clear the bit if using a software polling method. 5. set the control[start] bit to start the charger detection sequence. 46.5.1.3 data pin contact detection because the detection sequence depends upon the state of the usb d+, the module must ensure that the data pins have made contact. usb plugs and receptables are designed such that when the plug is inserted into the receptable, the power pins make contact before the data pins make contact. see the following figure. functional description k60 sub-family reference manual, rev. 6, nov 2011 1290 freescale semiconductor, inc. vbus d+ gnd vbus d d+ gnd receptacle plug vbus d figure 46-10. relative pin positions in usb plugs and receptacles as a result, when a portable usb device is attached to an upstream port, the portable usb device detects vbus before the data pins have made contact. the time between power pins and data pins making contact depends on how fast the plug is inserted into the receptable. delays of several hundred milliseconds are possible. 46.5.1.3.1 debouncing the data pin contact when system software has initiated the charger detection sequence, as described in initial system conditions the usbdcd module turns on the i dp_src current source and enables the r dm_dwn pulldown resistor. if the data pins have not made contact, the d+ line remains high. once the data pins make contact, the d+ line goes low and debouncing begins. once the d+ line goes low, the module continuously samples the d+ line over the duration of the t dcd_dbnc debounce time interval.t dcd_dbnc defaults to 10 ms but can be programmed in the timer0[tdcd_dbnc] field. see the description of the timer0 register for register information. when it has remained low for the entire interval, the debouncing is complete. however, if the d+ line returns high during the debounce interval, the module waits until the d+ line goes low again to restart the debouncing. this cycle repeats until either: ? the data pin contact has been successfully debounced (see success in detecting data pin contact (phase completion) ), or ? a timeout occurs (see charger detection sequence timeout ). 46.5.1.3.2 success in detecting data pin contact (phase completion) after successfully debouncing the d+ state, the module does the following: chapter 46 usb device charger detection module (usbdcd) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1291 ? updates the status register to reflect phase completion (see table 46-18 for field values.) ? directly proceeds to the next step in the sequence: detection of a charging port see charging port detection . 46.5.1.4 charging port detection once it is known that the data pins have made contact, the module waits for a fixed delay of 1 ms, and then attempts to detect if it has been plugged into a charging port. the module connects the following analog units to the usb d+ or d- lines during this phase (when the usbdcd_en and usbdcd_chg_det_en signals are asserted high): ? the voltage source v dp_src connects to the d+ line ? the current sink i dm_sink connects to the d- line ? the voltage comparator connects to the usb d- line, comparing it to the voltage v dat_ref . after a time of t vdpsrc_on , the module samples the d- line. the t vdpsrc_on parameter is programmable and defaults to 40 ms. after sampling the d- line, the module disconnects the voltage source, current sink, and comparator. the next steps in the sequence depend on the voltage on the d- line as determined by the voltage comparator. see the following table. table 46-16. sampling d- in the charging port detection phase if the voltage on d- is... then... see... below v dat_ref the port is a standard host that does not support the usb battery charging specification v1.1. standard host port above v dat_ref but below v c the port is a charging port . charging port above v c this is an error condition.. error in charging port detection 46..1.4.1 standard host port as part of the charger detection handshake with a standard usb host, the module does the following (without waiting for the t vdpsrc_con interval to elapse): ? updates the status register to reflect that a standard host has been detected with seq_res = 01. (see table 46-18 for field values.) functional description k60 sub-family reference manual, rev. 6, nov 2011 1292 freescale semiconductor, inc. ? sets the control[if] bit. ? generates an interrupt if enabled (the control[ie] bit is set). at this point, control has been passed to system software via the interrupt. the rest of the sequence (detecting the type of charging port) is not applicable, so software should: 1. read the status register. 2. set the control[iack] bit to acknowledge the interrupt. 3. set the control[sr] bit to issue a software reset to the module. 4. disable the module. 5. communicate the appropriate charge rate to the external battery charger ic; see table 46-13 . 46.5.1.4.2 charging port as part of the charger detection handshake with any type of usb host, the module waits until the t vdpsrc_con interval has elapsed before doing the following: ? updates the status register to reflect that a charging port has been detected with seq_res = 10. (see table 46-18 for field values.) ? sets the control[if] bit. ? generates an interrupt if enabled (the control[ie] bit is set). at this point, control has passed to system software via the interrupt. software should: 1. read the status register. 2. set the control[iack] bit to acknowledge the interrupt. 3. issue a command to the usb controller to pullup the usb d+ line. 4. wait for the module to complete the final phase of the sequence. see charger type detection . 46.5.1.4.3 error in charging port detection for this error condition, the module does the following: chapter 46 usb device charger detection module (usbdcd) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1293 ? updates the status register to reflect the error with seq_res = 00. (see table 46-18 for field values.) ? sets the control[if] bit. ? generates an interrupt if enabled (the control[ie] bit is set). note that in this case the module does not wait for the t vdpsrc_con interval to elapse. at this point, control has been passed to system software via the interrupt. the rest of the sequence (detecting the type of charging port) is not applicable, so software should: 1. read the status register. 2. set the control[iack] bit to acknowledge the interrupt. 3. set the control[sr] bit to issue a software reset to the module. 4. disable the module. 46.5.1.5 charger type detection after software enables the d+ pullup resistor, the module is notified automatically (via internal signaling; the module waits until the ipp_pue_pullup_dp input goes high) to start the check_dm timer counting down the time interval programmed into the timer2[check_dm] field. once the check_dm time has elapsed, the module samples the usb d- line to determine the type of charger. see the following table. table 46-17. sampling d- in the charger type detection phase if the voltage on d- is... then... see... high the port is a dedicated charging port . 1 dedicated charging port ow the port is a charging host port . 2 charging host port 1. in a dedicated charger, the d and d- lines are shorted together through a small resistor. 2. in a charging host port, the d and d- lines are not shorted. 46..1..1 dedicated charging port for a dedicated charger, the module does the following: functional description k60 sub-family reference manual, rev. 6, nov 2011 1294 freescale semiconductor, inc. ? updates the status register to reflect that a dedicated charger has been detected with seq_res = 11. (see table 46-18 for field values.) ? sets the control[if] bit. ? generates an interrupt if enabled (the control[ie] bit is set). at this point, control has been passed to system software via the interrupt. software should: 1. read the status register. 2. disable the usb controller to prevent transitions on the usb d+ or d- lines from causing spurious interrupt or wake-up events to the system. 3. set the control[iack] bit to acknowledge the interrupt. 4. set the control[sr] bit to issue a software reset to the module. 5. disable the module. 6. communicate the appropriate charge rate to the external battery charger ic; see table 46-13 . 46.5.1.5.2 charging host port for a charging host port, the module does the following: ? updates the status register to reflect that a charging host port has been detected with seq_res = 10. (see table 46-18 for field values.) ? sets the control[if] bit. ? generates an interrupt if enabled (the control[ie] bit is set). at this point, control has been passed to system software via the interrupt. software should: 1. read the status register. 2. set the control[iack] bit to acknowledge the interrupt. 3. set the control[sr] bit to issue a software reset to the module. 4. disable the module. 5. communicate the appropriate charge rate to the external battery charger ic; see table 46-13 . chapter 46 usb device charger detection module (usbdcd) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1295 46.5.1.6 charger detection sequence timeout the maximum time to connect allowed under the usb battery charging specification, v1.1 is one second. if the unit connection timer reaches the one second limit and the sequence is still running (indicated by the status[active] bit still being set), the module does the following: ? updates the status register to reflect that a timeout error has occured. (see table 46-18 for field values.) ? sets the control[if] bit. ? generates an interrupt if enabled (the control[ie] bit is set). ? the detection sequence continues until explicitly halted by software setting the control[sr] bit. ? the unit connection timer continues counting. see the description of the timer0 register. at this point, control has been passed to system software via the interrupt, which has two options: ignore the interrupt and allow more time for the sequence to complete, or halt the sequence. to halt the sequence, software should: 1. read the status register. 2. set the control[iack] bit to acknowledge the interrupt. 3. set the control[sr] bit to issue a software reset to the module. 4. disable the module. this timeout function is also useful in case software does not realize that the user unplugged the usb device from the usb port during the charger detection sequence. if the interrupt occurs but the v bus_detect input is low, software can disable and reset the module. system software might allow the sequence to run past the timeout interrupt under these conditions: 1. the usb battery charging spec is amended to allow more time. in this case, software should poll the t unitcon register field (see the description of the timer0 register) periodically to track elapsed time after 1s; or 2. for debug purposes. functional description k60 sub-family reference manual, rev. 6, nov 2011 1296 freescale semiconductor, inc. note that the t unitcon register field will stop incrementing when it reaches its maximum value so it will not rollover to zero and start counting up again. 46.5.2 interrupts and events the usbdcd module has an interrupt to alert system software of certain events, which are listed in the following table. all events except the phase complete event for the data pin detection phase can trigger an interrupt. table 46-18. events triggering an interrupt by sequence phase sequence phase event event description status fields 1 phase description data pin detection phase complete the module has detected data pin contact. no interrupt occurs cntrif 0. err 0 se_stat 01 se_res 00 t 0 vbus contact detection charging port detection phase complete the module has completed the process of identifying if the usb port is a charging port or not. err 0 se_stat 10 se_res 01 or 10 t 0 charging port detection error the module cannot identify the type of port because the d- line is above the usbs vc threshold. err 1 se_stat 10 se_res 00 t 0 error in charging port detection charger type detection phase complete the module has completed the process of identifying the charger type detection. note the err flag always reads as zero because no nown error conditions are checed during this phase. err 0 se_stat 11 se_res 11 or 10 t 0 charger type detection seuence timeout error the timeout interval from the time the usb device attaches to a usb port until it connects has elapsed err 1 se_stat last value 2 se_res last value 2 t 1 charger detection seuence timeout . 1. see the description of the status register for register information. 2. the se_stat and se_res fields retain the values held at the time of the timeout error. 46..2.1 interrupt handling software can read which event caused the interrupt from the status register during the interrupt service routine. chapter 46 usb device charger detection module (usbdcd) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1297 an interrupt is generated only if the control[ie] bit is set. the control[if] bit is always set under interrupt conditions, even if the ie bit is cleared. in this case, software can poll the if flag to determine if an interrupt condition is pending. writes to the if bit are ignored. to reset the if bit, set the control[iack] bit to acknowledge the interrupt.writing to the iack bit while the if bit is cleared has no effect. 46.5.3 resets there are two ways to reset various register contents in this module: hardware resets and a software reset. 46.5.3.1 hardware resets hardware resets originate at the system or device level and propagate down to the individual module level. they include power-on reset, low-voltage reset, and all other hardware reset sources. hardware resets cause the register contents to be restored to their default state as listed in the register descriptions. 46.5.3.2 software reset a software reset re-initializes the module's status information but leaves configuration information unchanged. the software reset allows software to prepare the module without needing to reprogram the same configuration each time the usb device is plugged into a usb port. setting the control[sr] bit initiates a software reset. the following table shows what register fields are reset to their default values by a software reset. table 46-19. software reset and register fields affected register fields affected fields not affected control 1 [if] [ie, start] status all none clock none all timer n tunitcn all other 1. the cntrsr, iac bits are self-clearing. functional description 60 sub-family reference manual, rev. 6, nov 2011 128 freescale semiconductor, inc. a software reset also returns all internal logic, timers, and counters to their reset states. state machines return to idle. if the module is already active (status[active] = 1), a software reset stops the sequence. note software should always initiate a software reset before starting the sequence (setting the control[start] bit) to ensure the module is in a known state. 46.6 initialization information this module has been designed for minimal configuration while retaining significant programmability. the clock register needs to be initialized to the actual system clock frequency (unless the default value already matches the system requirements). the other registers generally do not need to be modified because they default to values that comply with the usb battery charging specification v1.1. however, several timing parameters can be changed for a great deal of flexibility if a particular system requires it. all module configuration must occur before initiating the charger detection sequence. configuration changes made after setting the control[start] bit result in undefined behavior. 46.7 application information this section provides application information. 46.7.1 external pullups any external pullups applied to the usb d+ or d- data lines must be capable of being disabled to prevent incorrect pullup values or incorrect operation of the usb subsystem. 46.7.2 dead or weak battery according to the usb battery charging specification v1.1, a usb device with a dead, weak, or missing battery that is attached to a charging port can remain attached indefinitely drawing up to 1.5a until the battery is charged to the point that the usb device can connect. chapter 46 usb device charger detection module (usbdcd) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1299 the usbdcd module is compatible with systems that do not check the strength of the battery. therefore, this module assumes that the battery is good, so the usb device must immediately connect to the usb bus by pulling the d+ line high after the usbdcd module has determined that the device is attached to a charging port. the module is also compatible with systems that do check the strength of the battery. in these systems, if it is known that the battery is weak or dead, software can delay connecting to the usb while charging at 1.5a. once the battery is charged to the good battery threshold, software can then connect to the usb host by pulling the d+ line high. 46.7.3 handling unplug events if the device is unplugged from the usb bus during the charger detection sequence, the contents of the status register should be ignored and the usbdcd module should get a sotware reset, as described in software reset . application information k60 sub-family reference manual, rev. 6, nov 2011 1300 freescale semiconductor, inc. chapter 47 usb voltage regulator 47.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the usb voltage regulator module is a ldo linear voltage regulator to provide 3.3v power from an input power supply varying from 2.7 v to 5.5 v. it consists of one 3.3 v power channel. when the input power supply is below 3.6 v, the regulator goes to pass- through mode. the following figure shows the ideal relation between the regulator output and input power supply. output (volt) 3.3 2.7 2.4 2.7 3.0 3.6 5.5 input (volt) figure 47-1. ideal relation between the regulator output and input power supply k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1301 47.1.1 overview a simplified block diagram for the usb voltage regulator module is shown below. standby reg33_in reg33_out yes no run regulator standby regulator voltage regulator chip power supply regulated output voltage voltage regulator esr: 5m -> 100m ohms external capacitor typical = 2.2uf other modules figure 47-2. usb voltage regulator block diagram this module uses 2 regulators in parallel. in run mode, the run regulator with the bandgap voltage reference is enabled and can provide up to 120 ma load current. in run mode, the standby regulator and the low power reference are also enabled, but a switch disconnects its output from the external pin. in standby mode, the run regulator is disabled and the standby regulator output is connected to the external pin supplying up to 3 ma load current. internal power mode signals control whether the module is in run or standby mode. 47.1.2 features ? low drop-out linear voltage regulator with one power channel (3.3v). ? low drop-out voltage: 300 mv. ? output current: 120 ma. ? three different power modes: run, standby and shutdown. ? low quiescent current in run mode. ? typical value is around 120 ua (one thousand times smaller than the maximum load current). ? very low quiescent current in standby mode. ? typical value is around 1 ua. introduction k60 sub-family reference manual, rev. 6, nov 2011 1302 freescale semiconductor, inc. ? automatic current limiting if the load current is greater than 290 ma. ? automatic power-up once some voltage is applied to the regulator input. ? pass-through mode for regulator input voltages less than 3.6 v ? small output capacitor: 2.2 uf ? stable with aluminum, tantalum or ceramic capacitors. 47.1.3 modes of operation the regulator has these power modes: ? runthe regulating loop of the run regulator and the standby regulator are active, but the switch connecting the standby regulator output to the external pin is open. ? standbythe regulating loop of the run regulator is disabled and the standby regulator is active. the switch connecting the standby regulator output to the external pin is closed. ? shutdownthe module is disabled. the regulator is enabled by default. this means that once the power supply is provided, the module power-up sequence to run mode starts. 47.2 usb voltage regulator module signal descriptions the following table shows the external signals for the regulator. table 47-1. usb voltage regulator module signal descriptions signal description i/o reg33_in unregulated power supply i reg33_out regulator output voltage o chapter 47 usb voltage regulator k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1303 usb voltage regulator module signal descriptions k60 sub-family reference manual, rev. 6, nov 2011 1304 freescale semiconductor, inc. chapter 48 can (flexcan) 48.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the flexcan module is a communication controller implementing the can protocol according to the can 2.0b protocol specification. a general block diagram is shown in the following figure, which describes the main sub-blocks implemented in the flexcan module, including one associated memory for storing message buffers, rx global mask registers, rx individual mask registers, rx fifo and rx fifo id filters. the functions of the sub-modules are described in subsequent sections. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1305 can rx ram rx matching can tx registers can control host interface can protocol engine tx arbitration message buffers (mbs) peripheral bus interface address, data, clocks, interrupts chip can bus figure 48-1. flexcan block diagram 48.1.1 overview the can protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the emi environment of a vehicle, cost-effectiveness and required bandwidth. the flexcan module is a full implementation of the can protocol specification, version 2.0 b, which supports both standard and extended message frames. the message buffers are stored in an embedded ram dedicated to the flexcan module. see the chip configuration details for the actual number of message buffers configured in the mcu. the can protocol engine (pe) sub-module manages the serial communication on the can bus, requesting ram access for receiving and transmitting message frames, validating received messages and performing error handling. the controller host interface (chi) sub-module handles message buffer selection for reception and transmission, taking care of arbitration and id matching algorithms. the bus interface unit (biu) sub-module controls the access to and from the internal interface bus, in order to establish connection to the cpu and to other blocks. clocks, address and data buses, interrupt outputs and test signals are accessed through the bus interface unit. introduction k60 sub-family reference manual, rev. 6, nov 2011 1306 freescale semiconductor, inc. 48.1.2 flexcan module features the flexcan module includes these distinctive legacy features: ? full implementation of the can protocol specification, version 2.0b ? standard data and remote frames ? extended data and remote frames ? zero to eight bytes data length ? programmable bit rate up to 1 mb/sec ? content-related addressing ? flexible mailboxes of zero to eight bytes data length ? each mailbox configurable as rx or tx, all supporting standard and extended messages ? individual rx mask registers per mailbox ? full featured rx fifo with storage capacity for up to 6 frames and automatic internal pointer handling ? transmission abort capability ? programmable clock source to the can protocol interface, either bus clock or crystal oscillator ? unused structures space can be used as general purpose ram space ? listen-only mode capability ? programmable loop-back mode supporting self-test operation ? programmable transmission priority scheme: lowest id, lowest buffer number or highest priority ? time stamp based on 16-bit free-running timer ? global network time, synchronized by a specific message ? maskable interrupts ? independent of the transmission medium (an external transceiver is assumed) chapter 48 can (flexcan) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1307 ? short latency time due to an arbitration scheme for high-priority messages ? low power modes, with programmable wake up on bus activity furthermore, the new major features below are also provided in addition to the previous flexcan version: ? remote request frames may be handled automatically or by software ? safe mechanism for id filter configuration in normal mode ? can bit time settings and configuration bits can only be written in "freeze" mode ? tx mailbox status (lowest priority buffer or empty buffer) ? idhit register for received frames ? sync bit status to inform that the module is synchronous with can bus ? debug registers ? crc status for transmitted message ? rx fifo global mask register ? selectable priority of reception between mailboxes and rx fifo during matching process ? powerful rx fifo id filtering, capable of matching incoming ids against either 128 extended, 256 standard or 512 partial (8 bits) ids, with up to 32 individual masking capability ? 100% backward compatibility with previous flexcan version 48.1.3 modes of operation the flexcan module has four functional modes: normal mode (user and supervisor), freeze mode, listen-only mode and loop-back mode. there are also three low power modes: disable mode, doze mode and stop mode. ? normal mode (user or supervisor): in normal mode, the module operates receiving and/or transmitting message frames, errors are handled normally and all the can protocol functions are enabled. user and supervisor modes differ in the access to some restricted control registers. ? freeze mode: introduction k60 sub-family reference manual, rev. 6, nov 2011 1308 freescale semiconductor, inc. it is enabled when the frz bit in the mcr register is asserted. if enabled, freeze mode is entered when the halt bit in mcr is set or when debug mode is requested at mcu level and the frz_ack bit in the mcr register is asserted by the flexcan. in this mode, no transmission or reception of frames is done and synchronicity to the can bus is lost. see freeze mode for more information. ? listen-only mode: the module enters this mode when the lom bit in the control 1 register is asserted. in this mode, transmission is disabled, all error counters are frozen and the module operates in a can error passive mode. only messages acknowledged by another can station will be received. if flexcan detects a message that has not been acknowledged, it will flag a bit0 error (without changing the rec), as if it was trying to acknowledge the message. ? loop-back mode: the module enters this mode when the lpb bit in the control 1 register is asserted. in this mode, flexcan performs an internal loop back that can be used for self test operation. the bit stream output of the transmitter is internally fed back to the receiver input. the rx can input pin is ignored and the tx can output goes to the recessive state (logic '1'). flexcan behaves as it normally does when transmitting and treats its own transmitted message as a message received from a remote node. in this mode, flexcan ignores the bit sent during the ack slot in the can frame acknowledge field to ensure proper reception of its own message. both transmit and receive interrupts are generated. ? module disable mode: this low power mode is entered when the mdis bit in the mcr register is asserted by the cpu and the lpm_ack is asserted by the flexcan. when disabled, the module requests to disable the clocks to the can protocol engine and controller host interface sub-modules. exit from this mode is done by negating the mdis bit in the mcr register. see module disable mode for more information. ? doze mode: this low power mode is entered when the doze bit in mcr is asserted and doze mode is requested at mcu level and the lpm_ack bit in the mcr register is asserted by the flexcan. when in doze mode, the module requests to disable the clocks to the can protocol engine and the can controller-host interface sub- modules. exit from this mode happens when the doze bit in mcr is negated, when the mcu is removed from doze mode, or when activity is detected on the can bus and the self wake up mechanism is enabled. see doze mode for more information. ? stop mode: chapter 48 can (flexcan) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1309 this low power mode is entered when stop mode is requested at mcu level and the lpm_ack bit in the mcr register is asserted by the flexcan. when in stop mode, the module puts itself in an inactive state and then informs the cpu that the clocks can be shut down globally. exit from this mode happens when the stop mode request is removed or when activity is detected on the can bus and the self wake up mechanism is enabled. see stop mode for more information. 48.2 flexcan signal descriptions the flexcan module has two i/o signals connected to the external mcu pins. these signals are summarized in the following table and described in more detail in the next sub-sections. table 48-1. flexcan signal descriptions signal description i/o can rx can receive pin input can tx can transmit pin output 48.2.1 can rx this pin is the receive pin from the can bus transceiver. dominant state is represented by logic level '0'. recessive state is represented by logic level '1'. 48.2.2 can tx this pin is the transmit pin to the can bus transceiver. dominant state is represented by logic level '0'. recessive state is represented by logic level '1'. 48.3 memory map/register definition this section describes the registers and data structures in the flexcan module. the base address of the module depends on the particular memory map of the mcu. 48.3.1 flexcan memory mapping flexcan signal descriptions k60 sub-family reference manual, rev. 6, nov 2011 1310 freescale semiconductor, inc. the complete memory map for a flexcan module is shown in the following table. the address space occupied by flexcan has 128 bytes for registers starting at the module base address, followed by embedded ram starting at address 0x0080. each individual register is identified by its complete name and the corresponding mnemonic. the access type can be supervisor (s) or unrestricted (u). most of the registers can be configured to have either supervisor or unrestricted access by programming the supv bit in the mcr register. these registers are identified as s/u in the access column of table 48-2 . the registers iflag2 and imask2 are considered reserved space depending on the number of mailboxes available in the device. table 48-2. module memory map register access type affected by hard reset affected by soft reset module configuration register (mcr) s yes yes control 1 register (ctrl1) s/u yes no free running timer register (timer) s/u yes yes rx mailboxes global mask register (rxmgmask) s/u no no rx buffer 14 mask register (rx14mask) s/u no no rx buffer 15 mask register (rx15mask) s/u no no error counter register (ecr) s/u yes yes error and status 1 register (esr1) s/u yes yes interrupt masks 2 register (imask2) s/u yes yes interrupt masks 1 register (imask1) s/u yes yes interrupt flags 2 register (iflag2) s/u yes yes interrupt flags 1 register (iflag1) s/u yes yes control 2 register (ctrl2) s/u yes no error and status 2 register (esr2) s/u yes yes individual matching elements update register (imuer) s/u yes yes lost rx frames register (lrfr) s/u yes yes crc register (crcr) s/u yes yes rx fifo global mask register (rxfgmask) s/u no no rx fifo information register (rxfir) s/u no no message buffers s/u no no rx individual mask registers s/u no no chapter 48 can (flexcan) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1311 the flexcan module can store can messages for transmission and reception using mailboxes and rx fifo structures. this module's memory map includes sixteen 128-bit message buffers (mbs) that occupy the range from offset 0x80 to 0x17f. can memory map absolute address (hex) register name width (in bits) access reset value section/ page 4002_4000 module configuration register (can0_mcr) 32 r/w d890_000fh 48.3.2/ 1316 4002_4004 control 1 register (can0_ctrl1) 32 r/w 0000_0000h 48.3.3/ 1321 4002_4008 free running timer (can0_timer) 32 r/w 0000_0000h 48.3.4/ 1324 4002_4010 rx mailboxes global mask register (can0_rxmgmask) 32 r/w ffff_ ffffh 48.3.5/ 1325 4002_4014 rx 14 mask register (can0_rx14mask) 32 r/w ffff_ ffffh 48.3.6/ 1326 4002_4018 rx 15 mask register (can0_rx15mask) 32 r/w ffff_ ffffh 48.3.7/ 1327 4002_401c error counter (can0_ecr) 32 r/w 0000_0000h 48.3.8/ 1328 4002_4020 error and status 1 register (can0_esr1) 32 r/w 0000_0000h 48.3.9/ 1329 4002_4024 interrupt masks 2 register (can0_imask2) 32 r/w 0000_0000h 48.3.10/ 1333 4002_4028 interrupt masks 1 register (can0_imask1) 32 r/w 0000_0000h 48.3.11/ 1334 4002_402c interrupt flags 2 register (can0_iflag2) 32 r/w 0000_0000h 48.3.12/ 1334 4002_4030 interrupt flags 1 register (can0_iflag1) 32 r/w 0000_0000h 48.3.13/ 1335 4002_4034 control 2 register (can0_ctrl2) 32 r/w 00c0_0000h 48.3.14/ 1338 4002_4038 error and status 2 register (can0_esr2) 32 r/w 0000_0000h 48.3.15/ 1341 4002_4044 crc register (can0_crcr) 32 r 0000_0000h 48.3.16/ 1342 4002_4048 rx fifo global mask register (can0_rxfgmask) 32 r/w ffff_ ffffh 48.3.17/ 1343 4002_404c rx fifo information register (can0_rxfir) 32 r undefined 48.3.18/ 1344 table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 112 freescale semiconductor, inc. can memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4002_4880 rx individual mask registers (can0_rximr0) 32 r/w undefined 48.3.19/ 1345 4002_4884 rx individual mask registers (can0_rximr1) 32 r/w undefined 48.3.19/ 1345 4002_4888 rx individual mask registers (can0_rximr2) 32 r/w undefined 48.3.19/ 1345 4002_488c rx individual mask registers (can0_rximr3) 32 r/w undefined 48.3.19/ 1345 4002_4890 rx individual mask registers (can0_rximr4) 32 r/w undefined 48.3.19/ 1345 4002_4894 rx individual mask registers (can0_rximr5) 32 r/w undefined 48.3.19/ 1345 4002_4898 rx individual mask registers (can0_rximr6) 32 r/w undefined 48.3.19/ 1345 4002_489c rx individual mask registers (can0_rximr7) 32 r/w undefined 48.3.19/ 1345 4002_48a0 rx individual mask registers (can0_rximr8) 32 r/w undefined 48.3.19/ 1345 4002_48a4 rx individual mask registers (can0_rximr9) 32 r/w undefined 48.3.19/ 1345 4002_48a8 rx individual mask registers (can0_rximr10) 32 r/w undefined 48.3.19/ 1345 4002_48ac rx individual mask registers (can0_rximr11) 32 r/w undefined 48.3.19/ 1345 4002_48b0 rx individual mask registers (can0_rximr12) 32 r/w undefined 48.3.19/ 1345 4002_48b4 rx individual mask registers (can0_rximr13) 32 r/w undefined 48.3.19/ 1345 4002_48b8 rx individual mask registers (can0_rximr14) 32 r/w undefined 48.3.19/ 1345 4002_48bc rx individual mask registers (can0_rximr15) 32 r/w undefined 48.3.19/ 1345 400a_4000 module configuration register (can1_mcr) 32 r/w d890_000fh 48.3.2/ 1316 400a_4004 control 1 register (can1_ctrl1) 32 r/w 0000_0000h 48.3.3/ 1321 400a_4008 free running timer (can1_timer) 32 r/w 0000_0000h 48.3.4/ 1324 400a_4010 rx mailboxes global mask register (can1_rxmgmask) 32 r/w ffff_ ffffh 48.3.5/ 1325 table continues on the next page... chapter 48 can flexcan 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 11 can memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 400a_4014 rx 14 mask register (can1_rx14mask) 32 r/w ffff_ ffffh 48.3.6/ 1326 400a_4018 rx 15 mask register (can1_rx15mask) 32 r/w ffff_ ffffh 48.3.7/ 1327 400a_401c error counter (can1_ecr) 32 r/w 0000_0000h 48.3.8/ 1328 400a_4020 error and status 1 register (can1_esr1) 32 r/w 0000_0000h 48.3.9/ 1329 400a_4024 interrupt masks 2 register (can1_imask2) 32 r/w 0000_0000h 48.3.10/ 1333 400a_4028 interrupt masks 1 register (can1_imask1) 32 r/w 0000_0000h 48.3.11/ 1334 400a_402c interrupt flags 2 register (can1_iflag2) 32 r/w 0000_0000h 48.3.12/ 1334 400a_4030 interrupt flags 1 register (can1_iflag1) 32 r/w 0000_0000h 48.3.13/ 1335 400a_4034 control 2 register (can1_ctrl2) 32 r/w 00c0_0000h 48.3.14/ 1338 400a_4038 error and status 2 register (can1_esr2) 32 r/w 0000_0000h 48.3.15/ 1341 400a_4044 crc register (can1_crcr) 32 r 0000_0000h 48.3.16/ 1342 400a_4048 rx fifo global mask register (can1_rxfgmask) 32 r/w ffff_ ffffh 48.3.17/ 1343 400a_404c rx fifo information register (can1_rxfir) 32 r undefined 48.3.18/ 1344 400a_4880 rx individual mask registers (can1_rximr0) 32 r/w undefined 48.3.19/ 1345 400a_4884 rx individual mask registers (can1_rximr1) 32 r/w undefined 48.3.19/ 1345 400a_4888 rx individual mask registers (can1_rximr2) 32 r/w undefined 48.3.19/ 1345 400a_488c rx individual mask registers (can1_rximr3) 32 r/w undefined 48.3.19/ 1345 400a_4890 rx individual mask registers (can1_rximr4) 32 r/w undefined 48.3.19/ 1345 400a_4894 rx individual mask registers (can1_rximr5) 32 r/w undefined 48.3.19/ 1345 400a_4898 rx individual mask registers (can1_rximr6) 32 r/w undefined 48.3.19/ 1345 table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 114 freescale semiconductor, inc. can memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 400a_489c rx individual mask registers (can1_rximr7) 32 r/w undefined 48.3.19/ 1345 400a_48a0 rx individual mask registers (can1_rximr8) 32 r/w undefined 48.3.19/ 1345 400a_48a4 rx individual mask registers (can1_rximr9) 32 r/w undefined 48.3.19/ 1345 400a_48a8 rx individual mask registers (can1_rximr10) 32 r/w undefined 48.3.19/ 1345 400a_48ac rx individual mask registers (can1_rximr11) 32 r/w undefined 48.3.19/ 1345 400a_48b0 rx individual mask registers (can1_rximr12) 32 r/w undefined 48.3.19/ 1345 400a_48b4 rx individual mask registers (can1_rximr13) 32 r/w undefined 48.3.19/ 1345 400a_48b8 rx individual mask registers (can1_rximr14) 32 r/w undefined 48.3.19/ 1345 400a_48bc rx individual mask registers (can1_rximr15) 32 r/w undefined 48.3.19/ 1345 chapter 48 can (flexcan) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1315 48.3.2 module configuration register (can x r this register defines global system configurations, such as the module operation modes and the maximum message buffer configuration. addresses: can0_mcr is 4002_4000h base + 0h offset = 4002_4000h can1_mcr is 400a_4000h base + 0h offset = 400a_4000h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r mdis frz rfen halt notrdy wakmsk softrst frzack supv slfwak wrnen lpmack reserved doze srxdis irmq w reset 1 1 0 1 1 0 0 0 1 0 0 1 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 lprioen aen 0 idam 0 maxmb w reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 can x r iel escritions fiel escrition oule isale his it controls whether flex is enale or not hen isale flex isales the clocs to the rotocol nine an ontroller host nterace suoules his is the only it in r not aecte y sot reset nale the flex oule isale the flex oule fr freee nale he fr it seciies the flex ehaior when the hl it in the r reister is set or when eu oe is requeste at u leel hen fr is asserte flex is enale to enter freee oe eation o this it iel causes flex to exit ro freee oe ot enale to enter freee oe nale to enter freee oe rf rx ffo nale table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 116 freescale semiconductor, inc. can x r iel escritions continue fiel escrition his it controls whether the rx ffo eature is enale or not hen rf is set s to cannot e use or noral recetion an transission ecause the corresonin eory reion xx is use y the ffo enine as well as aitional s u to eenin on rlrff settin which are use as rx ffo filter ale eleents rf also iacts the einition o the iniu nuer o eriheral clocs er it as escrie in the tale iniu ratio etween eriheral loc frequency an it rate in section ritration an atchin iin his it can only e written in freee oe as it is loce y harware in other oes rx ffo not enale rx ffo enale hl halt flex ssertion o this it uts the flex oule into freee oe he u shoul clear it ater initialiin the essae uers an ontrol reister o recetion or transission is erore y flex eore this it is cleare freee oe cannot e entere while flex is in a low ower oe o freee oe request nters freee oe i the fr it is asserte or flex ot reay his reaonly it inicates that flex is either in isale oe oe oe to oe or freee oe t is neate once flex has exite these oes flex oule is either in oral oe listenonly oe or looac oe flex oule is either in isale oe oe oe to oe or freee oe ae u nterrut as his it enales the ae u nterrut eneration ae u nterrut is isale ae u nterrut is enale ofr ot reset hen this it is asserte flex resets its internal state achines an soe o the eory ae reisters he ollowin reisters are reset: r excet the it r r r r fl fl an rr oniuration reisters that control the interace to the us are not aecte y sot reset he ollowin reisters are unaecte: rl rl rr rr r r r rf rfr all essae uers he ofr it can e asserte irectly y the u when it writes to the r reister ut it is also asserte when loal sot reset is requeste at u leel ince sot reset is synchronous an has to ollow a requestacnowlee roceure across cloc oains it ay tae soe tie to ully roaate its eect he ofr it reains asserte while reset is enin an is autoatically neate when reset coletes hereore sotware can oll this it to now when the sot reset has colete ot reset cannot e alie while clocs are shut own in a low ower oe he oule shoul e irst reoe ro low ower oe an then sot reset can e alie o reset request resets the reisters aecte y sot reset fr freee oe cnowlee his reaonly it inicates that flex is in freee oe an its rescaler is stoe he freee oe request cannot e rante until current transission or recetion rocesses hae inishe table continues on the next page... chapter 48 can flexcan 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 117 can x r iel escritions continue fiel escrition hereore the sotware can oll the fr it to now when flex has actually entere freee oe freee oe request is neate then this it is neate once the flex rescaler is runnin aain freee oe is requeste while flex is in a low ower oe then the fr it will only e set when the low ower oe is exite ee ection freee oe o: fr will e asserte within its ro the reee oe request y the u an neate within its ater the reee oe request reoal see ection rotocol iin flex not in freee oe rescaler runnin flex in freee oe rescaler stoe u uerisor oe his it coniures the flex to e either in uerisor or user oe he reisters aecte y this it are are as u in the ccess ye colun o the oule eory a reset alue o this it is so the aecte reisters start with uerisor access allowance only his it can only e written in freee oe as it is loce y harware in other oes flex is in user oe ecte reisters allow oth uerisor an unrestricte accesses flex is in uerisor oe ecte reisters allow only uerisor access unrestricte access ehaes as thouh the access was one to an unileente reister location lf el ae u his it enales the el ae u eature when flex is in a low ower oe other than isale oe hen this eature is enale the flex oule onitors the us or wae u eent that is a recessietooinant transition a wae u eent is etecte urin oe oe flex requests to resue its clocs an i enale to o so enerates a ae u interrut to the u a wae u eent is etecte urin to oe then flex enerates i enale to o so a ae u interrut to the u so that it can exit to oe loally an flex can request to resue the clocs hen flex is in a low ower oe other than isale oe this it cannot e written as it is loce y harware flex el ae u eature is isale flex el ae u eature is enale r arnin nterrut nale hen asserte this it enales the eneration o the r an rr las in the rror an tatus reister r is neate the r an rr las will always e ero ineenent o the alues o the error counters an no warnin interrut will eer e enerate his it can only e written in freee oe as it is loce y harware in other oes r an rr its are ero ineenent o the alues in the error counters r an rr its are set when the resectie error counter transitions ro less than to reater than or equal to l low ower oe cnowlee his reaonly it inicates that flex is in a low ower oe isale oe oe oe to oe low ower oe can not e entere until all current transission or recetion rocesses hae inishe so the u can oll the l it to now when flex has actually entere low ower oe table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 118 freescale semiconductor, inc. can x r iel escritions continue fiel escrition o: l will e asserte within its ro the low ower oe request y the u an neate within its ater the low ower oe request reoal see ection rotocol iin flex is not in a low ower oe flex is in a low ower oe resere his iel is resere o oe oe nale his it eines whether flex is allowe to enter low ower oe when oe oe is requeste at u leel his it is autoatically reset when flex waes u ro oe oe uon etectin actiity on the us sel waeu enale flex is not enale to enter low ower oe when oe oe is requeste flex is enale to enter low ower oe when oe oe is requeste r el recetion isale his it eines whether flex is allowe to receie raes transitte y itsel this it is asserte raes transitte y the oule will not e store in any rearless i the is rorae with an that atches the transitte rae an no interrut la or interrut sinal will e enerate ue to the rae recetion his it can only e written in freee oe as it is loce y harware in other oes el recetion enale el recetion isale r niiual rx asin an ueue nale his it inicates whether rx atchin rocess will e ase either on iniiual asin an queue or on asin schee with r r an r rf his it can only e written in freee oe as it is loce y harware in other oes niiual rx asin an queue eature are isale for acwar coatiility the reain o wor locs the een i it is niiual rx asin an queue eature are enale resere his reaonly iel is resere an always has the alue ero lro local riority nale his it is roie or acwars coatiility reasons t controls whether the local riority eature is enale or not t is use to exan the use urin the aritration rocess ith this exane concet the aritration rocess is one ase on the ull it wor ut the actual transitte still has it or stanar raes an it or extene raes his it can only e written in freee oe as it is loce y harware in other oes local riority isale local riority enale ort nale his it is sulie or acwars coatiility reasons hen asserte it enales the x aort echanis his echanis uarantees a sae roceure or aortin a enin transission so that no table continues on the next page... chapter 48 can flexcan 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 11 can x r iel escritions continue fiel escrition rae is sent in the us without notiication his it can only e written in freee oe as it is loce y harware in other oes o: hen r is asserte only the aort echanis see ection ransission ort echanis ust e use or uatin ailoxes coniure or transission uo: ritin the ort coe into rx ailoxes can cause unreictale results when the r is asserte ort isale ort enale resere his reaonly iel is resere an always has the alue ero ccetance oe his it iel ientiies the orat o the rx ffo filter ale leents ote that all eleents o the tale are coniure at the sae tie y this iel they are all the sae orat ee ection rx ffo tructure his iel can only e written in freee oe as it is loce y harware in other oes forat : one ull stanar an extene er filter ale eleent forat : wo ull stanar s or two artial it stanar an extene s er filter ale eleent forat : four artial it tanar s er filter ale eleent forat : ll raes reecte resere his reaonly iel is resere an always has the alue ero uer o the last essae uer his it iel eines the nuer o the last essae uers that will tae art in the atchin an aritration rocesses he reset alue xf is equialent to coniuration his iel can only e written in freee oe as it is loce y harware in other oes uer o the last o: ust e rorae with a alue saller than the araeter urof otherwise the nuer o the last eectie essae uer will e: urof itionally the alue o ust encoass the ffo sie eine y rlrff also iacts the einition o the iniu nuer o eriheral clocs er it as escrie in ale iniu ratio etween eriheral loc frequency an it rate in ection ritration an atchin iin eory areister einition ufaily reerence anual re o freescale eiconuctor nc 48.3.3 control 1 register (can x rl this register is defined for specific flexcan control features related to the can bus, such as bit-rate, programmable sampling point within an rx bit, loop back mode, listen-only mode, bus off recovery behavior and interrupt enabling (bus-off, error, warning). it also determines the division factor for the clock prescaler. addresses: can0_ctrl1 is 4002_4000h base + 4h offset = 4002_4004h can1_ctrl1 is 400a_4000h base + 4h offset = 400a_4004h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r presdiv rjw pseg1 pseg2 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r boffmsk errmsk clksrc lpb twrnmsk rwrnmsk 0 smp boffrec tsyn lbuf lom propseg w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 can x rl iel escritions fiel escrition r rescaler iision factor his it iel eines the ratio etween the cloc requency an the erial loc cloc requency he cloc erio eines the tie quantu o the rotocol for the reset alue the cloc requency is equal to the cloc requency he axiu alue o this iel is xff that ies a iniu cloc requency equal to the cloc requency iie y ee ection rotocol iin his iel can only e written in freee oe as it is loce y harware in other oes cloc requency cloc requency r r resync u ith his it iel eines the axiu nuer o tie quanta that a it tie can e chane y one re synchroniation one tie quantu is equal to the cloc erio he ali roraale alues are his iel can only e written in freee oe as it is loce y harware in other oes resync u ith r hase eent his it iel eines the lenth o hase uer eent in the it tie he ali roraale alues are his iel can only e written in freee oe as it is loce y harware in other oes hase uer eent x ieuanta hase eent table continues on the next page... chapter 48 can flexcan 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 121 can x rl iel escritions continue fiel escrition his it iel eines the lenth o hase uer eent in the it tie he ali roraale alues are his iel can only e written in freee oe as it is loce y harware in other oes hase uer eent x ieuanta off us o as his it roies a as or the us o nterrut us o interrut isale us o interrut enale rr rror as his it roies a as or the rror nterrut rror interrut isale rror interrut enale lr nine loc ource his it selects the cloc source to the rotocol nine to e either the eriheral cloc rien y the ll or the crystal oscillator cloc he selecte cloc is the one e to the rescaler to enerate the erial loc cloc n orer to uarantee reliale oeration this it can only e written in isale oe as it is loce y harware in other oes ee ection rotocol iin he enine cloc source is the oscillator cloc uner this conition the oscillator cloc requency ust e lower than the us cloc he enine cloc source is the eriheral cloc l loo ac oe his it coniures flex to oerate in looac oe n this oe flex erors an internal loo ac that can e use or sel test oeration he it strea outut o the transitter is e ac internally to the receier inut he rx inut in is inore an the x outut oes to the recessie state loic flex ehaes as it norally oes when transittin an treats its own transitte essae as a essae receie ro a reote noe n this oe flex inores the it sent urin the slot in the rae acnowlee iel eneratin an internal acnowlee it to ensure roer recetion o its own essae oth transit an receie interruts are enerate his it can only e written in freee oe as it is loce y harware in other oes o: n this oe the rr cannot e asserte ecause this will iee the sel recetion o a transitte essae loo ac isale loo ac enale r x arnin nterrut as his it roies a as or the x arnin nterrut associate with the r la in the rror an tatus reister his it is rea as ero when rr it is neate his it can only e written i rr it is asserte x arnin nterrut isale x arnin nterrut enale rr rx arnin nterrut as table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 122 freescale semiconductor, inc. can x rl iel escritions continue fiel escrition his it roies a as or the rx arnin nterrut associate with the rr la in the rror an tatus reister his it is rea as ero when rr it is neate his it can only e written i rr it is asserte rx arnin nterrut isale rx arnin nterrut enale resere his reaonly iel is resere an always has the alue ero it alin his it eines the salin oe o its at the rx inut his it can only e written in freee oe as it is loce y harware in other oes ust one sale is use to eterine the it alue hree sales are use to eterine the alue o the receie it: the reular one sale oint an recein sales a aority rule is use offr us o recoery his it eines how flex recoers ro us o state this it is neate autoatic recoerin ro us o state occurs accorin to the eciication the it is asserte autoatic recoerin ro us o is isale an the oule reains in us o state until the it is neate y the user the neation occurs eore sequences o recessie its are etecte on the us then us o recoery haens as i the offr it ha neer een asserte the neation occurs ater sequences o recessie its occurre then flex will resynchronie to the us y waitin or recessie its eore oinin the us ter neation the offr it can e reasserte aain urin us o ut it will only e eectie the next tie the oule enters us o offr was neate when the oule entere us o assertin it urin us o will not e eectie or the current us o recoery utoatic recoerin ro us o state enale accorin to ec art utoatic recoerin ro us o state isale ier ync his it enales a echanis that resets the reerunnin tier each tie a essae is receie in essae uer his eature roies eans to synchronie ultile flex stations with a secial essae ie loal networ tie the rf it in r is set rx ffo enale the irst aailale ailox accorin to rlrff settin is use or tier synchroniation instea o his it can only e written in freee oe as it is loce y harware in other oes ier ync eature isale ier ync eature enale luf lowest uer ransitte first his it eines the orerin echanis or essae uer transission hen asserte the lro it oes not aect the riority aritration his it can only e written in freee oe as it is loce y harware in other oes uer with hihest riority is transitte irst lowest nuer uer is transitte irst lo listenonly oe table continues on the next page... chapter 48 can flexcan 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 12 can x rl iel escritions continue fiel escrition his it coniures flex to oerate in listenonly oe n this oe transission is isale all error counters are roen an the oule oerates in a rror assie oe only essaes acnowlee y another station will e receie flex etects a essae that has not een acnowlee it will la a error without chanin the r as i it was tryin to acnowlee the essae listenonly oe acnowleeent can e otaine y the state o rflof iel which is assie rror when listenonly oe is entere here can e soe elay etween the listenonly oe request an acnowlee his it can only e written in freee oe as it is loce y harware in other oes listenonly oe is eactiate flex oule oerates in listenonly oe ro roaation eent his it iel eines the lenth o the roaation eent in the it tie he ali roraale alues are his iel can only e written in freee oe as it is loce y harware in other oes roaation eent ie ro ieuanta ieuantu one cloc erio free runnin ier x r this register represents a 16-bit free running counter that can be read and written by the cpu. the timer starts from 0x0 after reset, counts linearly to 0xffff, and wraps around. the timer is clocked by the flexcan bit-clock (which defines the baud rate on the can bus). during a message transmission/reception, it increments by one for each bit that is received or transmitted. when there is no message on the bus, it counts using the previously programmed baud rate. the timer is not incremented during disable, doze, stop and freeze modes. the timer value is captured when the second bit of the identifier field of any frame is on the can bus. this captured value is written into the time stamp entry in a message buffer after a successful reception or transmission of a message. if bit ctrl1[tsyn] is asserted the timer is reset whenever a message is received in the first available mailbox, according to ctrl2[rffn] setting. the cpu can write to this register anytime. however, if the write occurs at the same time that the timer is being reset by a reception in the first mailbox, then the write value is discarded. reading this register affects the mailbox unlocking procedure; see section "message buffer lock mechanism". memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1324 freescale semiconductor, inc. addresses: can0_timer is 4002_4000h base + 8h offset = 4002_4008h can1_timer is 400a_4000h base + 8h offset = 400a_4008h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 timer w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 can x r iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero r ier alue ontains the reerunnin counter alue rx ailoxes loal as reister x r this register is located in ram. rxmgmask is provided for legacy support. ? when the mcr[irmq] bit is negated, rxmgmask is always in effect. ? when the mcr[irmq] bit is asserted, rxmgmask has no effect. rxmgmask is used to mask the filter fields of all rx mbs, excluding mbs 14-15, which have individual mask registers. this register can only be written in freeze mode as it is blocked by hardware in other modes. addresses: can0_rxmgmask is 4002_4000h base + 10h offset = 4002_4010h can1_rxmgmask is 400a_4000h base + 10h offset = 400a_4010h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r mg[31:0] w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 can x r iel escritions fiel escrition : rx ailoxes loal as its hater flex ufaily reerence anual re o freescale eiconuctor nc can x r iel escritions continue fiel escrition hese its as the ailox ilter its ote that the alinent with the wor o the ailox is not erect as the two ost siniicant its aect the iels rr an which are locate in the ontrol an tatus wor o the ailox he ollowin tale shows in etail which its as each ailox ilter iel rr rlrr rl ailox ilter iels rr resere note note : : : : : : : rr it o the ncoin frae t is sae into an auxiliary calle rx erial essae uer rx the rl it is neate the rr it o ailox is neer coare with the rr it o the incoin rae the rl it is neate the it o ailox is always coare with the it o the incoin rae he corresonin it in the ilter is ont care he corresonin it in the ilter is chece rr it o the ncoin frae t is sae into an auxiliary calle rx erial essae uer rx the rl it is neate the rr it o ailox is neer coare with the rr it o the incoin rae the rl it is neate the it o ailox is always coare with the it o the incoin rae rx as reister x r this register is located in ram. rx14mask is provided for legacy support. when the mcr[irmq] bit is asserted, rx14mask has no effect. rx14mask is used to mask the filter fields of message buffer 14. this register can only be programmed while the module is in freeze mode as it is blocked by hardware in other modes. addresses: can0_rx14mask is 4002_4000h base + 14h offset = 4002_4014h can1_rx14mask is 400a_4000h base + 14h offset = 400a_4014h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r rx14m[31:0] w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1326 freescale semiconductor, inc. can x r iel escritions fiel escrition r: rx uer as its ach as it ass the corresonin ailox ilter iel in the sae way that r ass other ailoxes ilters ee the escrition o the r reister he corresonin it in the ilter is ont care he corresonin it in the ilter is chece rx as reister x r this register is located in ram. rx15mask is provided for legacy support. when the mcr[irmq] bit is asserted, rx15mask has no effect. rx15mask is used to mask the filter fields of message buffer 15. this register can only be programmed while the module is in freeze mode as it is blocked by hardware in other modes. addresses: can0_rx15mask is 4002_4000h base + 18h offset = 4002_4018h can1_rx15mask is 400a_4000h base + 18h offset = 400a_4018h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r rx15m[31:0] w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 can x r iel escritions fiel escrition r: rx uer as its ach as it ass the corresonin ailox ilter iel in the sae way that r ass other ailoxes ilters ee the escrition o the r reister he corresonin it in the ilter is ont care he corresonin it in the ilter is chece hater flex ufaily reerence anual re o freescale eiconuctor nc 48.3.8 error counter (can x r this register has two 8-bit fields reflecting the value of two flexcan error counters: transmit error counter (txerrcnt field) and receive error counter (rxerrcnt field). the rules for increasing and decreasing these counters are described in the can protocol and are completely implemented in the flexcan module. both counters are read-only except in freeze mode, where they can be written by the cpu. flexcan responds to any bus state as described in the protocol, e.g. transmit error active or error passive flag, delay its transmission start time (error passive) and avoid any influence on the bus when in bus off state. the following are the basic rules for flexcan bus state transitions. ? if the value of txerrcnt or rxerrcnt increases to be greater than or equal to 128, the fltconf field in the error and status register is updated to reflect error passive state. ? if the flexcan state is error passive, and either txerrcnt or rxerrcnt decrements to a value less than or equal to 127 while the other already satisfies this condition, the fltconf field in the error and status register is updated to reflect error active state. ? if the value of txerrcnt increases to be greater than 255, the fltconf field in the error and status register is updated to reflect bus off state, and an interrupt may be issued. the value of txerrcnt is then reset to zero. ? if flexcan is in bus off state, then txerrcnt is cascaded together with another internal counter to count the 128th occurrences of 11 consecutive recessive bits on the bus. hence, txerrcnt is reset to zero and counts in a manner where the internal counter counts 11 such bits and then wraps around while incrementing the txerrcnt. when txerrcnt reaches the value of 128, the fltconf field in the error and status register is updated to be error active and both error counters are reset to zero. at any instance of dominant bit following a stream of less than 11 consecutive recessive bits, the internal counter resets itself to zero without affecting the txerrcnt value. ? if during system start-up, only one node is operating, then its txerrcnt increases in each message it is trying to transmit, as a result of acknowledge errors (indicated by the ackerr bit in the error and status register). after the transition to error passive state, the txerrcnt does not increment anymore by acknowledge errors. therefore the device never goes to the bus off state. ? if the rxerrcnt increases to a value greater than 127, it is not incremented further, even if more errors are detected while being a receiver. at the next successful message reception, the counter is set to a value between 119 and 127 to resume to error active state. memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1328 freescale semiconductor, inc. addresses: can0_ecr is 4002_4000h base + 1ch offset = 4002_401ch can1_ecr is 400a_4000h base + 1ch offset = 400a_401ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 rxerrcnt txerrcnt w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 can x r iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero rrr receie rror ounter rr ransit rror ounter rror an tatus reister x r this register reflects various error conditions, some general status of the device and it is the source of interrupts to the cpu. the cpu read action clears bits 15-10, therefore the reported error conditions (bits 15-10) are those that occurred since the last time the cpu read this register. bits 9-3 are status bits. the following table shows the flexcan state variables and their meanings. other combinations not shown in the table are reserved. synch idle tx rx flexcan state 0 0 0 0 not synchronized to can bus 1 1 x x idle 1 0 1 0 transmitting 1 0 0 1 receiving chapter 48 can (flexcan) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1329 addresses: can0_esr1 is 4002_4000h base + 20h offset = 4002_4020h can1_esr1 is 400a_4000h base + 20h offset = 400a_4020h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 synch twrnint rwrnint w w1c w1c reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r bit1err bit0err ackerr crcerr frmerr stferr txwrn rxwrn idle tx fltconf rx boffint errint wakint w w1c w1c w1c reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 can x r iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero h ynchroniation tatus his reaonly la inicates whether the flex is synchronie to the us an ale to articiate in the counication rocess t is set an cleare y the flex ee the tale in the oerall r reister escrition flex is not synchronie to the us flex is synchronie to the us r x arnin nterrut fla the r it in r is asserte the r it is set when the r la transitions ro to eanin that the x error counter reache the corresonin as it in the ontrol reister r is set an interrut is enerate to the u his it is cleare y writin it to hen r is neate this la is ase u ust clear this la eore isalin the it otherwise it will e set when the r is set aain ritin has no eect his la is not enerate urin us o state his it is not uate urin freee oe o such occurrence he x error counter transitione ro less than to reater than or equal to rr rx arnin nterrut fla the r it in r is asserte the rr it is set when the rr la transitions ro to eanin that the rx error counters reache the corresonin as it in the ontrol reister rr is set an interrut is enerate to the u his it is cleare y writin it to hen r is neate this la is ase u ust clear this la eore isalin the it table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 10 freescale semiconductor, inc. can x r iel escritions continue fiel escrition otherwise it will e set when the r is set aain ritin has no eect his it is not uate urin freee oe o such occurrence he rx error counter transitione ro less than to reater than or equal to rr it rror his it inicates when an inconsistency occurs etween the transitte an the receie it in a essae o: his it is not set y a transitter in case o aritration iel or slot or in case o a noe senin a assie error la that etects oinant its o such occurrence t least one it sent as recessie is receie as oinant rr it rror his it inicates when an inconsistency occurs etween the transitte an the receie it in a essae o such occurrence t least one it sent as oinant is receie as recessie rr cnowlee rror his it inicates that an cnowlee rror has een etecte y the transitter noe ie a oinant it has not een etecte urin the lo o such occurrence n error occurre since last rea o this reister rrr yclic reunancy hec rror his it inicates that a r rror has een etecte y the receier noe ie the calculate r is ierent ro the receie o such occurrence r error occurre since last rea o this reister frrr for rror his it inicates that a for rror has een etecte y the receier noe ie a ixeor it iel contains at least one illeal it o such occurrence for rror occurre since last rea o this reister frr tuin rror his it inicates that a tuin rror has een etecte o such occurrence tuin rror occurre since last rea o this reister r rror arnin table continues on the next page... chapter 48 can flexcan 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 11 can x r iel escritions continue fiel escrition his it inicates when reetitie errors are occurrin urin essae transission his it is not uate urin freee oe o such occurrence rr is reater than or equal to rr rx rror arnin his it inicates when reetitie errors are occurrin urin essae recetion his it is not uate urin freee oe o such occurrence rrr is reater than or equal to l his it inicates when us is in l state ee the tale in the oerall r reister escrition o such occurrence us is now l flex in ransission his it inicates i flex is transittin a essae ee the tale in the oerall r reister escrition flex is not transittin a essae flex is transittin a essae flof fault onineent tate his it iel inicates the onineent tate o the flex oule the lo it in the ontrol reister is asserte ater soe elay that eens on the it tiin the flof iel will inicate rror assie he ery sae elay aects the way how flof relects an uate to r reister y the u t ay e necessary u to one it tie to et the coherent aain ince the ontrol reister is not aecte y sot reset the flof iel will not e aecte y sot reset i the lo it is asserte rror ctie rror assie x us o r flex in recetion his it inicates i flex is receiin a essae ee the tale in the oerall r reister escrition flex is not receiin a essae flex is receiin a essae off us o nterrut his it is set when flex enters us o state the corresonin as it in the ontrol reister off is set an interrut is enerate to the u his it is cleare y writin it to ritin has no eect table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 12 freescale semiconductor, inc. can x r iel escritions continue fiel escrition o such occurrence flex oule entere us o state rr rror nterrut his it inicates that at least one o the rror its its is set the corresonin as it rlrr is set an interrut is enerate to the u his it is cleare y writin it to ritin has no eect o such occurrence nicates settin o any rror it in the rror an tatus reister aeu nterrut his iel alies when flex is in low ower oe: oe oe to oe hen a recessietooinant transition is etecte on the us an i the r it is set an interrut is enerate to the u his it is cleare y writin it to hen rlf is neate this la is ase he u ust clear this la eore isalin the it otherwise it will e set when the lf is set aain ritin has no eect o such occurrence nicates a recessie to oinant transition was receie on the us nterrut ass reister x this register allows any number of a range of 32 message buffer interrupts to be enabled or disabled. it contains one interrupt mask bit per buffer, enabling the cpu to determine which buffer generates an interrupt after a successful transmission or reception (i.e. when the corresponding iflag2 bit is set). addresses: can0_imask2 is 4002_4000h base + 24h offset = 4002_4024h can1_imask2 is 400a_4000h base + 24h offset = 400a_4024h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r bufhm w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 can x iel escritions fiel escrition ufh uer i as ach it enales or isales the corresonin flex essae uer nterrut o: ettin or clearin a it in the reister can assert or neate an interrut request i the corresonin fl it is set hater flex ufaily reerence anual re o freescale eiconuctor nc can x iel escritions continue fiel escrition he corresonin uer nterrut is isale he corresonin uer nterrut is enale nterrut ass reister x this register allows any number of a range of 32 message buffer interrupts to be enabled or disabled. it contains one interrupt mask bit per buffer, enabling the cpu to determine which buffer generates an interrupt after a successful transmission or reception (i.e. when the corresponding iflag1 bit is set). addresses: can0_imask1 is 4002_4000h base + 28h offset = 4002_4028h can1_imask1 is 400a_4000h base + 28h offset = 400a_4028h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r buflm w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 can x iel escritions fiel escrition ufl uer i as ach it enales or isales the corresonin flex essae uer nterrut o: ettin or clearin a it in the reister can assert or neate an interrut request i the corresonin fl it is set he corresonin uer nterrut is isale he corresonin uer nterrut is enale nterrut flas reister x fl this register defines the flags for 32 message buffer interrupts. it contains one interrupt flag bit per buffer. each successful transmission or reception sets the corresponding iflag2 bit. if the corresponding imask2 bit is set, an interrupt will be generated. the interrupt flag must be cleared by writing 1 to it. writing 0 has no effect. before updating mcr[maxmb] field, cpu must service the iflag2 bits whose mb value is greater than the mcr[maxmb] to be updated; otherwise, they will remain set and be inconsistent with the amount of mbs available. memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1334 freescale semiconductor, inc. addresses: can0_iflag2 is 4002_4000h base + 2ch offset = 4002_402ch can1_iflag2 is 400a_4000h base + 2ch offset = 400a_402ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r bufhi w w1c reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 can x fl iel escritions fiel escrition ufh uer i nterrut ach it las the corresonin flex essae uer interrut he corresonin uer has no occurrence o successully colete transission or recetion he corresonin uer has successully colete transission or recetion nterrut flas reister x fl this register defines the flags for 32 message buffer interrupts. it contains one interrupt flag bit per buffer. each successful transmission or reception sets the corresponding iflag1 bit. if the corresponding imask1 bit is set, an interrupt will be generated. the interrupt flag must be cleared by writing 1 to it. writing 0 has no effect. the buf7i to buf5i flags are also used to represent fifo interrupts when the rx fifo is enabled. when the bit mcr[rfen] is set the function of the 8 least significant interrupt flags buf[7:0]i changes: buf7i, buf6i and buf5i indicate operating conditions of the fifo, and buf4to0i are reserved. before enabling the rfen, the cpu must service the iflag bits asserted in the rx fifo region; see section "rx fifo". otherwise, these iflag bits will mistakenly show the related mbs now belonging to fifo as having contents to be serviced. when the rfen bit is negated, the fifo flags must be cleared. the same care must be taken when an rffn value is selected extending rx fifo filters beyond mb7. for example, when rffn is 0x8, the mb0-23 range is occupied by rx fifo filters and related iflag bits must be cleared. before updating mcr[maxmb] field, cpu must service the iflag1 bits whose mb value is greater than the mcr[maxmb] to be updated; otherwise, they will remain set and be inconsistent with the amount of mbs available. chapter 48 can (flexcan) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1335 addresses: can0_iflag1 is 4002_4000h base + 30h offset = 4002_4030h can1_iflag1 is 400a_4000h base + 30h offset = 400a_4030h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r buf31to8i[bit 8] w w1c reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r buf31to8i[7:0] buf7i buf6i buf5i buf4to0i w w1c w1c w1c w1c w1c reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 can x fl iel escritions fiel escrition ufo uer i nterrut ach it las the corresonin flex essae uer interrut he corresonin uer has no occurrence o successully colete transission or recetion he corresonin uer has successully colete transission or recetion uf uer nterrut or rx ffo oerlow hen the rf it in the r is cleare rx ffo isale this it las the interrut or o: his la is cleare y the flex wheneer the it rrf is chane y u writes he uf la reresents rx ffo oerlow when rrf is set n this case the la inicates that a essae was lost ecause the rx ffo is ull ote that the la will not e asserte when the rx ffo is ull an the essae was cature y a ailox o occurrence o coletin transissionrecetion when rrf or o rx ffo oerlow when rrf colete transissionrecetion when rrf or rx ffo oerlow when rrf uf uer nterrut or rx ffo arnin hen the rf it in the r is cleare rx ffo isale this it las the interrut or o: his la is cleare y the flex wheneer the it rrf is chane y u writes he uf la reresents rx ffo arnin when rrf is set n this case the la inicates when the nuer o unrea essaes within the rx ffo is increase to ro ue to the recetion o a new one eanin that the rx ffo is alost ull ote that i the la is cleare while the nuer o unrea essaes is reater than it oes not assert aain until the nuer o unrea essaes within the rx ffo is ecrease to e equal to or less than table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 16 freescale semiconductor, inc. can x fl iel escritions continue fiel escrition o occurrence o coletin transissionrecetion when rrf or o rx ffo alost ull when rrf colete transissionrecetion when rrf or rx ffo alost ull when rrf uf uer nterrut or fraes aailale in rx ffo hen the rf it in the r is cleare rx ffo isale this it las the interrut or o: his la is cleare y the flex wheneer the it rrf is chane y u writes he uf la reresents fraes aailale in rx ffo when rrf is set n this case the la inicates that at least one rae is aailale to e rea ro the rx ffo o occurrence o coletin transissionrecetion when rrf or o raes aailale in the rx ffo when rrf colete transissionrecetion when rrf or raes aailale in the rx ffo when rrf ufo uer i nterrut or resere hen the rf it in the r is cleare rx ffo isale these its la the interruts or to o: hese las are cleare y the flex wheneer the it rrf is chane y u writes he ufo las are resere when rrf is set he corresonin uer has no occurrence o successully colete transission or recetion when rrf he corresonin uer has successully colete transission or recetion when rrf hater flex ufaily reerence anual re o freescale eiconuctor nc 48.3.14 control 2 register (can x rl this register contains control bits for can errors, fifo features, and mode selection. addresses: can0_ctrl2 is 4002_4000h base + 34h offset = 4002_4034h can1_ctrl2 is 400a_4000h base + 34h offset = 400a_4034h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 wrmfrz rffn tasd mrp rrs eacen w 0 reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 can x rl iel escritions fiel escrition resere his iel is resere resere his reaonly iel is resere an always has the alue ero rfr riteccess to eory in freee oe nale unrestricte write access to flex eory in freee oe his it can only e written in freee oe an has no eect out o freee oe aintain the write access restrictions nale unrestricte write access to flex eory rff uer o rx ffo filters his it iel eines the nuer o rx ffo ilters as shown in the ollowin tale he axiu selectale nuer o ilters is eterine y the u his iel can only e written in freee oe as it is loce y harware in other oes his iel ust not e rorae with alues that ae the nuer o essae uers occuie y rx ffo an filter excee the nuer o ailoxes resent eine y r o: ach rou o eiht ilters occuies a eory sace equialent to two essae uers which eans that the ore ilters are ileente the less ailoxes will e aailale onsierin that the rx ffo occuies the eory sace oriinally resere or rff shoul e rorae with a alue correonin to a nuer o ilters not reater than the nuer o aailale eory wors which can e calculate as ollows: u x where u is the least etween urof an table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 18 freescale semiconductor, inc. can x rl iel escritions continue fiel escrition he nuer o reainin ailoxes aailale will e: u rff x the uer o rx ffo filters rorae throuh rff excees the u alue eory sace aailale the exceein ones will not e unctional rff: uer o rx ffo ilters essae uers occuie y rx ffo an filter ale reainin ailale ailoxes rx ffo filter ale leents ecte y rx niiual ass rx ffo filter ale leents ecte y rx ffo loal as x leents none x leents leents x leents leents x leents leents x leents leents x leents leents x leents leents x leents leents x leents leents x leents leents x leents leents x leents leents x leents leents x leents leents x leents leents xf leents leents he nuer o the last reainin aailale ailoxes is eine y the least alue etween the araeter urof inus an the r iel rx niiual as reisters are not enale then all rx ffo ilters are aecte y the rx ffo loal as x ritration tart elay his it iel inicates how any its the x aritration rocess start oint can e elaye ro the irst it o r iel on us his iel can only e written in freee oe as it is loce y harware in other oes his iel is useul to otiie the transit erorance ase on actors such as: eriheralserial cloc ratio it tiin an nuer o s he uration o an aritration rocess in ters o its is irectly roortional to the nuer o aailale s an au rate an inersely roortional to the eriheral cloc requency he otial aritration tiin is that in which the last is scanne riht eore the irst it o the nterission iel o a rae hereore i there are ew s an the systeserial cloc ratio is hih an the au rate is low then the aritration can e elaye an iceersa table continues on the next page... chapter 48 can flexcan 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1 can x rl iel escritions continue fiel escrition is then the aritration start is not elaye thus the u has less tie to coniure a x or the next aritration ut ore tie is resere or aritration n the other han i is then the u can coniure a x later an less tie is resere or aritration too little tie is resere or aritration the flex ay e not ale to in winner s in tie to coete with other noes or the us the aritration ens too uch tie eore the irst it o nterission iel then there is a chance that the u reconiures soe x s an the winner is not the est to e transitte he otial coniuration or can e calculate as: tasd = 25 - {f canclk x [maxb + 3 - (rfen x 8) - (rfen x rffn x 2)] x 2} / {f sys x [1+(pseg1+1)+(pseg2+1)+(propseg+1)] x (presdiv+1)} where: C f canclk is the protocol engine (pe) clock (see section "protocol timing"), in hz; C f sys is the peripheral clock, in hz; C maxmb is the value in ctrl1[maxmb] field; C rfen is the value in ctrl1[rfen] bit; C rffn is the value in ctrl2[rffn] field; C pseg1 is the value in ctrl1[pseg1] field; C pseg2 is the value in ctrl1[pseg2] field; C propseg is the value in ctrl1[propseg] field; C presdiv is the value in ctrl1[presdiv] field. see section "arbitration process" and section "protocol timing" for more details. note: the recommended value for tasd is 22. 18 mrp mailboxes reception priority if this bit is set the matching process starts from the mailboxes and if no match occurs the matching continues on the rx fifo. this bit can only be written in freeze mode as it is blocked by hardware in other modes. 0 matching starts from rx fifo and continues on mailboxes. 1 matching starts from mailboxes and continues on rx fifo. 17 rrs remote request storing if this bit is asserted remote request frame is submitted to a matching process and stored in the corresponding message buffer in the same fashion of a data frame. no automatic remote response frame will be generated. if this bit is negated the remote request frame is submitted to a matching process and an automatic remote response frame is generated if a message buffer with code=0b1010 is found with the same id. this bit can only be written in freeze mode as it is blocked by hardware in other modes. 0 remote response frame is generated. 1 remote request frame is stored. 16 eacen entire frame arbitration field comparison enable for rx mailboxes this bit controls the comparison of ide and rtr bits whithin rx mailboxes filters with their corresponding bits in the incoming frame by the matching process. this bit does not affect matching for rx fifo. this bit can only be written in freeze mode as it is blocked by hardware in other modes. table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 140 freescale semiconductor, inc. can x rl iel escritions continue fiel escrition rx ailox ilters it is always coare an rr is neer coare esite as its nales the coarison o oth rx ailox ilters an rr it with their corresonin its within the incoin rae as its o aly resere his reaonly iel is resere an always has the alue ero he nuer o the last reainin aailale ailoxes is eine y the least alue etween the araeter urof inus an the r iel rx niiual as reisters are not enale then all rx ffo ilters are aecte y the rx ffo loal as rror an tatus reister x r this register reflects various interrupt flags and some general status. addresses: can0_esr2 is 4002_4000h base + 38h offset = 4002_4038h can1_esr2 is 400a_4000h base + 38h offset = 400a_4038h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 lptm w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 vps imb 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 can x r iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero l lowest riority x ailox r is asserte this iel inicates the lowest nuer inactie ailox reer to the it escrition there is no inactie ailox then the ailox inicate eens on rlluf it alue rlluf it is neate then the ailox inicate is the one which has the reatest aritration alue see the hihest riority ailox irst section rlluf it is asserte then the ailox inicate is the hihest nuer actie x ailox a x ailox is ein transitte it is not consiere in l calculation r is not asserte an a rae is transitte successully l is uate with its ailox nuer resere his reaonly iel is resere an always has the alue ero ali riority tatus his it inicates whether an l contents are currently ali or not is asserte uon eery colete x aritration rocess unless the u writes to ontrol an tatus wor o a ailox that has table continues on the next page... chapter 48 can flexcan 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 141 can x r iel escritions continue fiel escrition alreay een scanne ie it is ehin x ritration ointer urin the x aritration rocess there is no inactie ailox an only one x ailox which is ein transitte then is not asserte is neate uon the start o eery x aritration rocess or uon a write to ontrol an tatus wor o any ailox o: r is not aecte y any u write into ontrol tatus o a which is loce y aort echanis hen r is asserte the aort coe write in o a that is ein transitte enin aort or any write attet into a x with fl set is loce ontents o an l are inali ontents o an l are ali nactie ailox r is asserte this it inicates whether there is any inactie ailox o iel is either or his it is asserte in the ollowin cases: urin aritration i an l is oun an it is inactie is not asserte an a rae is transitte successully his it is cleare in all start o aritration see ection ritration rocess o: l echanis hae the ollowin ehaior: i an is successully transitte an r no inactie ailox then r an r are asserte an the inex relate to the ust transitte is loae into rl r is asserte the rl is not an inactie ailox r is asserte there is at least one inactie ailox l content is the nuer o the irst one resere his reaonly iel is resere an always has the alue ero r reister x rr this register provides information about the crc of transmitted messages. addresses: can0_crcr is 4002_4000h base + 44h offset = 4002_4044h can1_crcr is 400a_4000h base + 44h offset = 400a_4044h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 mbcrc 0 txcrc w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 can x rr iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 142 freescale semiconductor, inc. can x rr iel escritions continue fiel escrition r r ailox his iel inicates the nuer o the ailox corresonin to the alue in r iel resere his reaonly iel is resere an always has the alue ero r r ransitte his iel inicates the r alue o the last essae transitte his iel is uate at the sae tie the x nterrut fla is asserte rx ffo loal as reister x rf this register is located in ram. if rx fifo is enabled rxfgmask is used to mask the rx fifo id filter table elements that do not have a corresponding rximr according to ctrl2[rffn] field setting. this register can only be written in freeze mode as it is blocked by hardware in other modes. addresses: can0_rxfgmask is 4002_4000h base + 48h offset = 4002_4048h can1_rxfgmask is 400a_4000h base + 48h offset = 400a_4048h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r fgm[31:0] w reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 can x rf iel escritions fiel escrition f: rx ffo loal as its hese its as the filter ale eleents its in a erect alinent he ollowin tale shows how the f its correson to each f iel hater flex ufaily reerence anual re o freescale eiconuctor nc can x rf iel escritions continue fiel escrition rx ffo filter ale leents forat r entiier ccetance filter fiels rr r r r resere f f f: f f f f f f: f: f: f: f: f: r iel is equialent to the orat only the ourteen ost siniicant its o the entiier o the incoin rae are coare with the rx ffo ilter r iel is equialent to the orat only the eiht ost siniicant its o the entiier o the incoin rae are coare with the rx ffo ilter he corresonin it in the ilter is ont care he corresonin it in the ilter is chece r iel is equialent to the orat only the ourteen ost siniicant its o the entiier o the incoin rae are coare with the rx ffo ilter r iel is equialent to the orat only the eiht ost siniicant its o the entiier o the incoin rae are coare with the rx ffo ilter rx ffo noration reister x rfr rxfir provides information on rx fifo. this register is the port through which the cpu accesses the output of the rxfir fifo located in ram. the rxfir fifo is written by the flexcan whenever a new message is moved into the rx fifo as well as its output is updated whenever the output of the rx fifo is updated with the next message. see section "rx fifo" for instructions on reading this register. addresses: can0_rxfir is 4002_4000h base + 4ch offset = 4002_404ch can1_rxfir is 400a_4000h base + 4ch offset = 400a_404ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 idhit w reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes: x = undefined at reset. memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1344 freescale semiconductor, inc. can x rfr iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero h entiier ccetance filter hit nicator his iel inicates which entiier ccetance filter was hit y the receie essae that is in the outut o the rx ffo ultile ilters atch the incoin essae then the irst atchin f oun lowest nuer y the atchin rocess is inicate his iel is ali only while the fluf is asserte rx niiual as reisters x rr these registers are located in ram. rximr are used as acceptance masks for id filtering in rx mbs and the rx fifo. if the rx fifo is not enabled, one mask register is provided for each available mailbox, providing id masking capability on a per mailbox basis. when the rx fifo is enabled (mcr[rfen] bit is asserted), up to 32 rx individual mask registers can apply to the rx fifo id filter table elements on a one-to-one correspondence depending on the setting of ctrl2[rffn]. rximr can only be written by the cpu while the module is in freeze mode; otherwise, they are blocked by hardware. the individual rx mask registers are not affected by reset and must be explicitly initialized prior to any reception. addresses: 4002_4000h base + 880h offset + (4d n , where n 0d to 1d bit 1 0 2 28 27 26 2 24 2 22 21 20 1 18 17 16 1 14 1 12 11 10 8 7 6 4 2 1 0 r mi10 w reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * notes x undefined at reset. can x rr n iel escritions fiel escrition : niiual as its ach niiual as it ass the corresonin it in oth the ailox ilter an rx ffo filter ale eleent in istinct ways for ailox ilters see the r reister escrition hater flex ufaily reerence anual re o freescale eiconuctor nc can x rr n iel escritions continue fiel escrition for rx ffo filter ale eleents see the rf reister escrition he corresonin it in the ilter is ont care he corresonin it in the ilter is chece essae uer tructure the message buffer structure used by the flexcan module is represented in the following figure. both extended and standard frames (29-bit identifier and 11-bit identifier, respectively) used in the can specification (version 2.0 part b) are represented. each individual mb is formed by 16 bytes. the memory area from 0x80 to 0x47c is used by the mailboxes. table 48-108. message buffer structure 31 30 29 28 27 24 23 22 21 20 19 18 17 16 15 8 7 0 0x0 code sr r ide rt r dlc time stamp 0x4 prio id (standard/extended) id (extended) 0x8 data byte 0 data byte 1 data byte 2 data byte 3 0xc data byte 4 data byte 5 data byte 6 data byte 7 = unimplemented or reserved code message buffer code this 4-bit field can be accessed (read or write) by the cpu and by the flexcan module itself, as part of the message buffer matching and arbitration process. the encoding is shown in table 48-109 and table 48-110 . see functional description for additional information. table 48-109. message buffer code for rx buffers code description rx code before receive new frame srv 1 rx code after successful reception 2 rrs 3 comment 0b0000: inactive- mb is not active. inactive - - - mb does not participate in the matching process. table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 146 freescale semiconductor, inc. table 48-109. message buffer code for rx buffers (continued) code description rx code before receive new frame srv 1 rx code after successful reception 2 rrs 3 comment 0b0100: empty - mb is active and empty. empty - full - when a frame is received successfully (after move-in process. refer to section "move-in" for details), the code field is automatically updated to full. 0b0010: full - mb is full. full yes full - the act of reading the c/s word followed by unlocking the mb (srv) does not make the code return to empty. it remains full. if a new frame is moved to the mb after the mb was serviced, the code still remains full. refer to section "matching process" for matching details related to full code. no overrun - if the mb is full and a new frame is moved to this mb before the cpu service it, the code field is automatically updated to overrun. refer to section "matching process" for details about overrun behavior. table continues on the next page... chapter 48 can flexcan 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 147 table 48-109. message buffer code for rx buffers (continued) code description rx code before receive new frame srv 1 rx code after successful reception 2 rrs 3 comment 0b0110: overrun - mb is being overwritten into a full buffer. overrun yes full - if the code field indicates overrun and cpu has serviced the mb, when a new frame is moved to the mb, the code returns to full. no overrun - if the code field already indicates overrun, and another new frame must be moved, the mb will be overwritten again, and the code will remain overrun. refer to section "matching process" for details about overrun behavior. table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 148 freescale semiconductor, inc. table 48-109. message buffer code for rx buffers (continued) code description rx code before receive new frame srv 1 rx code after successful reception 2 rrs 3 comment 0b1010: ranswer 4 - a frame was configured to recognize a remote request frame and transmit a response frame in return. ranswer - tanswer(0b111 0) 0 a remote answer was configured to recognize a remote request frame received, after that a mb is set to transmit a response frame. the code is automatically changed to tanswer (0b1110). refer to section "matching process" for details. if ctrl2[rrs] is negated, transmit a response frame whenever a remote request frame with the same id is received. - - 1 this code is ignored during matching and arbitration process. refer to section "matching process for details. code[0]=1b1: busy - flexcan is updating the contents of the mb. the cpu must not access the mb. busy 5 - full - indicates that the mb is being updated, it will be negated automatically and does not interfere on the next code. - overrun - 1. srv: serviced mb. mb was read and unlocked by reading timer or other mb. 2. a frame is considered successful reception after the frame to be moved to mb (move-in process). refer to section "move- in" for details) 3. remote request stored bit from ctrl2 register. refer to section "control 2 register (ctrl2)" for details. 4. code 0b1010 is not considered tx and a mb with this code should not be aborted. 5. note that for tx mbs, the busy bit should be ignored upon read, except when aen bit is set in the mcr register. if this bit is asserted, the corresponding mb does not participate in the matching process. chapter 48 can (flexcan) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1349 table 48-110. message buffer code for tx buffers code description tx code before tx frame mbrtr tx code after successful transmission comment 0b1000: inactive - mb is not active inactive - - mb does not participate in the arbitration process. 0b1001: abort - mb is aborted abort - - mb does not participate in the arbitration process. 0b1100: data - mb is a tx data frame (mb rtr must be 0) data 0 inactive transmit data frame unconditionally once. after transmission, the mb automatically returns to the inactive state. 0b1100: remote - mb is a tx remote request frame (mb rtr must be 1) remote 1 empty transmit remote request frame unconditionally once. after transmission, the mb automatically becomes an rx empty mb with the same id. 0b1110: tanswer - mb is a tx response frame from an incoming remote request frame tanswer - ranswer this is an intermediate code that is automatically written to the mb by the chi as a result of match to a remote request frame. the remote response frame will be transmitted unconditionally once and then the code will automatically return to ranswer (0b1010). the cpu can also write this code with the same effect. the remote response frame can be either a data frame or another remote request frame depending on the rtr bit value. refer to section matching process" and section arbitration process" for details. srr substitute remote request memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1350 freescale semiconductor, inc. fixed recessive bit, used only in extended format. it must be set to '1' by the user for transmission (tx buffers) and will be stored with the value received on the can bus for rx receiving buffers. it can be received as either recessive or dominant. if flexcan receives this bit as dominant, then it is interpreted as arbitration loss. 1 = recessive value is compulsory for transmission in extended format frames 0 = dominant is not a valid value for transmission in extended format frames ide id extended bit this bit identifies whether the frame format is standard or extended. 1 = frame format is extended 0 = frame format is standard rtr remote transmission request this bit affects the behavior of remote frames and is part of the reception filter. refer to table 48-109 , table 48-110 and the description of the rrs bit in control 2 register (ctrl2) for additional details. if flexcan transmits this bit as '1' (recessive) and receives it as '0' (dominant), it is interpreted as arbitration loss. if this bit is transmitted as '0' (dominant), then if it is received as '1' (recessive), the flexcan module treats it as bit error. if the value received matches the value transmitted, it is considered as a successful bit transmission. 1 = indicates the current mb may have a remote request frame to be transmitted if mb is tx. if the mb is rx then incoming remote request frames may be stored. 0 = indicates the current mb has a data frame to be transmitted.. in rx mb it may be considered in matching processes. dlc length of data in bytes this 4-bit field is the length (in bytes) of the rx or tx data, which is located in offset 0x8 through 0xf of the mb space (see table 48-108 ). in reception, this field is written by the flexcan module, copied from the dlc (data length code) field of the received frame. in transmission, this field is written by the cpu and corresponds to the dlc field value of the frame to be transmitted. when rtr=1, the frame to be transmitted is a remote frame and does not include the data field, regardless of the dlc field. time stamp free-running counter time stamp this 16-bit field is a copy of the free-running timer, captured for tx and rx frames at the time when the beginning of the identifier field appears on the can bus. prio local priority chapter 48 can (flexcan) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1351 this 3-bit field is only used when lprio_en bit is set in mcr and it only makes sense for tx mailboxes. these bits are not transmitted. they are appended to the regular id to define the transmission priority. see arbitration process . id frame identifier in standard frame format, only the 11 most significant bits (28 to 18) are used for frame identification in both receive and transmit cases. the 18 least significant bits are ignored. in extended frame format, all bits are used for frame identification in both receive and transmit cases. data byte 0-7 data field up to eight bytes can be used for a data frame. for rx frames, the data is stored as it is received from the can bus. data byte (n) is valid only if n is less than dlc as shown in the table below. for tx frames, the cpu prepares the data field to be transmitted within the frame. table 48-111. data bytes validity dlc valid data bytes 0 none 1 data byte 0 2 data byte 0-1 3 data byte 0-2 4 data byte 0-3 5 data byte 0-4 6 data byte 0-5 7 data byte 0-6 8 data byte 0-7 48.3.57 rx fifo structure when the mcr[rfen] bit is set, the memory area from 0x80 to 0xdc (which is normally occupied by mbs 0 to 5) is used by the reception fifo enginee. the region 0x80-0x8c contains the output of the fifo which must be read by the cpu as a message buffer. this output contains the oldest message received and not read yet. the region 0x90-0xdc is reserved for internal use of the fifo engine. memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1352 freescale semiconductor, inc. an additional memory area, that starts at 0xe0 and may extend up to 0x2dc (normally occupied by mbs 6 up to 37) depending on the ctrl2[rffn] field setting, contains the id filter table (configurable from 8 to 128 table elements) that specifies filtering criteria for accepting frames into the fifo. out of reset, the id filter table flexible memory area defaults to 0xe0 and only extends to 0xfc, which corresponds to mbs 6 to 7 for rffn=0, for backward compatibility with previous versions of flexcan. the following shows the rx fifo data structure. table 48-112. rx fifo structure 31 28 24 23 22 21 20 19 18 17 16 15 8 7 0 0x80 srr ide rtr dlc time stamp 0x84 id standard id extended 0x88 data byte 0 data byte 1 data byte 2 data byte 3 0x8c data byte 4 data byte 5 data byte 6 data byte 7 0x90 to 0xdc reserved 0xe0 id filter table element 0 0xe4 id filter table element 1 0xe8 to 0x2d4 id filter table elements 2 to 125 0x2d8 id filter table element 126 0x2dc id filter table element 127 = unimplemented or reserved each id filter table element occupies an entire 32-bit word and can be compound by one, two or four identifier acceptance filters (idaf) depending on the mcr[idam] field setting. the following figures show the idaf indexation. the following figures show the three different formats of the id table elements. note that all elements of the table must have the same format. see rx fifo for more information. table 48-113. id table structure format 31 30 29 24 23 16 15 14 13 8 7 1 0 a rtr ide rxida (standard = 29-19, extended = 29-1) table continues on the next page... chapter 48 can flexcan 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1 table 48-113. id table structure (continued) b rtr ide rxidb_0 (standard = 29-19, extended = 29-16) rtr ide rxidb_1 (standard = 13-3, extended = 13-0) c rxidc_0 (std/ext = 31-24) rxidc_1 (std/ext = 23-16) rxidc_2 (std/ext = 15-8) rxidc_3 (std/ext = 7-0) = unimplemented or reserved rtr remote frame this bit specifies if remote frames are accepted into the fifo if they match the target id. 1 = remote frames can be accepted and data frames are rejected 0 = remote frames are rejected and data frames can be accepted ide extended frame specifies whether extended or standard frames are accepted into the fifo if they match the target id. 1 = extended frames can be accepted and standard frames are rejected 0 = extended frames are rejected and standard frames can be accepted rxida rx frame identifier (format a) specifies an id to be used as acceptance criteria for the fifo. in the standard frame format, only the 11 most significant bits (29 to 19 ) are used for frame identification. in the extended frame format, all bits are used. rxidb_0, rxidb_1 rx frame identifier (format b) specifies an id to be used as acceptance criteria for the fifo. in the standard frame format, the 11 most significant bits (a full standard id) (29 to 19 and 13 to 3 ) are used for frame identification. in the extended frame format, all 14 bits of the field are compared to the 14 most significant bits of the received id. rxidc_0, rxidc_1, rxidc_2, rxidc_3 rx frame identifier (format c) specifies an id to be used as acceptance criteria for the fifo. in both standard and extended frame formats, all 8 bits of the field are compared to the 8 most significant bits of the received id. memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1354 freescale semiconductor, inc. 48.4 functional description the flexcan module is a can protocol engine with a very flexible mailbox system for transmitting and receiving can frames. the mailbox system is composed by a set of up to 64message buffers (mb) that store configuration and control data, time stamp, message id and data (see message buffer structure ). the memory corresponding to the first 38 mbs can be configured to support a fifo reception scheme with a powerful id filtering mechanism, capable of checking incoming frames against a table of ids (up to 128 extended ids or 256 standard ids or 512 8-bit id slices), with individual mask register for up to 32 id tables. simultaneous reception through fifo and mailbox is supported. for mailbox reception, a matching algorithm makes it possible to store received frames only into mbs that have the same id programmed on its id field. a masking scheme makes it possible to match the id programmed on the mb with a range of ids on received can frames. for transmission, an arbitration algorithm decides the prioritization of mbs to be transmitted based on the message id (optionally augmented by 3 local priority bits) or the mb ordering. before proceeding with the functional description, an important concept must be explained. a message buffer is said to be "active" at a given time if it can participate in both the matching and arbitration processes. an rx mb with a 0b0000 code is inactive (refer to table 48-109 ). similarly, a tx mb with a 0b1000 or 0b1001 code is also inactive (refer to table 48-110 ). 48.4.1 transmit process in order to transmit a can frame, the cpu must prepare a message buffer for transmission by executing the following procedure: 1. check if the respective interrupt bit is set and clear it. 2. if the mb is active (transmission pending), write the abort code (0b1001) to the code field of the control and status word to request an abortion of the transmission. wait for the corresponding iflag to be asserted by polling the iflag register or by the interrupt request if enabled by the respective imask. then read back the code field to check if the transmission was aborted or transmitted (see transmission abort mechanism ). if backwards compatibility is desired (mcr[aen] bit is negated), just write the inactive code (0b1000) to the code field to inactivate the mb but then the pending frame may be transmitted without notification (see section "message buffer inactivation"). chapter 48 can (flexcan) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1355 3. write the id word. 4. write the data bytes. 5. write the dlc, control and code fields of the control and status word to activate the mb. once the mb is activated in the fourth step, it will participate into the arbitration process and eventually be transmitted according to its priority. at the end of the successful transmission, the value of the free running timer is written into the time stamp field, the code field in the control and status word is updated, the crc register is updated, a status flag is set in the interrupt flag register and an interrupt is generated if allowed by the corresponding interrupt mask register bit. the new code field after transmission depends on the code that was used to activate the mb in step four (see table 48-109 and table 48-110 in section message buffer structure ). when the abort feature is enabled (mcr[aen] is asserted), after the interrupt flag is asserted for a mb configured as transmit buffer, the mb is blocked, therefore the cpu is not able to update it until the interrupt flag is negated by cpu. this means that the cpu must clear the corresponding iflag before starting to prepare this mb for a new transmission or reception. 48.4.2 arbitration process the arbitration process scans the mailboxes searching the tx one that holds the message to be sent in the next opportunity. this mailbox is called the arbitration winner . the scan starts from the lowest number mailbox and runs toward the higher ones. the arbitration process is triggered in the following events: ? from the crc field of the can frame. the start point depends on the ctrl2[tasd] field value. ? during the error delimiter field of a can frame. ? during the overload delimiter field of a can frame. ? when the winner is inactivated and the can bus has still not reached the first bit of the intermission field. ? when there is cpu write to the c/s word of a winner mb and the can bus has still not reached the first bit of the intermission field. ? when chi is in idle state and the cpu writes to the c/s word of any mb. functional description k60 sub-family reference manual, rev. 6, nov 2011 1356 freescale semiconductor, inc. ? when flexcan exits bus off state. ? upon leaving freeze mode or low power mode. if the arbitration process does not manage to evaluate all mailboxes before the can bus has reached the first bit of the intermission field the temporary arbitration winner is invalidated and the flexcan will not compete for the can bus in the next opportunity. the arbitration process selects the winner among the active tx mailboxes at the end of the scan according to both ctrl1[lbuf] and mcr[lprio_en] bits settings. 48.4.2.1 lowest number mailbox first if ctrl1[lbuf] bit is asserted the first (lowest number) active tx mailbox found is the arbitration winner. mcr[lprio_en] bit has no effect when ctrl1[lbuf] is asserted. 48.4.2.2 highest priority mailbox first if ctrl1[lbuf] bit is negated then the arbitration process searches the active tx mailbox with the highest priority, which means that this mailboxs frame would have a higher probability to win the arbitration on can bus with multiple nodes driving each tx mailboxs frame at the same time. the sequence of bits considered for this arbitration is called the arbitration value of the mailbox. the highest priority tx mailbox is the one that has the least arbitration value among all tx mailboxes. if two or more mailboxes have equivalent arbitration values the lowest number mailbox is the arbitration winner. the composition of the arbitration value depends on mcr[lprio_en] bit setting. 48.4.2.2.1 local priority disabled if mcr[lprio_en] bit is negated the arbitration value is built in the exact sequence of bits as they would be transmitted in a can frame (see the following table) in such a way that the local priority is disabled. chapter 48 can (flexcan) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1357 table 48-114. composition of the arbitration value when local priority is disabled format mailbox arbitration value (32 bits) standard (ide = 0) standard id (11 bits) rtr (1 bit) ide (1 bit) - (18 bits) - (1 bit) extended (ide = 1) extended id[28:18] (11 bits) srr (1 bit) ide (1 bit) extended id[17:0] (18 bits) rtr (1 bit) 48.4.2.2.2 local priority enabled if local priority is desired mcr[lprio_en] must be asserted. in this case the mailbox prio field is included at the very left of the arbitration value (see the following table). table 48-115. composition of the arbitration value when local priority is enabled format mailbox arbitration value (35 bits) standard (ide = 0) prio (3 bits) standard id (11 bits) rtr (1 bit) ide (1 bit) - (18 bits) - (1 bit) extended (ide = 1) prio (3 bits) extended id[28:18] (11 bits) srr (1 bit) ide (1 bit) extended id[17:0] (18 bits) rtr (1 bit) as the prio field is the most significant part of the arbitration value mailboxes with low prio values have higher priority than mailboxes with high prio values regardless the rest of their arbitration values. note that the prio field is not part of the frame on the can bus. its purpose is only to affect the internal arbitration process. 48.4.2.3 arbitration process (continued) once the arbitration winner is found, its content is copied to a hidden auxiliary mb called tx serial message buffer (tx smb), which has the same structure as a normal mb but is not user accessible. this operation is called move-out and after it is done, write access to the corresponding mb is blocked (if the aen bit in mcr is asserted). the write access is released in the following events: ? after the mb is transmitted ? flexcan enters in freeze mode or bus off ? flexcan loses the bus arbitration or there is an error during the transmission at the first opportunity window on the can bus, the message on the tx smb is transmitted according to the can protocol rules. flexcan transmits up to eight data bytes, even if the dlc (data length code) field value is greater than that. functional description k60 sub-family reference manual, rev. 6, nov 2011 1358 freescale semiconductor, inc. arbitration process can be triggered in the following situations: ? during rx and tx frames from can crc field to end of frame. arbitration start point depends on instantiation parameters number_of_mb and tasd. additionally, tasd value may be changed to optimize the arbitration start point. ? during can busoff state from tx_err_cnt=124 to 128. arbitration start point depends on instantiation parameters number_of_mb and tasd. additionally, tasd value may be changed to optimize the arbitration start point. ? during c/s write by cpu in busidle. first c/s write starts arbitration process and a second c/s write during this same arbitration restarts the process. if other c/s writes are performed, tx arbitration process is pending. if there is no arbitration winner after arbitration process has finished, then tx arbitration machine begins a new arbitration process. ? ? if there is a pending arbitration and busidle state starts then an arbitration process is triggered. in this case the first and second c/s write in busidle will not restart the arbitration process. it is possible that there is not enough time to finish arbitration in waitforbusidle state and the next state is idle. in this case the scan is not interrupted, and it is completed during busidle state. during this arbitration c/s write does not cause arbitration restart. ? arbitration winner deactivation during a valid arbitration window. ? upon leave freeze mode (first bit of the waitforbusidle state). if there is a re- synchronization during waitforbusidle arbitration process is restarted. arbitration process stops in the following situation: ? all mailboxes were scanned. ? a tx active mailbox is found in case of lowest buffer feature enabled. ? arbitration winner inactivation or abort during any arbitration process. ? there was not enough time to finish tx arbitration process. for instance, a deactivation was performed near the end of frame). in this case arbitration process is pending. ? error or overload flag in the bus . ? low power or freeze mode request in idle state arbitration is considered pending as described below: ? it was not possible to finish arbitration process in time. ? c/s write during arbitration if write is performed in a mb which number is lower than the tx arbitration pointer . ? any c/s write if there is no tx arbitration process in progress. ? rx match has just updated a rx code to tx code. ? entering busoff state. c/s write during arbitration has the following effect: chapter 48 can (flexcan) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1359 ? if c/s write is performed in the arbitration winner, a new process is restarted immediately. ? if c/s write is performed in a mb whose number is higher than the tx arbitration pointer, the ongoing arbitration process will scan this mb as normal. 48.4.3 receive process to be able to receive can frames into a mailbox, the cpu must prepare it for reception by executing the following steps: 1. if the mailbox is active (either tx or rx) inactivate the mailbox (see section "message buffer inactivation"), preferably with a safe inactivation (see transmission abort mechanism ). 2. write the id word 3. write the empty code (0b0100) to the code field of the control and status word to activate the mailbox. once the mb is activated, it will be able to receive frames that match the programmed filter. at the end of a successful reception, the mailbox is updated by the move-in process (see section "move-in") as follows: 1. the received data field (8 bytes at most) is stored. 2. the received identifier field is stored. 3. the value of the free running timer at the time of the second bit of frames identifier field is written into the mailboxs time stamp field. 4. the received srr, ide, rtr and dlc fields are stored. 5. the code field in the control and status word is updated (see table 48-109 and table 48-110 in section message buffer structure ). 6. a status flag is set in the interrupt flag register and an interrupt is generated if allowed by the corresponding interrupt mask register bit. the recommended way for cpu servicing (read) the frame received in an mailbox is using the following procedure: 1. read the control and status word of that mailbox. 2. check if the busy bit is deasserted, indicating that the mailbox is locked. repeat step 1) while it is asserted. see section "message buffer lock mechanism". functional description k60 sub-family reference manual, rev. 6, nov 2011 1360 freescale semiconductor, inc. 3. read the contents of the mailbox. once mailbox is locked now, its contents wont be modified by flexcan move-in processes. see section "move-in". 4. acknowledge the proper flag at iflag registers. 5. read the free running timer. it is optional but recommended to unlock mailbox as soon as possible and make it available for reception. the cpu should synchronize to frame reception by the status flag bit for the specific mailbox in one of the iflag registers and not by the code field of that mailbox. polling the code field does not work because once a frame was received and the cpu services the mailbox (by reading the c/s word followed by unlocking the mailbox), the code field will not return to empty. it will remain full, as explained in table 48-109 . if the cpu tries to workaround this behavior by writing to the c/s word to force an empty code after reading the mailbox without a prior safe inactivation , a newly received frame matching the filter of that mailbox may be lost. caution in summary: never do polling by reading directly the c/s word of the mailboxes. instead, read the iflag registers. note that the received frames identifier field is always stored in the matching mailbox, thus the contents of the id field in an mailbox may change if the match was due to masking. note also that flexcan does receive frames transmitted by itself if there exists a matching rx mailbox, provided the mcr[srxdis] bit is not asserted. if the mcr[srxdis] bit is asserted, flexcan will not store frames transmitted by itself in any mb, even if it contains a matching mb, and no interrupt flag or interrupt signal will be generated due to the frame reception. to be able to receive can frames through the rx fifo, the cpu must enable and configure the rx fifoduring freeze mode (see rx fifo ). upon receiving the frames available in rx fifo interrupt (see the description of the iflag[buf5i] "frames available in rx fifo" bit in the imask1 register), the cpu should service the received frame using the following procedure: 1. read the control and status word (optional C needed only if a mask was used for ide and rtr bits) 2. read the id field (optional C needed only if a mask was used) 3. read the data field 4. read the rxfir register (optional) chapter 48 can (flexcan) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1361 5. clear the frames available in rx fifo interrupt by writing 1 to iflag[buf5i] bit (mandatory C releases the mb and allows the cpu to read the next rx fifo entry) 48.4.4 matching process the matching process scans the mb memory looking for rx mbs programmed with the same id as the one received from the can bus. if the fifo is enabled, the priority of scanning can be selected between mailboxes and fifo filters. in any case, the matching starts from the lowest number message buffer toward the higher ones. if no match is found within the first structure then the other is scanned subsequently. in the event that the fifo is full, the matching algorithm will always look for a matching mb outside the fifo region. as the frame is being received, it is stored in a hidden auxiliary mb called rx serial message buffer (rx smb). the matching process start point depends on the following conditions: ? if the received frame is a remote frame, the start point is the crc field of the frame; ? if the received frame is a data frame with dlc field equal to zero, the start point is the crc field of the frame; ? if the received frame is a data frame with dlc field different than zero, the start point is the data field of the frame; if a matching id is found in the fifo table or in one of the mailboxes, the contents of the smb will be transferred to the fifo or to the matched mailbox by the move-in process. if any can protocol error is detected then no match results will be transferred to the fifo or to the matched mailbox at the end of reception. the matching process scans all matching elements of both rx fifo (if enabled) and active rx mailboxes (code is empty, full, overrun or ranswer) in search of a successful comparison with the matching elements of the rx smb that is receiving the frame on the can bus. the smb has the same structure of a mailbox. the reception structures (rx fifo or mailboxes) associated with the matching elements that had a successful comparison are the matched structures . the matching winner is selected at the end of the scan among those matched structures and depends on conditions described ahead. see the following table. functional description k60 sub-family reference manual, rev. 6, nov 2011 1362 freescale semiconductor, inc. table 48-116. matching architecture structure smb[rtr] ctrl2[rrs] ctrl2[eac en] mb[ide] mb[rtr] mb[id 1 ] mb[code] mailbox 0 - 0 cmp 2 no_cmp 3 cmp_msk 4 empty or full or overrun mailbox 0 - 1 cmp_msk cmp_msk cmp_msk empty or full or overrun mailbox 1 0 - cmp no_cmp cmp ranswer mailbox 1 1 0 cmp no_cmp cmp_msk empty or full or overrun mailbox 1 1 1 cmp_msk cmp_msk cmp_msk empty or full or overrun fifo 5 - - - cmp_msk cmp_msk cmp_msk - 1. for mailbox structure, if smb[ide] is asserted, the id is 29 bits (id standard + id extended). if smb[ide] is negated, the id is only 11 bits (id standard). for fifo structure, the id depends on idam. 2. cmp: compares the smb contents with the mb contents regardless the masks. 3. no_cmp: the smb contents are not compared with the mb contents 4. cmp_msk: compares the smb contents with mb contents taking into account the masks. 5. smb[ide] and smb[rtr] are not taken into account when idam is type c. a reception structure is free-to-receive when any of the following conditions is satisfied: ? the code field of the mailbox is empty; ? the code field of the mailbox is either full or overrun and it has already been serviced (the c/s word was read by the cpu and unlocked as described in message buffer lock mechanism ); ? the code field of the mailbox is either full or overrun and a inactivation (see message buffer inactivation ) is performed; ? the rx fifo is not full. the scan order for mailboxes and rx fifo is from the matching element with lowest number to the higher ones. the matching winner search for mailboxes is affected by the mcr[irmq] bit. if it is negated the matching winner is the first matched mailbox regardless if it is free-to- receive or not. if it is asserted, the matching winner is selected according to the priority below: 1. the first free-to-receive matched mailbox; 2. the last non free-to-receive matched mailbox. it is possible to select the priority of scan between mailboxes and rx fifo by the ctrl2[mrp] bit. chapter 48 can (flexcan) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1363 if the selected priority is rx fifo first: ? if the rx fifo is a matched structure and is free-to-receive then the rx fifo is the matching winner regardless of the scan for mailboxes; ? otherwise (the rx fifo is not a matched structure or is not free-to-receive), then the matching winner is searched among mailboxes as described above. if the selected priority is mailboxes first: ? if a free-to-receive matched mailbox is found, it is the matching winner regardless the scan for rx fifo; ? if no matched mailbox is found, then the matching winner is searched in the scan for the rx fifo; if both conditions above are not satisfied and a non free-to-receive matched mailbox is found then the matching winner determination is conditioned by the mcr[irmq] bit: ? if mcr[irmq] bit is negated the matching winner is the first matched mailbox; ? if mcr[irmq] bit is asserted the matching winner is the rx fifo if it is a free-to- receive matched structure, otherwise the matching winner is the last non free-to- receive matched mailbox. see the following table for a summary of matching possibilities. table 48-117. matching possibilities and resulting reception structures rfen irmq mrp matched in mb matched in fifo reception structure description no fifo, only mb, match is always mb first 0 0 x 1 none 2 - 3 none frame lost by no match 0 0 x free 4 - firstmb 0 1 x none - none frame lost by no match 0 1 x free - firstmb 0 1 x notfree - lastmb overrun fifo enabled, no match in fifo is as if fifo does not exist 1 0 x none none 5 none frame lost by no match 1 0 x free none firstmb 1 1 x none none none frame lost by no match 1 1 x free none firstmb 1 1 x notfree none lastmb overrun table continues on the next page... functional description 60 sub-family reference manual, rev. 6, nov 2011 164 freescale semiconductor, inc. table 48-117. matching possibilities and resulting reception structures (continued) rfen irmq mrp matched in mb matched in fifo reception structure description fifo enabled, queue disabled 1 0 0 x notfull 6 fifo 1 0 0 none full 7 none frame lost by fifo full (fifo overflow) 1 0 0 free full firstmb 1 0 0 notfree full firstmb 1 0 1 none notfull fifo 1 0 1 none full none frame lost by fifo full (fifo overflow) 1 0 1 free x firstmb 1 0 1 notfree x firtsmb overrun fifo enabled, queue enabled 1 1 0 x notfull fifo 1 1 0 none full none frame lost by fifo full (fifo overflow) 1 1 0 free full firstmb 1 1 0 notfree full lastmb overrun 1 1 1 none notfull fifo 1 1 1 free x firstmb 1 1 1 notfree notfull fifo 1 1 1 notfree full lastmb overrun 1. this is a don?t care condition. 2. matched in mb none? means that the frame has not matched any mb (free-to-receive or non-free-to-receive). 3. this is a forbidden condition. 4. matched in mb free? means that the frame matched at least one mb free-to-receive regardless of whether it has matched mbs non-free-to-receive. 5. matched in fifo none? means that the frame has not matched any filter in fifo. it is as if the fifo didn?t exist (ctrl2[rfen]=0). 6. matched in fifo notfull? means that the frame has matched a fifo filter and has empty slots to receive it. 7. matched in fifo full? means that the frame has matched a fifo filter but couldn?t store it because it has no empty slots to receive it. if a non-safe mailbox inactivation (see message buffer inactivation ) occurs during matching process and the mailbox inactivated is the temporary matching winner then the temporary matching winner is invalidated. the matching elements scan is not stopped nor restarted, it continues normally. the consequence is that the current matching process works as if the matching elements compared before the inactivation did not exist, therefore a message may be lost. chapter 48 can (flexcan) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1365 suppose, for example, that the fifo is disabled, irmq is enabled and there are two mbs with the same id, and flexcan starts receiving messages with that id. let us say that these mbs are the second and the fifth in the array. when the first message arrives, the matching algorithm will find the first match in mb number 2. the code of this mb is empty, so the message is stored there. when the second message arrives, the matching algorithm will find mb number 2 again, but it is not "free-to-receive", so it will keep looking and find mb number 5 and store the message there. if yet another message with the same id arrives, the matching algorithm finds out that there are no matching mbs that are "free-to-receive", so it decides to overwrite the last matched mb, which is number 5. in doing so, it sets the code field of the mb to indicate overrun. the ability to match the same id in more than one mb can be exploited to implement a reception queue (in addition to the full featured fifo) to allow more time for the cpu to service the mbs. by programming more than one mb with the same id, received messages will be queued into the mbs. the cpu can examine the time stamp field of the mbs to determine the order in which the messages arrived. matching to a range of ids is possible by using id acceptance masks. flexcan supports individual masking per mb. refer to the description of the rx individual mask registers (rximrx). during the matching algorithm, if a mask bit is asserted, then the corresponding id bit is compared. if the mask bit is negated, the corresponding id bit is "don't care". please note that the individual mask registers are implemented in ram, so they are not initialized out of reset. also, they can only be programmed while the module is in freeze mode; otherwise, they are blocked by hardware. flexcan also supports an alternate masking scheme with only four mask registers (rgxmask, rx14mask, rx15mask and rxfgmask) for backwards compatibility. this alternate masking scheme is enabled when the irmq bit in the mcr register is negated. 48.4.5 move process there are two types of move process: move-in and move-out. 48.4.5.1 move-in the move-in process is the copy of a message received by an rx smb to a rx mailbox or fifo that has matched it. if the move destination is the rx fifo, attributes of the message are also copied to the rxfir fifo. each rx smb has its own move-in process, functional description k60 sub-family reference manual, rev. 6, nov 2011 1366 freescale semiconductor, inc. but only one is performed at a given time as described ahead. the move-in starts only when the message held by the rx smb has a corresponding matching winner (see section "matching process") and all of the following conditions are true: ? the can bus has reached or let past either: ? ? the second bit of intermission field next to the frame that carried the message that is in the rx smb; ? the first bit of an overload frame next to the frame that carried the message that is in the rx smb; ? there is no ongoing matching process; ? the destination mailbox is not locked by the cpu; ? there is no ongoing move-in process from another rx smb. if more than one move- in processes are to be started at the same time both are performed and the newest substitutes the oldest. the term pending move-in is used throughout the document and stands for a move-to-be that still does not satisfy all of the aforementioned conditions. the move-in is cancelled and the rx smb is able to receive another message if any of the following conditions is satisfied: ? the destination mailbox is inactivated after the can bus has reached the first bit of intermission field next to the frame that carried the message and its matching process has finished; ? there is a previous pending move-in to the same destination mailbox; ? the rx smb is receiving a frame transmitted by the flexcan itself and the self- reception is disabled (mcr[srxdis] bit is asserted); ? any can protocol error is detected. note that the pending move-in is not cancelled if the module enters freeze or low power mode. it only stays on hold waiting for exiting freeze and low pwer mode and to be unlocked. if an mb is unlocked during freeze mode, the move-in happens immediately. the move-in process is the execution by the flexcan of the following steps: 1. if the message is destined to the rx fifo, push idhit into the rxfir fifo; 2. reads the words data0-3 and data4-7 from the rx smb; 3. writes it in the words data0-3 and data4-7 of the rx mailbox; 4. reads the words control/status and id from the rx smb; 5. writes it in the words control/status and id of the rx mailbox, updating the code field. chapter 48 can (flexcan) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1367 the move-in process is not atomic, in such a way that it is immediately cancelled by the inactivation of the destination mailbox (see section "message buffer inactivation") and in this case the mailbox may be left partially updated, thus incoherent. the exception is if the move-in destination is an rx fifo message buffer, then the process cannot be cancelled. the busy bit (least significant bit of the code field) of the destination message buffer is asserted while the move-in is being performed to alert the cpu that the message buffer content is temporarily incoherent. 48.4.5.2 move-out the move-out process is the copy of the content from a tx mailbox to the tx smb when a message for transmission is available (see section "arbitration process"). the move-out occurs in the following conditions: ? the first bit of intermission field; ? during bussoff field when tx error counter is in the 124 to 128 range; ? during busidle field ? during wait for bus idle field the move-out process is not atomic. only the cpu has priority to access the memory concurrently out of busidle state. in busidle, the move-out has the lowest priority to the concurrent memory accesses. 48.4.6 data coherence in order to maintain data coherency and flexcan proper operation, the cpu must obey the rules described in transmit process and receive process . any form of cpu accessing an mb structure within flexcan other than those specified may cause flexcan to behave in an unpredictable way. 48.4.6.1 transmission abort mechanism the abort mechanism provides a safe way to request the abortion of a pending transmission. a feedback mechanism is provided to inform the cpu if the transmission was aborted or if the frame could not be aborted and was transmitted instead. two primary conditions must be fulfilled in order to abort a transmission: functional description k60 sub-family reference manual, rev. 6, nov 2011 1368 freescale semiconductor, inc. ? mcr[aen] bit must be asserted; ? the first cpu action must be the writing of abort code (0b1001) into the code field of the control and status word. the active mbs configured as transmission must be aborted first and then they may be updated. if the abort code is written to a mailbox that is currently being transmitted, or to a mailbox that was already loaded into the smb for transmission, the write operation is blocked and the mb is kept active, but the abort request is captured and kept pending until one of the following conditions are satisfied: ? the module loses the bus arbitration ? there is an error during the transmission ? the module is put into freeze mode ? the module enters in busoff state ? there is an overload frame if none of conditions above are reached, the mb is transmitted correctly, the interrupt flag is set in the iflag register and an interrupt to the cpu is generated (if enabled). the abort request is automatically cleared when the interrupt flag is set. on the other hand, if one of the above conditions is reached, the frame is not transmitted; therefore, the abort code is written into the code field, the interrupt flag is set in the iflag and an interrupt is (optionally) generated to the cpu. if the cpu writes the abort code before the transmission begins internally, then the write operation is not blocked; therefore, the mb is updated and the interrupt flag is set. in this way the cpu just needs to read the abort code to make sure the active mb was safely inactivated . although the aen bit is asserted and the cpu wrote the abort code, in this case the mb is inactivated and not aborted, because the transmission did not start yet. one mailbox is only aborted when the abort request is captured and kept pending until one of the previous conditions are satisfied. the abort procedure can be summarized as follows: ? cpu checks the corresponding iflag and clears it, if asserted. ? cpu writes 0b1001 into the code field of the c/s word. ? cpu waits for the corresponding iflag indicating that the frame was either transmitted or aborted. chapter 48 can (flexcan) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1369 ? cpu reads the code field to check if the frame was either transmitted (code=0b1000) or aborted (code=0b1001). ? it is necessary to clear the corresponding iflag in order to allow the mb to be reconfigured. 48.4.6.2 message buffer inactivation inactivation is a mechanism provided to protect the mailbox against updates by the flexcan internal processes, thus allowing the cpu to rely on mailbox data coherence after having updated it, even in normal mode. inactivation of transmission mailboxes must be performed just when mcr[aen] bit is deasserted. if a mailbox is inactivated it participates in neither the arbitration process nor the matching process until it is reactivated. see section "transmit process" and section "receive process" for more detailed instruction on how to inactivate and reactivate a mailbox. in order to inactivate a mailbox the cpu must update its code field to inactive (either 0b0000 or 0b1000). as the user is not able to synchronize the code field update with the flexcan internal processes an inactivation can lead to undesirable results: ? a frame in the bus that matches the filtering of the inactivated rx mailbox may be lost without notice, even if there are other mailboxes with the same filter; ? a frame containing the message within the inactivated tx mailbox may be transmitted without notice. in order to eliminate such risk and perform a safe inactivation the cpu must use the following mechanism along with the inactivation itself: ? for tx mailboxes, the transmission abort (see section "transmission abort mechanism"); the inactivation automatically unlocks the mailbox (see section "message buffer lock mechanism"). note message buffers that are part of the rx fifo cannot be inactivated. there is no write protection on the fifo region by functional description k60 sub-family reference manual, rev. 6, nov 2011 1370 freescale semiconductor, inc. flexcan. cpu must maintain data coherency in the fifo region when rfen is asserted. 48.4.6.3 message buffer lock mechanism besides mb inactivation, flexcan has another data coherence mechanism for the receive process. when the cpu reads the control and status word of an rx mb with codes full or overrun, flexcan assumes that the cpu wants to read the whole mb in an atomic operation, and thus it sets an internal lock flag for that mb. the lock is released when the cpu reads the free running timer (global unlock operation), or when it reads the control and status word of another mb regardless of its code, or when the cpu writes into c/s word from locked mb. the mb locking is done to prevent a new frame to be written into the mb while the cpu is reading it. note the locking mechanism only applies to rx mbs that are not part of fifo and have a code different than inactive (0b0000) or empty 1 (0b0100). also, tx mbs can not be locked. suppose, for example, that the fifo is disabled and the second and the fifth mbs of the array are programmed with the same id, and flexcan has already received and stored messages into these two mbs. suppose now that the cpu decides to read mb number 5 and at the same time another message with the same id is arriving. when the cpu reads the control and status word of mb number 5, this mb is locked. the new message arrives and the matching algorithm finds out that there are no "free-to-receive" mbs, so it decides to override mb number 5. however, this mb is locked, so the new message can not be written there. it will remain in the smb waiting for the mb to be unlocked, and only then will be written to the mb. if the mb is not unlocked in time and yet another new message with the same id arrives, then the new message overwrites the one on the smb and there will be no indication of lost messages either in the code field of the mb or in the error and status register. while the message is being moved-in from the smb to the mb, the busy bit on the code field is asserted. if the cpu reads the control and status word and finds out that the busy bit is set, it should defer accessing the mb until the busy bit is negated. note if the busy bit is asserted or if the mb is empty, then reading the control and status word does not lock the mb. 1. in previous flexcan versions, reading the c/s word locked the mb even if it was empty. this behavior is maintained when the irmq bit is negated. chapter 48 can (flexcan) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1371 inactivation takes precedence over locking. if the cpu inactivates a locked rx mb, then its lock status is negated and the mb is marked as invalid for the current matching round. any pending message on the smb will not be transferred anymore to the mb. an mb is unlocked when the cpu reads the free running timer register (see section "free running timer register (timer)"), or the c/s word of another mb. lock and unlock mechanisms have the same functionality in both normal and freeze modes. an unlock during normal or freeze mode results in the move-in of the pending message. however, the move-in is postponed if an unlock occurs during any of the low power modes (see in section "modes of operation" specific information on module disable, doze or stop modes) and it will take place only when the module resumes to normal or freeze modes. 48.4.7 rx fifo the receive-only fifo is enabled by asserting the rfen bit in the mcr. the reset value of this bit is zero to maintain software backward compatibility with previous versions of the module that did not have the fifo feature. the fifo is 6-message deep, therefore when the fifo is enabled, the memory region occupied by the first 6 message buffers is reserved for use of the fifo engine (see rx fifo structure ). the cpu can read the received messages sequentially, in the order they were received, by repeatedly reading a message buffer structure at the output of the fifo. the iflag[buf5i] (frames available in rx fifo) is asserted when there is at least one frame available to be read from the fifo. an interrupt is generated if it is enabled by the corresponding mask bit. upon receiving the interrupt, the cpu can read the message (accessing the output of the fifo as a message buffer) and the rxfir register and then clear the interrupt. if there are more messages in the fifo the act of clearing the interrupt updates the output of the fifo with the next message and update the rxfir with the attributes of that message, reissuing the interrupt to the cpu. otherwise, the flag remains negated. the output of the fifo is only valid whilst the iflag[buf5i] is asserted. the iflag[buf6i] (rx fifo warning) is asserted when the number of unread messages within the rx fifo is increased to 5 from 4 due to the reception of a new one, meaning that the rx fifo is almost full. the flag remains asserted until the cpu clears it. the iflag[buf7i] (rx fifo overflow) is asserted when an incoming message was lost because the rx fifo is full. note that the flag will not be asserted when the rx fifo is full and the message was captured by a mailbox. the flag remains asserted until the cpu clears it. functional description k60 sub-family reference manual, rev. 6, nov 2011 1372 freescale semiconductor, inc. clearing one of those three flags does not affect the state of the other two. an interrupt is generated if an iflag bit is asserted and the corresponding mask bit is asserted too. a powerful filtering scheme is provided to accept only frames intended for the target application, thus reducing the interrupt servicing work load. the filtering criteria is specified by programming a table of up to 128 32-bit registers, according to ctrl2[rffn] setting, that can be configured to one of the following formats (see also rx fifo structure ): ? format a: 128 idafs (extended or standard ids including ide and rtr) ? format b: 256 idafs (standard ids or extended 14-bit id slices including ide and rtr) ? format c: 512 idafs (standard or extended 8-bit id slices) note a chosen format is applied to all entries of the filter table. it is not possible to mix formats within the table. every frame available in the fifo has a corresponding idhit (identifier acceptance filter hit indicator) that can be read by accessing the rxfir register. the rxfir[idhit] field refers to the message at the output of the fifo and is valid while the iflag[buf5i] flag is asserted. the rxfir register must be read only before clearing the flag, which guarantees that the information refers to the correct frame within the fifo. up to thirty two elements of the filter table are individually affected by the individual mask registers (rximrx), according to the setting of ctrl2[rffn], allowing very powerful filtering criteria to be defined. if the irmq bit is negated, then the fifo filter table is affected by rxfgmask. 48.4.8 can protocol related features this section describes the can protocol related features. chapter 48 can (flexcan) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1373 48.4.8.1 remote frames remote frame is a special kind of frame. the user can program a mailbox to be a remote request frame by writing the mailbox as transmit with the rtr bit set to '1'. after the remote request frame is transmitted successfully, the mailbox becomes a receive message buffer, with the same id as before. when a remote request frame is received by flexcan, it can be treated in three ways, depending on remote request storing (ctrl2[rrs]) and rx fifo enable (mcr[rfen]) bits: ? if rrs is negated the frame's id is compared to the ids of the transmit message buffers with the code field 0b1010. if there is a matching id, then this mailbox frame will be transmitted. note that if the matching mailbox has the rtr bit set, then flexcan will transmit a remote frame as a response. the received remote request frame is not stored in a receive buffer. it is only used to trigger a transmission of a frame in response. the mask registers are not used in remote frame matching, and all id bits (except rtr) of the incoming received frame should match. in the case that a remote request frame was received and matched a mailbox, this message buffer immediately enters the internal arbitration process, but is considered as normal tx mailbox, with no higher priority. the data length of this frame is independent of the dlc field in the remote frame that initiated its transmission. ? if rrs is asserted the frame's id is compared to the ids of the receive mailboxes with the code field 0b0100, 0b0010 or 0b0110. if there is a matching id, then this mailbox will store the remote frame in the same fashion of a data frame. no automatic remote response frame will be generated. the mask registers are used in the matching process. ? if rfen is asserted flexcan will not generate an automatic response for remote request frames that match the fifo filtering criteria. if the remote frame matches one of the target ids, it will be stored in the fifo and presented to the cpu. note that for filtering formats a and b, it is possible to select whether remote frames are accepted or not. for format c, remote frames are always accepted (if they match the id). remote request frames are considered as normal frames, and generate a fifo overflow when a successful reception occurs and the fifo is already full. 48.4.8.2 overload frames flexcan does transmit overload frames due to detection of following conditions on can bus: functional description k60 sub-family reference manual, rev. 6, nov 2011 1374 freescale semiconductor, inc. ? detection of a dominant bit in the first/second bit of intermission ? detection of a dominant bit at the 7th bit (last) of end of frame field (rx frames) ? detection of a dominant bit at the 8th bit (last) of error frame delimiter or overload frame delimiter 48.4.8.3 time stamp the value of the free running timer is sampled at the beginning of the identifier field on the can bus, and is stored at the end of "move-in" in the time stamp field, providing network behavior with respect to time. note that the free running timer can be reset upon a specific frame reception, enabling network time synchronization. refer to the tsyn description in the description of the control 1 register (ctrl1). 48.4.8.4 protocol timing the following figure shows the structure of the clock generation circuitry that feeds the can protocol engine (pe) sub-module. the clock source bit clksrc in the ctrl1 register defines whether the internal clock is connected to the output of a crystal oscillator (oscillator clock) or to the peripheral clock (generally from a pll). in order to guarantee reliable operation, the clock source should be selected while the module is in disable mode (bit mdis set in the module configuration register). peripheral clock (pll) oscillator clock (xtal) clk_src prescaler (1 .. 256) pe clock sclock figure 48-104. can engine clocking scheme the crystal oscillator clock should be selected whenever a tight tolerance (up to 0.1%) is required in the can bus timing. the crystal oscillator clock has better jitter performance than pll generated clocks. the flexcan module supports a variety of means to setup bit timing parameters that are required by the can protocol. the control register has various fields used to control bit timing parameters: presdiv, propseg, pseg1, pseg2 and rjw. see the description of the control 1 register (ctrl1). chapter 48 can (flexcan) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1375 the presdiv field controls a prescaler that generates the serial clock (sclock), whose period defines the 'time quantum' used to compose the can waveform. a time quantum is the atomic unit of time handled by the can engine. f tq = f canclk ( prescaler value ) a bit time is subdivided into three segments 2 (reference figure 48-105 and table 48-118 ): ? sync_seg: this segment has a fixed length of one time quantum. signal edges are expected to happen within this section ? time segment 1: this segment includes the propagation segment and the phase segment 1 of the can standard. it can be programmed by setting the propseg and the pseg1 fields of the ctrl1 register so that their sum (plus 2) is in the range of 4 to 16 time quanta ? time segment 2: this segment represents the phase segment 2 of the can standard. it can be programmed by setting the pseg2 field of the ctrl1 register (plus 1) to be 2 to 8 time quanta long bit rate = f tq ( number of time quanta ) s y n c _ s e g = 1 bit time sample point (single or triple sampling) (pseg2 + 1) transmit point time segment 1 1 4 ... 16 nrz signal whenever can bit is used as a measure of duration (e.g. mcr[frzack] and mcr[lpmack]), the number of peripheral clocks in one can bit can be calculated as: nccp = f canclk f sys x [1 + (pseg1 + 1) + (pseg2 + 1) + (propseg + 1)] x (presdiv + 1) where: ? nccp is the number of peripheral clocks in one can bit; ? f canclk is the protocol engine (pe) clock (see figure "can engine clocking scheme"), in hz; ? f sys is the frequency of operation of the system (chi) clock, in hz; ? pseg1 is the value in ctrl1[pseg1] field; ? pseg2 is the value in ctrl1[pseg2] field; ? propseg is the value in ctrl1[propseg] field; ? presdiv is the value in ctrl1[presdiv] field. for example, 180 can bits = 180 x nccp peripheral clock periods. table 48-118. time segment syntax syntax description sync_seg system expects transitions to occur on the bus during this period. transmit point a node in transmit mode transfers a new value to the can bus at this point. sample point a node samples the bus at this point. if the three samples per bit option is selected, then this point marks the position of the third sample. the following table gives an overview of the can compliant segment settings and the related parameter values. table 48-119. can standard compliant bit time segment settings time segment 1 time segment 2 re-synchronization jump width 5 .. 10 2 1 .. 2 4 .. 11 3 1 .. 3 5 .. 12 4 1 .. 4 6 .. 13 5 1 .. 4 7 .. 14 6 1 .. 4 8 .. 15 7 1 .. 4 9 .. 16 8 1 .. 4 chapter 48 can (flexcan) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1377 note it is the user's responsibility to ensure the bit time settings are in compliance with the can standard. for bit time calculations, use an ipt (information processing time) of 2, which is the value implemented in the flexcan module. 48.4.8.5 arbitration and matching timing during normal reception and transmission of frames, the matching, arbitration, move-in and move-out processes are executed during certain time windows inside the can frame, as shown in the following figures. interm start move move-in window eof (7) (bit 2) matching window (26 to 90 bits) data and/or crc (15 to 79) dlc (4) figure 48-106. matching and move-in time windows crc (15) interm start move arbitration window (25 bits) (bit 1) window start arbitration (delayed by tasd) eof (7) move-out process arb figure 48-107. arbitration and move-out time windows busoff 128 ... 126 125 124 123 ... 3 2 1 0 window move-out process arb count tasd ecr[txerrcnt] (transmit error counter) figure 48-108. arbitration at the end of bus off and move-out time windows note the matching and arbitration timing shown in the preceding figures do not take into account the delay caused by the functional description k60 sub-family reference manual, rev. 6, nov 2011 1378 freescale semiconductor, inc. concurrent memory access due to the cpu or other internal peripheral. when doing matching and arbitration, flexcan needs to scan the whole message buffer memory during the available time slot. in order to have sufficient time to do that, the following requirements must be observed: ? a valid can bit timing must be programmed, as indicated in table 48-119 ? the peripheral clock frequency can not be smaller than the oscillator clock frequency, i.e. the pll can not be programmed to divide down the oscillator clock; see clock domains and restrictions ? there must be a minimum ratio between the peripheral clock frequency and the can bit rate, as specified in the following table table 48-120. minimum ratio between peripheral clock frequency and can bit rate number of message buffers rfen minimum number of peripheral clocks per can bit 16 and 32 0 16 64 0 25 16 1 16 32 1 17 64 1 30 a direct consequence of the first requirement is that the minimum number of time quanta per can bit must be 8, so the oscillator clock frequency should be at least 8 times the can bit rate. the minimum frequency ratio specified in the preceding table can be achieved by choosing a high enough peripheral clock frequency when compared to the oscillator clock frequency, or by adjusting one or more of the bit timing parameters (presdiv, propseg, pseg1, pseg2) contained in the control 1 register (ctrl1). in case of synchronous operation (when the peripheral clock frequency is equal to the oscillator clock frequency), the number of peripheral clocks per can bit can be adjusted by selecting an adequate value for presdiv in order to meet the requirement in the preceding table. in case of asynchronous operation (the peripheral clock frequency greater than the oscillator clock frequency), the number of peripheral clocks per can bit can be adjusted by both presdiv and/or the frequency ratio. chapter 48 can (flexcan) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1379 as an example, taking the case of 64 mbs, if the oscillator and peripheral clock frequencies are equal and the can bit timing is programmed to have 8 time quanta per bit, then the prescaler factor (presdiv + 1) should be at least 2. for prescaler factor equal to one and can bit timing with 8 time quanta per bit, the ratio between peripheral and oscillator clock frequencies should be at least 2. 48.4.9 modes of operation details the flexcan module has four functional modes (normal mode, freeze mode, listen- only mode and loop-back mode) and three low power modes (disable mode, doze mode and stop mode). see modes of operation for an introductory description of all these modes of operation. the following sub-sections contain functional details on freeze mode and the low power modes. caution permanent dominant failure on can bus line is not supported by flexcan. if a low power request or freeze mode request is done during a permanent dominant, the corresponding acknowledge can never be asserted. 48.4.9.1 freeze mode this mode is requested by the cpu through the assertion of the halt bit in the mcr register or when the mcu is put into debug mode. in both cases it is also necessary that the frz bit is asserted in the mcr register and the module is not in any of the low power modes (disable, doze, stop). the acknowledgement is obtained through the assertion by the flexcan of frz_ack bit in the same register. the cpu must only consider the flexcan in freeze mode when both request and acknowledgement conditions are satisfied. when freeze mode is requested during transmission or reception, flexcan does the following: ? waits to be in either intermission, passive error, bus off or idle state ? waits for all internal activities like arbitration, matching, move-in and move-out to finish. a pending move-in is not taken into account. ? ignores the rx input pin and drives the tx pin as recessive ? stops the prescaler, thus halting all can protocol activities functional description k60 sub-family reference manual, rev. 6, nov 2011 1380 freescale semiconductor, inc. ? grants write access to the error counters register, which is read-only in other modes ? sets the not_rdy and frz_ack bits in mcr after requesting freeze mode, the user must wait for the frz_ack bit to be asserted in mcr before executing any other action, otherwise flexcan may operate in an unpredictable way. in freeze mode, all memory mapped registers are accessible, except for ctrl1[clk_src] bit that can be read but cannot be written. exiting freeze mode is done in one of the following ways: ? cpu negates the frz bit in the mcr register ? the mcu is removed from debug mode and/or the halt bit is negated the frz_ack bit is negated after the protocol engine recognizes the negation of the freeze request. once out of freeze mode, flexcan tries to re-synchronize to the can bus by waiting for 11 consecutive recessive bits. 48.4.9.2 module disable mode this low power mode is normally used to temporarily disable a complete flexcan block, with no power consumption. it is requested by the cpu through the assertion of the mdis bit in the mcr register and the acknowledgement is obtained through the assertion by the flexcan of the lpm_ack bit in the same register. the cpu must only consider the flexcan in disable mode when both request and acknowledgement conditions are satisfied. if the module is disabled during freeze mode, it requests to disable the clocks to the pe and chi sub-modules, sets the lpm_ack bit and negates the frz_ack bit. if the module is disabled during transmission or reception, flexcan does the following: ? waits to be in either idle or bus off state, or else waits for the third bit of intermission and then checks it to be recessive ? waits for all internal activities like arbitration, matching, move-in and move-out to finish. a pending move-in is not taken into account. ? ignores its rx input pin and drives its tx pin as recessive ? shuts down the clocks to the pe and chi sub-modules ? sets the notrdy and lpmack bits in mcr chapter 48 can (flexcan) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1381 the bus interface unit continues to operate, enabling the cpu to access memory mapped registers, except the rx mailboxes global mask registers, the rx buffer 14 mask register, the rx buffer 15 mask register, the rx fifo global mask register. the rx fifo information register, the message buffers, the rx individual mask registers, and the reserved words within ram may not be accessed when the module is in disable mode. exiting from this mode is done by negating the mdis bit by the cpu, which causes the flexcan to request to resume the clocks and negate the lpm_ack bit after the can protocol engine recognizes the negation of disable mode requested by the cpu. 48.4.9.3 doze mode this is a system low power mode in which the cpu bus is kept alive and a global doze mode request is sent to all peripherals asking them to enter low power mode. when doze mode is globally requested, the doze bit in mcr register needs to have been asserted previously for doze mode to be triggered. the acknowledgement is obtained through the assertion by the flexcan of the lpm_ack bit in the same register. the cpu must only consider the flexcan in doze mode when both request and acknowledgement conditions are satisfied. if doze mode is triggered during freeze mode, flexcan requests to shut down the clocks to the pe and chi sub-modules, sets the lpm_ack bit and negates the frz_ack bit. if doze mode is triggered during transmission or reception, flexcan does the following: ? waits to be in either idle or bus off state, or else waits for the third bit of intermission and checks it to be recessive ? waits for all internal activities like arbitration, matching, move-in and move-out to finish. a pending move-in is not taken into account. ? ignores its rx input pin and drives its tx pin as recessive ? shuts down the clocks to the pe and chi sub-modules ? sets the not_rdy and lpm_ack bits in mcr the bus interface unit continues to operate, enabling the cpu to access memory mapped registers, except the rx mailboxes global mask registers, the rx buffer 14 mask register, the rx buffer 15 mask register, the rx fifo global mask register. the rx fifo information register, the message buffers, the rx individual mask registers, and the reserved words within ram may not be accessed when the module is in doze mode. exiting doze mode is done in one of the following ways: functional description k60 sub-family reference manual, rev. 6, nov 2011 1382 freescale semiconductor, inc. ? cpu removing the doze mode request ? cpu negating the doze bit of the mcr register ? self wake mechanism in the self wake mechanism, if the slf_wak bit in mcr register was set at the time flexcan entered doze mode, then upon detection of a recessive to dominant transition on the can bus, flexcan negates the doze bit, requests to resume its clocks and negates the lpm_ack after the can protocol engine recognizes the negation of the doze mode request. it also sets the wak_int bit in the esr register and, if enabled by the wak_msk bit in mcr, generates a wake up interrupt to the cpu. flexcan will then wait for 11 consecutive recessive bits to synchronize to the can bus. as a consequence, it will not receive the frame that woke it up. the following table details the effect of slf_wak and wak_msk upon wake-up from doze mode. table 48-121. wake-up from doze mode slf_wak wak_int wak_msk flexcan clocks enabled wake-up interrupt generated 0 - - no no 0 - - no no 1 0 0 no no 1 0 1 no no 1 1 0 yes no 1 1 1 yes yes 48.4.9.4 stop mode this is a system low power mode in which all mcu clocks can be stopped for maximum power savings. the stop mode is globally requested by the cpu and the acknowledgement is obtained through the assertion by the flexcan of a stop acknowledgement signal. the cpu must only consider the flexcan in stop mode when both request and acknowledgement conditions are satisfied. if flexcan receives the global stop mode request during freeze mode, it sets the lpm_ack bit, negates the frz_ack bit and then sends the stop acknowledge signal to the cpu, in order to shut down the clocks globally. if stop mode is requested during transmission or reception, flexcan does the following: ? waits to be in either idle or bus off state, or else waits for the third bit of intermission and checks it to be recessive chapter 48 can (flexcan) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1383 ? waits for all internal activities like arbitration, matching, move-in and move-out to finish. a pending move-in is not taken into account. ? ignores its rx input pin and drives its tx pin as recessive ? sets the not_rdy and lpm_ack bits in mcr ? sends a stop acknowledge signal to the cpu, so that it can shut down the clocks globally exiting stop mode is done in one of the following ways: ? cpu resuming the clocks and removing the stop mode request ? cpu resuming the clocks and stop mode request as a result of the self wake mechanism in the self wake mechanism, if the slf_wak bit in mcr register was set at the time flexcan entered stop mode, then upon detection of a recessive to dominant transition on the can bus, flexcan sets the wak_int bit in the esr register and, if enabled by the wak_msk bit in mcr, generates a wake up interrupt to the cpu. upon receiving the interrupt, the cpu should resume the clocks and remove the stop mode request. flexcan will then wait for 11 consecutive recessive bits to synchronize to the can bus. as a consequence, it will not receive the frame that woke it up. the following table details the effect of slf_wak and wak_msk upon wake-up from stop mode. note that wake-up from stop mode only works when both bits are asserted. after the can protocol engine recognizes the negation of the stop mode request, the flexcan negates the lpm_ack bit. table 48-122. wake-up from stop mode slf_wak wak_int wak_msk mcu clocks enabled wake-up interrupt generated 0 - - no no 0 - - no no 1 0 0 no no 1 0 1 no no 1 1 0 no no 1 1 1 yes yes functional description k60 sub-family reference manual, rev. 6, nov 2011 1384 freescale semiconductor, inc. 48.4.10 interrupts each one of the message buffers can be an interrupt source, if its corresponding imask bit is set. there is no distinction between tx and rx interrupts for a particular buffer, under the assumption that the buffer is initialized for either transmission or reception. each of the buffers has assigned a flag bit in the iflag registers. the bit is set when the corresponding buffer completes a successful transmission/reception and is cleared when the cpu writes it to '1' (unless another interrupt is generated at the same time). note it must be guaranteed that the cpu only clears the bit causing the current interrupt. for this reason, bit manipulation instructions (bset) must not be used to clear interrupt flags. these instructions may cause accidental clearing of interrupt flags which are set after entering the current interrupt service routine. if the rx fifo is enabled (bit rfen on mcr set), the interrupts corresponding to mbs 0 to 7 have a different behavior. bit 7 of the iflag1 becomes the "fifo overflow" flag; bit 6 becomes the fifo warning flag, bit 5 becomes the "frames available in fifo flag" and bits 4-0 are unused. see the description of the interrupt flags 1 register (iflag1) for more information. a combined interrupt for all mbs is generated by an or of all the interrupt sources from mbs. this interrupt gets generated when any of the mbs or fifo generates an interrupt. in this case the cpu must read the iflag registers to determine which mb or fifo caused the interrupt. the other interrupt sources (bus off, error, tx warning, rx warning, and wake up) generate interrupts like the mb ones, and can be read from both the error and status register 1 and 2. the bus off, error, tx warning and rx warning interrupt mask bits are located in the control 1 register; the wake-up interrupt mask bit is located in the mcr. 48.4.11 bus interface the cpu access to flexcan registers are subject to the following rules: ? unrestricted read and write access to supervisor registers (registers identified with s/ u in table "module memory map" in supervisor mode or with s only) results in access error. ? read and write access to implemented reserved address space results in access error. chapter 48 can (flexcan) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1385 ? write access to positions whose bits are all currently read-only results in access error. if at least one of the bits is not read-only then no access error is issued. write permission to positions or some of their bits can change depending on the mode of operation or transitory state. refer to register and bit descriptions for details. ? read and write access to unimplemented address space results in access error. ? read and write access to ram located positions during low power mode results in access error. ? if maxmb is programmed with a value smaller than the available number of mbs, then the unused memory space can be used as general purpose ram space. note that reserved words within ram cannot be used. as an example, suppose flexcan is configured with 16 mbs, rffn is 0x0, and maxmb is programmed with zero. the maximum number of mbs in this case becomes one. the ram starts at 0x0080, and the space from 0x0080 to 0x008f is used by the one mb. the memory space from 0x0090 to 0x017f is available. the space between 0x0180 and 0x087f is reserved. the space from 0x0880 to 0x0883 is used by the one individual mask and the available memory in the mask registers space would be from 0x0884 to 0x08bf. from 0x08c0 through 0x09df there are reserved words for internal use which cannot be used as general purpose ram. as a general rule, free memory space for general purpose depends only on maxmb. note unused mb space must not be used as general purpose ram while flexcan is transmitting and receiving can frames. 48.5 initialization/application information this section provide instructions for initializing the flexcan module. 48.5.1 flexcan initialization sequence the flexcan module may be reset in three ways: ? mcu level hard reset, which resets all memory mapped registers asynchronously ? mcu level soft reset, which resets some of the memory mapped registers synchronously (refer to table 48-2 to see what registers are affected by soft reset) ? soft_rst bit in mcr, which has the same effect as the mcu level soft reset initialization/application information k60 sub-family reference manual, rev. 6, nov 2011 1386 freescale semiconductor, inc. soft reset is synchronous and has to follow an internal request/acknowledge procedure across clock domains. therefore, it may take some time to fully propagate its effects. the soft_rst bit remains asserted while soft reset is pending, so software can poll this bit to know when the reset has completed. also, soft reset can not be applied while clocks are shut down in any of the low power modes. the low power mode should be exited and the clocks resumed before applying soft reset. the clock source (clk_src bit) should be selected while the module is in disable mode. after the clock source is selected and the module is enabled (mdis bit negated), flexcan automatically goes to freeze mode. in freeze mode, flexcan is un- synchronized to the can bus, the halt and frz bits in mcr register are set, the internal state machines are disabled and the frz_ack and not_rdy bits in the mcr register are set. the tx pin is in recessive state and flexcan does not initiate any transmission or reception of can frames. note that the message buffers and the rx individual mask registers are not affected by reset, so they are not automatically initialized. for any configuration change/initialization it is required that flexcan is put into freeze mode (see freeze mode ). the following is a generic initialization sequence applicable to the flexcan module: ? initialize the module configuration register ? enable the individual filtering per mb and reception queue features by setting the irmq bit ? enable the warning interrupts by setting the wrn_en bit ? if required, disable frame self reception by setting the srx_dis bit ? enable the rx fifo by setting the rfen bit ? enable the abort mechanism by setting the aen bit ? enable the local priority feature by setting the lprio_en bit ? initialize the control register ? determine the bit timing parameters: propseg, pseg1, pseg2, rjw ? determine the bit rate by programming the presdiv field ? determine the internal arbitration mode (lbuf bit) ? initialize the message buffers ? the control and status word of all message buffers must be initialized chapter 48 can (flexcan) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1387 ? if rx fifo was enabled, the id filter table must be initialized ? other entries in each message buffer should be initialized as required ? initialize the rx individual mask registers ? set required interrupt mask bits in the imask registers (for all mb interrupts), in ctrl register (for bus off and error interrupts) and in mcr register for wake-up interrupt ? negate the halt bit in mcr starting with the last event, flexcan attempts to synchronize to the can bus. initialization/application information k60 sub-family reference manual, rev. 6, nov 2011 1388 freescale semiconductor, inc. chapter 49 spi (dspi) 49.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the serial peripheral interface module provides a synchronous serial bus for communication between an mcu and an external peripheral device. 49.1.1 block diagram the block diagram of this module is as follows: k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1389 baud rate, delay & transfer control shift register spi sck s pi 32 data data tx fifo slave bus interface clock/reset popr edma intc dma and interrupt control pushr rx fifo cmd 32 8 pcs[x]/ss/pcss sin sout figure 49-1. dspi block diagram 49.1.2 features the dspi supports these spi features: ? full-duplex, four-wire synchronous transfers ? master and slave modes ? data streaming operation in slave mode with continuous slave selection ? buffered transmit operation using the tx fifo with depth of 4 entries ? buffered receive operation using the rx fifo with depth of 4 entries ? tx and rx fifos can be disabled individually for low-latency updates to spi queues ? visibility into tx and rx fifos for ease of debugging ? programmable transfer attributes on a per-frame basis: introduction k60 sub-family reference manual, rev. 6, nov 2011 1390 freescale semiconductor, inc. ? 2 transfer attribute registers ? serial clock with programmable polarity and phase ? various programmable delays ? programmable serial frame size of 4 to 16 bits, expandable by software control ? spi frames longer than 16 bits can be supported using the continuous selection format. ? continuously held chip select capability ? 6 peripheral chip selects, expandable to 64 with external demultiplexer ? deglitching support for up to 32 peripheral chip select with external demultiplexer ? dma support for adding entries to tx fifo and removing entries from rx fifo: ? tx fifo is not full (tfff) ? rx fifo is not empty (rfdf) ? interrupt conditions: ? end of queue reached (eoqf) ? tx fifo is not full (tfff) ? transfer of current frame complete (tcf) ? attempt to transmit with an empty transmit fifo (tfuf) ? rx fifo is not empty (rfdf) ? frame received while receive fifo is full (rfof) ? global interrupt request line ? modified spi transfer formats for communication with slower peripheral devices ? power-saving architectural features ? support for stop mode ? support for doze mode 49.1.3 dspi configurations the dspi module always operates in spi configuration. chapter 49 spi (dspi) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1391 49.1.3.1 spi configuration the spi configuration allows the dspi to send and receive serial data. this configuration allows the dspi to operate as a basic spi block with internal fifos supporting external queues operation. transmit data and received data reside in separate fifos. the host cpu or a dma controller read the received data from the receive fifo and write transmit data to the transmit fifo. for queued operations the spi queues can reside in system ram, external to the dspi. data transfers between the queues and the dspi fifos are accomplished by a dma controller or host cpu. the following figure shows a system example with dma, dspi and external queues in system ram. system ram dspi dma controller tx queue rx fifo tx fifo shift register addr/ctrl rx queue addr/ctrl req data data done data data figure 49-2. dspi with queues and dma 49.1.4 modes of operation the dspi supports the following modes of operation that can be divided into two categories; ? module-specific modes: ? master mode ? slave mode ? module disable mode ? mcu-specific modes: introduction k60 sub-family reference manual, rev. 6, nov 2011 1392 freescale semiconductor, inc. ? external stop mode ? debug mode the dspi enters module-specific modes when the host writes a dspi register. the mcu- specific modes are controlled by signals, external to the dspi. the mcu-specific modes are modes that an mcu may enter in parallel to the dspi block-specific modes. 49.1.4.1 master mode master mode allows the dspi to initiate and control serial communication. in this mode, the sck signal and the pcs[ x ] signals are controlled by the dspi and configured as outputs. 49.1.4.2 slave mode slave mode allows the dspi to communicate with spi bus masters. in this mode, the dspi responds to externally controlled serial transfers. the sck signal and the pcs[0]/ ss signals are configured as inputs and driven by a spi bus master. 49.1.4.3 module disable mode the module disable mode can be used for mcu power management. the clock to the non-memory mapped logic in the dspi can be stopped while in the module disable mode. 49.1.4.4 external stop mode external stop mode is used for mcu power management. the dspi supports the peripheral bus stop mode mechanism. when a request is made to enter external stop mode, the dspi block acknowledges the request and completes the transfer in progress. when the dspi reaches the frame boundary it signals that the system clock to the dspi module may be shut off. chapter 49 spi (dspi) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1393 49.1.4.5 debug mode debug mode is used for system development and debugging. the mcr[frz] bit controls dspi behavior in the debug mode. if the bit is set, the dspi stops all serial transfers, when the mcu is in debug mode. if the bit is cleared, the mcu debug mode has no effect on the dspi. 49.2 dspi signal descriptions this section provides the dspi signals description. the following table lists the signals that may connect off chip depending on device implementation. table 49-1. dspi signal descriptions signal description i/o pcs0/ ss master mode: peripheral chip select 0 output slave mode: slave select input i/o pcs[3:1] master mode: peripheral chip select 1 - 3 slave mode: unused o pcs4 master mode: peripheral chip select 4 slave mode: unused o pcs5/ pcss master mode: peripheral chip select 5 / peripheral chip select strobe slave mode: unused o sin serial data in i sout serial data out o sck master mode: serial clock (output) slave mode: serial clock (input) i/o 49.2.1 pcs0/ ss peripheral chip select/slave select in master mode, the pcs0 signal is a peripheral chip select output that selects which slave device the current transmission is intended for. in slave mode, the active low ss signal is a slave select input signal that allows a spi master to select the dspi as the target for transmission. dspi signal descriptions k60 sub-family reference manual, rev. 6, nov 2011 1394 freescale semiconductor, inc. 49.2.2 pcs1 - pcs3 ? peripheral chip selects 1 - 3 pcs1 - pcs3 are peripheral chip select output signals in master mode. in slave mode, these signals are unused. 49.2.3 pcs4 peripheral chip select 4 in master mode, pcs4 is a peripheral chip select output signal. in slave mode, this signal is unused. 49.2.4 pcs5/ pcss peripheral chip select 5/peripheral chip select strobe pcs5 is a peripheral chip select output signal. when the dspi is in master mode and the mcr[pcsse] bit is cleared, this signal selects which slave device the current transfer is intended for. when the dspi is in master mode and the mcr[pcsse] bit is set, the pcss signal acts as a strobe to an external peripheral chip select demultiplexer, which decodes the pcs0 - pcs4 signals, preventing glitches on the demultiplexer outputs. this signal is not used in slave mode. 49.2.5 sin serial input sin is a serial data input signal. 49.2.6 sout serial output sout is a serial data output signal. 49.2.7 sck serial clock sck is a serial communication clock signal. in master mode, the dspi generates the sck. in slave mode, sck is an input from an external bus master. chapter 49 spi (dspi) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1395 49.3 memory map/register definition register accesses to memory addresses that are reserved or undefined result in a transfer error. write access to the popr register also results in a transfer error. spi memory map absolute address (hex) register name width (in bits) access reset value section/ page 4002_c000 dspi module configuration register (spi0_mcr) 32 r/w 0000_4001h 49.3.1/ 1399 4002_c008 dspi transfer count register (spi0_tcr) 32 r/w 0000_0000h 49.3.2/ 1402 4002_c00c dspi clock and transfer attributes register (in master mode) (spi0_ctar0) 32 r/w 7800_0000h 49.3.3/ 1402 4002_c00c dspi clock and transfer attributes register (in slave mode) (spi0_ctar0_slave) 32 r/w 7800_0000h 49.3.4/ 1407 4002_c010 dspi clock and transfer attributes register (in master mode) (spi0_ctar1) 32 r/w 7800_0000h 49.3.3/ 1402 4002_c02c dspi status register (spi0_sr) 32 r/w see section 49.3.5/ 1408 4002_c030 dspi dma/interrupt request select and enable register (spi0_rser) 32 r/w 0000_0000h 49.3.6/ 1411 4002_c034 dspi push tx fifo register in master mode (spi0_pushr) 32 r/w 0000_0000h 49.3.7/ 1413 4002_c034 dspi push tx fifo register in slave mode (spi0_pushr_slave) 32 r/w 0000_0000h 49.3.8/ 1415 4002_c038 dspi pop rx fifo register (spi0_popr) 32 r 0000_0000h 49.3.9/ 1415 4002_c03c dspi transmit fifo registers (spi0_txfr0) 32 r 0000_0000h 49.3.10/ 1416 4002_c040 dspi transmit fifo registers (spi0_txfr1) 32 r 0000_0000h 49.3.10/ 1416 4002_c044 dspi transmit fifo registers (spi0_txfr2) 32 r 0000_0000h 49.3.10/ 1416 4002_c048 dspi transmit fifo registers (spi0_txfr3) 32 r 0000_0000h 49.3.10/ 1416 4002_c07c dspi receive fifo registers (spi0_rxfr0) 32 r 0000_0000h 49.3.11/ 1416 4002_c080 dspi receive fifo registers (spi0_rxfr1) 32 r 0000_0000h 49.3.11/ 1416 table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 16 freescale semiconductor, inc. spi memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4002_c084 dspi receive fifo registers (spi0_rxfr2) 32 r 0000_0000h 49.3.11/ 1416 4002_c088 dspi receive fifo registers (spi0_rxfr3) 32 r 0000_0000h 49.3.11/ 1416 4002_d000 dspi module configuration register (spi1_mcr) 32 r/w 0000_4001h 49.3.1/ 1399 4002_d008 dspi transfer count register (spi1_tcr) 32 r/w 0000_0000h 49.3.2/ 1402 4002_d00c dspi clock and transfer attributes register (in master mode) (spi1_ctar0) 32 r/w 7800_0000h 49.3.3/ 1402 4002_d00c dspi clock and transfer attributes register (in slave mode) (spi1_ctar0_slave) 32 r/w 7800_0000h 49.3.4/ 1407 4002_d010 dspi clock and transfer attributes register (in master mode) (spi1_ctar1) 32 r/w 7800_0000h 49.3.3/ 1402 4002_d02c dspi status register (spi1_sr) 32 r/w see section 49.3.5/ 1408 4002_d030 dspi dma/interrupt request select and enable register (spi1_rser) 32 r/w 0000_0000h 49.3.6/ 1411 4002_d034 dspi push tx fifo register in master mode (spi1_pushr) 32 r/w 0000_0000h 49.3.7/ 1413 4002_d034 dspi push tx fifo register in slave mode (spi1_pushr_slave) 32 r/w 0000_0000h 49.3.8/ 1415 4002_d038 dspi pop rx fifo register (spi1_popr) 32 r 0000_0000h 49.3.9/ 1415 4002_d03c dspi transmit fifo registers (spi1_txfr0) 32 r 0000_0000h 49.3.10/ 1416 4002_d040 dspi transmit fifo registers (spi1_txfr1) 32 r 0000_0000h 49.3.10/ 1416 4002_d044 dspi transmit fifo registers (spi1_txfr2) 32 r 0000_0000h 49.3.10/ 1416 4002_d048 dspi transmit fifo registers (spi1_txfr3) 32 r 0000_0000h 49.3.10/ 1416 4002_d07c dspi receive fifo registers (spi1_rxfr0) 32 r 0000_0000h 49.3.11/ 1416 4002_d080 dspi receive fifo registers (spi1_rxfr1) 32 r 0000_0000h 49.3.11/ 1416 4002_d084 dspi receive fifo registers (spi1_rxfr2) 32 r 0000_0000h 49.3.11/ 1416 4002_d088 dspi receive fifo registers (spi1_rxfr3) 32 r 0000_0000h 49.3.11/ 1416 chapter 49 spi (dspi) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1397 spi memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 400a_c000 dspi module configuration register (spi2_mcr) 32 r/w 0000_4001h 49.3.1/ 1399 400a_c008 dspi transfer count register (spi2_tcr) 32 r/w 0000_0000h 49.3.2/ 1402 400a_c00c dspi clock and transfer attributes register (in master mode) (spi2_ctar0) 32 r/w 7800_0000h 49.3.3/ 1402 400a_c00c dspi clock and transfer attributes register (in slave mode) (spi2_ctar0_slave) 32 r/w 7800_0000h 49.3.4/ 1407 400a_c010 dspi clock and transfer attributes register (in master mode) (spi2_ctar1) 32 r/w 7800_0000h 49.3.3/ 1402 400a_c02c dspi status register (spi2_sr) 32 r/w see section 49.3.5/ 1408 400a_c030 dspi dma/interrupt request select and enable register (spi2_rser) 32 r/w 0000_0000h 49.3.6/ 1411 400a_c034 dspi push tx fifo register in master mode (spi2_pushr) 32 r/w 0000_0000h 49.3.7/ 1413 400a_c034 dspi push tx fifo register in slave mode (spi2_pushr_slave) 32 r/w 0000_0000h 49.3.8/ 1415 400a_c038 dspi pop rx fifo register (spi2_popr) 32 r 0000_0000h 49.3.9/ 1415 400a_c03c dspi transmit fifo registers (spi2_txfr0) 32 r 0000_0000h 49.3.10/ 1416 400a_c040 dspi transmit fifo registers (spi2_txfr1) 32 r 0000_0000h 49.3.10/ 1416 400a_c044 dspi transmit fifo registers (spi2_txfr2) 32 r 0000_0000h 49.3.10/ 1416 400a_c048 dspi transmit fifo registers (spi2_txfr3) 32 r 0000_0000h 49.3.10/ 1416 400a_c07c dspi receive fifo registers (spi2_rxfr0) 32 r 0000_0000h 49.3.11/ 1416 400a_c080 dspi receive fifo registers (spi2_rxfr1) 32 r 0000_0000h 49.3.11/ 1416 400a_c084 dspi receive fifo registers (spi2_rxfr2) 32 r 0000_0000h 49.3.11/ 1416 400a_c088 dspi receive fifo registers (spi2_rxfr3) 32 r 0000_0000h 49.3.11/ 1416 memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1398 freescale semiconductor, inc. 49.3.1 dspi module configuration register (spi x r contains bits to configure various attributes associated with dspi operations. the halt and mdis bits can be changed at any time, but they only take effect on the next frame boundary. only the halt and mdis bits in the mcr can be changed, while the dspi is in the running state. addresses: spi0_mcr is 4002_c000h base + 0h offset = 4002_c000h spi1_mcr is 4002_d000h base + 0h offset = 4002_d000h spi2_mcr is 400a_c000h base + 0h offset = 400a_c000h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r mstr cont_scke dconf frz mtfe pcsse rooe 0 pcsis[5:0] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r doze mdis dis_txf dis_rxf 0 0 smpl_pt 0 0 halt w clr_ txf clr_ rxf reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 spi x r iel escritions fiel escrition r asterlae oe elect oniures the or either aster oe or slae oe is in slae oe is in aster oe o ontinuous nale nales the erial ounication loc to run continuously ontinuous isale ontinuous enale of oniuration elects aon the ierent coniurations o the resere resere resere table continues on the next page... chapter 4 spi dspi 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1 spi x r iel escritions continue fiel escrition fr freee nales the transers to e stoe on the next rae ounary when the eice enters eu oe o not halt serial transers in eu oe halt serial transers in eu oe f oiie iin forat nale nales a oiie transer orat to e use oiie transer orat isale oiie transer orat enale eriheral hi elect troe nale nales the to oerate as a troe outut sinal is use as the eriheral hi elect sinal is use as an actielow troe sinal roo receie ffo oerlow oerwrite nale n the r ffo oerlow conition coniures the to inore the incoin serial ata or oerwrite existin ata the r ffo is ull an new ata is receie the ata ro the transer eneratin the oerlow is inore or shite into the shit reister ncoin ata is inore ncoin ata is shite into the shit reister resere his reaonly iel is resere an always has the alue ero : eriheral hi elect x nactie tate eterines the inactie state o x he inactie state o x is low he inactie state o x is hih o oe nale roies suort or an externally controlle oe oe owersain echanis oe oe has no eect on oe oe isales oule isale llows the cloc to e stoe to the noneory ae loic in the eectiely uttin the in a sotware controlle owersain state he reset alue o the it is araeterie with a eault reset alue o nale clocs llow external loic to isale clocs table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 1400 freescale semiconductor, inc. spi x r iel escritions continue fiel escrition f isale ransit ffo hen the ffo is isale the transit art o the oerates as a siliie ouleuere his it can only e written when the it is cleare x ffo is enale x ffo is isale rf isale receie ffo hen the r ffo is isale the receie art o the oerates as a siliie ouleuere his it can only e written when the it is cleare rx ffo is enale rx ffo is isale lrf lear ffo flushes the ffo ritin a to lrf clears the ffo ounter he lrf it is always rea as ero o not clear the x ffo counter lear the x ffo counter lrrf flushes the r ffo ritin a to lrrf clears the r ounter he lrrf it is always rea as ero o not clear the rx ffo counter lear the rx ffo counter l ale oint ontrols when the aster sales in oiie ranser forat his iel is ali only when h it in r reister is syste clocs etween ee an sale syste cloc etween ee an sale syste clocs etween ee an sale resere resere his reaonly iel is resere an always has the alue ero resere his reaonly iel is resere an always has the alue ero hl halt tarts an stos transers tart transers to transers hater ufaily reerence anual re o freescale eiconuctor nc 49.3.2 dspi transfer count register (spi x r tcr contains a counter that indicates the number of spi transfers made. the transfer counter is intended to assist in queue management. do not write the tcr when the dspi is in the running state. addresses: spi0_tcr is 4002_c000h base + 8h offset = 4002_c008h spi1_tcr is 4002_d000h base + 8h offset = 4002_d008h spi2_tcr is 400a_c000h base + 8h offset = 400a_c008h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r spi_tcnt 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 spi x r iel escritions fiel escrition ranser ounter ounts the nuer o transers the aes he iel increents eery tie the last it o a rae is transitte alue written to resets the counter to that alue is reset to ero at the einnin o the rae when the iel is set in the executin coan he ranser ounter wras aroun increentin the counter ast resets the counter to ero resere his reaonly iel is resere an always has the alue ero loc an ranser ttriutes reister n aster oe x r n ctar registers are used to define different transfer attributes. the number of ctar registers is parameterized in the rtl and can be from two to eight registers. do not write to the ctar registers while the dspi is in the running state. in master mode, the ctar registers define combinations of transfer attributes such as frame size, clock phase and polarity, data bit ordering, baud rate, and various delays. in slave mode, a subset of the bitfields in ctar0 are used to set the slave transfer attributes. when the dspi is configured as an spi master, the ctas field in the command portion of the tx fifo entry selects which of the ctar register is used. when the dspi is configured as an spi bus slave, the ctar0 register is used. memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1402 freescale semiconductor, inc. addresses: spi0_ctar0 is 4002_c000h base + ch offset = 4002_c00ch spi0_ctar1 is 4002_c000h base + 10h offset = 4002_c010h spi1_ctar0 is 4002_d000h base + ch offset = 4002_d00ch spi1_ctar1 is 4002_d000h base + 10h offset = 4002_d010h spi2_ctar0 is 400a_c000h base + ch offset = 400a_c00ch spi2_ctar1 is 400a_c000h base + 10h offset = 400a_c010h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r dbr fmsz cpol cpha lsbfe pcssck pasc pdt pbr w reset 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r cssck asc dt br w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 spi x r n iel escritions fiel escrition r oule au rate oules the eectie au rate o the erial ounications loc his iel is use only in aster oe t eectiely hales the au rate iision ratio suortin aster requencies an o iision ratios or the erial ounications loc hen the r it is set the uty cycle o the erial ounications loc eens on the alue in the au rate rescaler an the loc hase it as liste in the ollowin tale ee the r iel escrition or etails on how to coute the au rate ale uty ycle r h r uty ycle any any he au rate is coute norally with a uty cycle he au rate is oule with the uty cycle eenin on the au rate rescaler table continues on the next page... chapter 4 spi dspi 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 140 spi x r n iel escritions continue fiel escrition f frae ie he nuer o its transerre er rae is equal to the f iel alue lus he iniu ali f iel alue is ol loc olarity elects the inactie state o the erial ounications loc his it is use in oth aster an slae oe for successul counication etween serial eices the eices ust hae ientical cloc olarities hen the ontinuous election forat is selecte switchin etween cloc olarities without stoin the can cause errors in the transer ue to the eriheral eice interretin the switch o cloc olarity as a ali cloc ee he inactie state alue o is low he inactie state alue o is hih h loc hase elects which ee o causes ata to chane an which ee causes ata to e cature his it is use in oth aster an slae oe for successul counication etween serial eices the eices ust hae ientical cloc hase settins n ontinuous oe the it alue is inore an the transers are one as i the h it is set to ata is cature on the leain ee o an chane on the ollowin ee ata is chane on the leain ee o an cature on the ollowin ee lf l first eciies whether the l or o the rae is transerre irst ata is transerre irst ata is transerre l irst to elay rescaler elects the rescaler alue or the elay etween assertion o an the irst ee o the ee the iel escrition or inoration on how to coute the to elay reer to elay t or ore etails to rescaler alue is to rescaler alue is to rescaler alue is to rescaler alue is ter elay rescaler elects the rescaler alue or the elay etween the last ee o an the neation o ee the iel escrition or inoration on how to coute the ter elayreer ter elay t or ore etails elay ater ranser rescaler alue is elay ater ranser rescaler alue is elay ater ranser rescaler alue is elay ater ranser rescaler alue is elay ater ranser rescaler table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 1404 freescale semiconductor, inc. spi x r n iel escritions continue fiel escrition elects the rescaler alue or the elay etween the neation o the sinal at the en o a rae an the assertion o at the einnin o the next rae he iel is only use in aster oe ee the iel escrition or etails on how to coute the elay ater ranser reer elay ater ranser t or ore etails elay ater ranser rescaler alue is elay ater ranser rescaler alue is elay ater ranser rescaler alue is elay ater ranser rescaler alue is r au rate rescaler elects the rescaler alue or the au rate his iel is use only in aster oe he au rate is the requency o the he syste cloc is iie y the rescaler alue eore the au rate selection taes lace ee the r iel escrition or etails on how to coute the au rate au rate rescaler alue is au rate rescaler alue is au rate rescaler alue is au rate rescaler alue is to elay caler elects the scaler alue or the to elay his iel is use only in aster oe he to elay is the elay etween the assertion o an the irst ee o the he elay is a ultile o the syste cloc erio an it is coute accorin to the ollowin equation: t x x he ollowin tale lists the elay scaler alues ale elay caler ncoin fiel alue elay caler alue table continues on the next page... chapter 4 spi dspi 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 140 spi x r n iel escritions continue fiel escrition ale elay caler ncoin continue fiel alue elay caler alue reer to elay t or ore etails ter elay caler elects the scaler alue or the ter elay his iel is use only in aster oe he ter elay is the elay etween the last ee o an the neation o he elay is a ultile o the syste cloc erio an it is coute accorin to the ollowin equation: t x x ee elay caler ncoin tale in rn it iel escrition or scaler alues reer ter elay t or ore etails elay ter ranser caler elects the elay ater ranser caler his iel is use only in aster oe he elay ater ranser is the tie etween the neation o the sinal at the en o a rae an the assertion o at the einnin o the next rae n the ontinuous erial ounications loc oeration the alue is ixe to one cloc erio he elay ater ranser is a ultile o the syste cloc erio an it is coute accorin to the ollowin equation: t x x ee elay caler ncoin tale in rn it iel escrition or scaler alues r au rate caler elects the scaler alue or the au rate his iel is use only in aster oe he rescale syste cloc is iie y the au rate caler to enerate the requency o the he au rate is coute accorin to the ollowin equation: au rate r x rr he ollowin tale lists the au rate scaler alues ale au rate caler rnr au rate caler alue table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 1406 freescale semiconductor, inc. spi x r n iel escritions continue fiel escrition ale au rate caler continue rnr au rate caler alue loc an ranser ttriutes reister n lae oe x rl when the dspi is configured as an spi bus slave, the ctar0 register is used. addresses: spi0_ctar0_slave is 4002_c000h base + ch offset = 4002_c00ch spi1_ctar0_slave is 4002_d000h base + ch offset = 4002_d00ch spi2_ctar0_slave is 400a_c000h base + ch offset = 400a_c00ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r fmsz cpol cpha 0 0 w reset 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 spi x r n l iel escritions fiel escrition f frae ie he nuer o its transerre er rae is equal to the f iel alue lus he iniu ali f iel alue is ol loc olarity elects the inactie state o the erial ounications loc he inactie state alue o is low he inactie state alue o is hih h loc hase table continues on the next page... chapter 4 spi dspi 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1407 spi x r n l iel escritions continue fiel escrition elects which ee o causes ata to chane an which ee causes ata to e cature his it is use in oth aster an slae oe for successul counication etween serial eices the eices ust hae ientical cloc hase settins n ontinuous oe the it alue is inore an the transers are one as the h it is set to ata is cature on the leain ee o an chane on the ollowin ee ata is chane on the leain ee o an cature on the ollowin ee resere his reaonly iel is resere an always has the alue ero resere his reaonly iel is resere an always has the alue ero tatus reister x r sr contains status and flag bits. the bits reflect the status of the dspi and indicate the occurrence of events that can generate interrupt or dma requests. software can clear flag bits in the sr by writing a 1 to them. writing a 0 to a flag bit has no effect. this register may not be writable in module disable mode due to the use of power saving mechanisms. addresses: spi0_sr is 4002_c000h base + 2ch offset = 4002_c02ch spi1_sr is 4002_d000h base + 2ch offset = 4002_d02ch spi2_sr is 400a_c000h base + 2ch offset = 400a_c02ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r tcf txrxs 0 eoqf tfuf 0 tfff 0 0 0 0 0 rfof 0 rfdf 0 w w1c w1c w1c w1c w1c w1c w1c reset 0 0 0 0 0 0 * 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r txctr txnxtptr rxctr popnxtptr w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * notes: tfff bitfield: depends on mcr[mdis] bit. see bit description for more details. memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1408 freescale semiconductor, inc. spi x r iel escritions fiel escrition f ranser olete fla nicates that all its in a rae hae een shite out f reains set until it is cleare y writin a to it ranser not colete ranser colete r an r tatus relects the run status o the ransit an receie oerations are isale is in stoe state ransit an receie oerations are enale is in runnin state resere his reaonly iel is resere an always has the alue ero of n o ueue fla nicates that the last entry in a queue has een transitte when the is in aster oe he of it is set when the ffo entry has the o it set in the coan halwor an the en o the transer is reache he of it reains set until cleare y writin a to it hen the of it is set the r it is autoatically cleare o is not set in the executin coan o is set in the executin coan fuf ransit ffo unerlow fla nicates an unerlow conition in the ffo he transit unerlow conition is etecte only or locs oeratin in slae oe an coniuration fuf is set when the ffo o a oeratin in slae oe is ety an an external aster initiates a transer he fuf it reains set until cleare y writin to it o x ffo unerlow x ffo unerlow has occurre resere his reaonly iel is resere an always has the alue ero fff ransit ffo fill fla roies a etho or the to request ore entries to e ae to the ffo he fff it is set while the ffo is not ull he fff it can e cleare y writin to it or y acnowleeent ro the controller to the ffo ull request he reset alue o this it is i r he reset alue o this it is i r x ffo is ull x ffo is not ull resere his reaonly iel is resere an always has the alue ero resere his reaonly iel is resere an always has the alue ero resere his reaonly iel is resere an always has the alue ero table continues on the next page... chapter 4 spi dspi 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 140 spi x r iel escritions continue fiel escrition resere his reaonly iel is resere an always has the alue ero resere his reaonly iel is resere an always has the alue ero rfof receie ffo oerlow fla nicates an oerlow conition in the r ffo he it is set when the r ffo an shit reister are ull an a transer is initiate he it reains set until it is cleare y writin a to it o rx ffo oerlow rx ffo oerlow has occurre resere his reaonly iel is resere an always has the alue ero rff receie ffo rain fla roies a etho or the to request that entries e reoe ro the r ffo he it is set while the r ffo is not ety he rff it can e cleare y writin to it or y acnowleeent ro the controller when the r ffo is ety rx ffo is ety rx ffo is not ety resere his reaonly iel is resere an always has the alue ero r ffo ounter nicates the nuer o ali entries in the ffo he r is increente eery tie the uhr is written he r is ecreente eery tie a coan is execute an the ata is transerre to the shit reister r ransit ext ointer nicates which ffo ntry is transitte urin the next transer he r iel is uate eery tie ata is transerre ro the ffo to the shit reister rr r ffo ounter nicates the nuer o entries in the r ffo he rr is ecreente eery tie the or is rea he rr is increente eery tie ata is transerre ro the shit reister to the r ffo or o ext ointer ontains a ointer to the r ffo entry to e returne when the or is rea he or is uate when the or is rea eory areister einition ufaily reerence anual re o freescale eiconuctor nc 49.3.6 dspi dma/interrupt request select and enable register (spi x rr rser controls dma and interrupt requests. do not write to the rser while the dspi is in the running state. addresses: spi0_rser is 4002_c000h base + 30h offset = 4002_c030h spi1_rser is 4002_d000h base + 30h offset = 4002_d030h spi2_rser is 400a_c000h base + 30h offset = 400a_c030h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r tcf_re 0 0 eoqf_re tfuf_re 0 tfff_re tfff_dirs 0 0 0 0 rfof_re 0 rfdf_re rfdf_dirs w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 spi x rr iel escritions fiel escrition fr ransission olete request nale nales f la in the r to enerate an interrut request f interrut requests are isale f interrut requests are enale resere his reaonly iel is resere an always has the alue ero resere his reaonly iel is resere an always has the alue ero ofr finishe request nale nales the of la in the r to enerate an interrut request of interrut requests are isale of interrut requests are enale fufr ransit ffo unerlow request nale nales the fuf la in the r to enerate an interrut request fuf interrut requests are isale fuf interrut requests are enale table continues on the next page... chapter 4 spi dspi 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1411 spi x rr iel escritions continue fiel escrition resere his reaonly iel is resere an always has the alue ero fffr ransit ffo fill request nale nales the fff la in the r to enerate a request he fffr it selects etween eneratin an interrut request or a request fff interruts or requests are isale fff interruts or requests are enale fffr ransit ffo fill or nterrut request elect elects etween eneratin a request or an interrut request hen the fff la it in the r is set an the fffr it in the rr reister is set this it selects etween eneratin an interrut request or a request fff la enerates interrut requests fff la enerates requests resere his reaonly iel is resere an always has the alue ero resere his reaonly iel is resere an always has the alue ero resere his reaonly iel is resere an always has the alue ero resere his reaonly iel is resere an always has the alue ero rfofr receie ffo oerlow request nale nales the rfof la in the r to enerate an interrut request rfof interrut requests are isale rfof interrut requests are enale resere his reaonly iel is resere an always has the alue ero rffr receie ffo rain request nale nales the rff la in the r to enerate a request he rffr it selects etween eneratin an interrut request or a request rff interrut or requests are isale rff interrut or requests are enale rffr receie ffo rain or nterrut request elect elects etween eneratin a request or an interrut request hen the rff la it in the r is set an the rffr it in the rr is set the rffr it selects etween eneratin an interrut request or a request nterrut request request table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 1412 freescale semiconductor, inc. spi x rr iel escritions continue fiel escrition resere his reaonly iel is resere an always has the alue ero uh ffo reister n aster oe x uhr pushr provides the means to write to the tx fifo. data written to this register is transferred to the tx fifo. eight- or sixteen-bit write accesses to the pushr transfer all 32 register bits to the tx fifo. the register structure is different in master and slave modes. in master mode the register provides 16-bit command and 16-bit data to the tx fifo. in slave mode all 32 register bits can be used as data, supporting up to 32-bit spi frame operation. addresses: spi0_pushr is 4002_c000h base + 34h offset = 4002_c034h spi1_pushr is 4002_d000h base + 34h offset = 4002_d034h spi2_pushr is 400a_c000h base + 34h offset = 400a_c034h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r cont ctas eoq ctcnt 0 0 pcs[5:0] txdata w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 spi x uhr iel escritions fiel escrition o ontinuous eriheral hi elect nale elects a ontinuous election forat he it is use in aster oe he it enales the selecte sinals to reain asserte etween transers return n sinals to their inactie state etween transers ee n sinals asserte etween transers loc an ranser ttriutes elect elects which r reister to use in aster oe to seciy the transer attriutes or the associate rae n slae oe r is use ee the hi oniuration chater to eterine how any r reisters this eice has ou shoul not rora a alue in this iel or a reister that is not resent r r resere resere resere resere table continues on the next page... chapter 4 spi dspi 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 141 spi x uhr iel escritions continue fiel escrition resere resere o n o ueue host sotware uses this it to sinal to the that the current transer is the last in a queue t the en o the transer the of it in the r is set he ata is not the last ata to transer he ata is the last ata to transer lear ranser ounter lears the iel in the r reister he iel is cleare eore the starts transittin the current rae o not clear the r iel lear the r iel resere his reaonly iel is resere an always has the alue ero resere his reaonly iel is resere an always has the alue ero : elect which sinals are to e asserte or the transer reer to the chi coniuration chater or the nuer o sinals use in this u eate the x sinal ssert the x sinal ransit ata hols ata to e transerre accorin to the associate coan eory areister einition ufaily reerence anual re o freescale eiconuctor nc 49.3.8 dspi push tx fifo register in slave mode (spi x uhrl pushr provides the means to write to the tx fifo. data written to this register is transferred to the tx fifo. eight- or sixteen-bit write accesses to the pushr transfer all 32 register bits to the tx fifo. the register structure is different in master and slave modes. in master mode the register provides 16-bit command and 16-bit data to the tx fifo. in slave mode all 32 register bits can be used as data, supporting up to 32-bit spi frame operation. addresses: spi0_pushr_slave is 4002_c000h base + 34h offset = 4002_c034h spi1_pushr_slave is 4002_d000h base + 34h offset = 4002_d034h spi2_pushr_slave is 400a_c000h base + 34h offset = 400a_c034h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r txdata w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 spi x uhrl iel escritions fiel escrition ransit ata hols ata to e transerre accorin to the associate coan o r ffo reister x or popr is used to read the rx fifo. eight- or sixteen-bit read accesses to the popr have the same effect on the rx fifo as 32-bit read accesses. a write to this register will generate a transfer error. addresses: spi0_popr is 4002_c000h base + 38h offset = 4002_c038h spi1_popr is 4002_d000h base + 38h offset = 4002_d038h spi2_popr is 400a_c000h base + 38h offset = 400a_c038h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r rxdata w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 chapter 49 spi (dspi) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1415 spi x or iel escritions fiel escrition r receie ata ontains the ata ro the r ffo entry to which the o ext ata ointer oints ransit ffo reisters x fr n txfrn provide visibility into the tx fifo for debugging purposes. each register is an entry in the tx fifo. the registers are read-only and cannot be modified. reading the txfrx registers does not alter the state of the tx fifo. addresses: spi0_txfr0 is 4002_c000h base + 3ch offset = 4002_c03ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r txcmd_txdata txdata w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 spi x fr n iel escritions fiel escrition ransit oan or ransit ata n aster oe the iel contains the coan that sets the transer attriutes or the ata n slae oe the contains its o the ata to e shite out ransit ata ontains the ata to e shite out receie ffo reisters x rfr n rxfrn provide visibility into the rx fifo for debugging purposes. each register is an entry in the rx fifo. the rxfr registers are read-only. reading the rxfrx registers does not alter the state of the rx fifo. addresses: spi0_rxfr0 is 4002_c000h base + 7ch offset = 4002_c07ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r rxdata w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1416 freescale semiconductor, inc. spi x rfr n iel escritions fiel escrition r receie ata ontains the receie ata functional escrition the serial peripheral interface (dspi) block supports full-duplex, synchronous serial communications between mcus and peripheral devices. all communications are done with spi-like protocol. the dspi has the following configurations: ? spi configuration in which the dspi operates as a basic spi or a queued spi. the dconf field in the dspi module configuration register (mcr) determines the dspi configuration. see for the dspi configuration values. the ctarn registers hold clock and transfer attributes. the spi configuration allows to select which ctar to use on a frame by frame basis by setting a field in the spi command. see dspi clock and transfer attributes registers for information on the fields of the ctar registers. typical master to slave connections are shown in the following figure. when a data transfer operation is performed, data is serially shifted a predetermined number of bit positions. because the modules are linked, data is exchanged between the master and the slave. the data that was in the master shift register is now in the shift register of the slave, and vice versa. at the end of a transfer, the tcf bit in the sr is set to indicate a completed transfer. shift register baud rate generator shift register sout sck pcsx dspi slave dspi master sin sout sin ss sck figure 49-91. spi serial protocol overview chapter 49 spi (dspi) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1417 generally more than one slave device can be connected to the dspi master. 6 peripheral chip select (pcs) signals of the dspi masters can be used to select which of the slaves to communicate with. refer to the chip configuration chapter for the number of pcs signals used in this mcu. the three dspi configurations share transfer protocol and timing properties which are described independently of the configuration in transfer formats . the transfer rate and delay settings are described in dspi baud rate and clock delay generation . 49.4.1 start and stop of dspi transfers the dspi has two operating states: stopped and running. the states are independent of dspi configuration. the default state of the dspi is stopped. in the stopped state no serial transfers are initiated in master mode and no transfers are responded to in slave mode. the stopped state is also a safe state for writing the various configuration registers of the dspi without causing undetermined results. in the running state serial transfers take place. the txrxs bit in the sr indicates what state the dspi in. the bit is set if the module in running state. the dspi is started (dspi transitions to running) when all of the following conditions are true: ? sr[eoqf] bit is clear ? mcu is not in the debug mode or the mcr[frz] bit is clear ? mcr[halt] bit is clear the dspi stops (transitions from running to stopped) after the current frame when any one of the following conditions exist: ? sr[eoqf] bit is set ? mcu in the debug mode and the mcr[frz] bit is set ? mcr[halt] bit is set state transitions from running to stopped occur on the next frame boundary if a transfer is in progress, or immediately if no transfers are in progress. functional description k60 sub-family reference manual, rev. 6, nov 2011 1418 freescale semiconductor, inc. 49.4.2 serial peripheral interface (spi) configuration the spi configuration transfers data serially using a shift register and a selection of programmable transfer attributes. the dspi is in spi configuration when the dconf field in the mcr is 0b00. the spi frames can be 32 bits long. the host cpu or a dma controller transfers the spi data from the external to dspi ram queues to a transmit fifo (tx fifo) buffer. the received data is stored in entries in the receive fifo (rx fifo) buffer. the host cpu or the dma controller transfers the received data from the rx fifo to memory external to the dspi. the fifo buffers operation is described in transmit first in first out (tx fifo) buffering mechanism , and receive first in first out (rx fifo) buffering mechanism . the interrupt and dma request conditions are described in interrupts/dma requests . the spi configuration supports two block-specific modes master mode and slave mode. the fifo operations are similar for both modes. the main difference is that in master mode the dspi initiates and controls the transfer according to the fields in the spi command field of the tx fifo entry. in slave mode, the dspi only responds to transfers initiated by a bus master external to the dspi and the spi command field space is used for 16 most significant bit of the transmit data. 49.4.2.1 master mode in spi master mode the dspi initiates the serial transfers by controlling the serial communications clock (sck) and the peripheral chip select (pcs) signals. the spi command field in the executing tx fifo entry determines which ctar registers will be used to set the transfer attributes and which pcs signals to assert. the command field also contains various bits that help with queue management and transfer protocol. see dspi push tx fifo register (pushr) for details on the spi command fields. the data field in the executing tx fifo entry is loaded into the shift register and shifted out on the serial out (sout) pin. in spi master mode, each spi frame to be transmitted has a command associated with it allowing for transfer attribute control on a frame by frame basis. 49.4.2.2 slave mode in spi slave mode the dspi responds to transfers initiated by a spi bus master. the dspi does not initiate transfers. certain transfer attributes such as clock polarity, clock phase and frame size must be set for successful communication with a spi master. the spi slave mode transfer attributes are set in the ctar0. the data is shifted out with msb first. shifting out of lsb is not supported in this mode. chapter 49 spi (dspi) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1419 49.4.2.3 fifo disable operation the fifo disable mechanisms allow spi transfers without using the tx fifo or rx fifo. the dspi operates as a double-buffered simplified spi when the fifos are disabled. the fifos are disabled separately; setting the mcr[dis_txf] bit disables the tx fifo, and setting the mcr[dis_rxf] bit disables the rx fifo. the fifo disable mechanisms are transparent to the user and to host software; transmit data and commands are written to the pushr and received data is read from the popr. when the tx fifo is disabled the tfff, tfuf and txctr fields in sr behave as if there is a one-entry fifo but the contents of the txfr registers and txnxtptr are undefined. likewise, when the rx fifo is disabled, the rfdf, rfof and rxctr fields in the sr behave as if there is a one-entry fifo, but the contents of the rxfr registers and popnxtptr are undefined. 49.4.2.4 transmit first in first out (tx fifo) buffering mechanism the tx fifo functions as a buffer of spi data and spi commands for transmission. the tx fifo holds 4 words, each consisting of a command field and a data field. the number of entries in the tx fifo is device-specific. spi commands and data are added to the tx fifo by writing to the dspi push tx fifo register (pushr). tx fifo entries can only be removed from the tx fifo by being shifted out or by flushing the tx fifo. the tx fifo counter field (txctr) in the dspi status register (sr) indicates the number of valid entries in the tx fifo. the txctr is updated every time the dspi _pushr is written or spi data is transferred into the shift register from the tx fifo. the txnxtptr field indicates which tx fifo entry will be transmitted during the next transfer. the txnxtptr contains the positive offset from txfr0 in number of 32-bit registers. for example, txnxtptr equal to two means that the txfr2 contains the spi data and command for the next transfer. the txnxtptr field is incremented every time spi data is transferred from the tx fifo to the shift register. the maximum value of the field is equal to the maximum implemented txfr register number and it rolls over after reaching the maximum. functional description k60 sub-family reference manual, rev. 6, nov 2011 1420 freescale semiconductor, inc. 49.4.2.4.1 filling the tx fifo host software or other intelligent blocks can add (push) entries to the tx fifo by writing to the pushr. when the tx fifo is not full, the tx fifo fill flag (tfff) in the sr is set. the tfff bit is cleared when tx fifo is full and the dma controller indicates that a write to pushr is complete. writing a '1' to the tfff bit also clears it. the tfff can generate a dma request or an interrupt request. see transmit fifo fill interrupt or dma request for details. the dspi ignores attempts to push data to a full tx fifo, the state of the tx fifo does not change and no error condition is indicated. 49.4.2.4.2 draining the tx fifo the tx fifo entries are removed (drained) by shifting spi data out through the shift register. entries are transferred from the tx fifo to the shift register and shifted out as long as there are valid entries in the tx fifo. every time an entry is transferred from the tx fifo to the shift register, the tx fifo counter decrements by one. at the end of a transfer, the tcf bit in the sr is set to indicate the completion of a transfer. the tx fifo is flushed by writing a '1' to the clr_txf bit in mcr. if an external bus master initiates a transfer with a dspi slave while the slave's dspi tx fifo is empty, the transmit fifo underflow flag (tfuf) in the slave's sr is set. see transmit fifo underflow interrupt request for details. 49.4.2.5 receive first in first out (rx fifo) buffering mechanism the rx fifo functions as a buffer for data received on the sin pin. the rx fifo holds 4 received spi data frames. the number of entries in the rx fifo is device-specific. spi data is added to the rx fifo at the completion of a transfer when the received data in the shift register is transferred into the rx fifo. spi data are removed (popped) from the rx fifo by reading the dspi pop rx fifo register (popr). rx fifo entries can only be removed from the rx fifo by reading the popr or by flushing the rx fifo. the rx fifo counter field (rxctr) in the dspi status register (sr) indicates the number of valid entries in the rx fifo. the rxctr is updated every time the popr is read or spi data is copied from the shift register to the rx fifo. the popnxtptr field in the sr points to the rx fifo entry that is returned when the popr is read. the popnxtptr contains the positive offset from rxfr0 in number of 32-bit registers. for example, popnxtptr equal to two means that the rxfr2 contains the received spi data that will be returned when popr is read. the popnxtptr field is chapter 49 spi (dspi) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1421 incremented every time the popr is read. the maximum value of the field is equal to the maximum implemented rxfr register number and it rolls over after reaching the maximum. 49.4.2.5.1 filling the rx fifo the rx fifo is filled with the received spi data from the shift register. while the rx fifo is not full, spi frames from the shift register are transferred to the rx fifo. every time a spi frame is transferred to the rx fifo the rx fifo counter is incremented by one. if the rx fifo and shift register are full and a transfer is initiated, the rfof bit in the sr is set indicating an overflow condition. depending on the state of the rooe bit in the mcr, the data from the transfer that generated the overflow is either ignored or shifted in to the shift register. if the rooe bit is set, the incoming data is shifted in to the shift register. if the rooe bit is cleared, the incoming data is ignored. 49.4.2.5.2 draining the rx fifo host cpu or a dma can remove (pop) entries from the rx fifo by reading the dspi pop rx fifo register (popr). a read of the popr decrements the rx fifo counter by one. attempts to pop data from an empty rx fifo are ignored and the rx fifo counter remains unchanged. the data, read from the empty rx fifo, is undetermined. when the rx fifo is not empty, the rx fifo drain flag (rfdf) in the sr is set. the rfdf bit is cleared when the rx_fifo is empty and the dma controller indicates that a read from popr is complete or by writing a '1' to it. 49.4.3 dspi baud rate and clock delay generation the sck frequency and the delay values for serial transfer are generated by dividing the system clock frequency by a prescaler and a scaler with the option for doubling the baud rate. the following figure shows conceptually how the sck signal is generated. system clock prescaler 1 scaler 1+dbr sck figure 49-92. communications clock prescalers and scalers functional description k60 sub-family reference manual, rev. 6, nov 2011 1422 freescale semiconductor, inc. 49.4.3.1 baud rate generator the baud rate is the frequency of the serial communication clock (sck). the system clock is divided by a prescaler (pbr) and scaler (br) to produce sck with the possibility of halving the scaler division. the dbr, pbr and br fields in the ctar registers select the frequency of sck by the formula in the br field description. the following table shows an example of how to compute the baud rate. table 49-106. baud rate computation example f sys pbr prescaler br scaler dbr baud rate 100 mhz 0b00 2 0b0000 2 0 25 mb/s 20 mhz 0b00 2 0b0000 2 1 10 mb/s note the clock frequencies mentioned in the preceding table are given as an example. refer to the clocking chapter for the frequency used to drive this module in the device. 49.4.3.2 pcs to sck delay (t csc ) the pcs to sck delay is the length of time from assertion of the pcs signal to the first sck edge. see figure 49-94 for an illustration of the pcs to sck delay. the pcssck and cssck fields in the ctar x registers select the pcs to sck delay by the formula in the cssck field description. the following table shows an example of how to compute the pcs to sck delay. table 49-107. pcs to sck delay computation example f sys pcssck prescaler cssck scaler pcs to sck delay 100 mhz 0b01 3 0b0100 32 0.96 the clock frequency mentioned in the preceding table is given as an example. refer to the clocking chapter for the frequency used to drive this module in the device. chapter 49 spi (dspi) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1423 49.4.3.3 after sck delay (t asc ) the after sck delay is the length of time between the last edge of sck and the negation of pcs. see figure 49-94 and figure 49-95 for illustrations of the after sck delay. the pasc and asc fields in the ctar x registers select the after sck delay by the formula in the asc field description. the following table shows an example of how to compute the after sck delay. table 49-108. after sck delay computation example f sys pasc prescaler asc scaler after sck delay 100 mhz 0b01 3 0b0100 32 0.96 the clock frequency mentioned in the preceding table is given as an example. refer to the clocking chapter for the frequency used to drive this module in the device. 49.4.3.4 delay after transfer (t dt ) the delay after transfer is the minimum time between negation of the pcs signal for a frame and the assertion of the pcs signal for the next frame. see figure 49-94 for an illustration of the delay after transfer. the pdt and dt fields in the ctar x registers select the delay after transfer by the formula in the dt field description. the following table shows an example of how to compute the delay after transfer. table 49-109. delay after transfer computation example f sys pdt prescaler dt scaler delay after transfer 100 mhz 0b01 3 0b1110 32768 0.98 ms note the clock frequency mentioned in the preceding table is given as an example. refer to the clocking chapter for the frequency used to drive this module in the device. when in non-continuous clock mode the t dt delay is configured according to the equation specified in the ctar[dt] bitfield description. when in continuous clock mode, the delay is fixed at 1 sck period. functional description k60 sub-family reference manual, rev. 6, nov 2011 1424 freescale semiconductor, inc. 49.4.3.5 peripheral chip select strobe enable ( pcss ) the pcss signal provides a delay to allow the pcs signals to settle after a transition occurs thereby avoiding glitches. when the dspi is in master mode and the pcsse bit is set in the mcr, pcss provides a signal for an external demultiplexer to decode the pcs[0] - pcs[4] signals into as many as 128 glitch-free pcs signals. the following figure shows the timing of the pcss signal relative to pcs signals. t pcssck pcss pcsx t pasc figure 49-93. peripheral chip select strobe timing the delay between the assertion of the pcs signals and the assertion of pcss is selected by the pcssck field in the ctar based on the following formula: at the end of the transfer the delay between pcss negation and pcs negation is selected by the pasc field in the ctar based on the following formula: the following table shows an example of how to compute the t pcssck delay. table 49-110. peripheral chip select strobe assert computation example f sys pcssck prescaler delay before transfer 100 mhz 0b11 7 70.0 ns the following table shows an example of how to compute the t pasc delay. table 49-111. peripheral chip select strobe negate computation example f sys pasc prescaler delay after transfer 100 mhz 0b11 7 70.0 ns the pcss signal is not supported when continuous serial communication sck mode are enabled. chapter 49 spi (dspi) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1425 note the clock frequency mentioned in the preceding tables is given as an example. refer to the clocking chapter for the frequency used to drive this module in the device. 49.4.4 transfer formats the spi serial communication is controlled by the serial communications clock (sck) signal and the pcs signals. the sck signal provided by the master device synchronizes shifting and sampling of the data on the sin and sout pins. the pcs signals serve as enable signals for the slave devices. in master mode, the cpol and cpha bits in the clock and transfer attributes registers (ctarn) select the polarity and phase of the serial clock, sck. ? cpol - selects the idle state polarity of the sck ? cpha - selects if the data on sout is valid before or on the first sck edge even though the bus slave does not control the sck signal, in slave mode these values must be identical to the master device settings to ensure proper transmission. in spi slave mode, only ctar0 is used. the dspi supports four different transfer formats: ? classic spi with cpha=0 ? classic spi with cpha=1 ? modified transfer format with cpha = 0 ? modified transfer format with cpha = 1 a modified transfer format is supported to allow for high-speed communication with peripherals that require longer setup times. the dspi can sample the incoming data later than halfway through the cycle to give the peripheral more setup time. the mtfe bit in the mcr selects between classic spi format and modified transfer format. in the spi configurations, the dspi provides the option of keeping the pcs signals asserted between frames. see continuous selection format for details. functional description k60 sub-family reference manual, rev. 6, nov 2011 1426 freescale semiconductor, inc. 49.4.4.1 classic spi transfer format (cpha = 0) the transfer format shown in following figure is used to communicate with peripheral spi slave devices where the first data bit is available on the first clock edge. in this format, the master and slave sample their sin pins on the odd-numbered sck edges and change the data on their sout pins on the even-numbered sck edges. t asc = a fter sck delay t csc = p cs to sck delay msb first (lsbfe = 0): msb msb first (lsbfe = 1): lsb t dt = delay after transfer (minimum cs idle time) t csc bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 lsb msb t csc t dt t asc pcsx/ss slave sout master sin/ master sout/ slave sin master and slave sample sck (cpol = 1) sck (cpol = 0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 figure 49-94. dspi transfer timing diagram (mtfe=0, cpha=0, fmsz=8) the master initiates the transfer by placing its first data bit on the sout pin and asserting the appropriate peripheral chip select signals to the slave device. the slave responds by placing its first data bit on its sout pin. after the tcsc delay elapses, the master outputs the first edge of sck. the master and slave devices use this edge to sample the first input data bit on their serial data input signals. at the second edge of the sck the master and slave devices place their second data bit on their serial data output signals. for the rest of the frame the master and the slave sample their sin pins on the odd-numbered clock edges and changes the data on their sout pins on the even-numbered clock edges. after the last clock edge occurs a delay of t asc is inserted before the master negates the pcs signals. a delay of t dt is inserted before a new frame transfer can be initiated by the master. chapter 49 spi (dspi) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1427 49.4.4.2 classic spi transfer format (cpha = 1) this transfer format shown in the following figure is used to communicate with peripheral spi slave devices that require the first sck edge before the first data bit becomes available on the slave sout pin. in this format the master and slave devices change the data on their sout pins on the odd-numbered sck edges and sample the data on their sin pins on the even-numbered sck edges t asc = a fter sck delay t csc = p cs to sck delay msb first (lsbfe = 0): msb t dt = delay after transfer (minimum cs negation time) t csc bit 1 msb t dt t asc pcsx/ss slave sout master sin/ master sout/ slave sin master and slave sample sck (cpol = 0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sck (cpol = 1) bit 6 bit 2 bit 3 bit 4 bit 5 bit 6 lsb bit 5 bit 4 bit 3 bit 2 bit 1 lsb first (lsbfe = 1): lsb figure 49-95. dspi transfer timing diagram (mtfe=0, cpha=1, fmsz=8) the master initiates the transfer by asserting the pcs signal to the slave. after the t csc delay has elapsed, the master generates the first sck edge and at the same time places valid data on the master sout pin . the slave responds to the first sck edge by placing its first data bit on its slave sout pin. at the second edge of the sck the master and slave sample their sin pins. for the rest of the frame the master and the slave change the data on their sout pins on the odd- numbered clock edges and sample their sin pins on the even-numbered clock edges. after the last clock edge occurs a delay of t asc is inserted before the master negates the pcs signal. a delay of t dt is inserted before a new frame transfer can be initiated by the master. functional description k60 sub-family reference manual, rev. 6, nov 2011 1428 freescale semiconductor, inc. 49.4.4.3 continuous selection format some peripherals must be deselected between every transfer. other peripherals must remain selected between several sequential serial transfers. the continuous selection format provides the flexibility to handle the following case. the continuous selection format is enabled for the spi configuration by setting the cont bit in the spi command. the behavior of the pcs signals in the configurations is identical so only spi configuration will be described. when the cont bit = 0, the dspi drives the asserted chip select signals to their idle states in between frames. the idle states of the chip select signals are selected by the pcsisn bits in the mcr. the following timing diagram is for two four-bit transfers with cpha = 1 and cont = 0. pcsx sck master sin t csc = pcs to sck dela t asc = after sck delay sck (cpol = 0) sck (cpol = 1) master sout t dt = delay after transfer (minimum cs negation time) t csc t asc t csc t dt figure 49-96. example of non-continuous format (cpha=1, cont=0) when the cont bit = 1, the pcs signal remains asserted for the duration of the two transfers. the delay between transfers (t dt ) is not inserted between the transfers. the following figure shows the timing diagram for two four-bit transfers with cpha = 1 and cont = 1. chapter 49 spi (dspi) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1429 pcs master sin t csc = p c s to sck del ay t asc = after sck delay sck (cpol = 0) sck (cpol = 1) master sout t csc t asc t csc figure 49-97. example of continuous transfer (cpha=1, cont=1) when using dspi with continuous selection follow these rules: ? all transmit commands must have the same pcsn bits programming. ? the ctars, selected by transmit commands, must be programmed with the same transfer attributes. only fmsz field can be programmed differently in these ctars. ? when transmitting multiple frames in this mode, the user software must ensure that the last frame has the pushr[cont] bit de-asserted (in master mode) and the user software must provide sufficient frames in the tx_fifo to be sent out (in slave mode) and the master de-asserts the pcsn at end of transmission of last frame. ? the pushr[cont] / dsicr0[dcont] bits must be de-asserted before asserting mcr[halt] bit (in master mode). this will make sure that the pcsn signals are de- asserted. asserting mcr[halt] bit during continuous transfer will cause the pcsn signals to remain asserted and hence slave device cannot transition from running to stopped state. note user must fill the txfifo with the number of entries that will be concatenated together under one pcs assertion for both master and slave before the txfifo becomes empty. when operating in slave mode, ensure that when the last-entry in the txfifo is completely transmitted (that is the corresponding tcf flag is asserted and txfifo is empty), the slave is deselected for any further serial communication; otherwise, an underflow error occurs. functional description k60 sub-family reference manual, rev. 6, nov 2011 1430 freescale semiconductor, inc. 49.4.5 continuous serial communications clock the dspi provides the option of generating a continuous sck signal for slave peripherals that require a continuous clock. continuous sck is enabled by setting the cont_scke bit in the mcr. enabling this bit generates the continuous serial communications clock regardless of the mcr[halt] bit status.. continuous sck is valid in all configurations. continuous sck is only supported for cpha=1. clearing cpha is ignored if the cont_scke bit is set. continuous sck is supported for modified transfer format. clock and transfer attributes for the continuous sck mode are set according to the following rules: ? when the dspi is in spi configuration, ctar0 is used initially. at the start of each spi frame transfer, the ctar specified by the ctas for the frame is used. ? in all configurations, the currently selected ctar remains in use until the start of a frame with a different ctar specified, or the continuous sck mode is terminated. it is recommended to keep the baud rate the same while using the continuous sck. switching clock polarity between frames while using continuous sck can cause errors in the transfer. continuous sck operation is not guaranteed if the dspi is put into the external stop mode or module disable mode. enabling continuous sck disables the pcs to sck delay and the delay after transfer (t dt ) is fixed to one sck cycle. the following figure is the timing diagram for continuous sck format with continuous selection disabled. note when in continuous sck mode, for the spi transfer ctar0 should always be used, and the txfifo must be cleared using the mcr[clr_txf] field before initiating transfer. chapter 49 spi (dspi) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1431 pcs master sin sck (cpol = 0) sck (cpol = 1) master sout t dt figure 49-98. continuous sck timing diagram (cont=0) if the cont bit in the tx fifo entry is set, pcs remains asserted between the transfers. under certain conditions, sck can continue with pcs asserted, but with no data being shifted out of sout (sout pulled high). this can cause the slave to receive incorrect data. those conditions include: ? continuous sck with cont bit set, but no data in the transmit fifo. ? continuous sck with cont bit set and entering stopped state (refer to start and stop of dspi transfers ). ? continuous sck with cont bit set and entering stop mode or module disable mode. the following figure shows timing diagram for continuous sck format with continuous selection enabled. pcs master sin sck (cpol = 0) sck (cpol = 1) master sout transfer 1 transfer 2 figure 49-99. continuous sck timing diagram (cont=1) functional description k60 sub-family reference manual, rev. 6, nov 2011 1432 freescale semiconductor, inc. 49.4.6 slave mode operation constraints slave mode logic shift register is buffered. this allows data streaming operation, when the dspi is permanently selected and data is shifted in with a constant rate. the transmit data is transferred at second sck clock edge of the each frame to the shift register if the ss signal is asserted and any time when transmit data is ready and ss signal is negated. received data is transferred to the receive buffer at last sck edge of each frame, defined by frame size programmed to the ctar0/1 register. then the data from the buffer is transferred to the rxfifo or ddr register. if the ss negates before that last sck edge, the data from shift register is lost. this buffering scheme allows to operate slave clock with higher frequency than the system frequency. the clocks relationship is defined by the following equation. framesize is the value of the ctar0/1[fmsz] field plus one. 3 49.4.7 interrupts/dma requests the dspi has several conditions that can only generate interrupt requests and two conditions that can generate interrupt or dma requests. the following table lists these conditions. table 49-112. interrupt and dma request conditions condition flag interrupt dma end of queue (eoq) eoqf yes tx fifo fill tfff yes yes transfer complete tcf yes tx fifo underflow tfuf yes rx fifo drain rfdf yes yes rx fifo overflow rfof yes each condition has a flag bit in the dspi status register (sr) and an request enable bit in the dspi dma/interrupt request select and enable register (rser). the tx fifo fill flag (tfff) and rx fifo drain flag (rfdf) generate interrupt requests or dma requests depending on the tfff_dirs and rfdf_dirs bits in the rser. the dspi module also provides a global interrupt request line, which is asserted when any of individual interrupt requests lines is asserted. chapter 49 spi (dspi) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1433 49.4.7.1 end of queue interrupt request the end of queue request indicates that the end of a transmit queue is reached. the end of queue request is generated when the eoq bit in the executing spi command is set and the eoqf_re bit in the rser is set. note this interrupt request is generated when the last bit of the spi frame with eoq bit set is transmitted. 49.4.7.2 transmit fifo fill interrupt or dma request the transmit fifo fill request indicates that the tx fifo is not full. the transmit fifo fill request is generated when the number of entries in the tx fifo is less than the maximum number of possible entries, and the tfff_re bit in the rser is set. the tfff_dirs bit in the rser selects whether a dma request or an interrupt request is generated. note tfff flag clears automatically when dma is used to fill txfifo. to clear tfff when not using dma, follow these steps for every push performed using cpu to fill txfifo: 1. wait until tfff = 1 2. write data to pushr using cpu. 3. clear tfff by writing a 1 to its location. if fifo is not full, this flag will not clear. 49.4.7.3 transfer complete interrupt request the transfer complete request indicates the end of the transfer of a serial frame. the transfer complete request is generated at the end of each frame transfer when the tcf_re bit is set in the rser. functional description k60 sub-family reference manual, rev. 6, nov 2011 1434 freescale semiconductor, inc. 49.4.7.4 transmit fifo underflow interrupt request the transmit fifo underflow request indicates that an underflow condition in the tx fifo has occurred. the transmit underflow condition is detected only for the dspi, operating in slave mode and spi configuration . the tfuf bit is set when the tx fifo of a dspi is empty, and a transfer is initiated from an external spi master. if the tfuf bit is set while the tfuf_re bit in the rser is set, an interrupt request is generated. 49.4.7.5 receive fifo drain interrupt or dma request the receive fifo drain request indicates that the rx fifo is not empty. the receive fifo drain request is generated when the number of entries in the rx fifo is not zero, and the rfdf_re bit in the rser is set. the rfdf_dirs bit in the rser selects whether a dma request or an interrupt request is generated. 49.4.7.6 receive fifo overflow interrupt request the receive fifo overflow request indicates that an overflow condition in the rx fifo has occurred. a receive fifo overflow request is generated when rx fifo and shift register are full and a transfer is initiated. the rfof_re bit in the rser must be set for the interrupt request to be generated. depending on the state of the rooe bit in the mcr, the data from the transfer that generated the overflow is either ignored or shifted in to the shift register. if the rooe bit is set, the incoming data is shifted in to the shift register. if the rooe bit is cleared, the incoming data is ignored. 49.4.8 power saving features the dspi supports following power-saving strategies: ? external stop mode ? module disable mode - clock gating of non-memory mapped logic chapter 49 spi (dspi) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1435 49.4.8.1 stop mode (external stop mode) the dspi supports the stop mode protocol. when a request is made to enter external stop mode, the dspi block acknowledges the request . if a serial transfer is in progress, the dspi waits until it reaches the frame boundary before it is ready to have its clocks shut off .while the clocks are shut off, the dspi memory-mapped logic is not accessible. the states of the interrupt and dma request signals cannot be changed while in external stop mode. 49.4.8.2 module disable mode module disable mode is a block-specific mode that the dspi can enter to save power. host cpu can initiate the module disable mode by setting the mdis bit in the mcr. the module disable mode can also be initiated by hardware. a power management block can initiate the module disable mode by asserting the doze mode signal while the doze bit in the mcr is set. when the mdis bit is set or the doze mode signal is asserted while the doze bit is set, the dspi negates clock enable signal at the next frame boundary. if implemented, the clock enable signal can stop the clock to the non-memory mapped logic. when clock enable is negated, the dspi is in a dormant state, but the memory mapped registers are still accessible. certain read or write operations have a different effect when the dspi is in the module disable mode. reading the rx fifo pop register does not change the state of the rx fifo. likewise, writing to the tx fifo push register does not change the state of the tx fifo. clearing either of the fifos has no effect in the module disable mode. changes to the dis_txf and dis_rxf fields of the mcr have no effect in the module disable mode. in the module disable mode, all status bits and register flags in the dspi return the correct values when read, but writing to them has no effect. writing to the tcr during module disable mode has no effect. interrupt and dma request signals cannot be cleared while in the module disable mode. 49.5 initialization/application information this section describes how to initialize the dspi module. 49.5.1 how to manage dspi queues the queues are not part of the dspi, but the dspi includes features in support of queue management. queues are primarily supported in spi configuration. initialization/application information k60 sub-family reference manual, rev. 6, nov 2011 1436 freescale semiconductor, inc. 1. when dspi executes last command word from a queue, the eoq bit in the command word is set to indicate to the dspi that this is the last entry in the queue. 2. at the end of the transfer, corresponding to the command word with eoq set is sampled, the eoq flag (eoqf) in the sr is set. 3. the setting of the eoqf flag disables serial transmission and reception of data, putting the dspi in the stopped state. the txrxs bit is cleared to indicate the stopped state. 4. the dma can continue to fill tx fifo until it is full or step 5 occurs. 5. disable dspi dma transfers by disabling the dma enable request for the dma channel assigned to tx fifo and rx fifo. this is done by clearing the corresponding dma enable request bits in the dma controller. 6. ensure all received data in rx fifo has been transferred to memory receive queue by reading the rxcnt in sr or by checking rfdf in the sr after each read operation of the popr. 7. modify dma descriptor of tx and rx channels for new queues 8. flush tx fifo by writing a '1' to the clr_txf bit in the mcr. flush rx fifo by writing a '1' to the clr_rxf bit in the mcr. 9. clear transfer count either by setting ctcnt bit in the command word of the first entry in the new queue or via cpu writing directly to spi_tcnt field in the tcr. 10. enable dma channel by enabling the dma enable request for the dma channel assigned to the dspi tx fifo, and rx fifo by setting the corresponding dma set enable request bit. 11. enable serial transmission and serial reception of data by clearing the eoqf bit. 49.5.2 switching master and slave mode when changing modes in the dspi, follow the steps below to guarantee proper operation. 1. halt the dspi by setting mcr[halt]. 2. clear the transmit and receive fifos by writing a 1 to the clr_txf and clr_rxf bits in mcr. 3. set the appropriate mode in mcr[mstr] and enable the dspi by clearing mcr[halt]. chapter 49 spi (dspi) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1437 49.5.3 baud rate settings the following table shows the baud rate that is generated based on the combination of the baud rate prescaler pbr and the baud rate scaler br in the ctar registers. the values calculated assume a 100 mhz system frequency and the double baud rate dbr bit is clear. note the clock frequency mentioned above is given as an example in this chapter. refer to the clocking chapter for the frequency used to drive this module in the device. table 49-113. baud rate values (bps) baud rate divider prescaler values 2 3 5 7 baud rate scaler values 2 25.0m 16.7m 10.0m 7.14m 4 12.5m 8.33m 5.00m 3.57m 6 8.33m 5.56m 3.33m 2.38m 8 6.25m 4.17m 2.50m 1.79m 16 3.12m 2.08m 1.25m 893k 32 1.56m 1.04m 625k 446k 64 781k 521k 312k 223k 128 391k 260k 156k 112k 256 195k 130k 78.1k 55.8k 512 97.7k 65.1k 39.1k 27.9k 1024 48.8k 32.6k 19.5k 14.0k 2048 24.4k 16.3k 9.77k 6.98k 4096 12.2k 8.14k 4.88k 3.49k 8192 6.10k 4.07k 2.44k 1.74k 16384 3.05k 2.04k 1.22k 872 32768 1.53k 1.02k 610 436 49.5.4 delay settings the following table shows the values for the delay after transfer (t dt ) and cs to sck delay (t csc ) that can be generated based on the prescaler values and the scaler values set in the ctar registers. the values calculated assume a 100 mhz system frequency. initialization/application information k60 sub-family reference manual, rev. 6, nov 2011 1438 freescale semiconductor, inc. note the clock frequency mentioned above is given as an example in this chapter. refer to the clocking chapter for the frequency used to drive this module in the device. table 49-114. delay values delay prescaler values 1 3 5 7 delay scaler values 2 20.0 ns 60.0 ns 100.0 ns 140.0 ns 4 40.0 ns 120.0 ns 200.0 ns 280.0 ns 8 80.0 ns 240.0 ns 400.0 ns 560.0 ns 16 160.0 ns 480.0 ns 800.0 ns 1.1 1.6 2.2 1.9 3.2 4.5 1.3 3.8 6.4 9.0 2.6 7.7 12.8 17.9 5.1 15.4 25.6 35.8 10.2 30.7 51.2 71.7 20.5 61.4 102.4 143.4 41.0 122.9 204.8 286.7 81.9 245.8 409.6 573.4 163.8 491.5 819.2 327.7 983.0 655.4 complete visibility of the tx and rx fifo contents is available through the fifo registers, and valid entries can be identified through a memory mapped pointer and a memory mapped counter for each fifo. the pointer to the first-in entry in each fifo is memory mapped. for the tx fifo the first-in pointer is the transmit next pointer (txnxtptr). for the rx fifo the first-in pointer is the pop next pointer (popnxtptr). the following figure illustrates the concept of first-in and last-in fifo entries along with the fifo counter. the tx fifo is chosen for the illustration, but the concepts carry over to the rx fifo. see transmit first in first out (tx fifo) buffering mechanism and receive first in first out (rx fifo) buffering mechanism for details on the fifo operation. chapter 49 spi (dspi) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1439 push tx fifo register transmit next data pointer shift register sout +1 -1 tx fifo counter tx fifo base - entry c entry a (first in) entry d (last in) entry b - - - figure 49-100. tx fifo pointers and counter 49.5.5.1 address calculation for the first-in entry and last-in entry in the tx fifo the memory address of the first-in entry in the tx fifo is computed by the following equation: the memory address of the last-in entry in the tx fifo is computed by the following equation: tx fifo base - base address of tx fifo txctr - tx fifo counter txnxtptr - transmit next pointer tx fifo depth - transmit fifo depth, implementation specific 49.5.5.2 address calculation for the first-in entry and last-in entry in the rx fifo the memory address of the first-in entry in the rx fifo is computed by the following equation: initialization/application information k60 sub-family reference manual, rev. 6, nov 2011 1440 freescale semiconductor, inc. the memory address of the last-in entry in the rx fifo is computed by the following equation: rx fifo base - base address of rx fifo rxctr - rx fifo counter popnxtptr - pop next pointer rx fifo depth - receive fifo depth, implementation specific chapter 49 spi (dspi) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1441 initialization/application information k60 sub-family reference manual, rev. 6, nov 2011 1442 freescale semiconductor, inc. chapter 50 inter-integrated circuit (i2c) 50.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the inter-integrated circuit (i 2 c, i2c, or iic) module provides a method of communication between a number of devices. the interface is designed to operate up to 100 kbit/s with maximum bus loading and timing. the device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. the maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pf. the i2c module also complies with the system management bus (smbus) specification, version 2 . 50.1.1 features the i2c module has the following features: ? compatible with the i 2 c-bus specification ? multimaster operation ? software programmable for one of 64 different serial clock frequencies ? software-selectable acknowledge bit ? interrupt-driven byte-by-byte data transfer ? arbitration-lost interrupt with automatic mode switching from master to slave ? calling address identification interrupt ? start and stop signal generation and detection ? repeated start signal generation and detection ? acknowledge bit generation and detection ? bus busy detection ? general call recognition k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1443 ? 10-bit address extension ? support for system management bus (smbus) specification, version 2 ? programmable glitch input filter ? low power mode wakeup on slave address match ? range slave address support ? dma support 50.1.2 modes of operation the i2c module's operation in various low power modes is as follows: ? run mode: this is the basic mode of operation. to conserve power in this mode, disable the module. ? wait mode: the module continues to operate when the core is in wait mode and can provide a wakeup interrupt. ? stop mode: the module is inactive in stop mode for reduced power consumption, except that address matching is enabled in stop mode. the stop instruction does not affect the i2c module's register states. in any vllsx mode, the register contents are reset. 50.1.3 block diagram the following figure is a functional block diagram of the i2c module. introduction k60 sub-family reference manual, rev. 6, nov 2011 1444 freescale semiconductor, inc. interrupt write/read address scl sda module enable ctrl_reg data_mux addr_decode data_reg status_reg addr_reg freq_reg input sync clock control start stop arbitration control in/out data shift register address compare figure 50-1. i2c functional block diagram 50.2 i 2 c signal descriptions the signal properties of i 2 c are shown in the following table. table 50-1. i 2 c signal descriptions signal description i/o scl bidirectional serial clock line of the i 2 c system. i/o sda bidirectional serial data line of the i 2 c system. i/o memory map and register descriptions this section describes in detail all i2c registers accessible to the end user. 50.3 chapter 50 inter-integrated circuit (i2c) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1445 i2c memory map absolute address (hex) register name width (in bits) access reset value section/ page 4006_6000 i2c address register 1 (i2c0_a1) 8 r/w 00h 50.3.1/ 1447 4006_6001 i2c frequency divider register (i2c0_f) 8 r/w 00h 50.3.2/ 1447 4006_6002 i2c control register 1 (i2c0_c1) 8 r/w 00h 50.3.3/ 1448 4006_6003 i2c status register (i2c0_s) 8 r/w 80h 50.3.4/ 1450 4006_6004 i2c data i/o register (i2c0_d) 8 r/w 00h 50.3.5/ 1452 4006_6005 i2c control register 2 (i2c0_c2) 8 r/w 00h 50.3.6/ 1453 4006_6006 i2c programmable input glitch filter register (i2c0_flt) 8 r/w 00h 50.3.7/ 1454 4006_6007 i2c range address register (i2c0_ra) 8 r/w 00h 50.3.8/ 1454 4006_6008 i2c smbus control and status register (i2c0_smb) 8 r/w 00h 50.3.9/ 1455 4006_6009 i2c address register 2 (i2c0_a2) 8 r/w c2h 50.3.10/ 1456 4006_600a i2c scl low timeout register high (i2c0_slth) 8 r/w 00h 50.3.11/ 1457 4006_600b i2c scl low timeout register low (i2c0_sltl) 8 r/w 00h 50.3.12/ 1457 4006_7000 i2c address register 1 (i2c1_a1) 8 r/w 00h 50.3.1/ 1447 4006_7001 i2c frequency divider register (i2c1_f) 8 r/w 00h 50.3.2/ 1447 4006_7002 i2c control register 1 (i2c1_c1) 8 r/w 00h 50.3.3/ 1448 4006_7003 i2c status register (i2c1_s) 8 r/w 80h 50.3.4/ 1450 4006_7004 i2c data i/o register (i2c1_d) 8 r/w 00h 50.3.5/ 1452 4006_7005 i2c control register 2 (i2c1_c2) 8 r/w 00h 50.3.6/ 1453 4006_7006 i2c programmable input glitch filter register (i2c1_flt) 8 r/w 00h 50.3.7/ 1454 4006_7007 i2c range address register (i2c1_ra) 8 r/w 00h 50.3.8/ 1454 table continues on the next page... memory map and register descriptions 60 sub-family reference manual, rev. 6, nov 2011 1446 freescale semiconductor, inc. i2c memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4006_7008 i2c smbus control and status register (i2c1_smb) 8 r/w 00h 50.3.9/ 1455 4006_7009 i2c address register 2 (i2c1_a2) 8 r/w c2h 50.3.10/ 1456 4006_700a i2c scl low timeout register high (i2c1_slth) 8 r/w 00h 50.3.11/ 1457 4006_700b i2c scl low timeout register low (i2c1_sltl) 8 r/w 00h 50.3.12/ 1457 50.3.1 i2c address register 1 (i2c x this register contains the slave address to be used by the i2c module. addresses: i2c0_a1 is 4006_6000h base + 0h offset = 4006_6000h i2c1_a1 is 4006_7000h base + 0h offset = 4006_7000h bit 7 6 5 4 3 2 1 0 read ad[7:1] 0 write reset 0 0 0 0 0 0 0 0 i2c x iel escritions fiel escrition : ress ontains the riary slae aress use y the oule when it is aresse as a slae his iel is use in the it aress schee an the lower seen its in the it aress schee resere his reaonly iel is resere an always has the alue ero frequency iier reister x f resses: f is h ase h oset h f is h ase h oset h it rea ul r rite reset hater nternterate ircuit ufaily reerence anual re o freescale eiconuctor nc i2c x f iel escritions fiel escrition ul he ul its eine the ultilier actor ul his actor is use alon with the l iier to enerate the au rate ul ul ul resere r loc rate rescales the us cloc or it rate selection his iel an the ul iel eterine the au rate the hol tie the l start hol tie an the l sto hol tie for a list o alues corresonin to each r settin see iier an hol alues he l iier ultilie y ultilier actor ul eterines the au rate i2c baud rate = bus speed (hz)/(mul scl divider) the sda hold time is the delay from the falling edge of scl (i2c clock) to the changing of sda (i2c data). sda hold time = bus period (s) mul sda hold value the scl start hold time is the delay from the falling edge of sda (i2c data) while scl is high (start condition) to the falling edge of scl (i2c clock). scl start hold time = bus period (s) mul scl start hold value the scl stop hold time is the delay from the rising edge of scl (i2c clock) to the rising edge of sda (i2c data) while scl is high (stop condition). scl stop hold time = bus period (s) mul scl stop hold value 50.3.3 i2c control register 1 (i2c x resses: is h ase h oset h is h ase h oset h it rea u rite r reset x iel escritions fiel escrition enale nales oule oeration table continues on the next page... memory map and register descriptions 60 sub-family reference manual, rev. 6, nov 2011 1448 freescale semiconductor, inc. i2c x iel escritions continue fiel escrition isale nale interrut enale nales interrut requests isale nale aster oe select hen the it is chane ro a to a a r sinal is enerate on the us an aster oe is selecte hen this it chanes ro a to a a o sinal is enerate an the oe o oeration chanes ro aster to slae lae oe aster oe ransit oe select elects the irection o aster an slae transers n aster oe this it ust e set accorin to the tye o transer require hereore or aress cycles this it is always set hen aresse as a slae this it ust e set y sotware accorin to the r it in the status reister receie ransit ransit acnowlee enale eciies the alue rien onto the urin ata acnowlee cycles or oth aster an slae receiers he alue o the f it aects eneration n acnowlee sinal is sent to the us on the ollowin i f is cleare or current i f is set receiin yte o acnowlee sinal is sent to the us on the ollowin i f is cleare or current i f is set receiin ata yte o: l is hel low until is written r reeat r ritin a one to this it enerates a reeate r conition roie it is the current aster his it will always e rea as ero ttetin a reeat at the wron tie results in loss o aritration u aeu enale he oule can wae the u ro low ower oe with no eriheral us runnin when slae aress atchin occurs oral oeration o interrut enerate when aress atchin in low ower oe nales the waeu unction in low ower oe enale he it enales or isales the unction table continues on the next page... chapter 0 inter-integrated circuit i2c 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 144 i2c x iel escritions continue fiel escrition ll sinallin isale transer is enale an the ollowin conitions trier the request: hile f a ata yte is receie either aress or ata is transitte autoatic hile f the irst yte receie atches the reister or is eneral call aress any aress atchin occurs an f are set the irection o transer is nown ro aster to slae then it is not require to chec the r ith this assution can also e use in this case n other cases i the aster reas ata ro the slae then it is require to rewrite the reister oeration ith this assution cannot e use hen f an aress or a ata yte is transitte tatus reister x resses: is h ase h oset h is h ase h oset h it rea f u rl r r f r rite wc wc reset x iel escritions fiel escrition f ranser colete la his it sets on the coletion o a yte an acnowlee it transer his it is ali only urin or ieiately ollowin a transer to or ro the oule he f it is cleare y reain the ata reister in receie oe or y writin to the ata reister in transit oe ranser in roress ranser colete resse as a slae his it is set y one o the ollowin conitions: he callin aress atches the rorae slae riary aress in the reister or rane aress in the r reister which ust e set to a nonero alue is set an a eneral call is receie is set an the callin aress atches the secon rorae slae aress lr is set an an us alert resonse aress is receie r is set an an aress is receie that is within the rane etween the alues o the an r reisters his it sets eore the it he u ust chec the r it an set r accorinly ritin the reister with any alue clears this it table continues on the next page... memory map and register descriptions 60 sub-family reference manual, rev. 6, nov 2011 140 freescale semiconductor, inc. i2c x iel escritions continue fiel escrition ot aresse resse as a slae u us usy nicates the status o the us rearless o slae or aster oe his it is set when a r sinal is etecte an cleare when a o sinal is etecte us is ile us is usy rl ritration lost his it is set y harware when the aritration roceure is lost he rl it ust e cleare y sotware y writin a one to it tanar us oeration loss o aritration r rane aress atch his it is set y any o the ollowin conitions: ny nonero callin aress is receie that atches the aress in the r reister he r it is set an the callin aress is within the rane o alues o the an r reisters ritin the reister with any alue clears this it ot aresse resse as a slae r lae reawrite hen aresse as a slae r inicates the alue o the r coan it o the callin aress sent to the aster lae receie aster writin to slae lae transit aster reain ro slae f nterrut la his it sets when an interrut is enin his it ust e cleare y sotware or y writin a to it in the interrut routine one o the ollowin eents can set this it: one yte transer incluin it coletes i f one yte transer excluin it coletes i f n or is sent on the us y writin or to ater this it is set in receie oe atch o slae aress to callin aress incluin riary slae aress rane slae aress alert resonse aress secon slae aress or eneral call aress ritration lost n us oe any tieouts excet l an hih tieouts o interrut enin nterrut enin r receie acnowlee table continues on the next page... chapter 0 inter-integrated circuit i2c 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 141 i2c x iel escritions continue fiel escrition cnowlee sinal was receie ater the coletion o one yte o ata transission on the us o acnowlee sinal etecte ata o reister x resses: is h ase h oset h is h ase h oset h it rea rite reset x iel escritions fiel escrition ata n aster transit oe when ata is written to this reister a ata transer is initiate he ost siniicant it is sent irst n aster receie oe reain this reister initiates receiin o the next yte o ata o: hen ain the transition out o aster receie oe switch the oe eore reain the ata reister to reent an inaertent initiation o a aster receie ata transer n slae oe the sae unctions are aailale ater an aress atch occurs he it ust correctly relect the esire irection o transer in aster an slae oes or the transission to ein for exale i the oule is coniure or aster transit ut a aster receie is esire reain the ata reister oes not initiate the receie reain the ata reister returns the last yte receie while the oule is coniure in aster receie or slae receie oe he ata reister oes not relect eery yte that is transitte on the us an neither can sotware eriy that a yte has een written to the ata reister correctly y reain it ac n aster transit oe the irst yte o ata written to the ata reister ollowin assertion o start it or assertion o r reeate start it is use or the aress transer an ust consist o the callin aress in its concatenate with the require r it in osition it eory a an reister escritions ufaily reerence anual re o freescale eiconuctor nc 50.3.6 i2c control register 2 (i2c x resses: is h ase h oset h is h ase h oset h it rea hr r r : rite reset x iel escritions fiel escrition eneral call aress enale nales eneral call aress isale nale ress extension ontrols the nuer o its use or the slae aress it aress schee it aress schee hr hih rie select ontrols the rie caaility o the as oral rie oe hih rie oe r lae au rate control nales ineenent slae oe au rate at ax requency his orces cloc stretchin on l in ery ast oes he slae au rate ollows the aster au rate an cloc stretchin ay occur lae au rate is ineenent o the aster au rate r rane aress atchin enale his it controls slae aress atchin or aresses etween the alues o the an r reisters hen this it is set a slae aress atch occurs or any aress reater than the alue o the reister an less than or equal to the alue o the r reister rane oe isale o aress atch occurs or an aress within the rane o alues o the an r reisters rane oe enale ress atchin occurs when a slae receies an aress within the rane o alues o the an r reisters : lae aress ontains the uer three its o the slae aress in the it aress schee his iel is ali only when the it is set hater nternterate ircuit ufaily reerence anual re o freescale eiconuctor nc 50.3.7 i2c programmable input glitch filter register (i2c x fl resses: fl is h ase h oset h fl is h ase h oset h it rea fl rite reset x fl iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero resere his reaonly iel is resere an always has the alue ero fl roraale ilter actor ontrols the with o the litch in ters o us cloc cycles that the ilter ust asor for any litch whose sie is less than or equal to this with settin the ilter oes not allow the litch to ass h o ilteryass fh filter litches u to with o n bus cloc cycles, where n 1-1d 0..8 i2c range address register i2c x r resses: r is h ase h oset h r is h ase h oset h it rea r rite reset x r iel escritions fiel escrition r rane slae aress his iel contains the slae aress to e use y the oule he iel is use in the it aress schee ny nonero write enales this reister his reisters use is siilar to that o the reister ut in aition this reister can e consiere a axiu ounary in rane atchin oe resere his reaonly iel is resere an always has the alue ero eory a an reister escritions ufaily reerence anual re o freescale eiconuctor nc 50.3.9 i2c smbus control and status register (i2c x o when the scl and sda signals are held high for a length of time greater than the high timeout period, the shtf1 flag sets. before reaching this threshold, while the system is detecting how long these signals are being held high, a master assumes that the bus is free. however, the shtf1 bit rises in the bus transmission process with the idle bus state. note when the tcksel bit is set, there is no meaning to monitor the shtf1 bit because the bus speed is too high to match the protocol of smbus. addresses: i2c0_smb is 4006_6000h base + 8h offset = 4006_6008h i2c1_smb is 4006_7000h base + 8h offset = 4006_7008h bit 7 6 5 4 3 2 1 0 read fack alerten siicaen tcksel sltf shtf1 shtf2 shtf2ie write w1c w1c reset 0 0 0 0 0 0 0 0 i2c x iel escritions fiel escrition f fast enale for us acet error checin the u ust e ale to issue an or accorin to the result o receiin ata yte n or is sent on the ollowin receiin ata yte ritin to ater receiin a ata yte enerates an ritin to ater receiin a ata yte enerates a lr us alert resonse aress enale nales or isales us alert resonse aress atchin o: ter the host resons to a eice that use the alert resonse aress you ust use sotware to ut the eices aress on the us he alert rotocol is escrie in the us seciication us alert resonse aress atchin is isale us alert resonse aress atchin is enale econ aress enale nales or isales us eice eault aress table continues on the next page... chapter 0 inter-integrated circuit i2c 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 14 i2c x iel escritions continue fiel escrition aress reister atchin is isale aress reister atchin is enale l ieout counter cloc select elects the cloc source o the tieout counter ieout counter counts at the requency o the us cloc ieout counter counts at the requency o the us cloc lf l low tieout la his it is set when the l reister consistin o the lh an ll reisters is loae with a non ero alue loalue an an l low tieout occurs otware clears this it y writin a loic to it o: he low tieout unction is isale when the l reisters alue is ero o low tieout occurs low tieout occurs hf l hih tieout la his reaonly it sets when l an are hel hih ore than cloc loalue which inicates the us is ree his it is cleare autoatically o l hih an hih tieout occurs l hih an hih tieout occurs hf l hih tieout la his it sets when l is hel hih an is hel low ore than cloc loalue otware clears this it y writin a to it o l hih an low tieout occurs l hih an low tieout occurs hf hf interrut enale nales l hih an low tieout interrut hf interrut is isale hf interrut is enale ress reister x resses: is h ase h oset h is h ase h oset h it rea rite reset eory a an reister escritions ufaily reerence anual re o freescale eiconuctor nc i2c x iel escritions fiel escrition us aress ontains the slae aress use y the us his iel is use on the eice eault aress or other relate aresses resere his reaonly iel is resere an always has the alue ero l low ieout reister hih x lh resses: lh is h ase h oset h lh is h ase h oset h it rea l: rite reset x lh iel escritions fiel escrition l: ost siniicant yte o l low tieout alue that eterines the tieout erio o l low l low ieout reister low x ll resses: ll is h ase h oset h ll is h ase h oset h it rea l: rite reset x ll iel escritions fiel escrition l: least siniicant yte o l low tieout alue that eterines the tieout erio o l low hater nternterate ircuit ufaily reerence anual re o freescale eiconuctor nc 50.4 functional description this section provides a comprehensive functional description of the i2c module. 50.4.1 i2c protocol the i2c bus system uses a serial data line (sda) and a serial clock line (scl) for data transfers. all devices connected to it must have open drain or open collector outputs. a logic and function is exercised on both lines with external pull-up resistors. the value of these resistors depends on the system. normally, a standard instance of communication is composed of four parts: 1. start signal 2. slave address transmission 3. data transfer 4. stop signal the stop signal should not be confused with the cpu stop instruction. the following figure illustrates i2c bus system communication. s c l s d a d 0 d a t a b y t e n e w c a l l i n g a d d r e s s x x w r i t e c a l l i n g a d d r e s s w r i t e w r i t e s d a c a l l i n g a d d r e s s r e a d / x x x d 7 d 6 d 5 d 4 d 3 d 2 d 1 a d 6 a d 5 a d 7 a d 4 l s b m s b 1 6 2 5 8 3 4 7 9 1 6 2 5 8 3 4 7 9 l s b m s b 1 6 2 5 8 3 4 7 9 l s b m s b 1 6 2 5 8 3 4 7 9 l s b m s b a d 6 r / w a d 3 a d 2 a d 1 a d 5 a d 7 a d 4 a d 6 r / w a d 3 a d 2 a d 1 a d 5 a d 7 a d 4 r e a d / r e a d / r / w a d 3 a d 2 a d 1 scl 50.4.1.1 start signal the bus is free when no master device is engaging the bus (both scl and sda are high). when the bus is free, a master may initiate communication by sending a start signal. a start signal is defined as a high-to-low transition of sda while scl is high. this signal denotes the beginning of a new data transfer (each data transfer might contain several bytes of data) and brings all slaves out of their idle states. 50.4.1.2 slave address transmission immediately after the start signal, the first byte of a data transfer is the slave address transmitted by the master. this address is a 7-bit calling address followed by an r/ w bit. the r/ w bit tells the slave the desired direction of data transfer. ? 1 = read transfer: the slave transmits data to the master ? 0 = write transfer: the master transmits data to the slave only the slave with a calling address that matches the one transmitted by the master responds by sending an acknowledge bit. the slave sends the acknowledge bit by pulling sda low at the ninth clock. no two slaves in the system can have the same address. if the i2c module is the master, it must not transmit an address that is equal to its own slave address. the i2c module cannot be master and slave at the same time. however, if arbitration is lost during an address cycle, the i2c module reverts to slave mode and operates correctly even if it is being addressed by another master. 50.4.1.3 data transfers when successful slave addressing is achieved, data transfer can proceed on a byte-by- byte basis in the direction specified by the r/ w bit sent by the calling master. all transfers that follow an address cycle are referred to as data transfers, even if they carry subaddress information for the slave device. each data byte is 8 bits long. data may be changed only while scl is low. data must be held stable while scl is high. there is one clock pulse on scl for each data bit, and the msb is transferred first. each data byte is followed by a ninth (acknowledge) bit, which is signaled from the receiving device by pulling sda low at the ninth clock. in summary, one complete data transfer needs nine clock pulses. chapter 50 inter-integrated circuit (i2c) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1459 if the slave receiver does not acknowledge the master in the ninth bit, the slave must leave sda high. the master interprets the failed acknowledgement as an unsuccessful data transfer. if the master receiver does not acknowledge the slave transmitter after a data byte transmission, the slave interprets it as an end to data transfer and releases the sda line. in the case of a failed acknowledgement by either the slave or master, the data transfer is aborted and the master does one of two things: ? relinquishes the bus by generating a stop signal. ? commences a new call by generating a repeated start signal. 50.4.1.4 stop signal the master can terminate the communication by generating a stop signal to free the bus. a stop signal is defined as a low-to-high transition of sda while scl is asserted. the master can generate a stop signal even if the slave has generated an acknowledgement, at which point the slave must release the bus. 50.4.1.5 repeated start signal the master may generate a start signal followed by a calling command without generating a stop signal first. this action is called a repeated start. the master uses a repeated start to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus. 50.4.1.6 arbitration procedure the i2c bus is a true multimaster bus that allows more than one master to be connected on it. if two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock. the bus clock's low period is equal to the longest clock low period, and the high period is equal to the shortest one among the masters. the relative priority of the contending masters is determined by a data arbitration procedure. a bus master loses arbitration if it transmits logic level 1 while another master transmits logic level 0. the losing masters immediately switch to slave receive mode and functional description k60 sub-family reference manual, rev. 6, nov 2011 1460 freescale semiconductor, inc. stop driving sda output. in this case, the transition from master to slave mode does not generate a stop condition. meanwhile, hardware sets a status bit to indicate the loss of arbitration. 50.4.1.7 clock synchronization because wire and logic is performed on scl, a high-to-low transition on scl affects all devices connected on the bus. the devices start counting their low period and, after a device's clock has gone low, that device holds scl low until the clock reaches its high state. however, the change of low to high in this device clock might not change the state of scl if another device clock is still within its low period. therefore, the synchronized clock scl is held low by the device with the longest low period. devices with shorter low periods enter a high wait state during this time (see the following diagram). when all applicable devices have counted off their low period, the synchronized clock scl is released and pulled high. afterward there is no difference between the device clocks and the state of scl, and all devices start counting their high periods. the first device to complete its high period pulls scl low again. s c l 2 s t a r t c o u n t i n g h i g h p e r i o d i n t e r n a l c o u n t e r r e s e t s c l 1 s c l d e l a y the clock synchronization mechanism can be used as a handshake in data transfers. a slave device may hold scl low after completing a single byte transfer (9 bits). in this case, it halts the bus clock and forces the master clock into wait states until the slave releases scl. chapter 50 inter-integrated circuit (i2c) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1461 50.4.1.9 clock stretching the clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. after the master drives scl low, a slave can drive scl low for the required period and then release it. if the slave's scl low period is greater than the master's scl low period, the resulting scl bus signal's low period is stretched. 50.4.1.10 i2c divider and hold values table 50-41. i2c divider and hold values icr (hex) scl divider sda hold value scl hold (start) value scl hold (stop) value icr (hex) scl divider (clocks) sda hold (clocks) scl hold (start) value scl hold (stop) value 00 20 7 6 11 20 160 17 78 81 01 22 7 7 12 21 192 17 94 97 02 24 8 8 13 22 224 33 110 113 03 26 8 9 14 23 256 33 126 129 04 28 9 10 15 24 288 49 142 145 05 30 9 11 16 25 320 49 158 161 06 34 10 13 18 26 384 65 190 193 07 40 10 16 21 27 480 65 238 241 08 28 7 10 15 28 320 33 158 161 09 32 7 12 17 29 384 33 190 193 0a 36 9 14 19 2a 448 65 222 225 0b 40 9 16 21 2b 512 65 254 257 0c 44 11 18 23 2c 576 97 286 289 0d 48 11 20 25 2d 640 97 318 321 0e 56 13 24 29 2e 768 129 382 385 0f 68 13 30 35 2f 960 129 478 481 10 48 9 18 25 30 640 65 318 321 11 56 9 22 29 31 768 65 382 385 12 64 13 26 33 32 896 129 446 449 13 72 13 30 37 33 1024 129 510 513 14 80 17 34 41 34 1152 193 574 577 15 88 17 38 45 35 1280 193 638 641 16 104 21 46 53 36 1536 257 766 769 17 128 21 58 65 37 1920 257 958 961 18 80 9 38 41 38 1280 129 638 641 table continues on the next page... functional description 60 sub-family reference manual, rev. 6, nov 2011 1462 freescale semiconductor, inc. table 50-41. i2c divider and hold values (continued) icr (hex) scl divider sda hold value scl hold (start) value scl hold (stop) value icr (hex) scl divider (clocks) sda hold (clocks) scl hold (start) value scl hold (stop) value 19 96 9 46 49 39 1536 129 766 769 1a 112 17 54 57 3a 1792 257 894 897 1b 128 17 62 65 3b 2048 257 1022 1025 1c 144 25 70 73 3c 2304 385 1150 1153 1d 160 25 78 81 3d 2560 385 1278 1281 1e 192 33 94 97 3e 3072 513 1534 1537 1f 240 33 118 121 3f 3840 513 1918 1921 50.4.2 10-bit address for 10-bit addressing, 0x11110 is used for the first 5 bits of the first address byte. various combinations of read/write formats are possible within a transfer that includes 10-bit addressing. 50.4.2.1 master-transmitter addresses a slave-receiver the transfer direction is not changed. when a 10-bit address follows a start condition, each slave compares the first seven bits of the first byte of the slave address (11110xx) with its own address and tests whether the eighth bit (r/ w direction bit) is 0. it is possible that more than one device finds a match and generates an acknowledge (a1). each slave that finds a match compares the eight bits of the second byte of the slave address with its own address, but only one slave finds a match and generate an acknowledge (a2). the matching slave remains addressed by the master until it receives a stop condition (p) or a repeated start condition (sr) followed by a different slave address. table 50-42. master-transmitter addresses slave-receiver with a 10-bit address s slave addres s first 7 bits 11110 + ad10 + ad9 r/ w 0 a1 slave addres s second byte ad[8:1] a2 data a ... data a/a p chapter 50 inter-integrated circuit (i2c) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1463 after the master-transmitter has sent the first byte of the 10-bit address, the slave-receiver sees an i2c interrupt. user software must ensure that for this interrupt, the contents of the data register are ignored and not treated as valid data. 50.4.2.2 master-receiver addresses a slave-transmitter the transfer direction is changed after the second r/ w bit. up to and including acknowledge bit a2, the procedure is the same as that described for a master-transmitter addressing a slave-receiver. after the repeated start condition (sr), a matching slave remembers that it was addressed before. this slave then checks whether the first seven bits of the first byte of the slave address following sr are the same as they were after the start condition (s), and it tests whether the eighth (r/ w) bit is 1. if there is a match, the slave considers that it has been addressed as a transmitter and generates acknowledge a3. the slave-transmitter remains addressed until it receives a stop condition (p) or a repeated start condition (sr) followed by a different slave address. after a repeated start condition (sr), all other slave devices also compare the first seven bits of the first byte of the slave address with their own addresses and test the eighth (r/ w) bit. however, none of them are addressed because r/ w = 1 (for 10-bit devices), or the 11110xx slave address (for 7-bit devices) does not match. table 50-43. master-receiver addresses a slave-transmitter with a 10-bit address s slave address first 7 bits 11110 + ad10 + ad9 r/ w 0 a1 slave address second byte ad[8:1] a2 sr slave address first 7 bits 11110 + ad10 + ad9 r/ w 1 a3 data a ... data a p after the master-receiver has sent the first byte of the 10-bit address, the slave-transmitter sees an i2c interrupt. user software must ensure that for this interrupt, the contents of the data register are ignored and not treated as valid data. 50.4.3 address matching all received addresses can be requested in 7-bit or 10-bit address format. the address register 1, which contains the i2c primary slave address, always participates in the address matching process. if the gcaen bit is set, general call participates the address matching process. if the alerten bit is set, alert response participates the address matching process. if the siicaen bit is set, the address register 2 participates in the functional description k60 sub-family reference manual, rev. 6, nov 2011 1464 freescale semiconductor, inc. address matching process.if the range address register is programmed to a nonzero value, the range address itself participates in the address matching process. if the rmen bit is set, any address within the range of values of the address register 1 and the range address register participates in the address matching process. the range address register must be programmed to a value greater than the value of the address register 1. when the i2c module responds to one of these addresses, it acts as a slave-receiver and the iaas bit is set after the address cycle. software must read the data register after the first byte transfer to determine that the address is matched. 50.4.4 system management bus specification smbus provides a control bus for system and power management related tasks. a system can use smbus to pass messages to and from devices instead of tripping individual control lines. removing the individual control lines reduces pin count. accepting messages ensures future expandability. with the system management bus, a device can provide manufacturer information, tell the system what its model/part number is, save its state for a suspend event, report different types of errors, accept control parameters, and return its status. 50.4.4.1 timeouts the t timeout,min parameter allows a master or slave to conclude that a defective device is holding the clock low indefinitely or a master is intentionally trying to drive devices off the bus. it is highly recommended that a slave device release the bus (stop driving the bus and let scl and sda float high) when it detects any single clock held low longer than t timeout,min . devices that have detected this condition must reset their communication and be able to receive a new start condition within the timeframe of t timeout,max . smbus defines a clock low timeout, t timeout , of 35 ms, specifies t low:sext as the cumulative clock low extend time for a slave device, and specifies t low:mext as the cumulative clock low extend time for a master device. 50.4.4.1.1 scl low timeout if the scl line is held low by a slave device on the bus, no further communication is possible. furthermore, the master cannot force the scl line high to correct the error condition. to solve this problem, the smbus protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than a timeout value condition. devices that have detected the timeout condition must reset the communication. when chapter 50 inter-integrated circuit (i2c) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1465 the i2c module is an active master, if it detects that smbclk low has exceeded the value of t timeout,min , it must generate a stop condition within or after the current data byte in the transfer process. when the i2c module is a slave, if it detects the t timeout,min condition, it resets its communication and is then able to receive a new start condition. 50.4.4.1.2 scl high timeout when the i2c module has determined that the smbclk and smbdat signals have been high for at least t high:max , it assumes that the bus is idle. a high timeout can occur in two ways: 1. high timeout detected after a stop condition appears on the bus 2. high timeout detected after a start condition, but before a stop condition appears on the bus any master detecting either scenario can assume the bus is free when shtf1 rises. a high timeout occurs in scenario 2 if a master ever detects that both the busy bit is high and shtf1 is high. when the smbdat signal is low and the smbclk signal is high for a period of time, the other kind of timeout occurs. the time period must be defined in software. shtf2 is used as the flag when the time limit is reached. this flag is also an interrupt resource, so it also triggers iicif. 50.4.4.1.3 csmbclk timeout mext and csmbclk timeout sext the following figure illustrates the definition of the timeout intervals t low:sext and t low:mext . when in master mode, the i2c module must not cumulatively extend its clock cycles for a period greater than t low:mext within a byte, where each byte is defined as start-to-ack, ack-to-ack, or ack-to-stop. when csmbclk timeout mext occurs, smbus mext rises and also triggers the sltf. functional description k60 sub-family reference manual, rev. 6, nov 2011 1466 freescale semiconductor, inc. start low:sext t stop low:mext t clkack low:mext t clkack low:mext t scl sda figure 50-40. timeout measurement intervals a master is allowed to abort the transaction in progress to any slave that violates the t low:sext or t timeout,min specifications. to abort the transaction, the master issues a stop condition at the conclusion of the byte transfer in progress. when a slave, the i2c module must not cumulatively extend its clock cycles for a period greater than t low:sext during any message from the initial start to the stop. when csmbclk timeout sext occurs, sext rises and also triggers sltf. note csmbclk timeout sext and csmbclk timeout mext are optional functions that are implemented in the second step. 50.4.4.2 fast ack and nack to improve reliability and communication robustness, implementation of packet error checking (pec) by smbus devices is optional for smbus devices but required for devices participating in and only during the address resolution protocol (arp) process. the pec is a crc-8 error checking byte, calculated on all the message bytes. the pec is appended to the message by the device that supplied the last data byte. if the pec is present but not correct, a nack is issued by the receiver. otherwise an ack is issued. in order to calculate the crc-8 by software, this module can hold the scl line low after receiving the eighth scl (8th bit) if this byte is a data byte. so software can determine whether an ack or nack should be sent to the bus by setting or clearing the txak bit if the fack (fast ack/nack enable) bit is enabled. smbus requires a device always to acknowledge its own address, as a mechanism to detect the presence of a removable device (such as a battery or docking station) on the bus. in addition to indicating a slave device busy condition, smbus uses the nack mechanism to indicate the reception of an invalid command or invalid data. because such a condition may occur on the last byte of the transfer, smbus devices are required to chapter 50 inter-integrated circuit (i2c) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1467 have the ability to generate the not acknowledge after the transfer of each byte and before the completion of the transaction. this requirement is important because smbus does not provide any other resend signaling. this difference in the use of the nack signaling has implications on the specific implementation of the smbus port, especially in devices that handle critical system data such as the smbus host and the sbs components. note in the last byte of master receive slave transmit mode, the master must send a nack to the bus, so fack must be switched off before the last byte transmits. 50.4.5 resets the i2c module is disabled after a reset. the i2c module cannot cause a core reset. 50.4.6 interrupts the i2c module generates an interrupt when any of the events in the following table occur, provided that the iicie bit is set. the interrupt is driven by the iicif bit (of the i2c status register) and masked with the iicie bit (of the i2c control register 1). the iicif bit must be cleared (by software) by writing 1 to it in the interrupt routine. the smbus timeouts interrupt is driven by sltf and masked with the iicie bit. the sltf bit must be cleared by software by writing 1 to it in the interrupt routine. you can determine the interrupt type by reading the status register. note in master receive mode, the fack bit must be set to zero before the last byte transfer. table 50-44. interrupt summary interrupt source status flag local enable complete 1-byte transfer tcf iicif iicie match of received calling address iaas iicif iicie arbitration lost arbl iicif iicie smbus scl low timeout interrupt flag sltf iicif iicie smbus scl high sda low timeout interrupt flag shtf2 iicif iicie & shtf2ie wakeup from stop interrupt iaas iicif iicie & wuen functional description k60 sub-family reference manual, rev. 6, nov 2011 1468 freescale semiconductor, inc. 50.4.6.1 byte transfer interrupt the transfer complete flag (tcf) bit is set at the falling edge of the ninth clock to indicate the completion of a byte and acknowledgement transfer. when fack is enabled, tcf is then set at the falling edge of 8th clock to indicate the completion of byte. 50.4.6.2 address detect interrupt when the calling address matches the programmed slave address (i2c address register) or when the gcaen bit is set and a general call is received, the iaas bit in the status register is set. the cpu is interrupted, provided the iicie bit is set. the cpu must check the srw bit and set its tx mode accordingly. 50.4.6.3 exit from low-power/stop modes the slave receive input detect circuit and address matching feature are still active on low power modes (wait and stop). an asynchronous input matching slave address or general call address brings the cpu out of low power/stop mode if the interrupt is not masked. therefore, tcf and iaas both can trigger this interrupt. 50.4.6.4 arbitration lost interrupt the i2c is a true multimaster bus that allows more than one master to be connected on it. if two or more masters try to control the bus at the same time, the relative priority of the contending masters is determined by a data arbitration procedure. the i2c module asserts the arbitration-lost interrupt when it loses the data arbitration process and the arbl bit in the status register is set. arbitration is lost in the following circumstances: 1. sda is sampled as low when the master drives high during an address or data transmit cycle. 2. sda is sampled as low when the master drives high during the acknowledge bit of a data receive cycle. 3. a start cycle is attempted when the bus is busy. 4. a repeated start cycle is requested in slave mode. 5. a stop condition is detected when the master did not request it. chapter 50 inter-integrated circuit (i2c) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1469 the arbl bit must be cleared (by software) by writing 1 to it. 50.4.6.5 timeout interrupt in smbus when the iicie bit is set, the i2c module asserts a timeout interrupt (outputs sltf and shtf2) upon detection of any of the mentioned timeout conditions, with one exception. the scl high and sda high timeout mechanism must not be used to influence the timeout interrupt output, because this timeout indicates an idle condition on the bus. shtf1 rises when it matches the scl high and sda high timeout and falls automatically just to indicate the bus status. the shtf2's timeout period is the same as that of shtf1, which is short compared to that of sltf, so another control bit, shtf2ie, is added to enable or disable it. 50.4.7 programmable input glitch filter an i2c glitch filter has been added outside legacy i2c modules but within the i2c package. this filter can absorb glitches on the i2c clock and data lines for the i2c module. the width of the glitch to absorb can be specified in terms of the number of (half) bus clock cycles. a single programmable input glitch filter control register is provided. effectively, any down-up-down or up-down-up transition on the data line that occurs within the number of clock cycles programmed in this register is ignored by the i2c module. the programmer must specify the size of the glitch (in terms of bus clock cycles) for the filter to absorb and not pass. scl, sda external signals dff noise suppress circuits scl, sda internal signals dff dff dff figure 50-41. programmable input glitch filter diagram 50.4.8 address matching wakeup when a primary, range, or general call address match occurs when the i2c module is in slave receive mode, the mcu wakes from low power mode with no peripheral bus running. after the address matching iaas bit is set, an interrupt is sent at the end of address matching to wake the core. the iaas bit must be cleared after the clock recovery. functional description k60 sub-family reference manual, rev. 6, nov 2011 1470 freescale semiconductor, inc. note after the system recovers and is in run mode, restart the i2c module if necessary. the scl line is not held low until the i2c module resets after address matching. the main purpose of this feature is to wake the mcu from stop mode. data sent on the bus that is the same as a target device address might also wake the target mcu. 50.4.9 dma support if the dmaen bit is cleared and the iicie bit is set, an interrupt condition generates an interrupt request. if the dmaen bit is set and the iicie bit is set, an interrupt condition generates a dma request instead. dma requests are generated by the transfer complete flag (tcf). if the dmaen bit is set, the only arbitration lost is to another i2c module (error), and scl low timeouts (error) generate cpu interrupts. all other events initiate a dma transfer. note before the last byte of master receive mode, txak must be set to send a nack after the last bytes transfer. therefore, the dma must be disabled before the last bytes transfer. note in 10-bit address mode transmission, the addresses to send occupy 2-3 bytes. during this transfer period, the dma must be disabled because the c1 register is written to send a repeat start or to change the transfer direction. 50.5 initialization/application information module initialization (slave) 1. write: control register 2 ? to enable or disable general call ? to select 10-bit or 7-bit addressing mode 2. write: address register 1 to set the slave address 3. write: control register 1 to enable the i2c module and interrupts 4. initialize ram variables (iicen = 1 and iicie = 1) for transmit data 5. initialize ram variables used to achieve the routine shown in the following figure chapter 50 inter-integrated circuit (i2c) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1471 module initialization (master) 1. write: frequency divider register to set the i2c baud rate (example provided in this chapter) 2. write: control register 1 to enable the i2c module and interrupts 3. initialize ram variables (iicen = 1 and iicie = 1) for transmit data 4. initialize ram variables used to achieve the routine shown in the following figure 5. write: control register 1 to enable tx 6. write: control register 1 to enable mst (master mode) 7. write: data register with the address of the target slave (the lsb of this byte determines whether the communication is master receive or transmit) the routine shown in the following figure can handle both master and slave i2c operations. for slave operation, an incoming i2c message that contains the proper address begins i2c communication. for master operation, communication must be initiated by writing the data register. initialization/application information k60 sub-family reference manual, rev. 6, nov 2011 1472 freescale semiconductor, inc. clear iicif master mode? tx/rx? arbitration lost? iiaas=1? tx/rx? ack from receiver? srw=1? iiaas=1? clear arbl 2nd to last byte to be read? last byte to be read? rxak=0? last byte transmitted? end of address cycle (master rx)? write next byte to data reg set txack generate stop signal (mst=0) write data to data reg set tx mode transmit next byte read data from data reg and store rti switch to rx mode set rx mode switch to rx mode dummy read from data reg generate stop signal (mst=0) read data from data reg and store dummy read from data reg dummy read from data reg n y n n n n n n y y y y y (read) n (write) n y rx tx rx tx y n address transfer see note 1 data transfer see note 2 n y y y notes: 1. if general call is enabled, check to determine if the received address is a general call address (0x00). if the received address is a general call address, the general call must be handled by user software. 2. when 10-bit addressing addresses a slave, the slave sees an interrupt following the first byte of the extended address. ensure that for this interrupt, the contents of the data register are ignored and not treated as a valid data transfer. figure 50-42. typical i2c interrupt routine chapter 50 inter-integrated circuit (i2c) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1473 master mode? tx/rx? arbitration lost? iaas=1? tx/rx? ack from receiver? srw=1? iaas=1? clear arbl 2nd to last byte to be read? last byte to be read? rxak=0? last byte transmitted? end of address cycle (master rx)? write next byte to data reg generate stop signal (mst=0) set txak to proper value clear iicif delay (note 2) delay (note 2) read data from data reg and soft crc transmit next byte rti switch to rx mode switch to rx mode dummy read from data reg generate stop signal (mst=0) read data from data reg and store read data from data reg and store dummy read from data reg n y n n n n n n y y y y y (read) n (write) n y rx tx rx tx y n address transfer see note 1 n y y y sltf or shtf2=1? n y clear iicif fack=1? n y see typical i2c interrupt routine flow chart set txak to proper value clear iicif delay (note 2) set tx mode write data to data reg clear iicif notes: 1. if general call or siicaen is enabled, check to determine if the received address is a general call address (0x00) or an smbus device default address. in either case, they must be handled by user software. 2. in receive mode, one bit time delay may be needed before the first and second data reading. clear iicif delay (note 2) read data from data reg and soft crc set txak to proper value clear iicif delay (note 2) delay (note 2) read data from data reg and soft crc set txack=1 clear fack=0 delay (note 2) read data and soft crc set txak to proper value delay (note 2) figure 50-43. typical i2c smbus interrupt routine initialization/application information k60 sub-family reference manual, rev. 6, nov 2011 1474 freescale semiconductor, inc. chapter 51 universal asynchronous receiver/transmitter (uart) 51.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the uart allows asynchronous serial communication with peripheral devices and cpus. 51.1.1 features the uart includes these distinctive features: ? full-duplex operation ? standard mark/space non-return-to-zero (nrz) format ? selectable irda 1.4 return-to-zero-inverted (rzi) format with programmable pulse widths ? 13-bit baud rate selection with /32 fractional divide, based on module clock frequency ? programmable 8-bit or 9-bit data format ? separately enabled transmitter and receiver ? programmable transmitter output polarity ? programmable receive input polarity ? 13-bit break character option k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1475 ? 11-bit break character detection option ? independent fifo structure for transmit and receive ? two receiver wakeup methods: ? idle line wakeup ? address mark wakeup ? address match feature in receiver to reduce address mark wakeup isr overhead ? ability to select msb or lsb to be first bit on wire ? hardware flow control support for request to send (rts) and clear to send (cts) signals ? support for iso 7816 protocol for interfacing with sim cards and smart cards ? support of t=0 and t=1 protocols ? automatic retransmission of nack'd packets with programmable retry threshold ? support for 11 and 12 etu transfers ? detection of initial packet and automated transfer parameter programming ? interrupt-driven operation with seven iso-7816 specific interrupts ? wait time violated ? character wait time violated ? block wait time violated ? initial frame detected ? transmit error threshold exceeded ? receive error threshold exceeded ? guard time violated ? interrupt-driven operation with 12 flags (not specific to iso-7816 support): ? transmitter data buffer at or below watermark ? transmission complete ? receiver data buffer at or above watermark ? idle receiver input introduction k60 sub-family reference manual, rev. 6, nov 2011 1476 freescale semiconductor, inc. ? receiver data buffer overrun ? receiver data buffer underflow ? transmit data buffer overflow ? noise error ? framing error ? parity error ? active edge on receive pin ? lin break detect ? receiver framing error detection ? hardware parity generation and checking ? 1/16 bit-time noise detection ? dma interface 51.1.2 modes of operation the uart functions the same in all the normal modes. it has two low power modes: wait and stop modes. 51.1.2.1 run mode this is the normal mode of operation. 51.1.2.2 wait mode uart operation in wait mode depends on the state of the c1[uartswai] bit. ? if the c1[uartswai] bit is cleared, the uart operates normally when the cpu is in wait mode. ? if the c1[uartswai] bit is set, uart clock generation ceases and the uart module enters a power-conservation state when the cpu is in wait mode. chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1477 the c1[uartswai] bit does not initiate any power down or power up procedures for the smartcard (iso-7816) interface. setting c1[uartswai] does not affect the state of the c2[re], or c2[te]. if c1[uartswai] is set, any transmission or reception in progress stops at wait mode entry. the transmission or reception resumes when either an internal or external interrupt brings the cpu out of wait mode. exiting wait mode by reset aborts any transmission or reception in progress and resets the uart. 51.1.2.3 stop mode the uart is inactive during stop mode for reduced power consumption. the stop instruction does not affect the uart register states, but the uart module clock will be disabled. the uart operation resumes from where it left off after an external interrupt brings the cpu out of stop mode. exiting stop mode by reset aborts any transmission or reception in progress and resets the uart. entering or leaving stop mode does not initiate any power down or power up procedures for the smartcard (iso-7816) interface. 51.2 uart signal descriptions the uart signals are shown in the following table. table 51-1. uart signal descriptions signal description i/o cts clear to send i rts request to send o rxd receive data i txd transmit data o 51.2.1 detailed signal descriptions the uart detailed signal descriptions are shown in the following table. uart signal descriptions k60 sub-family reference manual, rev. 6, nov 2011 1478 freescale semiconductor, inc. table 51-2. uart?detailed signal descriptions signal i/o description cts i clear to send. indicates whether the uart can start to transmit data when flow control is enabled. state meaning asserteddata transmission can start. negateddata transmission can not start. timing assertionwhen transmitting devices rts asserts. negationwhen transmitting devices rts deasserts. rts o request to send. when driven by the receiver, indicates whether the uart is ready to receive data. when driven by the transmitter, can enable an external transceiver during transmission. state meaning assertedwhen driven by the receiver, ready to receive data. when driven by the transmitter, enable the external transmitter. negatedwhen driven by the receiver, not ready to receive data. when driven by the transmitter, disable the external transmitter. timing assertioncan occur at any time; can assert asynchronously to the other input signals. negationcan occur at any time; can deassert asynchronously to the other input signals. rxd i receive data. serial data input to receiver. state meaning whether rxd is interpreted as a 1 or 0 depends on the bit encoding method along with other configuration settings. timing sampled at a frequency determined by the module clock divided by the baud rate. txd o transmit data. serial data output from transmitter. state meaning whether txd is interpreted as a 1 or 0 depends on the bit encoding method along with other configuration settings. timing driven at the beginning or within a bit time according to the bit encoding method along with other configuration settings. otherwise, transmissions are independent of reception timing. 51.3 memory map and registers this section provides a detailed description of all memory and registers. accessing reserved addresses within the memory map will result in a transfer error. none of the contents of the implemented addresses will be modified as a result of that access. only byte accesses are supported. chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1479 uart memory map absolute address (hex) register name width (in bits) access reset value section/ page 4006_a000 uart baud rate registers:high (uart0_bdh) 8 r/w 00h 51.3.1/ 1487 4006_a001 uart baud rate registers: low (uart0_bdl) 8 r/w 04h 51.3.2/ 1489 4006_a002 uart control register 1 (uart0_c1) 8 r/w 00h 51.3.3/ 1490 4006_a003 uart control register 2 (uart0_c2) 8 r/w 00h 51.3.4/ 1491 4006_a004 uart status register 1 (uart0_s1) 8 r c0h 51.3.5/ 1493 4006_a005 uart status register 2 (uart0_s2) 8 r/w 00h 51.3.6/ 1496 4006_a006 uart control register 3 (uart0_c3) 8 r/w 00h 51.3.7/ 1498 4006_a007 uart data register (uart0_d) 8 r/w 00h 51.3.8/ 1500 4006_a008 uart match address registers 1 (uart0_ma1) 8 r/w 00h 51.3.9/ 1501 4006_a009 uart match address registers 2 (uart0_ma2) 8 r/w 00h 51.3.10/ 1502 4006_a00a uart control register 4 (uart0_c4) 8 r/w 00h 51.3.11/ 1502 4006_a00b uart control register 5 (uart0_c5) 8 r/w 00h 51.3.12/ 1503 4006_a00c uart extended data register (uart0_ed) 8 r 00h 51.3.13/ 1504 4006_a00d uart modem register (uart0_modem) 8 r/w 00h 51.3.14/ 1505 4006_a00e uart infrared register (uart0_ir) 8 r/w 00h 51.3.15/ 1507 4006_a010 uart fifo parameters (uart0_pfifo) 8 r/w see section 51.3.16/ 1508 4006_a011 uart fifo control register (uart0_cfifo) 8 r/w 00h 51.3.17/ 1509 4006_a012 uart fifo status register (uart0_sfifo) 8 r/w c0h 51.3.18/ 1510 4006_a013 uart fifo transmit watermark (uart0_twfifo) 8 r/w 00h 51.3.19/ 1512 4006_a014 uart fifo transmit count (uart0_tcfifo) 8 r 00h 51.3.20/ 1512 table continues on the next page... memory map and registers 60 sub-family reference manual, rev. 6, nov 2011 1480 freescale semiconductor, inc. uart memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4006_a015 uart fifo receive watermark (uart0_rwfifo) 8 r/w 01h 51.3.21/ 1513 4006_a016 uart fifo receive count (uart0_rcfifo) 8 r 00h 51.3.22/ 1514 4006_a018 uart 7816 control register (uart0_c7816) 8 r/w 00h 51.3.23/ 1514 4006_a019 uart 7816 interrupt enable register (uart0_ie7816) 8 r/w 00h 51.3.24/ 1516 4006_a01a uart 7816 interrupt status register (uart0_is7816) 8 r/w 00h 51.3.25/ 1517 4006_a01b uart 7816 wait parameter register (uart0_wp7816t0) 8 r/w 0ah 51.3.26/ 1519 4006_a01b uart 7816 wait parameter register (uart0_wp7816t1) 8 r/w 0ah 51.3.27/ 1520 4006_a01c uart 7816 wait n register (uart0_wn7816) 8 r/w 00h 51.3.28/ 1521 4006_a01d uart 7816 wait fd register (uart0_wf7816) 8 r/w 01h 51.3.29/ 1521 4006_a01e uart 7816 error threshold register (uart0_et7816) 8 r/w 00h 51.3.30/ 1522 4006_a01f uart 7816 transmit length register (uart0_tl7816) 8 r/w 00h 51.3.31/ 1523 4006_b000 uart baud rate registers:high (uart1_bdh) 8 r/w 00h 51.3.1/ 1487 4006_b001 uart baud rate registers: low (uart1_bdl) 8 r/w 04h 51.3.2/ 1489 4006_b002 uart control register 1 (uart1_c1) 8 r/w 00h 51.3.3/ 1490 4006_b003 uart control register 2 (uart1_c2) 8 r/w 00h 51.3.4/ 1491 4006_b004 uart status register 1 (uart1_s1) 8 r c0h 51.3.5/ 1493 4006_b005 uart status register 2 (uart1_s2) 8 r/w 00h 51.3.6/ 1496 4006_b006 uart control register 3 (uart1_c3) 8 r/w 00h 51.3.7/ 1498 4006_b007 uart data register (uart1_d) 8 r/w 00h 51.3.8/ 1500 4006_b008 uart match address registers 1 (uart1_ma1) 8 r/w 00h 51.3.9/ 1501 table continues on the next page... chapter 1 universal asynchronous receivertransmitter uart 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1481 uart memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4006_b009 uart match address registers 2 (uart1_ma2) 8 r/w 00h 51.3.10/ 1502 4006_b00a uart control register 4 (uart1_c4) 8 r/w 00h 51.3.11/ 1502 4006_b00b uart control register 5 (uart1_c5) 8 r/w 00h 51.3.12/ 1503 4006_b00c uart extended data register (uart1_ed) 8 r 00h 51.3.13/ 1504 4006_b00d uart modem register (uart1_modem) 8 r/w 00h 51.3.14/ 1505 4006_b00e uart infrared register (uart1_ir) 8 r/w 00h 51.3.15/ 1507 4006_b010 uart fifo parameters (uart1_pfifo) 8 r/w see section 51.3.16/ 1508 4006_b011 uart fifo control register (uart1_cfifo) 8 r/w 00h 51.3.17/ 1509 4006_b012 uart fifo status register (uart1_sfifo) 8 r/w c0h 51.3.18/ 1510 4006_b013 uart fifo transmit watermark (uart1_twfifo) 8 r/w 00h 51.3.19/ 1512 4006_b014 uart fifo transmit count (uart1_tcfifo) 8 r 00h 51.3.20/ 1512 4006_b015 uart fifo receive watermark (uart1_rwfifo) 8 r/w 01h 51.3.21/ 1513 4006_b016 uart fifo receive count (uart1_rcfifo) 8 r 00h 51.3.22/ 1514 4006_b018 uart 7816 control register (uart1_c7816) 8 r/w 00h 51.3.23/ 1514 4006_b019 uart 7816 interrupt enable register (uart1_ie7816) 8 r/w 00h 51.3.24/ 1516 4006_b01a uart 7816 interrupt status register (uart1_is7816) 8 r/w 00h 51.3.25/ 1517 4006_b01b uart 7816 wait parameter register (uart1_wp7816t0) 8 r/w 0ah 51.3.26/ 1519 4006_b01b uart 7816 wait parameter register (uart1_wp7816t1) 8 r/w 0ah 51.3.27/ 1520 4006_b01c uart 7816 wait n register (uart1_wn7816) 8 r/w 00h 51.3.28/ 1521 4006_b01d uart 7816 wait fd register (uart1_wf7816) 8 r/w 01h 51.3.29/ 1521 table continues on the next page... memory map and registers 60 sub-family reference manual, rev. 6, nov 2011 1482 freescale semiconductor, inc. uart memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4006_b01e uart 7816 error threshold register (uart1_et7816) 8 r/w 00h 51.3.30/ 1522 4006_b01f uart 7816 transmit length register (uart1_tl7816) 8 r/w 00h 51.3.31/ 1523 4006_c000 uart baud rate registers:high (uart2_bdh) 8 r/w 00h 51.3.1/ 1487 4006_c001 uart baud rate registers: low (uart2_bdl) 8 r/w 04h 51.3.2/ 1489 4006_c002 uart control register 1 (uart2_c1) 8 r/w 00h 51.3.3/ 1490 4006_c003 uart control register 2 (uart2_c2) 8 r/w 00h 51.3.4/ 1491 4006_c004 uart status register 1 (uart2_s1) 8 r c0h 51.3.5/ 1493 4006_c005 uart status register 2 (uart2_s2) 8 r/w 00h 51.3.6/ 1496 4006_c006 uart control register 3 (uart2_c3) 8 r/w 00h 51.3.7/ 1498 4006_c007 uart data register (uart2_d) 8 r/w 00h 51.3.8/ 1500 4006_c008 uart match address registers 1 (uart2_ma1) 8 r/w 00h 51.3.9/ 1501 4006_c009 uart match address registers 2 (uart2_ma2) 8 r/w 00h 51.3.10/ 1502 4006_c00a uart control register 4 (uart2_c4) 8 r/w 00h 51.3.11/ 1502 4006_c00b uart control register 5 (uart2_c5) 8 r/w 00h 51.3.12/ 1503 4006_c00c uart extended data register (uart2_ed) 8 r 00h 51.3.13/ 1504 4006_c00d uart modem register (uart2_modem) 8 r/w 00h 51.3.14/ 1505 4006_c00e uart infrared register (uart2_ir) 8 r/w 00h 51.3.15/ 1507 4006_c010 uart fifo parameters (uart2_pfifo) 8 r/w see section 51.3.16/ 1508 4006_c011 uart fifo control register (uart2_cfifo) 8 r/w 00h 51.3.17/ 1509 4006_c012 uart fifo status register (uart2_sfifo) 8 r/w c0h 51.3.18/ 1510 table continues on the next page... chapter 1 universal asynchronous receivertransmitter uart 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 148 uart memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4006_c013 uart fifo transmit watermark (uart2_twfifo) 8 r/w 00h 51.3.19/ 1512 4006_c014 uart fifo transmit count (uart2_tcfifo) 8 r 00h 51.3.20/ 1512 4006_c015 uart fifo receive watermark (uart2_rwfifo) 8 r/w 01h 51.3.21/ 1513 4006_c016 uart fifo receive count (uart2_rcfifo) 8 r 00h 51.3.22/ 1514 4006_c018 uart 7816 control register (uart2_c7816) 8 r/w 00h 51.3.23/ 1514 4006_c019 uart 7816 interrupt enable register (uart2_ie7816) 8 r/w 00h 51.3.24/ 1516 4006_c01a uart 7816 interrupt status register (uart2_is7816) 8 r/w 00h 51.3.25/ 1517 4006_c01b uart 7816 wait parameter register (uart2_wp7816t0) 8 r/w 0ah 51.3.26/ 1519 4006_c01b uart 7816 wait parameter register (uart2_wp7816t1) 8 r/w 0ah 51.3.27/ 1520 4006_c01c uart 7816 wait n register (uart2_wn7816) 8 r/w 00h 51.3.28/ 1521 4006_c01d uart 7816 wait fd register (uart2_wf7816) 8 r/w 01h 51.3.29/ 1521 4006_c01e uart 7816 error threshold register (uart2_et7816) 8 r/w 00h 51.3.30/ 1522 4006_c01f uart 7816 transmit length register (uart2_tl7816) 8 r/w 00h 51.3.31/ 1523 4006_d000 uart baud rate registers:high (uart3_bdh) 8 r/w 00h 51.3.1/ 1487 4006_d001 uart baud rate registers: low (uart3_bdl) 8 r/w 04h 51.3.2/ 1489 4006_d002 uart control register 1 (uart3_c1) 8 r/w 00h 51.3.3/ 1490 4006_d003 uart control register 2 (uart3_c2) 8 r/w 00h 51.3.4/ 1491 4006_d004 uart status register 1 (uart3_s1) 8 r c0h 51.3.5/ 1493 4006_d005 uart status register 2 (uart3_s2) 8 r/w 00h 51.3.6/ 1496 4006_d006 uart control register 3 (uart3_c3) 8 r/w 00h 51.3.7/ 1498 table continues on the next page... memory map and registers 60 sub-family reference manual, rev. 6, nov 2011 1484 freescale semiconductor, inc. uart memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4006_d007 uart data register (uart3_d) 8 r/w 00h 51.3.8/ 1500 4006_d008 uart match address registers 1 (uart3_ma1) 8 r/w 00h 51.3.9/ 1501 4006_d009 uart match address registers 2 (uart3_ma2) 8 r/w 00h 51.3.10/ 1502 4006_d00a uart control register 4 (uart3_c4) 8 r/w 00h 51.3.11/ 1502 4006_d00b uart control register 5 (uart3_c5) 8 r/w 00h 51.3.12/ 1503 4006_d00c uart extended data register (uart3_ed) 8 r 00h 51.3.13/ 1504 4006_d00d uart modem register (uart3_modem) 8 r/w 00h 51.3.14/ 1505 4006_d00e uart infrared register (uart3_ir) 8 r/w 00h 51.3.15/ 1507 4006_d010 uart fifo parameters (uart3_pfifo) 8 r/w see section 51.3.16/ 1508 4006_d011 uart fifo control register (uart3_cfifo) 8 r/w 00h 51.3.17/ 1509 4006_d012 uart fifo status register (uart3_sfifo) 8 r/w c0h 51.3.18/ 1510 4006_d013 uart fifo transmit watermark (uart3_twfifo) 8 r/w 00h 51.3.19/ 1512 4006_d014 uart fifo transmit count (uart3_tcfifo) 8 r 00h 51.3.20/ 1512 4006_d015 uart fifo receive watermark (uart3_rwfifo) 8 r/w 01h 51.3.21/ 1513 4006_d016 uart fifo receive count (uart3_rcfifo) 8 r 00h 51.3.22/ 1514 4006_d018 uart 7816 control register (uart3_c7816) 8 r/w 00h 51.3.23/ 1514 4006_d019 uart 7816 interrupt enable register (uart3_ie7816) 8 r/w 00h 51.3.24/ 1516 4006_d01a uart 7816 interrupt status register (uart3_is7816) 8 r/w 00h 51.3.25/ 1517 4006_d01b uart 7816 wait parameter register (uart3_wp7816t0) 8 r/w 0ah 51.3.26/ 1519 4006_d01b uart 7816 wait parameter register (uart3_wp7816t1) 8 r/w 0ah 51.3.27/ 1520 table continues on the next page... chapter 1 universal asynchronous receivertransmitter uart 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 148 uart memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4006_d01c uart 7816 wait n register (uart3_wn7816) 8 r/w 00h 51.3.28/ 1521 4006_d01d uart 7816 wait fd register (uart3_wf7816) 8 r/w 01h 51.3.29/ 1521 4006_d01e uart 7816 error threshold register (uart3_et7816) 8 r/w 00h 51.3.30/ 1522 4006_d01f uart 7816 transmit length register (uart3_tl7816) 8 r/w 00h 51.3.31/ 1523 400e_a000 uart baud rate registers:high (uart4_bdh) 8 r/w 00h 51.3.1/ 1487 400e_a001 uart baud rate registers: low (uart4_bdl) 8 r/w 04h 51.3.2/ 1489 400e_a002 uart control register 1 (uart4_c1) 8 r/w 00h 51.3.3/ 1490 400e_a003 uart control register 2 (uart4_c2) 8 r/w 00h 51.3.4/ 1491 400e_a004 uart status register 1 (uart4_s1) 8 r c0h 51.3.5/ 1493 400e_a005 uart status register 2 (uart4_s2) 8 r/w 00h 51.3.6/ 1496 400e_a006 uart control register 3 (uart4_c3) 8 r/w 00h 51.3.7/ 1498 400e_a007 uart data register (uart4_d) 8 r/w 00h 51.3.8/ 1500 400e_a008 uart match address registers 1 (uart4_ma1) 8 r/w 00h 51.3.9/ 1501 400e_a009 uart match address registers 2 (uart4_ma2) 8 r/w 00h 51.3.10/ 1502 400e_a00a uart control register 4 (uart4_c4) 8 r/w 00h 51.3.11/ 1502 400e_a00b uart control register 5 (uart4_c5) 8 r/w 00h 51.3.12/ 1503 400e_a00c uart extended data register (uart4_ed) 8 r 00h 51.3.13/ 1504 400e_a00d uart modem register (uart4_modem) 8 r/w 00h 51.3.14/ 1505 400e_a00e uart infrared register (uart4_ir) 8 r/w 00h 51.3.15/ 1507 400e_a010 uart fifo parameters (uart4_pfifo) 8 r/w see section 51.3.16/ 1508 table continues on the next page... memory map and registers 60 sub-family reference manual, rev. 6, nov 2011 1486 freescale semiconductor, inc. uart memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 400e_a011 uart fifo control register (uart4_cfifo) 8 r/w 00h 51.3.17/ 1509 400e_a012 uart fifo status register (uart4_sfifo) 8 r/w c0h 51.3.18/ 1510 400e_a013 uart fifo transmit watermark (uart4_twfifo) 8 r/w 00h 51.3.19/ 1512 400e_a014 uart fifo transmit count (uart4_tcfifo) 8 r 00h 51.3.20/ 1512 400e_a015 uart fifo receive watermark (uart4_rwfifo) 8 r/w 01h 51.3.21/ 1513 400e_a016 uart fifo receive count (uart4_rcfifo) 8 r 00h 51.3.22/ 1514 400e_a018 uart 7816 control register (uart4_c7816) 8 r/w 00h 51.3.23/ 1514 400e_a019 uart 7816 interrupt enable register (uart4_ie7816) 8 r/w 00h 51.3.24/ 1516 400e_a01a uart 7816 interrupt status register (uart4_is7816) 8 r/w 00h 51.3.25/ 1517 400e_a01b uart 7816 wait parameter register (uart4_wp7816t0) 8 r/w 0ah 51.3.26/ 1519 400e_a01b uart 7816 wait parameter register (uart4_wp7816t1) 8 r/w 0ah 51.3.27/ 1520 400e_a01c uart 7816 wait n register (uart4_wn7816) 8 r/w 00h 51.3.28/ 1521 400e_a01d uart 7816 wait fd register (uart4_wf7816) 8 r/w 01h 51.3.29/ 1521 400e_a01e uart 7816 error threshold register (uart4_et7816) 8 r/w 00h 51.3.30/ 1522 400e_a01f uart 7816 transmit length register (uart4_tl7816) 8 r/w 00h 51.3.31/ 1523 51.3.1 uart baud rate registers:high (uart x h this register, along with the bdl register, controls the prescale divisor for uart baud rate generation. to update the 13-bit baud rate setting (sbr[12:0]), first write to bdh to buffer the high half of the new value and then write to bdl. the working value in bdh does not change until bdl is written. bdl is reset to a non-zero value, but after reset the baud rate generator remains disabled until the first time the receiver or transmitter is enabled (c2[re] or c2[te] bits are set). chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1487 addresses: uart0_bdh is 4006_a000h base + 0h offset = 4006_a000h uart1_bdh is 4006_b000h base + 0h offset = 4006_b000h uart2_bdh is 4006_c000h base + 0h offset = 4006_c000h uart3_bdh is 4006_d000h base + 0h offset = 4006_d000h uart4_bdh is 400e_a000h base + 0h offset = 400e_a000h bit 7 6 5 4 3 2 1 0 read lbkdie rxedgie 0 sbr write reset 0 0 0 0 0 0 0 0 uart x h iel escritions fiel escrition l l rea etect nterrut nale l enales the l rea etect la lf to enerate interrut requests ase on the state o l lf interrut requests isale lf interrut requests enale r rx nut ctie e nterrut nale r enales the receie inut actie ee rf to enerate interrut requests harware interruts ro rf isale use ollin rf interrut request enale resere his reaonly iel is resere an always has the alue ero r ur au rate its he au rate or the ur is eterine y these its ee au rate eneration or etails o: he au rate enerator is isale until the it or the r it is set or the irst tie ater resethe au rate enerator is isale when r o: ritin to h has no eect without writin to l since writin to h uts the ata in a teorary location until l is written eory a an reisters ufaily reerence anual re o freescale eiconuctor nc 51.3.2 uart baud rate registers: low (uart x l this register, along with the bdh register, controls the prescale divisor for uart baud rate generation. to update the 13-bit baud rate setting (sbr[12:0]), first write to bdh to buffer the high half of the new value and then write to bdl. the working value in bdh does not change until bdl is written. bdl is reset to a non-zero value, but after reset the baud rate generator remains disabled until the first time the receiver or transmitter is enabled (c2[re] or c2[te] bits are set) addresses: uart0_bdl is 4006_a000h base + 1h offset = 4006_a001h uart1_bdl is 4006_b000h base + 1h offset = 4006_b001h uart2_bdl is 4006_c000h base + 1h offset = 4006_c001h uart3_bdl is 4006_d000h base + 1h offset = 4006_d001h uart4_bdl is 400e_a000h base + 1h offset = 400e_a001h bit 7 6 5 4 3 2 1 0 read sbr write reset 0 0 0 0 0 1 0 0 uart x l iel escritions fiel escrition r ur au rate its he au rate or the ur is eterine y these its ee au rate eneration or etails o: he au rate enerator is isale until the it or the r it is set or the irst tie ater resethe au rate enerator is isale when r o: ritin to h has no eect without writin to l since writin to h uts the ata in a teorary location until l is written o: hen the narrow ulse with is selecte or inrare r the au rate its ust e een the least siniicant it is reer to o reister hater uniersal synchronous receierransitter ur ufaily reerence anual re o freescale eiconuctor nc 51.3.3 uart control register 1 (uart x this read/write register controls various optional features of the uart system. addresses: uart0_c1 is 4006_a000h base + 2h offset = 4006_a002h uart1_c1 is 4006_b000h base + 2h offset = 4006_b002h uart2_c1 is 4006_c000h base + 2h offset = 4006_c002h uart3_c1 is 4006_d000h base + 2h offset = 4006_d002h uart4_c1 is 400e_a000h base + 2h offset = 400e_a002h bit 7 6 5 4 3 2 1 0 read loops uartswai rsrc m wake ilt pe pt write reset 0 0 0 0 0 0 0 0 uart x iel escritions fiel escrition loo loo oe elect hen loo is set the rx in is isconnecte ro the ur an the transitter outut is internally connecte to the receier inuthe transitter an the receier ust e enale to use the loo unction oral oeration loo oe where transitter outut is internally connecte to receier inut he receier inut is eterine y the rr it ur ur tos in ait oe ur cloc continues to run in wait oe ur cloc reees while u is in wait oe rr receier ource elect his it has no eanin or eect unless the loo it is set hen loo is set the rr it eterines the source or the receier shit reister inut elects internal loo ac oe an receier inut is internally connecte to transitter outut inlewire ur oe where the receier inut is connecte to the transit in inut sinal it or it oe elect his it ust e set when is setenale oral start ata its l irst as eterine y f sto use start ata its l irst as eterine y f sto receier aeu etho elect eterines which conition waes the ur: aress ar in the ost siniicant it osition o a receie ata character or an ile conition on the receie in inut sinal leline waeu ressar waeu table continues on the next page... memory map and registers 60 sub-family reference manual, rev. 6, nov 2011 140 freescale semiconductor, inc. uart x iel escritions continue fiel escrition l le line ye elect l eterines when the receier starts countin loic s as ile character its he countin eins either ater a ali start it or ater the sto it the count eins ater the start it then a strin o loic s recein the sto it can cause alse reconition o an ile character einnin the count ater the sto it aois alse ile character reconition ut requires roerly synchronie transissions o: n the case where ur is rorae with l a loic o is autoatically shite ater a receie sto it thus resettin the ile count o: n the case where ur is rorae or l line waeu ru an l has no eect on when the receier starts countin loic s as ile character its n ile line waeu an ile character is reconie at anytie the receier sees or s eenin on the an its le character it count starts ater start it le character it count starts ater sto it arity nale nales the arity unction hen arity is enale arity unction inserts a arity it in the it osition ieiately recein the sto it his it ust e set when is setenale arity unction isale arity unction enale arity ye eterines whether the ur enerates an checs or een arity or o arity ith een arity an een nuer o s clears the arity it an an o nuer o s sets the arity it ith o arity an o nuer o s clears the arity it an an een nuer o s sets the arity ithis it ust e cleare when is setenale en arity o arity ur ontrol reister ur x this register can be read or written at any time. addresses: uart0_c2 is 4006_a000h base + 3h offset = 4006_a003h uart1_c2 is 4006_b000h base + 3h offset = 4006_b003h uart2_c2 is 4006_c000h base + 3h offset = 4006_c003h uart3_c2 is 4006_d000h base + 3h offset = 4006_d003h uart4_c2 is 400e_a000h base + 3h offset = 400e_a003h bit 7 6 5 4 3 2 1 0 read tie tcie rie ilie te re rwu sbk write reset 0 0 0 0 0 0 0 0 chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1491 uart x iel escritions fiel escrition ransitter nterrut or ranser nale enales the r la to enerate interrut requests or transer requests ase on the state o o: an are oth set then ust e cleare an ust not e written outsie o sericin o a request r interrut an transer requests isale r interrut or transer requests enale ransission olete nterrut nale enales the transission colete la to enerate interrut requests interrut requests isale interrut requests enale r receier full nterrut or ranser nale r enales the rrf la to enerate interrut requests or transer requests ase on the state o r rrf interrut an transer requests isale rrf interrut or transer requests enale l le line nterrut nale l enales the ile line la l to enerate interrut requests ase on the state o l l interrut requests isale l interrut requests enale ransitter nale enales the ur transitterhe it can e use to queue an ile reale y clearin an then settin the it hen is setenale an this it is autoatically cleare ater the requeste loc has een transitte his conition is etecte when ll an our aitional characters hae een transitte ransitter o ransitter on r receier nale r enales the ur receier receier o receier on ru receier aeu ontrol his it can e set to lace the ur receier in a stany state ru autoatically clears when an ru eent occurs an l eent when is clear or an aress atch when is set his it ust e cleare when is set table continues on the next page... memory map and registers 60 sub-family reference manual, rev. 6, nov 2011 142 freescale semiconductor, inc. uart x iel escritions continue fiel escrition o: ru shoul only e set with waeu on ile i the channel is currently not ile his can e eterine y the rf la set to wae u an l eent an the channel is alreay ile it is ossile that the ur will iscar ata since ata ust e receie or a l rea etect ater an l is etecte eore l is allowe to reasserte oral oeration ru enales the waeu unction an inhiits urther receier interrut requests orally harware waes the receier y autoatically clearin ru en rea olin sens one rea character or loic s i r is cleare or loic s i r is set ee ransittin rea characters or the nuer o loic s or the ierent coniurations olin ilies clearin the it eore the rea character has inishe transittin s lon as is set the transitter continues to sen colete rea characters or its or or itshis it ust e cleare when is set oral transitter oeration ueue rea characters to e sent ur tatus reister ur x the s1 register provides inputs to the mcu for generation of uart interrupts or dma requests. this register can also be polled by the mcu to check the status of these bits. to clear a flag, the status register should be read followed by a read or write (depending on interrupt flag type) to the uart data register. other instructions can be executed between the two steps as long as it does not compromise the handling of i/o, but the order of operations is important for flag clearing. when a flag is configured to trigger a dma request, assertion of the associated dma done signal from the dma controller, clears the flag. note if the condition that results in the assertion of the flag, interrupt or dma request is not resolved prior to clearing the flag, the flag (and interrupt/dma request) will reassert. for example, if the dma or interrupt service routine failed to write sufficient data to the transmit buffer to raise it above the watermark level, the flag will reassert and generate another interrupt or dma request. note reading an empty data register to clear one of these flags causes the fifo pointers to get out of alignment. a receive fifo flush reinitializes the pointers. chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1493 addresses: uart0_s1 is 4006_a000h base + 4h offset = 4006_a004h uart1_s1 is 4006_b000h base + 4h offset = 4006_b004h uart2_s1 is 4006_c000h base + 4h offset = 4006_c004h uart3_s1 is 4006_d000h base + 4h offset = 4006_d004h uart4_s1 is 400e_a000h base + 4h offset = 400e_a004h bit 7 6 5 4 3 2 1 0 read tdre tc rdrf idle or nf fe pf write reset 1 1 0 0 0 0 0 0 uart x iel escritions fiel escrition r ransit ata reister ty fla r will set when the nuer o atawors in the transit uer an is equal to or less than the nuer inicate y ffor character that is in the rocess o ein transitte is not inclue in the count o clear r rea when r is set an then write to the ur ata reister for ore eicient interrut sericin all ata excet the inal alue to e written to the uer shoul written to hen can e rea eore writin the inal ata alue resultin in the clearin o the r la his is ore eicient since the r will reassert until the waterar has een exceee so attetin to clear the r eery write will e ineectie until suicient ata has een written he aount o ata in the transit uer is reater than the alue inicate y ffor he aount o ata in the transit uer is less than or equal to the alue inicate y ffor at soe oint in tie since the la has een cleare ransit olete fla is cleare when there is a transission in roress or when a reale or rea character is loae is set when the transit uer is ety an no ata reale or rea character is ein transitte hen is set the transit ata outut sinal ecoes ile loic hen is set enale this it is set ater any sinal has een receie ut rior to any corresonin uar ties exirin is cleare y reain with set an then oin one o the ollowin: ritin to the ur ata reister to transit new ata ueuin a reale y clearin an then settin the it ueuin a rea character y writin to in ransitter actie senin ata a reale or a rea ransitter ile transission actiity colete rrf receie ata reister full fla rrf is set when the nuer o atawors in the receie uer is equal to or ore than the nuer inicate y rfforr atawor that is in the rocess o ein receie is not inclue in the count rrf is reente ro settin while l is set itionally when l is set atawors that are receie will e store in the receie uer ut will oerwrite each other o clear rrf rea when rrf is set an then rea the ur ata reister for ore eicient interrut an oeration all ata excet the inal alue is to e rea ro the uer usin he shoul then e rea an the inal ata alue rea resultin in the clearin o the rrf la en i the rrf la is set ata will continue to e receie until an oerrun conition occurs table continues on the next page... memory map and registers 60 sub-family reference manual, rev. 6, nov 2011 144 freescale semiconductor, inc. uart x iel escritions continue fiel escrition he nuer o atawors in the receie uer is less than the nuer inicate y rr he nuer o atawors in the receie uer is equal to or reater than the nuer inicate y rr at soe oint in tie since this la was last cleare l le line fla l is set when consecutie loic s i consecutie loic s i an or consecutie loic s i an aear on the receier inut ter the l la is cleare a rae ust e receie althouh not necessarily store in the ata uer or exale i ru is set or a l rea character ust set the lf la eore an ile conition can set the l la o clear l rea ur status with l set an then rea le etection is not suorte when is setenale an hence this la is inore o: hen the receier waeu it ru is set an is cleare an ile line conition sets the l la i ru is set else the l la oes not et set receier inut is either actie now or has neer ecoe actie since the l la was last cleare receier inut has ecoe ile or the la has not een cleare since it last asserte or receier oerrun fla or is set when sotware ails to reent the receie ata reister ro oerlowin with ata he or it is set ieiately ater the sto it has een coletely receie or the atawor that oerlows the uer an all the other error las ff an f are reente ro settin he ata in the shit reister is lost ut the ata alreay in the ur ata reisters is not aecte the or la is set no ata will e store in the ata uer een i suicient roo exists itionally while the or la is set the rrf la an l las will e loce ro assertin ie transition ro an inactie to an actie state o clear or rea when or is set an then rea ur ata reister l is enale an a l rea is etecte the or it will assert i the lf la is not cleare eore the next ata character is receieee oerrun or la ilications or ore etails rearin the oeration o the or it n oe it is ossile to coniure a to e returne y rorain the o it o oerrun has occurre since the last tie the la was cleare oerrun has occurre or the oerrun la has not een cleare since the last oerrun occure f oise fla f is set when the ur etects noise on the receier inut f it oes not et set in the case o an oerrun or while the l rea etect eature is enale l hen f is set it only inicates that a atawor has een receie with noise since the last tie it was cleare here is no uarantee that the irst atawor rea ro the receie uer has noise or that there is only one atawor in the uer that was receie with noise unless the receie uer has a eth o one o clear f rea an then rea the ur ata reister o noise etecte since the last tie this la was cleare the receie uer has a eth reater than then there ay e ata in the receier uer that was receie with noise t least one atawor was receie with noise etecte since the last tie the la was cleare f frain rror fla f is set when a loic is accete as the sto it f it oes not set in the case o an oerrun or while the l rea etect eature is enale l f inhiits urther ata recetion until it is cleare o clear f rea with f set an then rea the ur ata reister he last ata in the receie uer reresents the ata that was receie with the rae error enale howeer rain errors are not suorte when is setenale howeer i this la is set ata will still not e receie in oe table continues on the next page... chapter 1 universal asynchronous receivertransmitter uart 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 14 uart x iel escritions continue fiel escrition o rain error etecte frain error f arity rror fla f is set when is set l is isale an the arity o the receie ata oes not atch its arity it he f is not set in the case o an oerrun conition hen the f it is set it only inicates that a atawor was receie with arity error since the last tie it was cleare here is no uarantee that the irst atawor rea ro the receie uer has a arity error or that there is only one atawor in the uer that was receie with a arity error unless the receie uer was a eth o one o clear f rea an then rea the ur ata reister ithin the receie uer structure the receie atawor is tae i it was receie with a arity error hat inoration is aailale y reain the reister rior to reain the reister o arity error has een etecte since the last tie this la was cleare the receie uer has a eth reater than then there ay e ata in the receie uer what was receie with a arity error t least one atawor was receie with a arity error since the last tie this la was cleare ur tatus reister ur x the s2 register provides inputs to the mcu for generation of uart interrupts or dma requests. also, this register can be polled by the mcu to check the status of these bits. this register can be read or written at any time, with the exception of the msbf and rxinv bits which should only be changed by the user between transmit and receive packets. addresses: uart0_s2 is 4006_a000h base + 5h offset = 4006_a005h uart1_s2 is 4006_b000h base + 5h offset = 4006_b005h uart2_s2 is 4006_c000h base + 5h offset = 4006_c005h uart3_s2 is 4006_d000h base + 5h offset = 4006_d005h uart4_s2 is 400e_a000h base + 5h offset = 400e_a005h bit 7 6 5 4 3 2 1 0 read lbkdif rxedgif msbf rxinv rwuid brk13 lbkde raf write reset 0 0 0 0 0 0 0 0 uart x iel escritions fiel escrition lf l rea etect nterrut fla lf is set when l is set an a l rea character is etecte when consecutie loic s i or consecutie loic s i aear on the receier inut lf is set riht ater receiin the last l rea character it lf is cleare y writin a to it table continues on the next page... memory map and registers 60 sub-family reference manual, rev. 6, nov 2011 146 freescale semiconductor, inc. uart x iel escritions continue fiel escrition o l rea character has een etecte l rea character has een etecte rf rx in ctie e nterrut fla rf is set when an actie ee allin i r risin i r on the rx in occurs rf is cleare y writin a to it ee rf escrition or aitional etails o: he actie ee is only etecte when in two wire oe an on receie ata coin ro the rx in o actie ee on the receie in has occurre n actie ee on the receie in has occurre f ost iniicant it first ettin this it reerses the orer o the its that are transitte an receie on the wire his it oes not aect the olarity o the its the location o the arity it or the location o the start or sto itshis it is autoatically set or cleare when an o are enale an an initial character is etecte l it is the irst it that is transitte ollowin the start it further the irst it receie ater the start it is ientiie as it it it or it is the irst it that is transitte ollowin the start it eenin on the settin o an further the irst it receie ater the start it is ientiie as it it or it eenin on the settin o an r receie ata nersion ettin this it reerses the olarity o the receie ata inut n r orat a one is reresente y a ar an a ero is reresente y a sace or noral olarity an the oosite or inerte olarity n r orat a ero is reresente y short hih ulse in the ile o a it tie reainin ile low or a one or noral olarity an a ero is reresente y short low ulse in the ile o a it tie reainin ile hih or a one or inerte olarityhis it is autoatically set or cleare when an o are enale an an initial character is etecte o: ettin r inerts the rx inut or: ata its start an sto its rea an ile hen o is setenale then only the ata its an the arity it are inerte receie ata is not inerte receie ata is inerte ru receie aeu le etect hen ru is set an is cleare this it controls whether the ile character that waes the receier sets the l ithis it ust e cleare when o is setenale he l it is not set uon etection o an ile character he l it is set uon etection o an ile character r rea ransit haracter lenth his it eterines whether the transit rea character is or its lon or or its lon reer to ransittin rea characters or the lenth o the rea character or the ierent coniurations he etection o a rain error is not aecte y this it rea character is or its lon rea character is or its lon table continues on the next page... chapter 1 universal asynchronous receivertransmitter uart 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 147 uart x iel escritions continue fiel escrition l l rea etection nale l selects a loner rea character etection lenth hile l is set the rrf f f an f las are reente ro settin hen l is set see oerrun oeration he l it ust e cleare when o is set rea character is etecte at lenth o it ties an or an rea character is etecte at lenth o its ties i or its tie i rf receier ctie fla rf is set when the ur receier etects a loic urin the r tie erio o the start it search rf is cleare when the receier etects an ile character when o is cleareisale hen o is enale the rf is cleare i the exires or the exires o: n the case when o is set an it is ossile to coniure the uar tie to e howeer in the eent that a is require to e transitte the ata transer actually taes u with the th u slot ein a inactie uer hence in this situation the rf ay eassert one u rior to actually ein inactie ur receier ileinactie waitin or a start it ur receier actie rx inut not ile ur ontrol reister ur x writing to r8 bit does not have any effect. the txdir and txinv bits can only be changed between transmit and receive packets. addresses: uart0_c3 is 4006_a000h base + 6h offset = 4006_a006h uart1_c3 is 4006_b000h base + 6h offset = 4006_b006h uart2_c3 is 4006_c000h base + 6h offset = 4006_c006h uart3_c3 is 4006_d000h base + 6h offset = 4006_d006h uart4_c3 is 400e_a000h base + 6h offset = 400e_a006h bit 7 6 5 4 3 2 1 0 read r8 t8 txdir txinv orie neie feie peie write reset 0 0 0 0 0 0 0 0 uart x iel escritions fiel escrition r receie it r is the ninth ata it receie when the ur is coniure or it ata orat or table continues on the next page... memory map and registers 60 sub-family reference manual, rev. 6, nov 2011 148 freescale semiconductor, inc. uart x iel escritions continue fiel escrition ransit it is the ninth ata it transitte when the ur is coniure or it ata orat or o: the alue o is the sae as in the reious transission oes not hae to e rewritten he sae alue is transitte until is rewritten r ransitter in ata irection in inleire oe his it eterines whether the in is use as an inut or outut in the sinlewire oe o oeration his it is releant only to the sinlewire oe hen o is setenale an this it is autoatically cleare ater the requeste loc has een transitte his conition is etecte when ll an aitional characters hae een transitte itionally i o is setenale an an a is ein transitte the harware will autoatically oerrie this it as neee n this situation r will not relect the teorary state associate with the in is an inut in sinlewire oe in is an outut in sinlewire oe ransit ata nersion ettin this it reerses the olarity o the transitte ata outut n r orat a one is reresente y a ar an a ero is reresente y a sace or noral olarity an the oosite or inerte olarity n r orat a ero is reresente y short hih ulse in the ile o a it tie reainin ile low or a one or noral olarity an a ero is reresente y short low ulse in the ile o a it tie reainin ile hih or a one or inerte olarity his it is autoatically set or cleare when an o are enale an an initial character is etecte o: ettin inerts all transitte alues incluin ile rea start an sto its n loo oe i is set the receier ets the transit inersion it when r is isalehen o is setenale then only the transitte ata its an arity it are inerte ransit ata is not inerte ransit ata is inerte or oerrun rror nterrut nale his it enales the oerrun error la or to enerate interrut requests or interruts are isale or interrut requests are enale oise rror nterrut nale his it enales the noise la f to enerate interrut requests f interrut requests are isale f interrut requests are enale f frain rror nterrut nale his it enales the rain error la f to enerate interrut requests f interrut requests are isale f interrut requests are enale table continues on the next page... chapter 1 universal asynchronous receivertransmitter uart 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 14 uart x iel escritions continue fiel escrition arity rror nterrut nale his it enales the arity error la f to enerate interrut requests f interrut requests are isale f interrut requests are enale ur ata reister ur x this register is actually two separate registers. reads return the contents of the read-only receive data register and writes go to the write-only transmit data register. note in 8-bit or 9-bit data format, only uart data register (d) needs to be accessed in order to clear the s1[rdrf] bit (assuming receiver buffer level is less than rwfifo[rxwater]). the c3 register only needs to be read (prior to the d register) if the ninth bit of data needs to be captured. likewise the ed register only needs to be read (prior to the d register) if the additional flag data for the dataword needs to be captured. note in the normal 8-bit mode (m bit cleared) if the parity is enabled, you get seven data bits and one parity bit. that one parity bit will be loaded into the d register. so if you care about only the data bits, you have to mask off the parity bit from the value you read out of this register. note when transmitting in 9-bit data format and using 8-bit write instructions, write first to transmit bit 8 in uart control register 3 (c3[t8]), then d. a write to c3[t8] stores the data in a temporary register. if d register is written first then the new data on data bus is stored in d register, while the temporary value (written by last write to c3[t8]) gets stored in c3[t8] register. memory map and registers k60 sub-family reference manual, rev. 6, nov 2011 1500 freescale semiconductor, inc. addresses: uart0_d is 4006_a000h base + 7h offset = 4006_a007h uart1_d is 4006_b000h base + 7h offset = 4006_b007h uart2_d is 4006_c000h base + 7h offset = 4006_c007h uart3_d is 4006_d000h base + 7h offset = 4006_d007h uart4_d is 400e_a000h base + 7h offset = 400e_a007h bit 7 6 5 4 3 2 1 0 read rt write reset 0 0 0 0 0 0 0 0 uart x iel escritions fiel escrition r reas return the contents o the reaonly receie ata reister an writes o to the writeonly transit ata reister ur atch ress reisters ur x the ma1 and ma2 registers are compared to input data addresses when the most significant bit is set and the associated c4[maen] bit is set. if a match occurs, the following data is transferred to the data register. if a match fails, the following data is discarded. these registers can be read and written at anytime. addresses: uart0_ma1 is 4006_a000h base + 8h offset = 4006_a008h uart1_ma1 is 4006_b000h base + 8h offset = 4006_b008h uart2_ma1 is 4006_c000h base + 8h offset = 4006_c008h uart3_ma1 is 4006_d000h base + 8h offset = 4006_d008h uart4_ma1 is 400e_a000h base + 8h offset = 400e_a008h bit 7 6 5 4 3 2 1 0 read ma write reset 0 0 0 0 0 0 0 0 uart x iel escritions fiel escrition atch ress hater uniersal synchronous receierransitter ur ufaily reerence anual re o freescale eiconuctor nc 51.3.10 uart match address registers 2 (uart x these registers can be read and written at anytime. the ma1 and ma2 registers are compared to input data addresses when the most significant bit is set and the associated c4[maen] bit is set. if a match occurs, the following data is transferred to the data register. if a match fails, the following data is discarded. addresses: uart0_ma2 is 4006_a000h base + 9h offset = 4006_a009h uart1_ma2 is 4006_b000h base + 9h offset = 4006_b009h uart2_ma2 is 4006_c000h base + 9h offset = 4006_c009h uart3_ma2 is 4006_d000h base + 9h offset = 4006_d009h uart4_ma2 is 400e_a000h base + 9h offset = 400e_a009h bit 7 6 5 4 3 2 1 0 read ma write reset 0 0 0 0 0 0 0 0 uart x iel escritions fiel escrition atch ress ur ontrol reister ur x resses: ur is h ase h oset h ur is h ase h oset h ur is h ase h oset h ur is h ase h oset h ur is h ase h oset h it rea rf rite reset ur x iel escritions fiel escrition atch ress oe nale reer to atch aress oeration or ore inoration table continues on the next page... memory map and registers 60 sub-family reference manual, rev. 6, nov 2011 102 freescale semiconductor, inc. uart x iel escritions continue fiel escrition ll ata receie is transerre to the ata uer i is cleare ll ata receie with the ost siniicant it cleare is iscare ll ata receie with the ost siniicant it set is coare with contents o reister no atch occurs the ata is iscare atch occurs ata is transerre to the ata uerhis it ust e cleare when o is setenale atch ress oe nale reer to atch aress oeration or ore inoration ll ata receie is transerre to the ata uer i is cleare ll ata receie with the ost siniicant it cleare is iscare ll ata receie with the ost siniicant it set is coare with contents o reister no atch occurs the ata is iscare atch occurs ata is transerre to the ata uerhis it ust e cleare when o is setenale it oe select he it causes a tenth noneory ae it to e art o the serial transission his tenth it is enerate an interrete as a arity it he it oes not aect the l sen or etect rea ehaior is set then oth an its ust also e set his it ust e cleare when o is setenale reer to ata orat non o or ore inoration he arity it is the ninth it in the serial transission he arity it is the tenth it in the serial transission rf au rate fine ust his it iel is use to a ore tiin resolution to the aerae au requency in increents o reer to au rate eneration or ore inoration ur ontrol reister ur x resses: ur is h ase h oset h ur is h ase h oset h ur is h ase h oset h ur is h ase h oset h ur is h ase h oset h it rea r rite reset ur x iel escritions fiel escrition ransitter elect table continues on the next page... chapter 1 universal asynchronous receivertransmitter uart 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 10 uart x iel escritions continue fiel escrition coniures the transit ata reister ety la r to enerate interrut or requests i is set o: is cleare r an r interrut request sinals are not asserte when the r la is set rearless o the state o o: an are oth set then ust e cleare an reister ust not e written outsie o sericin o a request is set an the r la is set the r interrut request sinal is asserte to request interrut serice is set an the r la is set the r request sinal is asserte to request a transer resere his reaonly iel is resere an always has the alue ero r receier full elect r coniures the receier ata reister ull la rrf to enerate interrut or requests i r is set o: r is cleare the rrf an rfr interrut request sinals are not asserte when the rrf la is set rearless o the state o r r is set an the rrf la is set the rfr interrut request sinal is asserte to request interrut serice r is set an the rrf la is set the rrf request sinal is asserte to request a transer resere his reaonly iel is resere an always has the alue ero ur xtene ata reister ur x this register contains additional information flags that are stored with a received dataword. this register may be read at any time but only contains valid data if there is a dataword in the receive fifo. note the data contained in this register represents additional information regarding the conditions on which a dataword was received. the importance of this data varies with application, and in some cases maybe completely optional. these fields automatically update to reflect the conditions of the next dataword whenever d is read. memory map and registers k60 sub-family reference manual, rev. 6, nov 2011 1504 freescale semiconductor, inc. note if the s1[nf] and s1[pf] flags have not been set since the last time the receive buffer was empty, the noisy and paritye bits will be zero. addresses: uart0_ed is 4006_a000h base + ch offset = 4006_a00ch uart1_ed is 4006_b000h base + ch offset = 4006_b00ch uart2_ed is 4006_c000h base + ch offset = 4006_c00ch uart3_ed is 4006_d000h base + ch offset = 4006_d00ch uart4_ed is 400e_a000h base + ch offset = 400e_a00ch bit 7 6 5 4 3 2 1 0 read noisy paritye 0 write reset 0 0 0 0 0 0 0 0 uart x iel escritions fiel escrition o he current receie atawor containe in an r was receie with noise he atawor was receie without noise he ata was receie with noise r he current receie atawor containe in an r was receie with a arity error he atawor was receie without a arity error he atawor was receie with a arity error resere his reaonly iel is resere an always has the alue ero ur oe reister ur x o the modem register controls options for setting the modem configuration. note rxrtse, txrtspol, txrtse and txctse must all be cleared when c7816[iso7816en] is enabled. this will cause the rts to deassert during iso-7816 wait times. the iso-7816 protocol does not make use of the rts and cts signals. chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1505 addresses: uart0_modem is 4006_a000h base + dh offset = 4006_a00dh uart1_modem is 4006_b000h base + dh offset = 4006_b00dh uart2_modem is 4006_c000h base + dh offset = 4006_c00dh uart3_modem is 4006_d000h base + dh offset = 4006_d00dh uart4_modem is 400e_a000h base + dh offset = 400e_a00dh bit 7 6 5 4 3 2 1 0 read 0 rxrtse txrtspol txrtse txctse write reset 0 0 0 0 0 0 0 0 uart x o iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero rr receier requesttosen enale llows the r outut to control the inut o the transittin eice to reent receier oerrun o: o not set oth rr an r he receier has no eect on r r is easserte i the nuer o characters in the receier ata reister ffo is equal to or reater than rfforr r is asserte when the nuer o characters in the receier ata reister ffo is less than rfforr rol ransitter requesttosen olarity ontrols the olarity o the transitter r rol oes not aect the olarity o the receier r r will reain neate in the actie low state unless r is set ransitter r is actie low ransitter r is actie hih r ransitter requesttosen enale ontrols r eore an ater a transission he transitter has no eect on r hen a character is lace into an ety transitter ata uerffo r asserts one it tie eore the start it is transitte r easserts one it tie ater all characters in the transitter ata uerffo an shit reister are coletely sent incluin the last sto it ransitter cleartosen enale controls the oeration o the transitter can e set ineenently ro the state o r an rr has no eect on the transitter nales cleartosen oeration he transitter checs the state o each tie it is reay to sen a character is asserte the character is sent is easserte the sinal reains in the ar state an transission is elaye until is asserte hanes in as a character is ein sent o not aect its transission eory a an reisters ufaily reerence anual re o freescale eiconuctor nc 51.3.15 uart infrared register (uart x r the ir register controls options for setting the infrared configuration. addresses: uart0_ir is 4006_a000h base + eh offset = 4006_a00eh uart1_ir is 4006_b000h base + eh offset = 4006_b00eh uart2_ir is 4006_c000h base + eh offset = 4006_c00eh uart3_ir is 4006_d000h base + eh offset = 4006_d00eh uart4_ir is 400e_a000h base + eh offset = 400e_a00eh bit 7 6 5 4 3 2 1 0 read 0 iren tnp write reset 0 0 0 0 0 0 0 0 uart x r iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero r nrare enale his it enalesisales the inrare oulationeoulation r isale r enale ransitter narrow ulse hese its enale whether the ur transits a or narrow ulse hater uniersal synchronous receierransitter ur ufaily reerence anual re o freescale eiconuctor nc 51.3.16 uart fifo parameters (uart x ffo this register provides the ability for the programmer to turn on and off fifo functionality. it also provides the size of the fifo that has been implemented. this register may be read at any time. this register should only be written when the c2[re] and c2[te] bits are cleared / not set and when the data buffer/fifo is empty. addresses: uart0_pfifo is 4006_a000h base + 10h offset = 4006_a010h uart1_pfifo is 4006_b000h base + 10h offset = 4006_b010h uart2_pfifo is 4006_c000h base + 10h offset = 4006_c010h uart3_pfifo is 4006_d000h base + 10h offset = 4006_d010h uart4_pfifo is 400e_a000h base + 10h offset = 400e_a010h bit 7 6 5 4 3 2 1 0 read txfe txfifosize rxfe rxfifosize write reset 0 * * * 0 * * * * notes: txfifosize bitfield: the reset value depends on whether the specific uart instance supports the fifo and on the size of that fifo. see the chip configuration details for more information on the fifo size supported for each uart instance. rxfifosize bitfield: the reset value depends on whether the specific uart instance supports the fifo and on the size of that fifo. see the chip configuration details for more information on the fifo size supported for each uart instance. uart x ffo iel escritions fiel escrition f ransit ffo nale hen this it is set the uilt in ffo structure or the transit uer is enale he sie o the ffo structure is inicate y the ffo iel this it is not set then the transit uer oerates as a ffo o eth one atawor rearless o the alue in ffo oth an r ust e cleare rior to chanin this it itionally fluh an rfluh coans shoul e issue ieiately ater chanin this it ransit ffo is not enale uer is eth leacy suort ransit ffo is enale uer is eth inicte y ffo ffo ransit ffo uer eth he axiu nuer o transit atawors that can e store in the transit uer his iel is rea only ransit ffouer eth atawor ransit ffouer eth atawors ransit ffouer eth atawors ransit ffouer eth atawors ransit ffouer eth atawors table continues on the next page... memory map and registers 60 sub-family reference manual, rev. 6, nov 2011 108 freescale semiconductor, inc. uart x ffo iel escritions continue fiel escrition ransit ffouer eth atawors ransit ffouer eth atawors resere rf receie ffo nale hen this it is set the uilt in ffo structure or the receie uer is enale he sie o the ffo structure is inicate y the rffo iel this it is not set then the receie uer oerates as a ffo o eth one atawor rearless o the alue in rffo oth an r ust e cleare rior to chanin this it itionally fluh an rfluh coans shoul e issue ieiately ater chanin this it receie ffo is not enale uer is eth leacy suort receie ffo is enale uer is eth inicte y rffo rffo receie ffo uer eth he axiu nuer o receie atawors that can e store in the receie uer eore an oerrun occurs his iel is rea only receie ffouer eth atawor receie ffouer eth atawors receie ffouer eth atawors receie ffouer eth atawors receie ffouer eth atawors receie ffouer eth atawors receie ffouer eth atawors resere ur ffo ontrol reister ur x ffo this register provides the ability to program various control bits for fifo operation. this register may be read or written at any time. note that writing the txflush and rxflush bits may result in data loss and requires careful action to prevent unintended / unpredictable behavior, hence it is recommended that te and re be cleared prior to flushing the corresponding fifo. addresses: uart0_cfifo is 4006_a000h base + 11h offset = 4006_a011h uart1_cfifo is 4006_b000h base + 11h offset = 4006_b011h uart2_cfifo is 4006_c000h base + 11h offset = 4006_c011h uart3_cfifo is 4006_d000h base + 11h offset = 4006_d011h uart4_cfifo is 400e_a000h base + 11h offset = 400e_a011h bit 7 6 5 4 3 2 1 0 read 0 0 0 txofe rxufe write txflush rxflush reset 0 0 0 0 0 0 0 0 chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1509 uart x ffo iel escritions fiel escrition fluh ransit ffouer flush ritin to this it causes all ata that is store in the transit ffouer to e lushe his oes not aect ata that is in the transit shit reister o lush oeration occurs ll ata in the transit ffouer is cleare out rfluh receie ffouer flush ritin to this it causes all ata that is store in the receie ffouer to e lushe his oes not aect ata that is in the receie shit reister o lush oeration occurs ll ata in the receie ffouer is cleare out resere his reaonly iel is resere an always has the alue ero of ransit ffo oerlow nterrut nale hen this it is set the of la will enerate an interrut to the host of la oes not enerate an interrut to the host of la enerates an interrut to the host ruf receie ffo unerlow nterrut nale hen this it is set the ruf la will enerate an interrut to the host ruf la oes not enerate an interrut to the host ruf la enerates an interrut to the host ur ffo tatus reister ur x ffo this register provides various status information regarding the transmit and receiver buffers/fifos, including interrupt information. this register may be written or read at anytime. addresses: uart0_sfifo is 4006_a000h base + 12h offset = 4006_a012h uart1_sfifo is 4006_b000h base + 12h offset = 4006_b012h uart2_sfifo is 4006_c000h base + 12h offset = 4006_c012h uart3_sfifo is 4006_d000h base + 12h offset = 4006_d012h uart4_sfifo is 400e_a000h base + 12h offset = 400e_a012h bit 7 6 5 4 3 2 1 0 read txempt rxempt 0 txof rxuf write reset 1 1 0 0 0 0 0 0 memory map and registers k60 sub-family reference manual, rev. 6, nov 2011 1510 freescale semiconductor, inc. uart x ffo iel escritions fiel escrition ransit uerffo ty his status it asserts when there is no ata in the ransit ffouer his it oes not tae into account ata that is in the transit shit reister ransit uer is not ety ransit uer is ety r receie uerffo ty his status it asserts when there is no ata in the receie ffouer his it oes not tae into account ata that is in the receie shit reister receie uer is not ety receie uer is ety resere his reaonly iel is resere an always has the alue ero of ransitter uer oerlow fla his la inicates that ore ata has een written to the transit uer than it can hol his it will assert rearless o the alue o ffoof howeer an interrut will only e issue to the host i the ffoof it is set his la is cleare y writin a o transit uer oerlow has occurre since the last tie the la was cleare t least one transit uer oerlow has occurre since the last tie the la was cleare ruf receier uer unerlow fla his la inicates that ore ata has een rea ro the receie uer than was resent his it will assert rearless o the alue o fforuf howeer an interrut will only e issue to the host i the fforuf it is set his la is cleare y writin a o receie uer unerlow has occurre since the last tie the la was cleare t least one receie uer unerlow has occurre since the last tie the la was cleare hater uniersal synchronous receierransitter ur ufaily reerence anual re o freescale eiconuctor nc 51.3.19 uart fifo transmit watermark (uart x ffo this register provides the ability to set a programmable threshold for notification of needing additional transmit data. this register may be read at any time but should only be written when c2[te] is not set. changing the value of the watermark will not clear the s1[tdre] flag. addresses: uart0_twfifo is 4006_a000h base + 13h offset = 4006_a013h uart1_twfifo is 4006_b000h base + 13h offset = 4006_b013h uart2_twfifo is 4006_c000h base + 13h offset = 4006_c013h uart3_twfifo is 4006_d000h base + 13h offset = 4006_d013h uart4_twfifo is 400e_a000h base + 13h offset = 400e_a013h bit 7 6 5 4 3 2 1 0 read txwater write reset 0 0 0 0 0 0 0 0 uart x ffo iel escritions fiel escrition r ransit aterar hen the nuer o atawors in the transit ffouer is equal to or less than the alue in this reister iel then an interrut ia r or a request ia will e enerate as eterine y an iels for roer oeration the alue in the r iel ust e set to e less than the sie o the transit uerffo sie as inicate y ffoffo an ffof ur ffo ransit ount ur x ffo this is a read only register that indicates how many datawords are currently in the transmit buffer/fifo. it may be read at anytime. addresses: uart0_tcfifo is 4006_a000h base + 14h offset = 4006_a014h uart1_tcfifo is 4006_b000h base + 14h offset = 4006_b014h uart2_tcfifo is 4006_c000h base + 14h offset = 4006_c014h uart3_tcfifo is 4006_d000h base + 14h offset = 4006_d014h uart4_tcfifo is 400e_a000h base + 14h offset = 400e_a014h bit 7 6 5 4 3 2 1 0 read txcount write reset 0 0 0 0 0 0 0 0 memory map and registers k60 sub-family reference manual, rev. 6, nov 2011 1512 freescale semiconductor, inc. uart x ffo iel escritions fiel escrition ou ransit ounter he alue in this reister inicates the nuer o atawors that are in the transit uerffo a atawor is in the rocess o ein transitte ie in the transit shit reister it is not inclue in the count his alue ay e use in conunction with the ffoffo iel to calculate how uch roo is let in the transit uerffo ur ffo receie aterar ur x rffo this register provides the ability to set a programmable threshold for notification of needing to remove data from the receiver buffer/fifo. this register may be read at any time but should only be written when c2[re] is not asserted. changing the value in this register will not clear the s1[rdrf] flag. addresses: uart0_rwfifo is 4006_a000h base + 15h offset = 4006_a015h uart1_rwfifo is 4006_b000h base + 15h offset = 4006_b015h uart2_rwfifo is 4006_c000h base + 15h offset = 4006_c015h uart3_rwfifo is 4006_d000h base + 15h offset = 4006_d015h uart4_rwfifo is 400e_a000h base + 15h offset = 400e_a015h bit 7 6 5 4 3 2 1 0 read rxwater write reset 0 0 0 0 0 0 0 1 uart x rffo iel escritions fiel escrition rr receie aterar hen the nuer o atawors in the receie ffouer is equal to or reater than the alue in this reister iel the eent is lae n interrut ia rrf or a request ia r will e enerate as eterine y r an r iels for roer oeration the alue in the rr iel ust e set to e less than the sie o the receie uerffo sie as inicate y fforffo an fforf an reater than hater uniersal synchronous receierransitter ur ufaily reerence anual re o freescale eiconuctor nc 51.3.22 uart fifo receive count (uart x rffo this is a read only register that indicates how many datawords are currently in the receive buffer/fifo. it may be read at anytime. addresses: uart0_rcfifo is 4006_a000h base + 16h offset = 4006_a016h uart1_rcfifo is 4006_b000h base + 16h offset = 4006_b016h uart2_rcfifo is 4006_c000h base + 16h offset = 4006_c016h uart3_rcfifo is 4006_d000h base + 16h offset = 4006_d016h uart4_rcfifo is 400e_a000h base + 16h offset = 400e_a016h bit 7 6 5 4 3 2 1 0 read rxcount write reset 0 0 0 0 0 0 0 0 uart x rffo iel escritions fiel escrition rou receie ounter he alue in this reister inicates the nuer o atawors that are in the receie uerffo a atawor is in the rocess o ein receie ie in the receie shit reister it is not inclue in the count his alue ay e use in conunction with the fforffo iel to calculate how uch roo is let in the receie uerffo ur ontrol reister ur x the c7816 register is the primary control register for iso-7816 specific functionality. this register is specific to 7816 functionality and the values in this register have no effect on uart operation and should be ignored if iso_7816e is not set/enabled. this register may be read at anytime but values should only be changed when the iso_7816e bit is not set. addresses: uart0_c7816 is 4006_a000h base + 18h offset = 4006_a018h uart1_c7816 is 4006_b000h base + 18h offset = 4006_b018h uart2_c7816 is 4006_c000h base + 18h offset = 4006_c018h uart3_c7816 is 4006_d000h base + 18h offset = 4006_d018h uart4_c7816 is 400e_a000h base + 18h offset = 400e_a018h bit 7 6 5 4 3 2 1 0 read 0 onack anack init ttype iso_7816e write reset 0 0 0 0 0 0 0 0 memory map and registers k60 sub-family reference manual, rev. 6, nov 2011 1514 freescale semiconductor, inc. uart x iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero o enerate on oerlow hen this it is set the receier will autoatically enerate a resonse i a receie uer oerrun occurs as inicate y the or iel n any systes this will result in the transitter resenin the acet that oerlowe until the retransit threshol or that transitter has een reache is only enerate i his it oerates ineenently o ee oerrun consierations he receie ata oes not enerate a when the receit o the ata results in an oerlow eent the receier uer oerlows a is autoatically sent on a receie character enerate on rror hen this it is set the receier will autoatically enerate a resonse i a arity error occurs or i is set an an inali initial character is etecte is only enerate i is set the ur will attet to retransit the ata ineinitely o sto retransission attets clear or o an o not set until set aain o is autoatically enerate is autoatically enerate i a arity error is etecte or i an inali initial character is etecte etect nitial haracter hen this it is set all receie characters will e searche or a ali initial character an inali initial character is ientiie then a will e sent i is set ll receie ata is iscare an error las loce f or f f until a ali initial character is etecte uon etection o a ali initial character the coniuration alues f an r are autoatically uate to relect the initial character that was receie he actual ata alue is not store in the receie uer itionally uon etection o a ali initial character the la is set an an interrut issue as rorae y the it hen a ali initial character is etecte the it is autoatically cleare oral oeratin oe receier oes not see to ientiy initial character receier searches or initial character ranser ye his it inicates the transer rotocol ein use reer to o sartcar suort or ore etails er the o seciication er the o seciication o o functionality nale his it inicates that the ur is oeratin accorin to the o rotocol o: his it shoul only e oiie when no transit or receie is occurrin this it is chane urin a ata transer the ata ein transitte or receie ay e transerre incorrectly o unctionality is turne o not enale o unctionality is turne on enale hater uniersal synchronous receierransitter ur ufaily reerence anual re o freescale eiconuctor nc 51.3.24 uart 7816 interrupt enable register (uart x the ie7816 register controls which flags result in an interrupt being issued. this register is specific to 7816 functionality, the corresponding flags that drive the interrupts will not assert when 7816e is not set/enabled. however, these flags may remain set if they asserted while 7816e was set and not subsequently cleared. this register maybe read or written at anytime. addresses: uart0_ie7816 is 4006_a000h base + 19h offset = 4006_a019h uart1_ie7816 is 4006_b000h base + 19h offset = 4006_b019h uart2_ie7816 is 4006_c000h base + 19h offset = 4006_c019h uart3_ie7816 is 4006_d000h base + 19h offset = 4006_d019h uart4_ie7816 is 400e_a000h base + 19h offset = 400e_a019h bit 7 6 5 4 3 2 1 0 read wte cwte bwte initde 0 gtve txte rxte write reset 0 0 0 0 0 0 0 0 uart x iel escritions fiel escrition ait ier nterrut nale he assertion o the it will not result in the eneration o an interrut he assertion o the it will result in the eneration o an interrut haracter ait ier nterrut nale he assertion o the it will not result in the eneration o an interrut he assertion o the it will result in the eneration o an interrut loc ait ier nterrut nale he assertion o the it will not result in the eneration o an interrut he assertion o the it will result in the eneration o an interrut nitial haracter etecte nterrut nale he assertion o the it will not result in the eneration o an interrut he assertion o the it will result in the eneration o an interrut resere his reaonly iel is resere an always has the alue ero uar ier iolate nterrut nale he assertion o the it will not result in the eneration o an interrut he assertion o the it will result in the eneration o an interrut ransit hreshol xceee nterrut nale table continues on the next page... memory map and registers 60 sub-family reference manual, rev. 6, nov 2011 116 freescale semiconductor, inc. uart x iel escritions continue fiel escrition he assertion o the it will not result in the eneration o an interrut he assertion o the it will result in the eneration o an interrut r receie hreshol xceee nterrut nale he assertion o the r it will not result in the eneration o an interrut he assertion o the r it will result in the eneration o an interrut ur nterrut tatus reister ur x the is7816 register provides a mechanism to read and clear the interrupt flags. all flags/ interrupts are cleared by writing a "1" to the bit location. writing a "0" has no effect. all bits are "sticky", meaning they only indicate that the flag condition occurred since the last time the bit was cleared not that the condition currently exists. the status flags are set regardless of if the corresponding bit in the ic7816 is set or cleared, the ic7816 only controls if a interrupt is issued to the host processor. this register is specific to 7816 functionality and the values in this register have no affect on uart operation and should be ignored if 7816e is not set/enabled. this register may be read or written at anytime. addresses: uart0_is7816 is 4006_a000h base + 1ah offset = 4006_a01ah uart1_is7816 is 4006_b000h base + 1ah offset = 4006_b01ah uart2_is7816 is 4006_c000h base + 1ah offset = 4006_c01ah uart3_is7816 is 4006_d000h base + 1ah offset = 4006_d01ah uart4_is7816 is 400e_a000h base + 1ah offset = 400e_a01ah bit 7 6 5 4 3 2 1 0 read wt cwt bwt initd 0 gtv txt rxt write reset 0 0 0 0 0 0 0 0 uart x iel escritions fiel escrition ait ier nterrut his la inicates that the wait tie the tie etween the leain ee o a character ein transitte an the leain ee o the next resonse character has exceee the rorae alue his la only asserts when his interrut is cleare y writin ait tie has not een iolate ait tie has een iolate haracter ait ier nterrut table continues on the next page... chapter 1 universal asynchronous receivertransmitter uart 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 117 uart x iel escritions continue fiel escrition his la inicates that the character wait tie the tie etween the leain ees o two consecutie characters in a loc has excee the rorae alue his la only asserts when his interrut is cleare y writin haracter wait tie has not een iolate haracter wait tie has een iolate loc ait ier nterrut his la inicates that the loc wait tie the tie etween the leain ee o irst receie character o a loc an the leain ee o the last character the reiously transitte loc his la only asserts when his interrut is cleare y writin loc wait tie has not een iolate loc wait tie has een iolate nitial haracter etecte nterrut his la inicates that a ali initial character was receie his interrut is cleare y writin ali initial character has not een receie ali initial character has een receie resere his reaonly iel is resere an always has the alue ero uar ier iolate nterrut his la inicates that one or ore o the character uar tie loc uar tie or uar tie were iolate his interrut is cleare y writin uar tie or has not een iolate uar tie or has een iolate ransit hreshol xceee nterrut his la inicates that the transit threshol has een exceee as inicate y the hrhol iel rearless i this la is set the ur will continue to retransit ineinitely his la only asserts when is cleareisale is cleareisale is cleareisale or acet is transerre without receiin a the internal etection counter is cleare an the count restarts ro ero on the next receie his interrut is cleare y writin he nuer o retries an corresonin oes not excee the alue in the hrhol iel he nuer o retries an corresonin excees the alue in the hrhol iel r receie hreshol xceee nterrut his la inicates that there were ore than rhrhol consecutie enerate in resonse to arity errors on receie ata his la requires to e set itionally this la only asserts when learin this it also resets the counter eein trac o consecutie he ur will continue to attet to receie ata rearless o i this la is set is cleareisale r is cleareisale or acet is receie without neein to issue a the internal etection counter is cleare an the count restarts ro ero on the next transitte his interrut is cleare y writin table continues on the next page... memory map and registers 60 sub-family reference manual, rev. 6, nov 2011 118 freescale semiconductor, inc. uart x iel escritions continue fiel escrition he nuer o consecutie enerate as a result o arity errors an uer oerruns is less than or equal to the alue in rhrhol he nuer o consecutie enerate as a result o arity errors an uer oerruns is reater than the alue in rhrhol ur ait araeter reister ur x the wp7816 register contains constants used in the generation of various wait timer counters. to save register space this register is used differently when c7816[ttype] = 0 and c7816[ttype] = 1. this register may be read at anytime. this register must only be written when c7816[iso_7816e] is not set. addresses: uart0_wp7816t0 is 4006_a000h base + 1bh offset = 4006_a01bh uart1_wp7816t0 is 4006_b000h base + 1bh offset = 4006_b01bh uart2_wp7816t0 is 4006_c000h base + 1bh offset = 4006_c01bh uart3_wp7816t0 is 4006_d000h base + 1bh offset = 4006_d01bh uart4_wp7816t0 is 400e_a000h base + 1bh offset = 400e_a01bh bit 7 6 5 4 3 2 1 0 read wi write reset 0 0 0 0 1 0 1 0 uart x iel escritions fiel escrition ait ier nterrut his alue is use to calculate the alue use or the counter t reresents a alue etween an he alue o ero is not ali his alue is only use when ee ait tie an uar tie araeters hater uniersal synchronous receierransitter ur ufaily reerence anual re o freescale eiconuctor nc 51.3.27 uart 7816 wait parameter register (uart x the wp7816 register contains constants used in the generation of various wait timer counters. to save register space this register is used differently when c7816[ttype] = 0 and c7816[ttype] = 1. this register maybe read at anytime. this register must only be written when c7816[iso_7816e] is not set. addresses: uart0_wp7816t1 is 4006_a000h base + 1bh offset = 4006_a01bh uart1_wp7816t1 is 4006_b000h base + 1bh offset = 4006_b01bh uart2_wp7816t1 is 4006_c000h base + 1bh offset = 4006_c01bh uart3_wp7816t1 is 4006_d000h base + 1bh offset = 4006_d01bh uart4_wp7816t1 is 400e_a000h base + 1bh offset = 400e_a01bh bit 7 6 5 4 3 2 1 0 read cwi bwi write reset 0 0 0 0 1 0 1 0 uart x iel escritions fiel escrition haracter ait ie nteer his alue is use to calculate the alue use or the counter t reresents a alue etween an his alue is only use when ee ait tie an uar tie araeters loc ait ie nteer his alue is use to calculate the alue use or the counter t reresent a alue etween an his alue is only use when ee ait tie an uar tie araeters eory a an reisters ufaily reerence anual re o freescale eiconuctor nc 51.3.28 uart 7816 wait n register (uart x the wn7816 register contains a parameter that is used in the calculation of the guard time counter. this register may be read at anytime. this register must only be written when c7816[iso_7816e] is not set. addresses: uart0_wn7816 is 4006_a000h base + 1ch offset = 4006_a01ch uart1_wn7816 is 4006_b000h base + 1ch offset = 4006_b01ch uart2_wn7816 is 4006_c000h base + 1ch offset = 4006_c01ch uart3_wn7816 is 4006_d000h base + 1ch offset = 4006_d01ch uart4_wn7816 is 400e_a000h base + 1ch offset = 400e_a01ch bit 7 6 5 4 3 2 1 0 read gtn write reset 0 0 0 0 0 0 0 0 uart x iel escritions fiel escrition uar an his reister iel eines a araeter use in the calculation o an counters he alue reresents an inteer nuer ee ait tie an uar tie araeters ur ait f reister ur x f the wf7816 contains parameters that are used in the generation of various counters including gt, cgt, bgt, wt and bwt. this register may be read from at anytime. this register must only be written to when c7816[iso_7816e] is not set. addresses: uart0_wf7816 is 4006_a000h base + 1dh offset = 4006_a01dh uart1_wf7816 is 4006_b000h base + 1dh offset = 4006_b01dh uart2_wf7816 is 4006_c000h base + 1dh offset = 4006_c01dh uart3_wf7816 is 4006_d000h base + 1dh offset = 4006_d01dh uart4_wf7816 is 400e_a000h base + 1dh offset = 400e_a01dh bit 7 6 5 4 3 2 1 0 read gtfd write reset 0 0 0 0 0 0 0 1 chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1521 uart x f iel escritions fiel escrition f f ultilier his iel is use as another ultilier in the calculation o an his alues reresents a nuer etween an he alue o is inali his alue is o use in au rate eneration ee ait tie an uar tie araeters an au rate eneration ur rror hreshol reister ur x the et7816 register contains fields that determine the number of nacks that must be received or transmitted before the host processor is notified. this register may be read at anytime. this register must only be written when c7816[iso_7816e] is not set. addresses: uart0_et7816 is 4006_a000h base + 1eh offset = 4006_a01eh uart1_et7816 is 4006_b000h base + 1eh offset = 4006_b01eh uart2_et7816 is 4006_c000h base + 1eh offset = 4006_c01eh uart3_et7816 is 4006_d000h base + 1eh offset = 4006_d01eh uart4_et7816 is 400e_a000h base + 1eh offset = 400e_a01eh bit 7 6 5 4 3 2 1 0 read txthreshold rxthreshold write reset 0 0 0 0 0 0 0 0 uart x iel escritions fiel escrition hrhol ransit hreshol he alue written to this iel inicates the axiu nuer o aile attets s a transitte character can hae eore the host rocessor is notiie eanin a alue o will always result in assertin on the irst that is receie alue o will result in ein asserte on the secon that is receie his iel is only eaninul when an he alue rea ro this iel reresents the nuer o consecutie s that hae een receie since the last successul transission his counter saturates at hf an oes not wra aroun rearless o how any s that are receie the ur will continue to retransit ineinitely his la only asserts when for aitional inoration see the it escrition rhrhol receie hreshol he alue written to this iel inicates the axiu nuer o consecutie s enerate as a result o a arity error or receier uer oerruns eore the host rocessor is notiie once the counter excees that alue in the iel the r will e asserte his iel is only eaninul when he alue rea ro this iel reresents the nuer o consecutie s that hae een transitte since the last successul recetion his counter saturates at hf an oes not wra aroun rearless o the nuer o s sent the ur will continue to receie ali acets ineinitely for aitional inoration see r it escrition eory a an reisters ufaily reerence anual re o freescale eiconuctor nc 51.3.31 uart 7816 transmit length register (uart x l the tl7816 register is used to indicate how many characters are contained in the block being transmitted. this register is only used when c7816[ttype] = 1. this register may be read at anytime. this register should only be written when c2[te] is not enabled. addresses: uart0_tl7816 is 4006_a000h base + 1fh offset = 4006_a01fh uart1_tl7816 is 4006_b000h base + 1fh offset = 4006_b01fh uart2_tl7816 is 4006_c000h base + 1fh offset = 4006_c01fh uart3_tl7816 is 4006_d000h base + 1fh offset = 4006_d01fh uart4_tl7816 is 400e_a000h base + 1fh offset = 400e_a01fh bit 7 6 5 4 3 2 1 0 read tlen write reset 0 0 0 0 0 0 0 0 uart x l iel escritions fiel escrition l ransit lenth his alue lus inicates the nuer o characters containe in the loc ein transitte his reister is autoatically ecreente y or each character in the inoration iel ortion o the loc itionally this reister is autoatically ecreente y or the irst character o a r in the eiloue iel hence this reister shoul e rorae with the nuer o ytes in the ata acet i a lr is ein transitte an the nuer o ytes i a r is ein transitte his reister is not ecreente or characters that are assue to e art o the roloue iel irst three characters transitte in a loc or the lr or last r character in the iloue iel last character transitte his iel shoul only e rorae or auste when is cleare functional escrition this section provides a complete functional description of the uart block. the uart allows full duplex, asynchronous, nrz serial communication between the cpu and remote devices, including other cpus. the uart transmitter and receiver operate independently, although they use the same baud rate generator. the cpu monitors the status of the uart, writes the data to be transmitted, and processes received data. chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1523 51.4.1 transmitter shift direction parity generation pe pt transmitter control m msbf internal bus tx port en tx input buffer en tx output buffer en stop txinv txd pin control start baudrate generate module clock sbr12:0 brfa4:0 variable 12-bit transmit shift register m10 r485 control rts_b cts_b txdir sbk te dma done 7816 logic txd irq / dma logic infrared logic dma requests irq requests txd loop control loops rsrc uart data register (uart_d) figure 51-187. transmitter block diagram 51.4.1.1 transmitter character length the uart transmitter can accommodate either 8, 9, or 10-bit data characters. the state of the c1[m] and c1[pe] bits and the c4[m10] bit determine the length of data characters. when transmitting 9-bit data, bit c3[t8] is the ninth bit (bit 8). functional description k60 sub-family reference manual, rev. 6, nov 2011 1524 freescale semiconductor, inc. 51.4.1.2 transmission bit order when the s2[msbf] bit is set, the uart automatically transmits the msb of the data word as the first bit after the start bit. likewise the lsb of the data word is transmitted immediately preceding the parity bit (or the stop bit if parity is not enabled). all necessary bit ordering is handled automatically by the module hence the format of the data written to the d register for transmission is completely independent of the s2[msbf] setting. 51.4.1.3 character transmission to transmit data, the mcu writes the data bits to the uart transmit buffer using uart data registers (c3[t8]/d). data in the transmit buffer is then in turn transferred to the transmitter shift register as needed. the transmit shift register then shifts a frame out through the transmit data output signal after it has prefaced it with any required start and stop bits. the uart data registers (c3[t8] and d) provide access to the transmit buffer structure. the uart also sets a flag, the transmit data register empty flag (s1[tdre]) and generates interrupt or dma request (c5[tdmas]), whenever the number of datawords in the transmit buffer is equal to or less than the value indicated by the twfifo[txwater]. the transmit driver routine may respond to this flag by writing additional datawords to the transmit buffer using (c3[t8]/d) as space permits. see application information for specific programing sequences. setting the c2[te] bit automatically loads the transmit shift register with a preamble of 10 logic 1s (if c1[m] = 0), 11 logic 1s (if c1[m] = 1 and c4[m10] = 0), or 12 logic 1s (if c1[m] = 1, c4[m10] = 1, c1[pe] = 1). after the preamble shifts out, control logic transfers the data from the uart data register into the transmit shift register. the transmitter automatically transmits the correct start bit and stop bit before and after the dataword. when c7816[iso_7816e] = 1 setting the c2[te] bit does not result in a preamble being generated. the transmitter starts transmitting as soon as the corresponding guard time expires. when c7816[ttype] = 0 the value in gt is used, when c7816[ttype] = 1 the value bgt is used since it is assumed that the c2[te] will remain asserted until the end of the block transfer. the c2[te] bit is automatically cleared when in c7816[ttype] = 1 and the block being transmitted has been completed. when c7816[ttype] = 0, the transmitter listens for a nack indication. if no nack is received it is assumed that character was correctly received. if a nack is received the transmitter will resend the data, assuming that the number of retries for that character (number of nacks received) is less than or equal to the value in et7816[txthreshold]. chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1525 hardware supports odd or even parity. when parity is enabled, the bit immediately preceding the stop bit is the parity bit. when the transmit shift register is not transmitting a frame, the transmit data output signal goes to the idle condition, logic 1. if at any time software clears the c2[te] bit, the transmitter enable signal goes low and the transmit signal goes idle. if software clears c2[te] while a transmission is in progress, the character in the transmit shift register continues to shift out, provided s1[tc] flag was cleared during the data write sequence. to clear the s1[tc] flag, the s1 register must be read followed by a write to uartx_d register. if the s1[tc] flag is cleared during character transmission and the c2[te] bit is cleared, the transmission enable signal is deasserted at the completion of current frame. following this, the transmit data out signal enters the idle state even if there is data pending in the uart transmit data buffer. to ensure that all the data written in the fifo is transmitted on the link before clearing c2[te], wait for the s1[tc] flag to set. alternatively, the same can be achieved by setting twfifo[txwater] to 0x0 and waiting for s1[tdre] to set. 51.4.1.4 transmitting break characters setting the c2[sbk] loads the transmit shift register with a break character. a break character contains all logic 0s and has no start, stop, or parity bit. break character length depends on the c1[m] and c1[pe] bits, the s2[brk13] bit, and the c4[m10] bit. refer to the following table. table 51-195. transmit break character length s2[brk13] c1[m] c4[m10] c1[pe] bits transmitted 0 0 10 0 1 0 11 0 1 1 0 11 0 1 1 1 12 1 0 13 1 1 14 as long as c2[sbk] is set, transmitter logic continuously loads break characters into the transmit shift register. after software clears the c2[sbk] bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. the automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next character. break bits are not supported when c7816[iso_7816e] is set/enabled. functional description k60 sub-family reference manual, rev. 6, nov 2011 1526 freescale semiconductor, inc. note when queuing a break character, it will be transmitted following the completion of the data value currently being shifted out from the shift register. this means that if data is queued in the data buffer to be transmitted, the break character will preempt that queued data. the queued data will then be transmitted after the break character is complete. 51.4.1.5 idle characters an idle character contains all logic 1s and has no start, stop, or parity bit. idle character length depends on the c1[m] and c1[pe] bits and the c4[m10] bit. the preamble is a synchronizing idle character that begins the first transmission initiated after setting the c2[te] bit. when c7816[iso_7816e] is set/enabled, idle characters are not sent or detected. when data is not being transmitted the data i/o line is in an inactive state. if the c2[te] bit is cleared during a transmission, the transmit data output signal becomes idle after completion of the transmission in progress. clearing and then setting the c2[te] bit during a transmission queues an idle character to be sent after the dataword currently being transmitted. note when queuing an idle character the idle character will be transmitted following the completion of the data value currently being shifted out from the shift register. this means that if data is queued in the data buffer to be transmitted, the idle character will preempt that queued data. the queued data will then be transmitted after the idle character is complete. if the c2[te] bit is cleared and the transmission is completed, the uart is not the master of the txd pin. 51.4.1.6 hardware flow control the transmitter supports hardware flow control by gating the transmission with the value of cts. if the clear-to-send operation is enabled, the character is transmitted when cts is asserted. if cts is deasserted in the middle of a transmission with characters remaining in the receiver data buffer, the character in the shift register is sent and txd remains in the mark state until cts is reasserted. chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1527 if the clear-to-send operation is disabled, the transmitter ignores the state of cts. also, if the transmitter is forced to send a continuous low condition because it is sending a break character, the transmitter ignores the state of cts regardless of whether the clear-to-send operation is enabled. the transmitter's cts signal can also be enabled even if the same uart receiver's rts signal is disabled. 51.4.1.7 transceiver driver enable the transmitter can use rts as an enable signal for the driver of an external transceiver, see transceiver driver enable using rts for details. if the request-to-send operation is enabled, when a character is placed into an empty transmitter data buffer, rts asserts one bit time before the start bit is transmitted. rts remains asserted for the whole time that the transmitter data buffer has any characters. rts deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. transmitting a break character also asserts rts, with the same assertion and deassertion timing as having a character in the transmitter data buffer. the transmitter's rts signal only asserts when the transmitter is enabled. however, the transmitter's rts signal is unaffected by its cts signal. rts will remain asserted until the transfer is completed, even if the transmitter is disabled mid-way through a data transfer. the following figure shows the functional timing information for the transmitter. along with the actual character itself, txd shows the start bit. the stop bit is also indicated, with a dashed line if necessary. functional description k60 sub-family reference manual, rev. 6, nov 2011 1528 freescale semiconductor, inc. c1 c2 c3 break c4 txd c5 c1 c2 c3 c4 start break stop break c5 data buffer write cts_b rts_b c1 in transmission 1 1. cn = transmit characters figure 51-188. transmitter rts and cts timing diagram chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1529 51.4.2 receiver m pe pt re variable 12-bit receive stop start receive wakeup data buffer internal bus module sbr12:0 baudrate clock raf logic shift direction active edge detect lbkde brfa4:0 msbf generator shift register m10 rxinv irq / dma logic dma requests irq requests parity logic control rxd rxd loops rsrc from transmitter receiver source control 7816 logic to txd infrared logic figure 51-189. uart receiver block diagram 51.4.2.1 receiver character length the uart receiver can accommodate 8-, 9-, or 10-bit data characters. the states of the c1[m] and c1[pe] bits and the c4[m10] bit determine the length of data characters. when receiving 9 or 10-bit data, bit c3[r8] is the ninth bit (bit 8). 51.4.2.2 receiver bit ordering when the s2[msbf] bit is set, the receiver operates such that the first bit received after the start bit is the msb of the data word. likewise the bit received immediately preceding the parity bit (or the stop bit if parity is not enabled) is treated as the lsb for functional description k60 sub-family reference manual, rev. 6, nov 2011 1530 freescale semiconductor, inc. the data word. all necessary bit ordering is handled automatically by the module hence the format of the data read from receive data buffer is completely independent of the s2[msbf] setting. 51.4.2.3 character reception during uart reception, the receive shift register shifts a frame in from the unsynchronized receiver input signal. after a complete frame shifts into the receive shift register, the data portion of the frame transfers to the uart receive buffer. additionally, the noise and parity error flags that are calculated during the receive process are also captured in the uart receive buffer. the receive data buffer is accessible via the d and c3[t8] registers. additional received information flags regarding the receive dataword can be read in ed register. the s1[rdrf] flag is set if the number of resulting datawords in the receive buffer is equal to or greater than the number indicated by rwfifo[rxwater]. if the c2[rie] is also set, the rdrf flag generates an rdrf interrupt request. alternatively, by programming the c5[rdmas] bit correctly a dma request can be generated. when 7816e is set/enabled and c7816[ttype] = 0, character reception operates slightly differently. upon receipt of the parity bit, the validity of the parity bit is checked. if c7816[anack] is set and the parity check fails or if init and the received character is not a valid initial character, then a nack is sent by the receiver. if the number of consecutive receive errors exceeds the threshold set by et7816[rxthreshold] then the is7816[rxt] flag is set and an interrupt generated if ie7816[rxte] is set. if an error is detected (parity or invalid initial character) the data is not transferred from the receive shift register to the receive buffer. instead, the data is overwritten by the next incoming data. when the c7816[iso_7816e] is set/enabled and c7816[onack] is set/enabled and the received character would result in the receive buffer overflowing a nack is issued by the receiver. additionally, the s1[or] flag is set and interrupt issued if appropriate and the data in the shift register is discarded. 51.4.2.4 data sampling the receiver samples the unsynchronized receiver input signal at the rt clock rate. the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock (see the following figure) is re-synchronized: chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1531 ? after every start bit. ? after the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid logic 1 and the majority of the next rt8, rt9, and rt10 samples returns a valid logic 0). to locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s. when the falling edge of a possible start bit occurs, the rt clock begins to count to 16. samples rx pin input rt clock rt clock count reset rt clock 1 1 1 1 0 start bit lsb rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt6 rt2 rt3 rt4 rt7 rt8 rt9 rt11 rt13 rt14 rt15 rt16 1 1 1 1 0 0 0 0 0 0 rt10 rt12 rt1 start bit qualification data sampling start bit verification figure 51-190. receiver data sampling to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7 when c7816[iso_7816e] is cleared/disabled and rt8, rt9 and rt10 when c7816[iso_7816e] is set/enabled. the following table summarizes the results of the start bit verification samples. table 51-196. start bit verification rt3, rt5, and rt7 samples rt8, rt9, rt10 samples when 7816e start bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 if start bit verification is not successful, the rt clock is reset and a new search for a start bit begins. functional description k60 sub-family reference manual, rev. 6, nov 2011 1532 freescale semiconductor, inc. to determine the value of a data bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. the following table summarizes the results of the data bit samples. table 51-197. data bit recovery rt8, rt9, and rt10 samples data bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 note the rt8, rt9, and rt10 samples do not affect start bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are logic 1s following a successful start bit verification, the noise flag (s1[nf]) is set and the receiver assumes that the bit is a start bit (logic 0). with the exception of when c7816[iso_7816e] is set/enabled, where the values of rt8, rt9 and rt10 exclusively determine if a start bit exists. to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. the following table summarizes the results of the stop bit samples. in the event that c7816[iso_7816e] is set/enabled and c7816[ttype] = 0, verification of a stop bit does not take place. rather, starting with rt8 the receiver transmits a nack as programmed until time rt9 of the following time period. framing error detection is not supported when c7816[iso_7816e] is set/enabled. table 51-198. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1533 in the following figure, the verification samples rt3 and rt5 determine that the first low detected was noise and not the beginning of a start bit. in this example c7816[iso_7816e] = 0. the rt clock is reset and the start bit search begins again. the noise flag is not set because the noise occurred before the start bit was found. samples rx pin input rt clock rt clock count reset rt clock 1 1 1 0 1 0 0 0 start bit lsb rt1 rt1 rt1 rt1 rt2 rt4 rt3 rt5 rt1 rt1 rt2 rt3 rt10 rt1 rt2 rt3 1 1 0 0 0 0 rt11 rt12 rt13 rt14 rt15 rt16 rt4 rt5 rt6 rt7 rt8 rt9 figure 51-191. start bit search example 1 (c7816[iso_7816e] = 0) in the following figure, verification sample at rt3 is high. in this example c7816[iso_7816e] = 0. the rt3 sample sets the noise flag. although the perceived bit time is misaligned, the data samples rt8, rt9, and rt10 are within the bit time and data recovery is successful. samples rx pin input rt clock rt clock count reset rt clock 1 1 1 0 1 0 0 0 perceived start bit actual start bit lsb rt1 rt1 rt1 rt1 rt1 rt2 rt1 rt3 rt4 rt5 rt6 rt7 rt13 rt12 rt11 rt14 rt1 rt2 rt3 rt4 rt5 rt6 rt7 1 1 0 0 rt10 rt8 rt9 rt15 rt16 figure 51-192. start bit search example 2 (c7816[iso_7816e] = 0) in the following figure, a large burst of noise is perceived as the beginning of a start bit, although the test sample at rt5 is high. in this example c7816[iso_7816e] = 0. the rt5 sample sets the noise flag. although this is a worst-case misalignment of perceived bit time, the data samples rt8, rt9, and rt10 are within the bit time and data recovery is successful. functional description k60 sub-family reference manual, rev. 6, nov 2011 1534 freescale semiconductor, inc. samples rx pin input rt clock rt clock count reset rt clock 1 1 1 0 0 1 0 0 0 0 perceived start bit actual start bit lsb rt1 rt1 rt1 rt1 rt2 rt4 rt3 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 figure 51-193. start bit search example 3 (c7816[iso_7816e] = 0) the following figure shows the effect of noise early in the start bit time. in this example c7816[iso_7816e] = 0. although this noise does not affect proper synchronization with the start bit time, it does set the noise flag. samples rx pin input rt clock rt clock count reset rt clock 1 1 1 1 0 perceived and actual start bit lsb rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt1 rt2 rt3 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 111 1 1 1 0 figure 51-194. start bit search example 4 (c7816[iso_7816e] = 0) the following figure shows a burst of noise near the beginning of the start bit that resets the rt clock. in this example c7816[iso_7816e] = 0. the sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge. depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error flag. chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1535 samples rx pin input rt clock rt clock count reset rt clock 1 1 1 1 0 0 start bit lsb rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 no start bit found 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 rt4 rt5 rt6 rt7 rt1 rt1 rt1 figure 51-195. start bit search example 5 (c7816[iso_7816e] = 0) in the following figure, a noise burst makes the majority of data samples rt8, rt9, and rt10 high. in this example c7816[iso_7816e] = 0. this sets the noise flag but does not reset the rt clock. in start bits only, the rt8, rt9, and rt10 data samples are ignored. in this example, if c7816[iso_7816e] = 1 then a start bit would not have been detected at all since at least two of the three samples (rt8, rt9, rt10) were high. samples rx pin input rt clock rt clock count reset rt clock 1 1 1 1 0 0 start bit lsb rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt10 rt1 rt2 rt3 1 1 1 1 1 0 0 1 0 1 rt4 rt5 rt6 rt7 rt8 rt9 rt11 rt12 rt13 rt14 rt15 rt16 figure 51-196. start bit search example 6 51.4.2.5 framing errors if the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it sets the framing error flag, s1[fe] if s2[lbkde] is disabled. a break character when s2[lbkde] is disabled also sets the s1[fe] because a break character has no stop bit. the s1[fe] is set at the same time that received data is placed in the receive data buffer. framing errors are not supported when c7816[iso7816e] is set/ enabled. however, if the s1[fe] is set data will not be received when c7816[iso7816e] is set. functional description k60 sub-family reference manual, rev. 6, nov 2011 1536 freescale semiconductor, inc. 51.4.2.6 receiving break characters the uart recognizes a break character when a start bit is followed by eight, nine, or ten logic 0 data bits and a logic 0 where the stop bit should be. receiving a break character has these effects on uart registers: ? sets the framing error flag, s1[fe]. ? writes an all "0" dataword to the data buffer, which may cause s1[rdrf] to set depending on the watermark and number of values in the data buffer. ? may set the overrun flag, s1[or], noise flag, s1[nf], parity error flag, s1[pe], or the receiver active flag, s2[raf]. the detection threshold for a break character can be adjusted when using an internal oscillator in a lin system by setting the s2[lbkde] bit. the uart break character detection threshold depends on the c1[m] and c1[pe] bits, the c4[lbkde] bit, and the c4[m10] bit. refer to the following table. table 51-199. receive break character detection threshold lbkde m m10 pe threshold (bits) 0 0 10 0 1 0 11 0 1 1 0 11 0 1 1 1 12 1 0 11 1 1 12 while c4[lbkde] is set, it will have these effects on the uart registers: ? prevents the s1[rdrf], s1[fe], s1[nf], and s1[pf] flags from being set. however, if they are already set they will remain set. ? sets the lin break detect interrupt flag, s2[lbkdif] if a lin break character is received. break characters are not detected or supported when c7816[iso_7816e] is set/enabled. chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1537 51.4.2.7 hardware flow control to support hardware flow control, the receiver can be programmed to automatically deassert and assert rts. ? rts will remain asserted until the transfer is completed, even if the transmitter is disabled mid way through a data transfer, see transceiver driver enable using rts for more details. ? if the receiver request-to-send functionality is enabled, the receiver automatically deasserts rts if the number of characters in the receiver data register is equal to or greater than receiver data buffer's watermark, rwfifo[rxwater]. ? the receiver asserts rts when the number of characters in the receiver data register is less than the watermark. it is not affected by whether rdrf is asserted. ? even if rts is deasserted, the receiver continues to receive characters until the receiver data buffer is full or is overrun. ? if the receiver request-to-send functionality is disabled, the receiver rts remains deasserted. the following figure shows receiver hardware flow control functional timing. along with the actual character itself, rxd shows the start bit. the stop bit also indicated, with a dashed line if necessary. the watermark is set to 2. c1 c2 c3 c4 rxd c3 data buffer read s1[rdrf] rts_b c1 in reception 1 c1 c3 status register 1 read c1 c2 figure 51-197. receiver hardware flow control timing diagram 51.4.2.8 infrared decoder the infrared decoder converts the received character from the irda format to the nrz format used by the receiver. it also has a 16-rt clock counter that filters noise and indicates when a '1' is being received. functional description k60 sub-family reference manual, rev. 6, nov 2011 1538 freescale semiconductor, inc. 51.4.2.8.1 start bit detection when s2[rxinv] is cleared, the first rising edge of the received character corresponds to the start bit. the infrared decoder resets its counter. at this time, the receiver also begins its start bit detection process. once the start bit is detected, the receiver synchronizes its bit times to this start bit time. for the rest of the character reception, the infrared decoder's counter and the receiver's bit time counter count independently from each other. 51.4.2.8.2 noise filtering any further rising edges detected during the first half of the infrared decoder counter are ignored by the decoder. any pulses less than one rt clocks can be undetected by it regardless of whether it is seen in the first or second half of the count. 51.4.2.8.3 low-bit detection during the second half of the decoder count, a rising edge is decoded as a '0', which is sent to the receiver. the decoder counter also is reset. 51.4.2.8.4 high-bit detection at 16-rt clocks after the previous rising edge, if a rising edge is not seen, then the decoder sends a `1' to the receiver. if the next bit is a `0' which arrives late, then a low-bit is detected according to low-bit detection . the value sent to the receiver is changed from `1' to a `0'. then if a noise pulse occurs outside of the receiver's bit time sampling period, then the delay of a `0' is not recorded as noise. 51.4.2.9 baud rate tolerance a transmitting device may be operating at a baud rate below or above the receiver baud rate. accumulated bit time misalignment can cause one of the three stop bit data samples (rt8, rt9, and rt10) to fall outside the actual stop bit. a noise error will occur if the rt8, rt9, and rt10 samples are not all the same logical values. a framing error will occur if the receiver clock is misaligned in such a way that the majority of the rt8, rt9, and rt10 stop bit samples are a logic zero. chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1539 as the receiver samples an incoming frame, it re-synchronizes the rt clock on any valid falling edge within the frame. resynchronization within frames will correct a misalignment between transmitter bit times and receiver bit times. 51.4.2.9.1 slow data tolerance the following figure shows how much a slow received frame can be misaligned without causing a noise error or a framing error. the slow stop bit begins at rt8 instead of rt1 but arrives in time for the stop bit data samples at rt8, rt9, and rt10. receiver rt clock msb stop data samples rt16 rt15 rt14 rt13 rt12 rt11 rt10 rt9 rt8 rt7 rt6 rt5 rt4 rt3 rt2 rt1 figure 51-198. slow data for an 8-bit data character, data sampling of the stop bit takes the receiver 154 rt cycles (9 bit times 16 rt cycles + 10 rt cycles). with the misaligned character shown in the above figure, the receiver counts 154 rt cycles at the point when the count of the transmitting device is 147 rt cycles (9 bit times 16 rt cycles + 3 rt cycles). the maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data character with no errors is: ((154 ? 147) 154) 100 = 4.54% for a 9-bit data character, data sampling of the stop bit takes the receiver 170 rt cycles (10 bit times 16 rt cycles + 10 rt cycles). with the misaligned character shown in the above figure, the receiver counts 170 rt cycles at the point when the count of the transmitting device is 163 rt cycles (10 bit times 16 rt cycles + 3 rt cycles). the maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: ((170 ? 163) 170) 100 = 4.12% functional description k60 sub-family reference manual, rev. 6, nov 2011 1540 freescale semiconductor, inc. 51.4.2.9.2 fast data tolerance the following figure shows how much a fast received frame can be misaligned. the fast stop bit ends at rt10 instead of rt16 but is still sampled at rt8, rt9, and rt10. receiver rt clock stop idle or next frame data samples rt16 rt15 rt14 rt13 rt12 rt11 rt10 rt9 rt8 rt7 rt6 rt5 rt4 rt3 rt2 rt1 figure 51-199. fast data for an 8-bit data character, data sampling of the stop bit takes the receiver 154 rt cycles (9 bit times 16 rt cycles + 10 rt cycles). with the misaligned character shown in the above figure, the receiver counts 154 rt cycles at the point when the count of the transmitting device is 160 rt cycles (10 bit times 16 rt cycles). the maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is: ((154 ? 160) 154) 100 = 3.90% for a 9-bit data character, data sampling of the stop bit takes the receiver 170 rt cycles (10 bit times 16 rt cycles + 10 rt cycles). with the misaligned character shown in the above figure, the receiver counts 170 rt cycles at the point when the count of the transmitting device is 176 rt cycles (11 bit times 16 rt cycles). the maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is: ((170 ? 176) 170) 100 = 3.53% 51.4.2.10 receiver wakeup the c1[wake] bit determines how the uart is brought out of the standby state to process an incoming message. the c1[wake] bit enables either idle line wakeup or address mark wakeup. receiver wakeup is not supported when c7816[iso_7816e] is set/enabled since multi- receiver systems are not allowed. chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1541 51.4.2.10.1 idle input line wakeup (c1[wake] = 0) in this wakeup method, an idle condition on the unsynchronized receiver input signal clears the c2[rwu] bit and wakes the uart. the initial frame or frames of every message contain addressing information. all receivers evaluate the addressing information, and receivers for which the message is addressed process the frames that follow. any receiver for which a message is not addressed can set its c2[rwu] bit and return to the standby state. the c2[rwu] bit remains set and the receiver remains in standby until another idle character appears on the unsynchronized receiver input signal. idle line wakeup requires that messages be separated by at least one idle character and that no message contains idle characters. when c2[rwu] is one and s2[rwuid] is zero, the idle character that wakes the receiver does not set the s1[idle] flag or the receive data register full flag, s1[rdrf]. the receiver wakes and waits for the first data character of the next message which will be stored in the receive data buffer. when s2[rwuid] and c2[rwu] bits are set and c1[wake] is cleared, any idle condition sets the s1[idle] flag and generates an interrupt if enabled. idle input line wakeup is not supported when c7816[iso_7816e] is set/enabled. 51.4.2.10.2 address mark wakeup (c1[wake] = 1) in this wakeup method, a logic 1 in the bit position immediately preceding the stop bit of a frame clears the c2[rwu] bit and wakes the uart. a logic 1 in the bit position immediately preceeding the stop bit marks a frame as an address frame that contains addressing information. all receivers evaluate the addressing information, and the receivers for which the message is addressed process the frames that follow. any receiver for which a message is not addressed can set its c2[rwu] bit and return to the standby state. the c2[rwu] bit remains set and the receiver remains in standby until another address frame appears on the unsynchronized receiver input signal. a logic 1 in the bit position immediately preceding the stop bit clears the receiver's c2[rwu] bit before the stop bit is received and places the received data into the receiver data buffer. address mark wakeup allows messages to contain idle characters but requires that the bit position immediately preceding the stop bit be reserved for use in address frames. if module is in standby mode and nothing triggers to wake the uart, no error flag is set even if an invalid error condition is detected on the receiving data line. address mark wakeup is not supported when c7816[iso_7816e] is set/enabled. functional description k60 sub-family reference manual, rev. 6, nov 2011 1542 freescale semiconductor, inc. 51.4.2.10.3 match address operation match address operation is enabled when the c4[maen1] or c4[maen2] bit is set. in this function, a frame received by the rx pin with a logic 1 in the bit position immediately preceding the stop bit is considered an address and is compared with the associated ma1 or ma2 register. the frame is only transferred to the receive buffer, and s1[rdrf] is set, if the comparison matches. all subsequent frames received with a logic 0 in the bit position immediately preceding the stop bit are considered to be data associated with the address and are transferred to the receive data buffer. if no marked address match occurs then no transfer is made to the receive data buffer, and all following frames with logic zero in the bit position immediately preceding the stop bit are also discarded. if both the c4[maen1] and c4[maen2] bits are negated, the receiver operates normally and all data received is transferred to the receive data buffer. match address operation functions in the same way for both ma1 and ma2 registers. ? if only one of c4[maen1] and c4[maen2] is asserted, a marked address is compared only with the associated match register and data is transferred to the receive data buffer only on a match. ? if c4[maen1] and c4[maen2] are asserted, a marked address is compared with both match registers and data is transferred only on a match with either register. address match operation is not supported when c7816[iso_7816e] is set/enabled. 51.4.3 baud rate generation a 13-bit modulus counter and a 5-bit fractional fine-adjust counter in the baud rate generator derive the baud rate for both the receiver and the transmitter. the value from 1 to 8191 written to the sbr[12:0] bits determines the module clock divisor. the sbr bits are in the uart baud rate registers (bdh and bdl). the baud rate clock is synchronized with the module clock and drives the receiver. the fractional fine-adjust counter adds fractional delays to the baud rate clock to allow fine trimming of the baud rate to match the system baud rate. the baud rate clock divided by 16 drives the transmitter. the receiver has an acquisition rate of 16 samples per bit time. baud rate generation is subject to two sources of error: ? integer division of the module clock may not give the exact target frequency. this error can be reduced by means of the fine-adjust counter. ? synchronization with the module clock can cause phase shift. chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1543 the table 51-200 lists the available baud divisor fine adjust values. uart baud rate = uart module clock / (16 (sbr[12:0] + brfd)) the following table lists some examples of achieving target baud rates with a module clock frequency of 10.2 mhz, with and without fractional fine adjustment. table 51-200. baud rates (example: module clock = 10.2 mhz) bits sbr (decimal) bits brfa brfd value receiver clock (hz) transmitter clock (hz) target baud rate error (%) 17 00000 0 600,000.0 37,500.0 38,400 2.3 16 10011 19/32=0.59375 614,689.3 38,418.08 38,400 0.047 33 00000 0 309,090.9 19,318.2 19,200 0.62 33 00110 6/32=0.1875 307,344.6 19,209.04 19,200 0.047 66 00000 0 154,545.5 9659.1 9600 0.62 133 00000 0 76,691.7 4793.2 4800 0.14 266 00000 0 38,345.9 2396.6 2400 0.14 531 00000 0 19,209.0 1200.6 1200 0.11 1062 00000 0 9604.5 600.3 600 0.05 2125 00000 0 4800.0 300.0 300 0.00 4250 00000 0 2400.0 150.0 150 0.00 5795 00000 0 1760.1 110.0 110 0.00 table 51-201. baud rate fine adjust brfa baud rate fractional divisor (brfd) 0 0 0 0 0 0/32 = 0 0 0 0 0 1 1/32 = 0.03125 0 0 0 1 0 2/32 = 0.0625 0 0 0 1 1 3/32 = 0.09375 0 0 1 0 0 4/32 = 0.125 0 0 1 0 1 5/32 = 0.15625 0 0 1 1 0 6/32 = 0.1875 0 0 1 1 1 7/32 = 0.21875 0 1 0 0 0 8/32 = 0.25 0 1 0 0 1 9/32 = 0.28125 0 1 0 1 0 10/32 = 0.3125 0 1 0 1 1 11/32 = 0.34375 0 1 1 0 0 12/32 = 0.375 table continues on the next page... functional description 60 sub-family reference manual, rev. 6, nov 2011 144 freescale semiconductor, inc. table 51-201. baud rate fine adjust (continued) brfa baud rate fractional divisor (brfd) 0 1 1 0 1 13/32 = 0.40625 0 1 1 1 0 14/32 = 0.4375 0 1 1 1 1 15/32 = 0.46875 1 0 0 0 0 16/32 = 0.5 1 0 0 0 1 17/32 = 0.53125 1 0 0 1 0 18/32 = 0.5625 1 0 0 1 1 19/32 = 0.59375 1 0 1 0 0 20/32 = 0.625 1 0 1 0 1 21/32 = 0.65625 1 0 1 1 0 22/32 = 0.6875 1 0 1 1 1 23/32 = 0.71875 1 1 0 0 0 24/32 = 0.75 1 1 0 0 1 25/32 = 0.78125 1 1 0 1 0 26/32 = 0.8125 1 1 0 1 1 27/32 = 0.84375 1 1 1 0 0 28/32 = 0.875 1 1 1 0 1 29/32 = 0.90625 1 1 1 1 0 30/32 = 0.9375 1 1 1 1 1 31/32 = 0.96875 51.4.4 data format (non iso-7816) each data character is contained in a frame that includes a start bit and a stop bit. the rest of the data format depends upon uartx_c1[m], uartx_c1[pe], uartx_s2[msbf], and uartx_c4[m10]. 51.4.4.1 eight-bit configuration clearing the uart_c1[m] configures the uart for 8-bit data characters, that is, eight bits are memory mapped in uart_d. a frame with eight data bits has a total of 10 bits. the most significant bit of the eight data bits can be used as an address mark to wake the receiver. if that bit is used in this way, then it serves as an address or data indication, leaving the remaining seven bits as actual data. when uart_c1[pe] is set, the 8th databit is automatically calculated as the parity bit. refer to the following table. chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1545 table 51-202. configuration of 8-bit data format uart_c1[pe] start bit data bits address bits parity bits stop bit 0 1 8 0 0 1 0 1 7 1 1 0 1 1 1 7 0 1 1 1. the address bit identifies the frame as an address character. see receiver wakeup . 51.4.4.2 nine-bit configuration when uartx_c1[m] is set and uartx_c4[m10] is cleared the uart is configured for 9-bit data characters. the 9th bit is either uartx_c3[t8/r8] or the internally generated parity bit if uartx_c1[pe] is enabled. this results in a frame consisting of a total of 11 bits. in the event that the 9th data bit is selected to be uartx_c3[t8] it will remain unchanged after transmission and can be used repeatedly without rewriting it unless the value needs to be changed. this feature may be useful when the 9th data bit is being used as an address mark. when uartx_c1[m] is set and uartx_c4[m10] is set the uart is configured for 9- bit data characters, but the frame consists of a total of 12 bits. the 12 bits include the start and stop bits, the 9 data character bits and a 10th internal data bit. note that if uartx_c4[m10] is set uartx_c1[pe] must also be set. in this case, the 10th bit is the internally generated parity bit. the 9th bit is can either be used as a address mark or a 9th data bit. refer to the following table. table 51-203. configuration of 9-bit data formats c1[pe] uc1[m] c1[m10] start bit data bits address bits parity bits stop bit 0 0 0 see eight-bit configuration 0 0 1 invalid configuration 0 1 0 1 9 0 0 1 0 1 0 1 8 1 1 0 1 0 1 1 invalid configuration 1 0 0 see eight-bit configuration 1 0 1 invalid configuration 1 1 0 1 8 0 1 1 1 1 1 1 9 0 1 1 1 1 1 1 8 1 2 1 1 functional description k60 sub-family reference manual, rev. 6, nov 2011 1546 freescale semiconductor, inc. 1. the address bit identifies the frame as an address character. 2. the address bit identifies the frame as an address character. note unless in 9-bit mode with m10 set, do not use address mark wakeup with parity enabled. 51.4.4.3 timing examples timing examples of these configurations in the nrz mark/space data format are illustrated in the following figures. the timing examples show all of the configurations in the following sub-sections along with the lsb and msb first variations. 51.4.4.3.1 eight-bit format with parity disabled the most significant bit can be used for address mark wakeup. bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 stop bit address mark start bit start bit figure 51-200. eight bits of data with lsb first bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stop bit address mark start bit start bit figure 51-201. eight bits of data with msb first 51.4.4.3.2 eight-bit format with parity enabled bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 stop bit start bit start bit parity figure 51-202. seven bits of data with lsb first and parity bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stop bit start bit start bit parity figure 51-203. seven bits of data with msb first and parity 51.4.4.3.3 nine-bit format with parity disabled the most significant bit can be used for address mark wakeup. bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 stop bit address mark start bit start bit figure 51-204. nine bits of data with lsb first chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1547 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stop bit address mark start bit start bit figure 51-205. nine bits of data with msb first 51.4.4.3.4 nine-bit format with parity enabled bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 parity stop bit start bit start bit figure 51-206. eight bits of data with lsb first and parity bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 parity stop bit start bit start bit figure 51-207. eight bits of data with msb first and parity 51.4.4.3.5 non-memory mapped tenth bit for parity the most significant memory-mapped bit can be used for address mark wakeup. bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 parity stop bit start bit start bit bit 0 address mark figure 51-208. nine bits of data with lsb first and parity bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 parity stop bit start bit start bit bit 8 address mark figure 51-209. nine bits of data with msb first and parity 51.4.5 single-wire operation normally, the uart uses two pins for transmitting and receiving. in single-wire operation, the rxd pin is disconnected from the uart and the uart implements a half-duplex serial connection. the uart uses the txd pin for both receiving and transmitting. rxd tx pin input tx pin output txinv transmitter receiver rxinv figure 51-210. single-wire operation (c1[loops] = 1, c1[rsrc] = 1) functional description k60 sub-family reference manual, rev. 6, nov 2011 1548 freescale semiconductor, inc. enable single-wire operation by setting the c1[loops] bit and the receiver source bit, c1[rsrc]. setting the c1[loops] bit disables the path from the unsynchronized receiver input signal to the receiver. setting the c1[rsrc] bit connects the receiver input to the output of the txd pin driver. both the transmitter and receiver must be enabled (c2[te] = 1 and c2[re] = 1). when c7816[iso_7816en] is set, it is not a requirement that both c2[te] and c2[re] are set. 51.4.6 loop operation in loop operation the transmitter output goes to the receiver input. the unsynchronized receiver input signal is disconnected from the uart. rxd tx pin output rxinv txinv transmitter receiver figure 51-211. loop operation (c1[loops] = 1, c1[rsrc] = 0) enable loop operation by setting the c1[loops] bit and clearing the c1[rsrc] bit. setting the c1[loops] bit disables the path from the unsynchronized receiver input signal to the receiver. clearing the c1[rsrc] bit connects the transmitter output to the receiver input. both the transmitter and receiver must be enabled (c2[te] = 1 and c2[re] = 1). when c7816[iso_7816en] is set, it is not a requirement that both c2[te] and c2[re] are set. 51.4.7 iso-7816 / smartcard support the uart provides mechanisms to support the iso-7816 protocol that is commonly used to interface with smartcards. the iso-7816 protocol is an nrz, single wire, half- duplex interface. the txd pin is used in open-drain mode since the data signal is used for both transmitting and receiving. there are multiple subprotocols within the iso-7816 standard. the uart supports both t = 0 and t = 1 protocols. the module also provides for automated initial character detection and configuration which allows for support of both direct convention and inverse convention data formats. a variety of interrupts specific to 7816 are provided in addition to the general interrupts to assist software. chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1549 additionally the module is able to provide automated nack responses and has programing automated retransmission of failed packets. an assortment of programmable timeouts and guard band times are also supported. the term elemental time unit (etu) is frequently used in the context of iso-7816. this concept is used to relate the frequency that the system (uart) is running at and the frequency that data is being transmitted and received. one etu represents the time it takes to transmit or receive a single bit. for example, a standard 7816 packet, excluding any guard time or nack elements is 10 etus (start bit, 8 data bits and a parity bit). guard times and wait times are also measured in etus. note the iso-7816 specification may have certain configuration options that are reserved. in order to maintain maximum flexibility to support future 7816 enhancements or devices which may not strictly conform to the specification, the uart does not prevent those options being used. further, the uart may provide configuration options that exceed the flexibility of options explicitly allowed by the 7816 specification. failure to correctly configure the uart may result in unexpected behavior or incompatibility with the iso-7816 specification. 51.4.7.1 initial characters in iso-7816 mode, the uart can be configured to use the c7816[init] bit to detect the next valid initial character, referred to by the iso-7816 specifically as a ts character. when the initial character is detected, the uart provides the host processor with an interrupt if ie7816[initde] is set. additionally, the uart will set the s2[msbf], c3[txinv] and s2[rxinv] register fields automatically based on the initial character. the corresponding initial character and resulting register settings are listed in the following table. table 51-204. initial character automated settings initial character (bit 1-10) initial character (hex) msbf txinv rxinv lhhl lll llh inverse convention 3f 1 1 1 lhhl hhh llh direct convention 3b 0 0 0 functional description k60 sub-family reference manual, rev. 6, nov 2011 1550 freescale semiconductor, inc. when the c7816[init] bit is set, the receiver will search all received data for the first valid initial character. all data received which is not a valid initial character will be ignored and all flags resulting from the invalid data will be blocked from asserting. if the c7816[anack] bit is set, a nack will be returned for invalid received initial characters and a rxt interrupt will be generated as programmed. 51.4.7.2 protocol t = 0 when t = 0 protocol is selected, a relatively complex error detection scheme is used. data characters are formatted as illustrated in the following figure. this scheme is also used for answer to reset and pps formats. bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit stop bit parity next start bit start bit iso 7816 format without parity error (t=0) stop bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit stop bit parity next start bit start bit nack error iso 7816 format with parity error (t=0) figure 51-212. iso-7816 t = 0 data format as with other protocols supported by the uart the data character includes a start bit. however, in this case there are two stop bits rather than the typical single stop bit. in addition to a standard even parity check, the receiver has the ability to generate and return a nack during the second half of the first stop bit period. the nack must be at least one time period (etu) in length and no more than 2 time periods (etu) in length. the transmitter must wait for at least two time units (etu) after detection of the error signal before attempting to retransmit the character. it is assumed that the uart and the device (smartcard) know in advance which device is receiving and which is transmitting. no special mechanism is supplied by the uart to control receive and transmit in the mode other than the c2[te] and c2[re] bits. 51.4.7.3 protocol t = 1 when t = 1 protocol is selected the nack error detection scheme is not used. rather, the parity bit is used on a character basis and a crc or lrc is used on the block basis (i.e. each group of characters). as such, in this mode the data format allows for a single stop bit although additional inactive bit periods may be present between the stop bit and the next start bit. data characters are formatted as illustrated in the following figure. chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1551 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit stop bit parity next start bit start bit iso 7816 format (t=1) figure 51-213. iso 7816 t=1 data format the smallest data unit that is transferred is a block. a block is made up of several data characters and may vary in size depending on the block type. the uart does not provide a mechanism to decode the block type. as part of the block, an lrc or crc is included. the uart does not calculate the crc or lrc for transmitted blocks nor does it verify the validity of the crc or lrc for received blocks. the 7816 protocol requires that the initiator and the smartcard (device) takes alternate turns in transmitting and receiving blocks. when the uart detects that the last character in a block has been transmitted it will automatically clear the c2[te] bit and enter receive mode. hence, software must program the transmit buffer with the next data to be transmitted and then enable the c2[te] bit once software has determined that the last character of the received block has been received. the uart detects that the last character of the transmit block has been sent when tl7816[tlen] = 0 and four additional characters have been sent. the four additional characters are made up of three prior to tl7816[tlen] decrementing (prologue) and one after tl7816[tlen] = 0, the final character of the epilogue. 51.4.7.4 wait time and guard time parameters the iso-7816 specification defines several wait time and guard time parameters. the uart allows for flexible configuration and violation detection of these settings. on reset the wait time (is7816[wt]) defaults to 9600 etus and guard time (gt) to 12 etus. these values are controlled by parameters in the wp7816, wn7816 and wf7816 registers. additionally the value of c7816[ttype] also factors into the calculation. the formulas used to calculate the number etu for each wait time and guard time value are shown in the following table. wait time (wt) is defined as the maximum allowable time between the leading edge of a character transmitted by the device (smartcard) and the leading edge of the previous character that was transmitted by the uart or the device. likewise character wait time (cwt) is defined as the maximum allowable time between the leading edge of two characters within the same block, and block wait time (bwt) is defined as the maximum time between the leading edge character of the last block received by the device/ smartcard and the leading edge of the first character transmitted by the device/smartcard. guard time (gt) is defined as the minimum allowable time between the leading edge of two consecutive characters. character guard time (cgt) is the minimum allowable time between the leading edges of two consecutive characters in the same direction functional description k60 sub-family reference manual, rev. 6, nov 2011 1552 freescale semiconductor, inc. (transmission or reception). block guard time (bgt) is the minimum allowable time between the leading edges of two consecutive characters in opposite directions (transmission then reception or reception then transmission). the gt and wt counters reset whenever c7816[ttype] = 1 or c7816[iso_7816e] = 0 or a new dataword start bit has been received or transmitted as specified by the counter descriptions. the cwt, cgt, bwt, bgt counters reset whenever c7816[ttype] = 0 or c7816[iso_7816e] = 0 or a new dataword start bit has been received or transmitted as specified by the counter descriptions. when c7816[ttype] = 1 some of the counter values require an assumption regarding the first data transferred when the uart first starts. this assumption is required when the 7816e has been disabled, when transition from c7816[ttype] = 0 to c7816[ttype] = 1 or when coming out of reset. in this case, it is assumed that the previous (non-existent) transfer was a received transfer. the uart will automatically handle gt, cgt and bgt such that the uart will not send a packet prior to the corresponding guard time expiring. table 51-205. wait and guard time calculations parameter reset value [etu] c7816[ttype] = 0 [etu] c7816[ttype] = 1 [etu] wait time (wt) 9600 wi 960 gtfd not used character wait time (cwt) not used not used 11 + 2 cwi block wait time (bwt) not used not used 11 + 2 bwi 960 gtfd guard time (gt) 12 gtn not wqual to 255 12 + gtn gtn wqual to 255 12 not used character guard time (cgt) not used not used gtn not equal to 255 12 + gtn gtn equal to 255 11 block guard time (bgt) not used not used 22 51.4.7.5 baud rate generation the value in wf7816[gtfd] does not impact the clock frequency. the sbr and brfd are used to generate the clock frequency. this clock frequency is used by the uart only and is not seen by the device (smartcard). the transmitter clocks operates at 1/16 the frequency of the receive clock so that the receiver is able to sample the received value 16 times during the etu. chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1553 51.4.7.6 uart restrictions in iso-7816 operation due to the flexibility of the uart module, there are several features and interrupts that are not supported while running in iso-7816 mode. these restrictions are documented within the register bit definitions. 51.4.8 infrared interface the uart provides the capability of transmitting narrow pulses to an ir led and receiving narrow pulses and transforming them to serial bits, which are sent to the uart. the irda physical layer specification defines a half-duplex infrared communication link for exchanging data. the full standard includes data rates up to 16 mbits/s. this design covers data rates only between 2.4 kbits/s and 115.2 kbits/s. the uart has an infrared transmit encoder and receive decoder. the uart transmits serial bits of data which are encoded by the infrared submodule to transmit a narrow pulse for every zero bit. no pulse is transmitted for every one bit. when receiving data, the ir pulses are detected using an ir photo diode and transformed to cmos levels by the ir receive decoder (external from the mcu). the narrow pulses are then stretched by the infrared receive decoder to get back to a serial bit stream to be received by the uart. the polarity of transmitted pulses and expected receive pulses can be inverted so that a direct connection can be made to external irda transceiver modules that use active low pulses. the infrared submodule receives its clock sources from the uart. one of these two clocks are selected in the infrared submodule in order to generate either 3/16, 1/16, 1/32 or 1/4 narrow pulses during transmission. 51.4.8.1 infrared transmit encoder the infrared transmit encoder converts serial bits of data from transmit shift register to the txd signal. a narrow pulse is transmitted for a zero bit and no pulse for a one bit. the narrow pulse is sent in the middle of the bit with a duration of 1/32, 1/16, 3/16 or 1/4 of a bit time. a narrow high pulse is transmitted for a zero bit when c3[txinv] is cleared, while a narrow low pulse is transmitted for a zero bit when c3[txinv] is set. functional description k60 sub-family reference manual, rev. 6, nov 2011 1554 freescale semiconductor, inc. 51.4.8.2 infrared receive decoder the infrared receive block converts data from the rxd signal to the receive shift register. a narrow pulse is expected for each zero received and no pulse is expected for each one received. a narrow high pulse is expected for a zero bit when s2[rxinv] is cleared, while a narrow low pulse is expected for a zero bit when s2[rxinv] is set. this receive decoder meets the edge jitter requirement as defined by the irda serial infrared physical layer specification. 51.5 reset all registers reset to a particular value are indicated in memory map and registers . 51.6 system level interrupt sources there are several interrupt signals that are sent from the uart. the following table lists the interrupt sources generated by the uart. the local enables for the uart interrupt sources are described in this table. details regarding the individual operation of each interrupt are contained under various sub-sections of memory map and registers . however, rxedgif description also outlines additional details regarding the rxedgif interrupt because of its complexity of operation. any of the uart interrupt requests listed in the table can be used to bring the cpu out of wait mode. table 51-206. uart interrupt sources interrupt source flag local enable dma select transmitter tdre tie tdmas = 0 transmitter tc tcie - receiver idle ilie - receiver rdrf rie rdmas = 0 receiver lbkdif lbkdie - receiver rxedgif rxedgie - receiver or orie - receiver nf neie - receiver fe feie - receiver pf peie - receiver rxuf rxufe - transmitter txof txofe - table continues on the next page... chapter 1 universal asynchronous receivertransmitter uart 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1 table 51-206. uart interrupt sources (continued) interrupt source flag local enable dma select receiver wt wtwe - receiver cwt cwte - receiver bwt bwte - receiver initd initde - receiver txt txte - receiver rxt rxte - receiver gtv gtve - 51.6.1 rxedgif description the s2[rxedgif] is set when an active edge is detected on the rxd pin. hence, the active edge can only be detected when in two wire mode. a rxedgif interrupt is only generated when s2[rxedgif] is set. if rxedgie is not enabled prior to s2[rxedgif] getting set, an interrupt is not generated until s2[rxedgif] bit gets set. 51.6.1.1 rxd edge detect sensitivity edge sensitivity can be software programmed to be either falling or rising. the polarity of the edge sensitivity is selected using the s2[rxinv] bit. to detect falling edge s2[rxinv] is programmed to zero and to detect rising edge s2[rxinv] is programmed to one. synchronizing logic is used prior to detect edges. prior to detecting an edge, the receive data on rxd input must be at the de-asserted logic level. a falling edge is detected when the rxd input signal is seen as a logic 1 (the deasserted level) during one module clock cycle and then a logic 0 (the asserted level) during the next cycle. a rising edge is detected when the input is seen as a logic 0 during one module clock cycle and then a logic 1 during the next cycle. 51.6.1.2 clearing rxedgif interrupt request writing a logic 1 to the s2[rxedgif] bit immediately clears the rxedgif interrupt request even if the rxd input remains asserted. s2[rxedgif] will remain set if another active edge is detected on rxd while attempting to clear the s2[rxedgif] flag by writing a 1 to it. system level interrupt sources k60 sub-family reference manual, rev. 6, nov 2011 1556 freescale semiconductor, inc. 51.6.1.3 exit from low-power modes the receive input active edge detect circuit is still active on low power modes (wait and stop). an active edge on the receive input brings the cpu out of low power mode if the interrupt is not masked (s2[rxedgif]=1). 51.7 dma operation in the transmitter, flags s1[tdre] can be configured to assert a dma transfer request. in the receiver, flag s1[rdrf], can be configured to assert a dma transfer request. the following table shows the configuration bit settings required to configure each flag for dma operation. table 51-207. dma configuration flag request enable bit dma select bit tdre tie = 1 tdmas = 1 rdrf rie = 1 rdmas = 1 when a flag is configured for a dma request, its associated dma request is asserted when the flag is set. when the s1[rdrf] flag is configured as a dma request, the clearing mechanism of reading s1 register followed by reading d register does not clear the associated flag. the dma request remains asserted until an indication is received that the dma transactions are done. when this indication is received, the flag bit and the associated dma request are cleared. if the dma operation failed to remove the situation that caused the dma request another request will be issued. 51.8 application information this section describes the uart application information. 51.8.1 transmit/receive data buffer operation the uart has independent receive and transmit buffers. the size of these buffers may vary depending on the implementation of the module. the implemented size of the buffers is a fixed constant via the pfifo[txfifosize] and pfifo[rxfifosize] fields. additionally, legacy support is provided that allows for the fifo structure to chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1557 operate as a depth of one. this is the default/reset behavior of the module and can be adjusted using the pfifo[rxfe] and pfifo[txfe] bits. individual watermark levels are also provided for transmit and receive. there are multiple ways to ensure that a data block (set of characters) has completed transmission. these methods include: 1. set txfifo[txwater] to 0. the tdre flag will assert when there is no further data in the transmit buffer. alternatively the s1[tc] flag can be used to indicate when the transmit shift register is also empty. 2. poll the tcfifo[txcount] field. assuming that only data for a data block has been put into the data buffer, when tcfifo[txcount] = 0 all data has been transmitted or is in the process of transmission. 3. the s1[tc] flag can be monitored. when s1[tc] asserts it indicates that all data has been transmitted and there is no data currently being transmitted in the shift register. 51.8.2 iso-7816 initialization sequence this section outlines how to program the uart for iso-7816 operation. elements such as procedures to power up or power down the smartcard, and when to take those actions, are beyond the scope of this description. to setup the uart for iso-7816 operation: 1. select a baud rate. write this value to the uart baud registers (bdh/l) to begin the baud rate generator. remember that the baud rate generator is disabled when the baud rate is zero. writing to the bdh has no effect without also writing to bdl. according to the 7816 specification the initial (default) baud rating setting should be fi = 372 and di = 1 and a maximum frequency of 5 mhz. in other words the bdh, bdl and c4 registers should be programmed such that the transmission frequency should be 1/372th of the clock provided to the smartcard device and should not exceed 5 mhz. 2. write to set bdh[lbkdie] = 0. 3. write to c1 to configure word length, parity, and other configuration bits (loops, rsrc) and set c1[m] = 1, c1[pe] = 1, c1[pt] = 0. 4. write to set s2[rwuid] = 0, s2[lbkde] = 0. 5. write to set modem[rxrtse] = 0, modem[txrtspol] = 0, modem[txrtse] = 0, and modem[txctse] = 0. application information k60 sub-family reference manual, rev. 6, nov 2011 1558 freescale semiconductor, inc. 6. write to set up interrupt enable bits desired (c3[orie], c3[neie], c3[peie], and c3[feie]) 7. write to set c4[maen1] = 0 and c4[maen2] = 0. 8. write to c5 register and configure dma control register bits as desired for application. 9. write to set c7816[init] = 1,c7816[ ttype] = 0, 7c7816[iso_7816e] = 1. program c7816[onack] and c7816[anack] as desired. 10. write to ie7816 register to set interrupt enable parameters as desired. 11. write to et7816 register and set as desired. 12. write to set c2[ilie] = 0, c2[re] = 1, c2[te] = 1, c2[rwu] = 0 and c2[sbk] = 0. setup interrupt enables c2[tie], c2[tcie] and c2[rie] as desired. at this time the uart will start listening for an initial character. once identified it will automatically adjust the s2[msbf], c3[txinv] and s2[rxinv] bits. the software should then receive and process an answer to reset. upon processing the answer to reset software should write to set c2[re] = 0 and c2[te] = 0. software should then adjust 7816 specific and uart generic parameters to match and configuration data that was received during the answer on reset period. once the new settings have been programmed (including the new baud rate and c7816[ttype]) the c2[re] and c2[te] can be re- enabled as required. 51.8.2.1 transmission procedure for (c7816[ttype] = 0) when the protocol selected is c7816[ttype] = 0, it is assumed that the software has a prior knowledge of who should be transmitting and receiving. hence, no mechanism is provided for automated transmission/receipt control. software should monitor the s1[tdre] flag (or configure for an interrupt) and provide additional data for transmission as appropriate. additionally, software should set c2[te] = 1 and control txdir whenever it is the uart's turn to transmit information. for ease of monitoring it is suggested that only data to be transmitted until the next receiver/transmit switch over be loaded into the transmit buffer/fifo. chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1559 51.8.2.2 transmission procedure for (c7816[ttype] = 1) when the protocol selected is c7816[ttype] = 1, data is transferred in blocks. prior to starting a transmission software should write the size (number of bytes) for the information field portion of the block in to the tlen register. if a crc is being transmitted for the block the value in tlen should be one more than the size of the information field. software should then set c2[te] = 1, and c2[re] = 1. software should then monitor the s1[tdre] flag / interrupt and write the prologue, information and epilogue field to the transmit buffer. the tlen register will automatically decrement (except for prologue bytes and the final epilogue byte). when the final epilogue byte has been transmitted the uart automatically clears the c2[te] bit to 0, and the uart automatically starts capturing the response to the block that was transmitted. once software has detected the receipt of the response, the transmission process should be repeated as needed with sufficient urgency to ensure that the block wait time and character wait times are not violated. 51.8.3 initialization sequence (non iso-7816) to initiate an uart transmission: 1. configure the uart: a. select a baud rate. write this value to the uart baud registers (bdh/l) to begin the baud rate generator. remember that the baud rate generator is disabled when the baud rate is zero. writing to the bdh register has no effect without also writing to bdl register. b. write to c1 register to configure word length, parity, and other configuration bits (loops, rsrc, m, wake, ilt, pe, pt). write to c4, ma1 and ma2 register to configure. c. enable the transmitter, interrupts, receiver, and wakeup as required by writing to the c2 register bits (tie, tcie, rie, ilie, te, re, rwu, sbk), s2 register bits (msbf, brk13) and c3 register bits (orie, neie, peie, feie). a preamble or idle character is then shifted out of the transmitter shift register. 2. transmit procedure for each byte: a. monitor the s1[tdre] flag by reading the s1 or responding to the tdre interrupt. or monitor the amount of free space in the transmit buffer directly using tcfifo[txcount]. application information k60 sub-family reference manual, rev. 6, nov 2011 1560 freescale semiconductor, inc. b. if the tdre flag is set, or there is space in the transmit buffer, write the data to be transmitted to (c3[t8]/d). a new transmission will not result until data exists in the transmit buffer. 3. repeat step 2 for each subsequent transmission. note during normal operation, the s1[tdre] flag is set when the shift register is loaded with the next data to be transmitted from the transmit buffer and the number of datawords contained in the transmit buffer is less than or equal to the value in twfifo[txwater], which occurs 9/16ths of a bit time after the start of the stop bit of the previous frame. to separate messages with preambles with minimum idle line time, use this sequence between messages: 1. write the last dataword of the first message to c3[t8]/d. 2. wait for the s1[tdre] flag to go high (with twfifo[txwater] = 0), indicating the transfer of the last frame to the transmit shift register. 3. queue a preamble by clearing and then setting the c2[te] bit. 4. write the first (and subsequent) datawords of the second message to c3[t8]/d. 51.8.4 overrun (or) flag implications to be flexible the overrun flag (or) operates slight differently depending on the mode of operation. as such there may be implications that need to be carefully considered. this section clarifies that behavior and the resulting implications. regardless of mode, if a dataword is received while the s1[or] flag is set, the s1[rdrf] and s1[idle] flags are blocked from asserting. if the s1[rdrf] or s1[idle] flag were previously asserted they will remain asserted until cleared. 51.8.4.1 overrun operation the assertion of the s1[or] flag indicates that a significant event has occurred. the assertion indicates that received data has been lost since there was a lack of room to store it in the data buffer. hence, while the s1[or] flag is set no further data will be stored in the data buffer until the s1[or] flag is cleared. this ensures that the application will be able to handle the overrun condition. chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1561 in most applications since the total amount of lost data is known, the application will desire to return the system to a known state. prior to the s1[or] flag being cleared all received data will be dropped. to do this the software would: 1. remove data from the receive data buffer. this could be done by reading data from the data buffer and processing it if the data in the fifo was still valuable when though the overrun event occurred or using the cfifo[rxflush] bit to clear the buffer. 2. clear the s1[or] flag. note that if data was cleared using the cfifo[rxflush] bit, then clearing the s1[or] flag will result in the sfifo[rxuf] flag asserting because the only way to clear the s1[or] requires reading additional information from the fifo. care should be taken to disable the sfifo[rxuf] interrupt prior to clearing the or flag and then clearing the sfifo[rxuf] flag after the or flag has been cleared. note that in some applications if an overrun event is responded to fast enough, the lost data can be recovered. for example when c7816[iso_7816e] is asserted, c7816[ttype]=1 and c7816[onack] = 1 the application may reasonably be able to determine if the lost data will be resent by the device. in this scenario flushing the receiver data buffer might not be required. rather, if the s1[or] flag is cleared the lost data may be resent and hence recoverable. when lin break detect (lbkde) is asserted the s1[or] flag has significantly different behavior than in other modes. the s1[or] bit will be set, regardless of how much space is actually available in the data buffer, if a lin break character has been detected and the corresponding flag (s2[lbkdif]) is not cleared before the first data character is received after the s2[lbkdif] asserted. this behavior is intended to allow software sufficient time to read the lin break character from the data buffer to ensure that a break character was actually detected. the checking of the break character was used on some older implementations and is hence supported for legacy reasons. applications that do not require this checking can simply clear the s2[lbkdif] without checking the stored value to ensure it is a break character. 51.8.5 overrun nack considerations when c7816[iso_7816e] is enabled and c7816[ttype] = 0 the retransmission feature of the 7816 protocol can be used to help avoid lost data when the data buffer overflows. using c7816[onack] the module can be programmed to issue a nack on an overflow event. assuming that the device (smartcard) has implemented retransmission, the lost data will be retransmitted. while useful, there is a programming implication which may require special consideration. the need to transmit a nack must be determined and application information k60 sub-family reference manual, rev. 6, nov 2011 1562 freescale semiconductor, inc. committed to prior to the dataword being fully received. while the nack is being received it is possible that the application code will read the data buffer such that sufficient room will be made to store the dataword that is being nacked. even if room has been made in the data buffer once the transmission of a nack is completed, the received data will always be discarded as a result of an overflow and the et7816[rxthreshold] value will be incremented by one. however, if sufficient space now exists to write the received data which was nack'ed the s1[or] flag will be blocked and kept from asserting. 51.8.6 match address registers the two match address registers allow a second match address function for a broadcast or general call address to the serial bus, as an example. 51.8.7 modem feature this section describes the modem features. 51.8.7.1 ready-to-receive using rts to help to stop overrun of the receiver data buffer, the rts signal can be used by the receiver to indicate to another uart that it is ready to receive data. the other uart can send the data when its cts signal is asserted. this handshaking conforms to the tia-232-e standard. a transceiver is necessary if the required voltage levels of the communication link do not match the voltage levels of the uart's rts and cts signals. transmitter uart receiver transmitter uart receiver txd cts_b rxd rts_b rxd rts_b txd cts_b figure 51-214. ready-to-receive the transmitter's cts signal can be used for hardware flow control whether its rts signal is used for hardware flow control, transceiver driver enable, or not at all. chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1563 51.8.7.2 transceiver driver enable using rts rs-485 is a multiple drop communication protocol in which the uart transceiver's driver is 3-stated unless that uart is driving. the rts signal can be used by the transmitter to enable the driver of a transceiver. the polarity of rts can be matched to the polarity of the transceiver's driver enable signal. refer to the following figure. transmitter uart receiver driver rs-485 transceiver receiver txd rts_b rxd di de ro re_b y z a b figure 51-215. transceiver driver enable using rts in the figure, the receiver enable signal is asserted. another option for that connection is to connect rts_b to both de and re_b. the transceiver's receiver is disabled while driving. a pullup can pull rxd to a non-floating value during this time. this option can be refined further by operating the uart in single-wire mode, freeing the rxd pin for other uses. 51.8.8 irda minimum pulse width the irda specifies a minimum pulse width of 1.6 s. the uart hardware does not include a mechanism to restrict/force the pulse width to be greater than or equal to 1.6 s. however, configuring the baud rate to 115.2 kbit/s and the narrow pulse width to 3/16 of a bit time results in a pulse width of 1.6 s. 51.8.9 clearing 7816 wait timer (wt, bwt, cwt) interrupts the 7816 wait timer interrupts associated with is7816[wt], is7816[bwt] and is7816[cwt] will automatically reassert if they are cleared and the wait time is still violated. this behavior is similar to most of the other interrupts on the uart as in most cases if the condition that caused the interrupt to trigger still exists when the interrupt is cleared, than the interrupt will reassert. for example, consider the following scenario: 1. is7816[wt] is programmed to assert after 9600 cycles of unresponsiveness. 2. the 9600 cycles pass without a response resulting in the wt interrupt asserting. 3. the is7816[wt] is cleared at cycle 9700 by the interrupt service routine. application information k60 sub-family reference manual, rev. 6, nov 2011 1564 freescale semiconductor, inc. 4. after the wt interrupt has been cleared, the smartcard remains unresponsive. at cycle 9701 the wt interrupt will reasserted. if the intent of clearing the interrupt is such that it does not reassert, the interrupt service routine must remove or clear the condition that originally caused the interrupt to assert prior to clearing the interrupt. there are multiple ways that this can be accomplished including ensuring that an event that results in the wait timer resetting occurs such as the transmission of another packet. 51.8.10 legacy and reverse compatibility considerations recent versions of the uart have added several new features. whenever reasonably possible reverse compatibility was maintained, however, in some cases this was either not feasible or the behavior was deemed as not intended. this section describes several differences to legacy operation that resulted from these recent enhancements. if application codes from previous versions is used, they should be reviewed and modified to take the following items into account. depending on the application code, additional items that are not listed here may also need to be considered. 1. various reserved registers and register bits were used (i.e. msfb and m10). 2. this module now generates an error when invalid address spaces are used. 3. while documentation indicated otherwise, in some cases it was possible for s1[idle] to assert even if s1[or] was set. 4. the s1[or] flag will only be set if the data buffer (fifo) does not have sufficient room. previously, the data buffer was always a fixed size of one and the s1[or] flag would set so long as the s1[rdrf] flag was set even if there was room in the data buffer. while the clearing mechanism is has remained the save for the s1[rdrf] flag, keeping the or flag assertion tied to the rdrf event rather than the data buffer being full would have greatly reduced the usefulness of the buffer when its size is larger than one. 5. previously when the c2[rwu] was set (and wake = 0), the idle flag could reassert up to every bit period causing an interrupt and requiring the host processor to reassert the c2[rwu] bit. this behavior has been modified. now, when the c2[rwu] is set (and wake = 0) at least one non-idle bit must be detected before an idle can be detected. chapter 51 universal asynchronous receiver/transmitter (uart) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1565 application information k60 sub-family reference manual, rev. 6, nov 2011 1566 freescale semiconductor, inc. chapter 52 secured digital host controller (sdhc) 52.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the chapter is intended for a module driver software developer. it describes module-level operation and programming. 52.2 overview 52.2.1 supported types of cards different types of cards supported by the sdhc are described briefly as follows: the multi-media card (mmc) is a universal low cost data storage and communication media that is designed to cover a wide area of applications including mobile video and gaming. old mmc cards are based on a 7-pin serial bus with a single data pin, while the new high speed mmc communication is based on an advanced 11-pin serial bus designed to operate in the low voltage range. the secure digital card (sd) is an evolution of the old mmc technology. it is specifically designed to meet the security, capacity, performance, and environment requirements inherent in newly emerging audio and video consumer electronic devices. the physical form factor, pin assignment and data transfer protocol are forward compatible with the old mmc (with some additions). under the sd protocol, it can be categorized into memory card, i/o card and combo card, which has both memory and i/o functions. the memory card invokes a copyright protection mechanism that complies with the security of the sdmi standard. the i/o k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1567 card, which is also known as sdio card, provides high-speed data i/o with low power consumption for mobile electronic devices. for the sake of simplicity, the figure does not show cards with reduced size or mini cards. mmc/sd/sdio dma interface transceiver crossbar switch card slot power supply mmc card host controller peripheral bus sd card sdio card figure 52-1. system connection of the sdhc ce-ata is a hard drive interface that is optimized for embedded applications storage. the device is layered on the top of the mmc protocol stack using the same physical interface. the interface electrical and signaling definition is defined like that in the mmc specification. refer to the ce-ata specification for more details. overview k60 sub-family reference manual, rev. 6, nov 2011 1568 freescale semiconductor, inc. 52.2.2 sdhc block diagram cmd/ data channel tx/rx handler data channel state machine sd bus monitor & gating logic control logic control cmd channel state machine crc crc crc advanced dma interface register bank r/w interrupt controller status register peripheral bus clocks interrupt internal dual-port 128x32-bit buffer ram clock controller and reset manager dat0 sd_clk sd_cd# sd_wp dat1 dat2 dat3 dat4 dat5 dat6 dat7 cmd sd_lctl sd_vs configurable buffer controller crossbar switch master port dma request figure 52-2. enhanced secure digital host controller block diagram 52.2.3 features the features of the sdhc module include the following: ? conforms to the sd host controller standard specification version 2.0 including test event register support ? compatible with the mmc system specification version 4.2/4.3 ? compatible with the sd memory card specification version 2.0 and supports the high capacity sd memory card ? compatible with the sdio card specification version 2.0 ? compatible with the ce-ata card specification version 1.0 chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1569 ? designed to work with ce-ata, sd memory, minisd memory, sdio, minisdio, sd combo, mmc, mmc plus, and mmc rs cards ? card bus clock frequency up to 52 mhz ? supports 1-bit / 4-bit sd and sdio modes, 1-bit / 4-bit / 8-bit mmc modes, 1-bit / 4-bit / 8-bit ce-ata devices ? up to 200 mbps of data transfer for sd/sdio cards using 4 parallel data lines ? up to 416 mbps of data transfer for mmc cards using 8 parallel data lines in sdr (single data rate) mode ? supports single block, multi-block read and write ? supports block sizes of 1 ~ 4096 bytes ? supports the write protection switch for write operations ? supports both synchronous and asynchronous abort (both hardware and software cmd12) ? supports pause during the data transfer at block gap ? supports sdio read wait and suspend resume operations ? supports auto cmd12 for multi-block transfer ? host can initiate non-data transfer command while data transfer is in progress ? allows cards to interrupt the host in 1-bit and 4-bit sdio modes, also supports interrupt period ? embodies a fully configurable 128x32-bit fifo for read/write data ? supports internal and external dma capabilities ? supports advanced dma to perform linked memory access 52.2.4 modes and operations the sdhc can select the following modes for data transfer: ? sd 1-bit ? sd 4-bit ? mmc 1-bit overview k60 sub-family reference manual, rev. 6, nov 2011 1570 freescale semiconductor, inc. ? mmc 4-bit ? mmc 8-bit ? ce-ata 1-bit ? ce-ata 4-bit ? ce-ata 8-bit ? identification mode (up to 400 khz) ? mmc full speed mode (up to 20 mhz) ? mmc high speed mode (up to 52 mhz) ? sd/sdio full speed mode (up to 25 mhz) ? sd/sdio high speed mode (up to 50 mhz) 52.3 sdhc signal descriptions table 52-1. sdhc signal descriptions signal description i/o sdhc_dclk generated clock used to drive the mmc, sd, sdio or ce-ata cards. o sdhc_cmd send commands to and receive responses from the card. i/o sdhc_d0 dat0 line or busy-state detect i/o sdhc_d1 8-bit mode: dat1 line 4-bit mode: dat1 line or interrupt detect 1-bit mode: interrupt detect i/o sdhc_d2 4-/8-bit mode: dat2 line or read wait 1-bit mode: read wait i/o sdhc_d3 4-/8-bit mode: dat3 line or configured as card detection pin 1-bit mode: may be configured as card detection pin i/o sdhc_d4 dat4 line in 8-bit mode not used in other modes i/o sdhc_d5 dat5 line in 8-bit mode not used in other modes i/o table continues on the next page... chapter 2 secured digital host controller sdhc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 171 table 52-1. sdhc signal descriptions (continued) signal description i/o sdhc_d6 dat6 line in 8-bit mode not used in other modes i/o sdhc_d7 dat7 line in 8-bit mode not used in other modes i/o 52.4 memory map and register definition this section includes the module memory map and detailed descriptions of all registers. sdhc memory map absolute address (hex) register name width (in bits) access reset value section/ page 400b_1000 dma system address register (sdhc_dsaddr) 32 r/w 0000_0000h 52.4.1/ 1573 400b_1004 block attributes register (sdhc_blkattr) 32 r/w 0000_0000h 52.4.2/ 1574 400b_1008 command argument register (sdhc_cmdarg) 32 r/w 0000_0000h 52.4.3/ 1575 400b_100c transfer type register (sdhc_xfertyp) 32 r/w 0000_0000h 52.4.4/ 1576 400b_1010 command response 0 (sdhc_cmdrsp0) 32 r 0000_0000h 52.4.5/ 1580 400b_1014 command response 1 (sdhc_cmdrsp1) 32 r 0000_0000h 52.4.6/ 1581 400b_1018 command response 2 (sdhc_cmdrsp2) 32 r 0000_0000h 52.4.7/ 1581 400b_101c command response 3 (sdhc_cmdrsp3) 32 r 0000_0000h 52.4.8/ 1581 400b_1020 buffer data port register (sdhc_datport) 32 r/w 0000_0000h 52.4.9/ 1583 400b_1024 present state register (sdhc_prsstat) 32 r 0000_0000h 52.4.10/ 1583 400b_1028 protocol control register (sdhc_proctl) 32 r/w 0000_0020h 52.4.11/ 1588 400b_102c system control register (sdhc_sysctl) 32 r/w 0000_8008h 52.4.12/ 1592 table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 172 freescale semiconductor, inc. sdhc memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 400b_1030 interrupt status register (sdhc_irqstat) 32 r/w 0000_0000h 52.4.13/ 1595 400b_1034 interrupt status enable register (sdhc_irqstaten) 32 r/w 117f_013fh 52.4.14/ 1601 400b_1038 interrupt signal enable register (sdhc_irqsigen) 32 r/w 0000_0000h 52.4.15/ 1604 400b_103c auto cmd12 error status register (sdhc_ac12err) 32 r 0000_0000h 52.4.16/ 1606 400b_1040 host controller capabilities (sdhc_htcapblt) 32 r 07f3_0000h 52.4.17/ 1609 400b_1044 watermark level register (sdhc_wml) 32 r/w 0010_0010h 52.4.18/ 1611 400b_1050 force event register (sdhc_fevt) 32 w (always reads zero) 0000_0000h 52.4.19/ 1611 400b_1054 adma error status register (sdhc_admaes) 32 r 0000_0000h 52.4.20/ 1614 400b_1058 adma system address register (sdhc_adsaddr) 32 r/w 0000_0000h 52.4.21/ 1616 400b_10c0 vendor specific register (sdhc_vendor) 32 r/w 0000_0001h 52.4.22/ 1616 400b_10c4 mmc boot register (sdhc_mmcboot) 32 r/w 0000_0000h 52.4.23/ 1618 400b_10fc host controller version (sdhc_hostver) 32 r 0000_1201h 52.4.24/ 1619 52.4.1 dma system address register (sdhc_dsaddr) this register contains the physical system memory address used for dma transfers. address: sdhc_dsaddr is 400b_1000h base + 0h offset = 400b_1000h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r dsaddr 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sdhc_dsaddr field descriptions field description 31?2 dsaddr dma system address table continues on the next page... chapter 2 secured digital host controller sdhc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 17 sdhc_dsaddr field descriptions (continued) field description this register contains the 32-bit system memory address for a dma transfer. since the address must be word (4 bytes) align, the least 2 bits are reserved, always 0. when the sdhc stops a dma transfer, this register points to the system address of the next contiguous data position. it can be accessed only when no transaction is executing (i.e. after a transaction has stopped). read operation during transfers may return an invalid value. the host driver shall initialize this register before starting a dma transaction. after dma has stopped, the system address of the next contiguous data position can be read from this register. this register is protected during a data transfer. when data lines are active, write to this register is ignored. the host driver shall wait, until the prsstat[dla] is cleared, before writing to this register. the sdhc internal dma does not support a virtual memory system. it only supports continuous physical memory access. and due to ahb burst limitations, if the burst must cross the 1 kb boundary, sdhc will automatically change seq burst type to nseq. since this register supports dynamic address reflecting, when irqstat[tc] bit is set, it automatically alters the value of internal address counter, so sw cannot change this register when irqstat[tc] bit is set. 10 reserved this read-only field is reserved and always has the value zero. 52.4.2 block attributes register (sdhc_blkattr) this register is used to configure the number of data blocks and the number of bytes in each block. address: sdhc_blkattr is 400b_1000h base + 4h offset = 400b_1004h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r blkcnt 0 blksize w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sdhc_blkattr field descriptions field description 31?16 blkcnt blocks count for current transfer this register is enabled when the xfertyp[bcen] is set to 1 and is valid only for multiple block transfers. for single block transfer, this register will always read as 1. the host driver shall set this register to a value between 1 and the maximum block count. the sdhc decrements the block count after each block transfer and stops when the count reaches zero. setting the block count to 0 results in no data blocks being transferred. this register should be accessed only when no transaction is executing (that is after transactions are stopped). during data transfer, read operations on this register may return an invalid value and write operations are ignored. when saving transfer content as a result of a suspend command, the number of blocks yet to be transferred can be determined by reading this register. the reading of this register should be applied after transfer is paused by stop at block gap operation and before sending the command marked as suspend. this is because when suspend command is sent out, sdhc will regard the current transfer is aborted and change blkcnt back to its original value instead of keeping the dynamical indicator of remained block count. table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 174 freescale semiconductor, inc. sdhc_blkattr field descriptions (continued) field description when restoring transfer content prior to issuing a resume command, the host driver shall restore the previously saved block count. note: although the blkcnt field is 0 after reset, the read of reset value is 0x1. this is because when xfertyp[msbsel] bit is 0, indicating a single block transfer, the read value of blkcnt is always 1. 0000h stop count 0001h 1 block 0002h 2 blocks ... ffffh 65535 blocks 1513 reserved this read-only field is reserved and always has the value zero. 120 blksize transfer block size this register specifies the block size for block data transfers. values ranging from 1 byte up to the maximum buffer size can be set. it can be accessed only when no transaction is executing (that is after a transaction has stopped). read operations during transfers may return an invalid value, and write operations will be ignored. 000h no data transfer 001h 1 byte 002h 2 bytes 003h 3 bytes 004h 4 bytes ... 1ffh 511 bytes 200h 512 bytes ... 800h 2048 bytes ... 1000h 4096 bytes 52.4.3 command argument register (sdhc_cmdarg) this register contains the sd/mmc command argument. address: sdhc_cmdarg is 400b_1000h base + 8h offset = 400b_1008h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r cmdarg w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1575 sdhc_cmdarg field descriptions field description 310 cmdarg command argument the sd/mmc command argument is specified as bits 39-8 of the command format in the sd or mmc specification.this register is write protected when the prsstat[cdihb0] bit is set. 52.4.4 transfer type register (sdhc_xfertyp) this register is used to control the operation of data transfers. the host driver shall set this register before issuing a command followed by a data transfer, or before issuing a resume command. to prevent data loss, the sdhc prevents writing to the bits, that are involved in the data transfer of this register, when data transfer is active. these bits are dpsel, mbsel, dtdsel, ac12en, bcen and dmaen. the host driver shall check the prsstat[cdihb] and the prsstat[cihb] before writing to this register. when the prsstat[cdihb] is set, any attempt to send a command with data by writing to this register is ignored; when the prsstat[cihb] bit is set, any write to this register is ignored. on sending commands with data transfer invovled, it is mandatory that the block size is non-zero. besides, block count must also be non-zero, or indicated as single block transfer (bit 5 of this register is 0 when written), or block count is disabled (bit 1 of this register is 0 when written), otherwise sdhc will ignore the sending of this command and do nothing. for write command, with all above restrictions, it is also mandatory that the write protect switch is not active (wpspl bit of present state register is 1), otherwise sdhc will also ignore the command. if the commands with data transfer does not receive the response in 64 clock cycles, i.e., response time-out, sdhc will regard the external device does not accept the command and abort the data transfer. in this scenario, the driver should issue the command again to re-try the transfer. it is also possible that for some reason the card responds the command but sdhc does not receive the response, and if it is internal dma (either simple dma or adma) read operation, the external system memory is over-written by the internal dma with data sent back from the card. the following table shows the summary of how register settings determine the type of data transfer. table 52-7. transfer type register setting for various transfer types multi/single block select block count enable block count function 0 don't care don't care single transfer table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 176 freescale semiconductor, inc. table 52-7. transfer type register setting for various transfer types (continued) multi/single block select block count enable block count function 1 0 dont care infinite transfer 1 1 positive number multiple transfer 1 1 zero no data transfer the following table shows the relationship between the xfertyp[cicen] and xfertyp[cccen], in regards to the xfertyp[rsptyp] as well as the name of the response type. table 52-8. relationship between parameters and the name of the response type response type (rsptyp) index check enable (cicen) crc check enable (cccen) name of response type 00 0 0 no response 01 0 1 ir2 10 0 0 r3,r4 10 1 1 r1,r5,r6 11 1 1 r1b,r5b note ? in the sdio specification, response type notation for r5b is not defined. r5 includes r5b in the sdio specification. but r5b is defined in this specification to specify that the sdhc will check the busy status after receiving a response. for example, usually cmd52 is used with r5, but the i/o abort command shall be used with r5b. ? the crc field for r3 and r4 is expected to be all 1 bits. the crc check shall be disabled for these response types. chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1577 address: sdhc_xfertyp is 400b_1000h base + ch offset = 400b_100ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 cmdinx cmdtyp dpsel cicen cccen 0 rsptyp w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 msbsel dtdsel 0 ac12en bcen dmaen w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sdhc_xfertyp field descriptions field description 3130 reserved this read-only field is reserved and always has the value zero. 2924 cmdinx command index these bits shall be set to the command number that is specified in bits 45-40 of the command-format in the sd memory card physical layer specification and sdio card specification. 2322 cmdtyp command type there are three types of special commands: suspend, resume and abort. these bits shall be set to 00b for all other commands. ? suspend command: if the suspend command succeeds, the sdhc shall assume that the card bus has been released and that it is possible to issue the next command which uses the dat line. since the sdhc does not monitor the content of command response, it does not know if the suspend command succeeded or not. it is the host drivers responsibility to check the status of the suspend command and send another command marked as suspend to inform the sdhc that a suspend command was successfully issued. after the end bit of command is sent, the sdhc de-asserts read wait for read transactions and stops checking busy for write transactions. in 4-bit mode, the interrupt cycle starts. if the suspend command fails, the sdhc will maintain its current state, and the host driver shall restart the transfer by setting the proctl[creq]. ? resume command: the host driver re-starts the data transfer by restoring the registers saved before sending the suspend command and then sends the resume command. the sdhc will check for a pending busy state before starting write transfers. ? abort command: if this command is set when executing a read transfer, the sdhc will stop reads to the buffer. if this command is set when executing a write transfer, the sdhc will stop driving the dat line. after issuing the abort command, the host driver should issue a software reset (abort transaction). 00b normal other commands 01b suspend cmd52 for writing bus suspend in cccr 10b resume cmd52 for writing function select in cccr 11b abort cmd12, cmd52 for writing i/o abort in cccr 21 dpsel data present select table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 178 freescale semiconductor, inc. sdhc_xfertyp field descriptions (continued) field description this bit is set to 1 to indicate that data is present and shall be transferred using the dat line. it is set to 0 for the following: ? commands using only the cmd line (for example: cmd52). ? commands with no data transfer, but using the busy signal on dat[0] line (r1b or r5b, for example: cmd38). note: in resume command, this bit shall be set, and other bits in this register shall be set the same as when the transfer was initially launched. when the write protect switch is on, (i.e. the wpspl bit is active as 0?), any command with a write operation will be ignored. that is to say, when this bit is set, while the dtdsel bit is 0, writes to the register transfer type are ignored. 0b no data present 1b data present 20 cicen command index check enable if this bit is set to 1, the sdhc will check the index field in the response to see if it has the same value as the command index. if it is not, it is reported as a command index error. if this bit is set to 0, the index field is not checked. 0b disable 1b enable 19 cccen command crc check enable if this bit is set to 1, the sdhc shall check the crc field in the response. if an error is detected, it is reported as a command crc error. if this bit is set to 0, the crc field is not checked. the number of bits checked by the crc field value changes according to the length of the response. 0b disable 1b enable 18 reserved this read-only field is reserved and always has the value zero. 1716 rsptyp response type select 00b no response 01b response length 136 10b response length 48 11b response length 48, check busy after response 156 reserved this read-only field is reserved and always has the value zero. 5 msbsel multi/single block select this bit enables multiple block dat line data transfers. for any other commands, this bit shall be set to 0. if this bit is 0, it is not necessary to set the block count register. 0b single block 1b multiple blocks 4 dtdsel data transfer direction select this bit defines the direction of dat line data transfers. the bit is set to 1 by the host driver to transfer data from the sd card to the sdhc and is set to 0 for all other commands. table continues on the next page... chapter 2 secured digital host controller sdhc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 17 sdhc_xfertyp field descriptions (continued) field description 0b write (host to card) 1b read (card to host) 3 reserved this read-only field is reserved and always has the value zero. 2 ac12en auto cmd12 enable multiple block transfers for memory require a cmd12 to stop the transaction. when this bit is set to 1, the sdhc will issue a cmd12 automatically when the last block transfer has completed. the host driver shall not set this bit to issue commands that do not require cmd12 to stop a multiple block data transfer. in particular, secure commands defined in file security specification (see reference list) do not require cmd12. in single block transfer, the sdhc will ignore this bit no matter if it is set or not. 0b disable 1b enable 1 bcen block count enable this bit is used to enable the block count register, which is only relevant for multiple block transfers. when this bit is 0, the internal counter for block is disabled, which is useful in executing an infinite transfer. 0b disable 1b enable 0 dmaen dma enable this bit enables dma functionality. if this bit is set to 1, a dma operation shall begin when the host driver sets the dpsel bit of this register. whether the simple dma, or the advanced dma, is active depends on the proctl[dmas]. 0b disable 1b enable 52.4.5 command response 0 (sdhc_cmdrsp0) this register is used to store part 0 of the response bits from the card. address: sdhc_cmdrsp0 is 400b_1000h base + 10h offset = 400b_1010h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r cmdrsp0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sdhc_cmdrsp0 field descriptions field description 31?0 cmdrsp0 command response 0 memory map and register definition k60 sub-family reference manual, rev. 6, nov 2011 1580 freescale semiconductor, inc. 52.4.6 command response 1 (sdhc_cmdrsp1) this register is used to store part 1 of the response bits from the card. address: sdhc_cmdrsp1 is 400b_1000h base + 14h offset = 400b_1014h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r cmdrsp1 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sdhc_cmdrsp1 field descriptions field description 31?0 cmdrsp1 command response 1 52.4.7 command response 2 (sdhc_cmdrsp2) this register is used to store part 2 of the response bits from the card. address: sdhc_cmdrsp2 is 400b_1000h base + 18h offset = 400b_1018h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r cmdrsp2 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sdhc_cmdrsp2 field descriptions field description 31?0 cmdrsp2 command response 2 52.4.8 command response 3 (sdhc_cmdrsp3) this register is used to store part 3 of the response bits from the card. the following table describes the mapping of command responses from the sd bus to command response registers for each response type. in the table, r[ ] refers to a bit range within the response data as transmitted on the sd bus. chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1581 table 52-13. response bit definition for each response type response type meaning of response response field response register r1,r1b (normal response) card status r[39:8] cmdrsp0 r1b (auto cmd12 response) card status for auto cmd12 r[39:8] cmdrsp3 r2 (cid, csd register) cid/csd register [127:8] r[127:8] {cmdrsp3[23:0], cmdrsp2, cmdrsp1, cmdrsp0} r3 (ocr register) ocr register for memory r[39:8] cmdrsp0 r4 (ocr register) ocr register for i/o etc. r[39:8] cmdrsp0 r5, r5b sdio response r[39:8] cmdrsp0 r6 (publish rca) new published rca[31:16] and card status[15:0] r[39:9] cmdrsp0 this table shows that most responses with a length of 48 (r[47:0]) have 32-bit of the response data (r[39:8]) stored in the cmdrsp0 register. responses of type r1b (auto cmd12 responses) have response data bits (r[39:8]) stored in the cmdrsp3 register. responses with length 136 (r[135:0]) have 120-bit of the response data (r[127:8]) stored in the cmdrsp0, 1, 2, and 3 registers. to be able to read the response status efficiently, the sdhc only stores part of the response data in the command response registers. this enables the host driver to efficiently read 32-bit of response data in one read cycle on a 32-bit bus system. parts of the response, the index field and the crc, are checked by the sdhc (as specified by the xfertyp[cicen] and the xfertyp[cccen] bits) and generate an error interrupt if any error is detected. the bit range for the crc check depends on the response length. if the response length is 48, the sdhc will check r[47:1], and if the response length is 136 the sdhc will check r[119:1]. since the sdhc may have a multiple block data transfer executing concurrently with a cmd_wo_dat command, the sdhc stores the auto cmd12 response in the cmdrsp3 register. the cmd_wo_dat response is stored in cmdrsp0. this allows the sdhc to avoid overwriting the auto cmd12 response with the cmd_wo_dat and vice versa. when the sdhc modifies part of the command response registers, as shown in the table above, it preserves the unmodified bits. address: sdhc_cmdrsp3 is 400b_1000h base + 1ch offset = 400b_101ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r cmdrsp3 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 memory map and register definition k60 sub-family reference manual, rev. 6, nov 2011 1582 freescale semiconductor, inc. sdhc_cmdrsp3 field descriptions field description 310 cmdrsp3 command response 3 52.4.9 buffer data port register (sdhc_datport) this is a 32-bit data port register used to access the internal buffer and it can not be updated in idle mode. address: sdhc_datport is 400b_1000h base + 20h offset = 400b_1020h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r datcont w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sdhc_datport field descriptions field description 31?0 datcont data content the buffer data port register is for 32-bit data access by the cpu or the external dma. when the internal dma is enabled, any write to this register is ignored, and any read from this register will always yield 0s. 52.4.10 present state register (sdhc_prsstat) the host driver can get status of the sdhc from this 32-bit read only register. note the host driver can issue cmd0, cmd12, cmd13 (for memory) and cmd52 (for sdio) when the dat lines are busy during a data transfer. these commands can be issued when command inhibit (cihb) is set to zero. other commands shall be issued when command inhibit (cdihb) is set to zero. possible changes to the sd physical specification may add other commands to this list in the future. chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1583 address: sdhc_prsstat is 400b_1000h base + 24h offset = 400b_1024h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r dlsl clsl 0 cins w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 bren bwen rta wta sdoff peroff hckoff ipgoff sdstb dla cdihb cihb w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sdhc_prsstat field descriptions field description 3124 dlsl dat line signal level this status is used to check the dat line level to recover from errors, and for debugging.this is especially useful in detecting the busy signal level from dat[0]. the reset value is effected by the external pullup/ pulldown resistors. by default, the read value of this bit field after reset is 8?b11110111, when dat[3] is pulled down and the other lines are pulled up. dat[0] data 0 line signal level dat[1] data 1 line signal level dat[2] data 2 line signal level dat[3] data 3 line signal level dat[4] data 4 line signal level dat[5] data 5 line signal level dat[6] data 6 line signal level dat[7] data 7 line signal level 23 clsl cmd line signal level this status is used to check the cmd line level to recover from errors, and for debugging. the reset value is effected by the external pullup/pulldown resistor, by default, the read value of this bit after reset is 1b, when the command line is pulled up. 2217 reserved this read-only field is reserved and always has the value zero. 16 cins card inserted this bit indicates whether a card has been inserted. the sdhc debounces this signal so that the host driver will not need to wait for it to stabilize. changing from a 0 to 1 generates a card insertion interrupt in the interrupt status register. changing from a 1 to 0 generates a card removal interrupt in the interrupt status register. a write to the force event register does not effect this bit. table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 184 freescale semiconductor, inc. sdhc_prsstat field descriptions (continued) field description the sysctl[rsta] does not effect this bit.a software reset does not effect this bit. 0b power on reset or no card 1b card inserted 1512 reserved this read-only field is reserved and always has the value zero. 11 bren buffer read enable this status bit is used for non-dma read transfers. the sdhc may implement multiple buffers to transfer data efficiently. this read only flag indicates that valid data exists in the host side buffer. if this bit is high, valid data greater than the watermark level exist in the buffer. this read only flag indicates that valid data exists in the host side buffer. 0b read disable, valid data less than the watermark level exist in the buffer. 1b read enable, valid data greater than the watermark level exist in the buffer. 10 bwen buffer write enable this status bit is used for non-dma write transfers. the sdhc can implement multiple buffers to transfer data efficiently. this read only flag indicates if space is available for write data. if this bit is 1, valid data greater than the watermark level can be written to the buffer.this read only flag indicates if space is available for write data. 0b write disable, the buffer can hold valid data less than the write watermark level. 1b write enable, the buffer can hold valid data greater than the write watermark level. 9 rta read transfer active this status bit is used for detecting completion of a read transfer. this bit is set for either of the following conditions: ? after the end bit of the read command. ? when writing a 1 to the proctl[creq] to restart a read transfer. a transfer complete interrupt is generated when this bit changes to 0. this bit is cleared for either of the following conditions: ? when the last data block as specified by block length is transferred to the system, that is all data are read away from sdhc internal buffer. ? when all valid data blocks have been transferred from sdhc internal buffer to the system and no current block transfers are being sent as a result of the stop at block gap request being set to 1. 0b no valid data 1b transferring data 8 wta write transfer active this status bit indicates a write transfer is active. if this bit is 0, it means no valid write data exists in the sdhc. this bit is set in either of the following cases: ? after the end bit of the write command. ? when writing 1 to the proctl[creq] to restart a write transfer. this bit is cleared in either of the following cases: ? after getting the crc status of the last data block as specified by the transfer count (single and multiple). ? after getting the crc status of any block where data transmission is about to be stopped by a stop at block gap request. table continues on the next page... chapter 2 secured digital host controller sdhc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 18 sdhc_prsstat field descriptions (continued) field description during a write transaction, a block gap event interrupt is generated when this bit is changed to 0, as result of the stop at block gap request being set. this status is useful for the host driver in determining when to issue commands during write busy state. 0b no valid data 1b transferring data 7 sdoff sd clock gated off internally this status bit indicates that the sd clock is internally gated off, because of buffer over/under-run or read pause without read wait assertion, or the driver has cleared sysctl[sdclken] bit to stop the sd clock. this bit is for the host driver to debug data transaction on the sd bus. 0b sd clock is active 1b sd clock is gated off 6 peroff sdhc clock gated off internally this status bit indicates that the sdhc clock is internally gated off. this bit is for the host driver to debug transaction on the sd bus. when inita bit is set, sdhc sending 80 clock cycles to the card, the sdclken bit must be 1? to enable the output card clock, otherwise the sdhc clock will never be gate off, so sdhc clock and bus clock will be always active. 0b sdhc clock is active 1b sdhc clock is gated off 5 hckoff system clock gated off internally this status bit indicates that the system clock is internally gated off. this bit is for the host driver to debug during a data transfer. 0b system clock is active 1b system clock is gated off 4 ipgoff bus clock gated off internally this status bit indicates that the bus clock is internally gated off. this bit is for the host driver to debug. table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 186 freescale semiconductor, inc. sdhc_prsstat field descriptions (continued) field description 0b bus clock is active 1b bus clock is gated off 3 sdstb sd clock stable this status bit indicates that the internal card clock is stable. this bit is for the host driver to poll clock status when changing the clock frequency. it is recommended to clear sysctl[sdclken] bit to remove glitch on the card clock when the frequency is changing. 0b clock is changing frequency and not stable 1b clock is stable 2 dla data line active this status bit indicates whether one of the dat lines on the sd bus is in use. in the case of read transactions: this status indicates if a read transfer is executing on the sd bus. changes in this value from 1 to 0, between data blocks, generates a block gap event interrupt in the interrupt status register. this bit will be set in either of the following cases: ? after the end bit of the read command. ? when writing a 1 to the proctl[creq] to restart a read transfer. this bit will be cleared in either of the following cases: 1. when the end bit of the last data block is sent from the sd bus to the sdhc. 2. when the read wait state is stopped by a suspend command and the dat2 line is released. the sdhc will wait at the next block gap by driving read wait at the start of the interrupt cycle. if the read wait signal is already driven (data buffer cannot receive data), the sdhc can wait for a current block gap by continuing to drive the read wait signal. it is necessary to support read wait in order to use the suspend / resume function. this bit will remain 1 during read wait. in the case of write transactions: this status indicates that a write transfer is executing on the sd bus. changes in this value from 1 to 0 generate a transfer complete interrupt in the interrupt status register. this bit will be set in either of the following cases: ? after the end bit of the write command. ? when writing to 1 to the proctl[creq] to continue a write transfer. this bit will be cleared in either of the following cases: ? when the sd card releases write busy of the last data block, the sdhc will also detect if the output is not busy. if the sd card does not drive the busy signal after the crc status is received, the sdhc shall assume the card drive not busy?. ? when the sd card releases write busy, prior to waiting for write transfer, and as a result of a stop at block gap request. in the case of command with busy pending: this status indicates that a busy state follows the command and the data line is in use. this bit will be cleared when the dat0 line is released. 0b dat line inactive 1b dat line active 1 cdihb command inhibit (dat) table continues on the next page... chapter 2 secured digital host controller sdhc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 187 sdhc_prsstat field descriptions (continued) field description this status bit is generated if either the dla or the rta is set to 1. if this bit is 0, it indicates that the sdhc can issue the next sd/mmc command. commands with a busy signal belong to cdihb (e.g. r1b, r5b type). except in the case when the command busy is finished, changing from 1 to 0 generates a transfer complete interrupt in the interrupt status register. note: the sd host driver can save registers for a suspend transaction after this bit has changed from 1 to 0. 0b can issue command which uses the dat line 1b cannot issue command which uses the dat line 0 cihb command inhibit (cmd) if this status bit is 0, it indicates that the cmd line is not in use and the sdhc can issue a sd/mmc command using the cmd line. this bit is set also immediately after the transfer type register is written. this bit is cleared when the command response is received. even if the cdihb bit is set to 1, commands using only the cmd line can be issued if this bit is 0. changing from 1 to 0 generates a command complete interrupt in the interrupt status register. if the sdhc cannot issue the command because of a command conflict error (refer to command crc error) or because of a command not issued by auto cmd12 error, this bit will remain 1 and the command complete is not set. the status of issuing an auto cmd12 does not show on this bit. 0b can issue command using only cmd line 1b cannot issue command 52.4.11 protocol control register (sdhc_proctl) there are three cases to restart the transfer after stop at the block gap. which case is appropriate depends on whether the sdhc issues a suspend command or the sd card accepts the suspend command. 1. if the host driver does not issue a suspend command, the continue request shall be used to restart the transfer. 2. if the host driver issues a suspend command and the sd card accepts it, a resume command shall be used to restart the transfer. 3. if the host driver issues a suspend command and the sd card does not accept it, the continue request shall be used to restart the transfer. any time stop at block gap request stops the data transfer, the host driver shall wait for a transfer complete (in the interrupt status register), before attempting to restart the transfer. when restarting the data transfer by continue request, the host driver shall clear the stop at block gap request before or simultaneously. memory map and register definition k60 sub-family reference manual, rev. 6, nov 2011 1588 freescale semiconductor, inc. address: sdhc_proctl is 400b_1000h base + 28h offset = 400b_1028h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 wecrm wecins wecint 0 iabg rwctl creq sabgreq w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 dmas cdss cdtl emode d3cd dtw lctl w reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 sdhc_proctl field descriptions field description 3127 reserved this read-only field is reserved and always has the value zero. 26 wecrm wakeup event enable on sd card removal this bit enables a wakeup event, via irqstat[crm]. fn_wus (wake up support) in cis does not effect this bit. when this bit is set, the irqstat[crm] and the sdhc interrupt can be asserted without sd_clk toggling. when the wakeup feature is not enabled, the sd_clk must be active in order to assert the irqstat[crm] and the sdhc interrupt. 0b disabled 1b enabled 25 wecins wakeup event enable on sd card insertion this bit enables a wakeup event, via irqstat[cins]. fn_wus (wake up support) in cis does not effect this bit. when this bit is set, the irqstaten[cinsen] and the sdhc interrupt can be asserted without sd_clk toggling. when the wakeup feature is not enabled, the sd_clk must be active in order to assert the irqstaten[cinsen] and the sdhc interrupt. 0b disabled 1b enabled 24 wecint wakeup event enable on card interrupt this bit enables a wakeup event, via irqstat[cint]. this bit can be set to 1 if fn_wus (wake up support) in cis is set to 1. when this bit is set, the card interrupt status and the sdhc interrupt can be asserted without sd_clk toggling. when the wakeup feature is not enabled, the sd_clk must be active in order to assert the card interrupt status and the sdhc interrupt. 0b disabled 1b enabled 2320 reserved this read-only field is reserved and always has the value zero. 19 iabg interrupt at block gap table continues on the next page... chapter 2 secured digital host controller sdhc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 18 sdhc_proctl field descriptions (continued) field description this bit is valid only in 4-bit mode, of the sdio card, and selects a sample point in the interrupt cycle. setting to 1 enables interrupt detection at the block gap for a multiple block transfer. setting to 0 disables interrupt detection during a multiple block transfer. if the sdio card cant signal an interrupt during a multiple block transfer, this bit should be set to 0 to avoid an inadvertent interrupt. when the host driver detects an sdio card insertion, it shall set this bit according to the cccr of the card. 0b disabled 1b enabled 18 rwctl read wait control the read wait function is optional for sdio cards. if the card supports read wait, set this bit to enable use of the read wait protocol to stop read data using the dat[2] line. otherwise the sdhc has to stop the sd clock to hold read data, which restricts commands generation. when the host driver detects an sdio card insertion, it shall set this bit according to the cccr of the card. if the card does not support read wait, this bit shall never be set to 1, otherwise dat line conflicts may occur. if this bit is set to 0, stop at block gap during read operation is also supported, but the sdhc will stop the sd clock to pause reading operation. 0b disable read wait control, and stop sd clock at block gap when sabgreq bit is set. 1b enable read wait control, and assert read wait without stopping sd clock at block gap when sabgreq bit is set. 17 creq continue request this bit is used to restart a transaction which was stopped using the proctl[sabgreq]. when a suspend operation is not accepted by the card, it is also by setting this bit to restart the paused transfer. to cancel stop at the block gap, set proctl[sabgreq] to 0 and set this bit to 1 to restart the transfer. the sdhc automatically clears this bit, therefore it is not necessary for the host driver to set this bit to 0. if both proctl[sabgreq] and this bit are 1, the continue request is ignored. 0b no effect 1b restart 16 sabgreq stop at block gap request this bit is used to stop executing a transaction at the next block gap for both dma and non-dma transfers. until the irqstaten[tcsen] is set to 1, indicating a transfer completion, the host driver shall leave this bit set to 1. clearing both the proctl[sabgreq] and proctl[creq] does not cause the transaction to restart. read wait is used to stop the read transaction at the block gap. the sdhc will honor the proctl[sabgreq] for write transfers, but for read transfers it requires that the sdio card support read wait. therefore, the host driver shall not set this bit during read transfers unless the sdio card supports read wait and has set the proctl[rwctl] to 1, otherwise the sdhc will stop the sd bus clock to pause the read operation during block gap. in the case of write transfers in which the host driver writes data to the data port register, the host driver shall set this bit after all block data is written. if this bit is set to 1, the host driver shall not write data to the data port register after a block is sent. once this bit is set, the host driver shall not clear this bit before the irqstaten[tcsen] is set, otherwise the sdhcs behavior is undefined. this bit effects prsstat[rta], prsstat[wta], prsstat[cdihb]. 0b transfer 1b stop 1510 reserved this read-only field is reserved and always has the value zero. table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 10 freescale semiconductor, inc. sdhc_proctl field descriptions (continued) field description 98 dmas dma select this field is valid while dma (sdma or adma) is enabled and selects the dma operation. 00 no dma or simple dma is selected 01 adma1 is selected 10 adma2 is selected 11 reserved 7 cdss card detect signal selection this bit selects the source for the card detection. 0b card detection level is selected (for normal purpose) 1b card detection test level is selected (for test purpose) 6 cdtl card detect test level this is bit is enabled while the cdss is set to 1 and it indicates card insertion. 0b card detect test level is 0, no card inserted 1b card detect test level is 1, card inserted 54 emode endian mode the sdhc supports all four endian modes in data transfer. 00b big endian mode 01b half word big endian mode 10b little endian mode 11b reserved 3 d3cd dat3 as card detection pin if this bit is set, dat3 should be pulled down to act as a card detection pin. be cautious when using this feature, because dat3 is also a chip-select for the spi mode. a pulldown on this pin and cmd0 may set the card into the spi mode, which the sdhc does not support. note: keep this bit set if sdio interrupt is used. 0b dat3 does not monitor card insertion 1b dat3 as card detection pin 21 dtw data transfer width this bit selects the data width of the sd bus for a data transfer. the host driver shall set it to match the data width of the card. possible data transfer width is 1-bit, 4-bits or 8-bits. 00b 1-bit mode 01b 4-bit mode 10b 8-bit mode 11b reserved 0 lctl led control this bit, fully controlled by the host driver, is used to caution the user not to remove the card while the card is being accessed. if the software is going to issue multiple sd commands, this bit can be set during table continues on the next page... chapter 2 secured digital host controller sdhc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 11 sdhc_proctl field descriptions (continued) field description all these transactions. it is not necessary to change for each transaction. when the software issues multiple sd commands, setting the bit once before the first command is sufficient: it is not necessary to reset the bit between commands. 0b led off 1b led on 52.4.12 system control register (sdhc_sysctl) address: sdhc_sysctl is 400b_1000h base + 2ch offset = 400b_102ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 inita 0 0 0 0 dtocv w rstd rstc rsta reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r sdclkfs dvs sdclken peren hcken ipgen w reset 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 sdhc_sysctl field descriptions field description 3128 reserved this read-only field is reserved and always has the value zero. 27 inita initialization active when this bit is set, 80 sd-clocks are sent to the card. after the 80 clocks are sent, this bit is self cleared. this bit is very useful during the card power-up period when 74 sd-clocks are needed and the clock auto gating feature is enabled. writing 1 to this bit when this bit is already 1 has no effect. writing 0 to this bit at any time has no effect. when either of the prsstat[cihb] and prsstat[cdihb] bits are set, writing 1 to this bit is ignored (i.e. when command line or data lines are active, write to this bit is not allowed). on the otherhand, when this bit is set, i.e., during intialization active period, it is allowed to issue command, and the command bit stream will appear on the cmd pad after all 80 clock cycles are done. so when this command ends, the driver can make sure the 80 clock cycles are sent out. this is very useful when the driver needs send 80 cycles to the card and does not want to wait till this bit is self cleared. 26 rstd software reset for dat line only part of the data circuit is reset. dma circuit is also reset. the following registers and bits are cleared by this bit: ? data port register ? buffer is cleared and initialized.present state register ? buffer read enable table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 12 freescale semiconductor, inc. sdhc_sysctl field descriptions (continued) field description ? buffer write enable ? read transfer active ? write transfer active ? dat line active ? command inhibit (dat) protocol control register ? continue request ? stop at block gap request interrupt status register ? buffer read ready ? buffer write ready ? dma interrupt ? block gap event ? transfer complete 0b no reset 1b reset 25 rstc software reset for cmd line only part of the command circuit is reset. the following registers and bits are cleared by this bit: ? prsstat[cihb] ? irqstat[cc] 0b no reset 1b reset 24 rsta software reset for all this reset effects the entire host controller except for the card detection circuit. register bits of type roc, rw, rw1c, rwac are cleared. during its initialization, the host driver shall set this bit to 1 to reset the sdhc. the sdhc shall reset this bit to 0 when the capabilities registers are valid and the host driver can read them. additional use of software reset for all does not affect the value of the capabilities registers. after this bit is set, it is recommended that the host driver reset the external card and re-initialize it. 0b no reset 1b reset 2320 reserved this read-only field is reserved and always has the value zero. 1916 dtocv data timeout counter value this value determines the interval by which dat line timeouts are detected. refer to the irqstat[dtoe] for information on factors that dictate time-out generation. time-out clock frequency will be generated by dividing the base clock sdclk value by this value. the host driver can clear the irqstaten[dtoesen] to prevent inadvertent time-out events. 0000b sdclk x 2 13 0001b sdclk x 2 14 ... 1110b sdclk x 2 27 1111b reserved 158 sdclkfs sdclk frequency select this register is used to select the frequency of the sdclk pin. the frequency is not programmed directly, rather this register holds the prescaler (this register) and divisor (next register) of the base clock frequency register. table continues on the next page... chapter 2 secured digital host controller sdhc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1 sdhc_sysctl field descriptions (continued) field description setting 00h bypasses the frequency prescaler of the sd clock. multiple bits must not be set, or the behavior of this prescaler is undefined. the two default divider values can be calculated by the frequency of sdhc clock and the following divisor bits. the frequency of sdclk is set by the following formula: clock frequency = (base clock) / (prescaler x divisor) for example, if the base clock frequency is 96 mhz, and the target frequency is 25 mhz, then choosing the prescaler value of 01h and divisor value of 1h will yield 24 mhz, which is the nearest frequency less than or equal to the target. similarly, to approach a clock value of 400 khz, the prescaler value of 08h and divisor value of eh yields the exact clock value of 400 khz. the reset value of this bit field is 80h, so if the input base clock (sdhc clock) is about 96 mhz, the default sd clock after reset is 375 khz. according to the sd physical specification version 1.1 and the sdio card specification version 1.2, the maximum sd clock frequency is 50 mhz and shall never exceed this limit. only the following settings are allowed: 01h base clock divided by 2 02h base clock divided by 4 04h base clock divided by 8 08h base clock divided by 16 10h base clock divided by 32 20h base clock divided by 64 40h base clock divided by 128 80h base clock divided by 256 74 dvs divisor this register is used to provide a more exact divisor to generate the desired sd clock frequency. note the divider can even support odd divisor without deterioration of duty cycle. the setting are as following: 0h divisor by 1 1h divisor by 2 ... eh divisor by 15 fh divisor by 16 3 sdclken sd clock enable the host controller shall stop sdclk when writing this bit to 0. sdclk frequency can be changed when this bit is 0. then, the host controller shall maintain the same clock frequency until sdclk is stopped (stop at sdclk = 0). if the irqstat[cins] is cleared, this bit should be cleared by the host driver to save power. 2 peren peripheral clock enable if this bit is set, sdhc clock will always be active and no automatic gating is applied. thus the sdclk is active except for when auto gating-off during buffer danger (buffer about to over-run or under-run). when this bit is cleared, the sdhc clock will be automatically off whenever there is no transaction on the sd bus. since this bit is only a feature enabling bit, clearing this bit does not stop sdclk immediately. the sdhc clock will be internally gated off, if none of the following factors are met: ? the cmd part is reset, or ? data part is reset, or ? a soft reset, or ? the cmd is about to send, or ? clock divisor is just updated, or table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 14 freescale semiconductor, inc. sdhc_sysctl field descriptions (continued) field description ? continue request is just set, or ? this bit is set, or ? card insertion is detected, or ? card removal is detected, or ? card external interrupt is detected, or ? 80 clocks for initialization phase is ongoing 0b sdhc clock will be internally gated off 1b sdhc clock will not be automatically gated off 1 hcken system clock enable if this bit is set, system clock will always be active and no automatic gating is applied. when this bit is cleared, system clock will be automatically off when no data transfer is on the sd bus. 0b system clock will be internally gated off 1b system clock will not be automatically gated off 0 ipgen ipg clock enable if this bit is set, bus clock will always be active and no automatic gating is applied. the bus clock will be internally gated off, if none of the following factors are met: ? the cmd part is reset, or ? data part is reset, or ? soft reset, or ? the cmd is about to send, or ? clock divisor is just updated, or ? continue request is just set, or ? this bit is set, or ? card insertion is detected, or ? card removal is detected, or ? card external interrupt is detected, or ? the sdhc clock is not gated off note: the bus clock will not be auto gated off if the sdhc clock is not gated off. so clearing only this bit has no effect unless the peren bit is also cleared. 0b bus clock will be internally gated off 1b bus clock will not be automatically gated off 52.4.13 interrupt status register (sdhc_irqstat) an interrupt is generated when the normal interrupt signal enable is enabled and at least one of the status bits is set to 1. for all bits, writing 1 to a bit clears it; writing to 0 keeps the bit unchanged. more than one status can be cleared with a single register write. for card interrupt, before writing 1 to clear, it is required that the card stops asserting the interrupt, meaning that when the card driver services the interrupt condition, otherwise the cint bit will be asserted again. chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1595 the table below shows the relationship between the ctoe and the cc bits. table 52-19. sdhc status for ctoe/cc bit combinations command complete command timeout error meaning of the status 0 0 x x 1 response not received within 64 sdclk cycles 1 0 response received the table below shows the relationship between the transfer complete and the data timeout error. table 52-20. sdhc status for data timeout error/transfer complete bit combinations transfer complete data timeout error meaning of the status 0 0 x 0 1 timeout occurred during transfer 1 x data transfer complete the table below shows the relationship between the command crc error (cce) and command timeout error (ctoe). table 52-21. sdhc status for cce/ctoe bit combinations command complete command timeout error meaning of the status 0 0 no error 0 1 response timeout error 1 0 response crc error 1 1 cmd line conflict memory map and register definition k60 sub-family reference manual, rev. 6, nov 2011 1596 freescale semiconductor, inc. address: sdhc_irqstat is 400b_1000h base + 30h offset = 400b_1030h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 dmae 0 ac12e 0 debe dce dtoe cie cebe cce ctoe w w1c w1c w1c w1c w1c w1c w1c w1c w1c reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 cint crm cins brr bwr dint bge tc cc w w1c w1c w1c w1c w1c w1c w1c w1c w1c reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sdhc_irqstat field descriptions field description 3129 reserved this read-only field is reserved and always has the value zero. 28 dmae dma error occurs when an internal dma transfer has failed. this bit is set to 1, when some error occurs in the data transfer. this error can be caused by either simple dma or adma, depending on which dma is in use. the value in dma system address register is the next fetch address where the error occurs. since any error corrupts the whole data block, the host driver shall re-start the transfer from the corrupted block boundary. the address of the block boundary can be calculated either from the current dsaddr value or from the remaining number of blocks and the block size. 0b no error 1b error 2725 reserved this read-only field is reserved and always has the value zero. 24 ac12e auto cmd12 error occurs when detecting that one of the bits in the auto cmd12 error status register has changed from 0 to 1. this bit is set to 1, not only when the errors in auto cmd12 occur, but also when the auto cmd12 is not executed due to the previous command error. 0b no error 1b error 23 reserved this read-only field is reserved and always has the value zero. 22 debe data end bit error occurs either when detecting 0 at the end bit position of read data, which uses the dat line, or at the end bit position of the crc. table continues on the next page... chapter 2 secured digital host controller sdhc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 17 sdhc_irqstat field descriptions (continued) field description 0b no error 1b error 21 dce data crc error occurs when detecting a crc error when transferring read data, which uses the dat line, or when detecting the write crc status having a value other than 010. 0b no error 1b error 20 dtoe data timeout error occurs when detecting one of following time-out conditions. ? busy time-out for r1b,r5b type ? busy time-out after write crc status ? read data time-out 0b no error 1b time out 19 cie command index error occurs if a command index error occurs in the command response. 0b no error 1b error 18 cebe command end bit error occurs when detecting that the end bit of a command response is 0. 0b no error 1b end bit error generated 17 cce command crc error command crc error is generated in two cases. ? if a response is returned and the command timeout error is set to 0 (indicating no time-out), this bit is set when detecting a crc error in the command response. ? the sdhc detects a cmd line conflict by monitoring the cmd line when a command is issued. if the sdhc drives the cmd line to 1, but detects 0 on the cmd line at the next sdclk edge, then the sdhc shall abort the command (stop driving cmd line) and set this bit to 1. the command timeout error shall also be set to 1 to distinguish cmd line conflict. 0b no error 1b crc error generated 16 ctoe command timeout error occurs only if no response is returned within 64 sdclk cycles from the end bit of the command. if the sdhc detects a cmd line conflict, in which case a command crc error shall also be set, this bit shall be set without waiting for 64 sdclk cycles. this is because the command will be aborted by the sdhc. 0b no error 1b time out table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 18 freescale semiconductor, inc. sdhc_irqstat field descriptions (continued) field description 159 reserved this read-only field is reserved and always has the value zero. 8 cint card interrupt this status bit is set when an interrupt signal is detected from the external card. in 1-bit mode, the sdhc will detect the card interrupt without the sd clock to support wakeup. in 4-bit mode, the card interrupt signal is sampled during the interrupt cycle, so the interrupt from card can only be sampled during interrupt cycle, introducing some delay between the interrupt signal from the sdio card and the interrupt to the host system. writing this bit to 1 can clear this bit, but as the interrupt factor from the sdio card does not clear, this bit is set again. in order to clear this bit, it is required to reset the interrupt factor from the external card followed by a writing 1 to this bit. when this status has been set, and the host driver needs to service this interrupt, the card interrupt signal enable in the interrupt signal enable register should be 0 to stop driving the interrupt signal to the host system. after completion of the card interrupt service (it should reset the interrupt factors in the sdio card and the interrupt signal may not be asserted), write 1 to clear this bit, set the card interrupt signal enable to 1, and start sampling the interrupt signal again. 0b no card interrupt 1b generate card interrupt 7 crm card removal this status bit is set if the card inserted bit in the present state register changes from 1 to 0. when the host driver writes this bit to 1 to clear this status, the status of the card inserted in the present state register should be confirmed. because the card state may possibly be changed when the host driver clears this bit and the interrupt event may not be generated. when this bit is cleared, it will be set again if no card is inserted. in order to leave it cleared, clear the card removal status enable bit in interrupt status enable register. 0b card state unstable or inserted 1b card removed 6 cins card insertion this status bit is set if the card inserted bit in the present state register changes from 0 to 1. when the host driver writes this bit to 1 to clear this status, the status of the card inserted in the present state register should be confirmed. because the card state may possibly be changed when the host driver clears this bit and the interrupt event may not be generated. when this bit is cleared, it will be set again if a card is inserted. in order to leave it cleared, clear the card inserted status enable bit in interrupt status enable register. 0b card state unstable or removed 1b card inserted 5 brr buffer read ready this status bit is set if the buffer read enable bit, in the present state register, changes from 0 to 1. refer to the buffer read enable bit in the present state register for additional information. 0b not ready to read buffer 1b ready to read buffer 4 bwr buffer write ready this status bit is set if the buffer write enable bit, in the present state register, changes from 0 to 1. refer to the buffer write enable bit in the present state register for additional information. table continues on the next page... chapter 2 secured digital host controller sdhc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1 sdhc_irqstat field descriptions (continued) field description 0b not ready to write buffer 1b ready to write buffer 3 dint dma interrupt occurs only when the internal dma finishes the data transfer successfully. whenever errors occur during data transfer, this bit will not be set. instead, the dmae bit will be set. either simple dma or adma finishes data transferring, this bit will be set. 0b no dma interrupt 1b dma interrupt is generated 2 bge block gap event if the proctl[sabgreq] is set, this bit is set when a read or write transaction is stopped at a block gap. if proctl[sabgreq] is not set to 1, this bit is not set to 1. in the case of a read transaction: this bit is set at the falling edge of the dat line active status (when the transaction is stopped at sd bus timing). the read wait must be supported in order to use this function. in the case of write transaction: this bit is set at the falling edge of write transfer active status (after getting crc status at sd bus timing). 0b no block gap event 1b transaction stopped at block gap 1 tc transfer complete this bit is set when a read or write transfer is completed. in the case of a read transaction: this bit is set at the falling edge of the read transfer active status. there are two cases in which this interrupt is generated. the first is when a data transfer is completed as specified by the data length (after the last data has been read to the host system). the second is when data has stopped at the block gap and completed the data transfer by setting the proctl[sabgreq] (after valid data has been read to the host system). in the case of a write transaction: this bit is set at the falling edge of the dat line active status. there are two cases in which this interrupt is generated. the first is when the last data is written to the sd card as specified by the data length and the busy signal is released. the second is when data transfers are stopped at the block gap, by setting the proctl[sabgreq], and the data transfers are completed. (after valid data is written to the sd card and the busy signal released). 0b transfer not complete 1b transfer complete 0 cc command complete this bit is set when you receive the end bit of the command response (except auto cmd12). refer to the prsstat[cihb]. 0b command not complete 1b command complete memory map and register definition k60 sub-family reference manual, rev. 6, nov 2011 1600 freescale semiconductor, inc. 52.4.14 interrupt status enable register (sdhc_irqstaten) setting the bits in this register to 1 enables the corresponding interrupt status to be set by the specified event. if any bit is cleared, the corresponding interrupt status bit is also cleared (i.e. when the bit in this register is cleared, the corresponding bit in interrupt status register is always 0). note ? depending on proctl[iabg] bit setting, sdhc may be programmed to sample the card interrupt signal during the interrupt period and hold its value in the flip-flop. there will be some delays on the card interrupt, asserted from the card, to the time the host system is informed. ? to detect a cmd line conflict, the host driver must set both irqstaten[ctoesen] and irqstaten[ccesen] to 1. address: sdhc_irqstaten is 400b_1000h base + 34h offset = 400b_1034h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 dmaesen 0 ac12esen 0 debesen dcesen dtoesen ciesen cebesen ccesen ctoesen w reset 0 0 0 1 0 0 0 1 0 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 cintsen crmsen cinsen brrsen bwrsen dintsen bgesen tcsen ccsen w reset 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 sdhc_irqstaten field descriptions field description 31?29 reserved this read-only field is reserved and always has the value zero. 28 dmaesen dma error status enable 0b masked 1b enabled 27?25 reserved this read-only field is reserved and always has the value zero. table continues on the next page... chapter 2 secured digital host controller sdhc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1601 sdhc_irqstaten field descriptions (continued) field description 24 ac12esen auto cmd12 error status enable 0b masked 1b enabled 23 reserved this read-only field is reserved and always has the value zero. 22 debesen data end bit error status enable 0b masked 1b enabled 21 dcesen data crc error status enable 0b masked 1b enabled 20 dtoesen data timeout error status enable 0b masked 1b enabled 19 ciesen command index error status enable 0b masked 1b enabled 18 cebesen command end bit error status enable 0b masked 1b enabled 17 ccesen command crc error status enable 0b masked 1b enabled 16 ctoesen command timeout error status enable 0b masked 1b enabled 159 reserved this read-only field is reserved and always has the value zero. 8 cintsen card interrupt status enable if this bit is set to 0, the sdhc will clear the interrupt request to the system. the card interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. the host driver should clear the this bit before servicing the card interrupt and should set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts. 0b masked 1b enabled 7 crmsen card removal status enable table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 1602 freescale semiconductor, inc. sdhc_irqstaten field descriptions (continued) field description 0b masked 1b enabled 6 cinsen card insertion status enable 0b masked 1b enabled 5 brrsen buffer read ready status enable 0b masked 1b enabled 4 bwrsen buffer write ready status enable 0b masked 1b enabled 3 dintsen dma interrupt status enable 0b masked 1b enabled 2 bgesen block gap event status enable 0b masked 1b enabled 1 tcsen transfer complete status enable 0b masked 1b enabled 0 ccsen command complete status enable 0b masked 1b enabled chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1603 52.4.15 interrupt signal enable register (sdhc_irqsigen) this register is used to select which interrupt status is indicated to the host system as the interrupt. these status bits all share the same interrupt line. setting any of these bits to 1 enables interrupt generation. the corresponding status register bit will generate an interrupt when the corresponding interrupt signal enable bit is set. address: sdhc_irqsigen is 400b_1000h base + 38h offset = 400b_1038h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 dmaeien 0 ac12eien 0 debeien dceien dtoeien cieien cebeien cceien ctoeien w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 cintien crmien cinsien brrien bwrien dintien bgeien tcien ccien w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sdhc_irqsigen field descriptions field description 31?29 reserved this read-only field is reserved and always has the value zero. 28 dmaeien dma error interrupt enable 0b masked 1b enabled 27?25 reserved this read-only field is reserved and always has the value zero. 24 ac12eien auto cmd12 error interrupt enable 0b masked 1b enabled 23 reserved this read-only field is reserved and always has the value zero. 22 debeien data end bit error interrupt enable 0b masked 1b enabled 21 dceien data crc error interrupt enable table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 1604 freescale semiconductor, inc. sdhc_irqsigen field descriptions (continued) field description 0b masked 1b enabled 20 dtoeien data timeout error interrupt enable 0b masked 1b enabled 19 cieien command index error interrupt enable 0b masked 1b enabled 18 cebeien command end bit error interrupt enable 0b masked 1b enabled 17 cceien command crc error interrupt enable 0b masked 1b enabled 16 ctoeien command timeout error interrupt enable 0b masked 1b enabled 159 reserved this read-only field is reserved and always has the value zero. 8 cintien card interrupt enable 0b masked 1b enabled 7 crmien card removal interrupt enable 0b masked 1b enabled 6 cinsien card insertion interrupt enable 0b masked 1b enabled 5 brrien buffer read ready interrupt enable 0b masked 1b enabled 4 bwrien buffer write ready interrupt enable 0b masked 1b enabled 3 dintien dma interrupt enable table continues on the next page... chapter 2 secured digital host controller sdhc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 160 sdhc_irqsigen field descriptions (continued) field description 0b masked 1b enabled 2 bgeien block gap event interrupt enable 0b masked 1b enabled 1 tcien transfer complete interrupt enable 0b masked 1b enabled 0 ccien command complete interrupt enable 0b masked 1b enabled 52.4.16 auto cmd12 error status register (sdhc_ac12err) when the ac12esen bit in the status register is set, the host driver shall check this register to identify what kind of error the auto cmd12 indicated. this register is valid only when the auto cmd12 error status bit is set. the following table shows the relationship between the auto cmgd12 crc error and the auto cmd12 command timeout error. table 52-25. relationship between command crc error and command timeout error for auto cmd12 auto cmd12 crc error auto cmd12 timeout error type of error 0 0 no error 0 1 response timeout error 1 0 response crc error 1 1 cmd line conflict changes in auto cmd12 error status register can be classified in three scenarios: 1. when the sdhc is going to issue an auto cmd12. ? set bit 0 to 1 if the auto cmd12 can't be issued due to an error in the previous command. ? set bit 0 to 0 if the auto cmd12 is issued. 2. at the end bit of an auto cmd12 response. memory map and register definition k60 sub-family reference manual, rev. 6, nov 2011 1606 freescale semiconductor, inc. ? check errors correspond to bits 1-4. ? set bits 1-4 corresponding to detected errors. ? clear bits 1-4 corresponding to detected errors. 3. before reading the auto cmd12 error status bit 7. ? set bit 7 to 1 if there is a command that can't be issued. ? clear bit 7 if there is no command to issue. the timing for generating the auto cmd12 error and writing to the command register are asynchronous. after that, bit 7 shall be sampled when the driver is not writing to the command register. so it is suggested to read this register only when the irqstat[ac12e] is set. an auto cmd12 error interrupt is generated when one of the error bits (0-4) is set to 1. the command not issued by auto cmd12 error does not generate an interrupt. address: sdhc_ac12err is 400b_1000h base + 3ch offset = 400b_103ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 cnibac12e 0 ac12ie ac12ce ac12ebe ac12toe ac12ne w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sdhc_ac12err field descriptions field description 31?8 reserved this read-only field is reserved and always has the value zero. table continues on the next page... chapter 2 secured digital host controller sdhc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1607 sdhc_ac12err field descriptions (continued) field description 7 cnibac12e command not issued by auto cmd12 error setting this bit to 1 means cmd_wo_dat is not executed due to an auto cmd12 error (d04-d01) in this register. 0b no error 1b not issued 65 reserved this read-only field is reserved and always has the value zero. 4 ac12ie auto cmd12 index error occurs if the command index error occurs in response to a command. 0b no error 1b error, the cmd index in response is not cmd12 3 ac12ce auto cmd12 crc error occurs when detecting a crc error in the command response. 0b no crc error 1b crc error met in auto cmd12 response 2 ac12ebe auto cmd12 end bit error occurs when detecting that the end bit of command response is 0 which should be 1. 0b no error 1b end bit error generated 1 ac12toe auto cmd12 timeout error occurs if no response is returned within 64 sdclk cycles from the end bit of the command. if this bit is set to 1, the other error status bits (2-4) have no meaning. 0b no error 1b time out 0 ac12ne auto cmd12 not executed if memory multiple block data transfer is not started, due to a command error, this bit is not set because it is not necessary to issue an auto cmd12. setting this bit to 1 means the sdhc cannot issue the auto cmd12 to stop a memory multiple block data transfer due to some error. if this bit is set to 1, other error status bits (1-4) have no meaning. 0b executed 1b not executed memory map and register definition k60 sub-family reference manual, rev. 6, nov 2011 1608 freescale semiconductor, inc. 52.4.17 host controller capabilities (sdhc_htcapblt) this register provides the host driver with information specific to the sdhc implementation. the value in this register is the power-on-reset value, and does not change with a software reset. any write to this register is ignored. address: sdhc_htcapblt is 400b_1000h base + 40h offset = 400b_1040h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 vs18 vs30 vs33 srs dmas hss admas 0 mbl w reset 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sdhc_htcapblt field descriptions field description 31?27 reserved this read-only field is reserved and always has the value zero. 26 vs18 voltage support 1.8 v this bit shall depend on the host system ability. 0b 1.8 v not supported 1b 1.8 v supported 25 vs30 voltage support 3.0 v this bit shall depend on the host system ability. 0b 3.0 v not supported 1b 3.0 v supported 24 vs33 voltage support 3.3 v this bit shall depend on the host system ability. 0b 3.3 v not supported 1b 3.3 v supported table continues on the next page... chapter 2 secured digital host controller sdhc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 160 sdhc_htcapblt field descriptions (continued) field description 23 srs suspend/resume support this bit indicates whether the sdhc supports suspend / resume functionality. if this bit is 0, the suspend and resume mechanism, as well as the read wwait, are not supported, and the host driver shall not issue either suspend or resume commands. 0b not supported 1b supported 22 dmas dma support this bit indicates whether the sdhc is capable of using the internal dma to transfer data between system memory and the data buffer directly. 0b dma not supported 1b dma supported 21 hss high speed support this bit indicates whether the sdhc supports high speed mode and the host system can supply a sd clock frequency from 25 mhz to 50 mhz. 0b high speed not supported 1b high speed supported 20 admas adma support this bit indicates whether the sdhc supports the adma feature. 0b advanced dma not supported 1b advanced dma supported 19 reserved this read-only field is reserved and always has the value zero. 1816 mbl max block length this value indicates the maximum block size that the host driver can read and write to the buffer in the sdhc. the buffer shall transfer block size without wait cycles. 000b 512 bytes 001b 1024 bytes 010b 2048 bytes 011b 4096 bytes 150 reserved this read-only field is reserved and always has the value zero. memory map and register definition k60 sub-family reference manual, rev. 6, nov 2011 1610 freescale semiconductor, inc. 52.4.18 watermark level register (sdhc_wml) both write and read watermark levels (fifo threshold) are configurable. there value can range from 1 to 128 words. both write and read burst lengths are also configurable. there value can range from 1 to 31 words. address: sdhc_wml is 400b_1000h base + 44h offset = 400b_1044h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 wrwml 0 0 rdwml w reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 sdhc_wml field descriptions field description 31?29 reserved this read-only field is reserved and always has the value zero. 28?24 reserved this read-only field is reserved and always has the value zero. 23?16 wrwml write watermark level the number of words used as the watermark level (fifo threshold) in a dma write operation. also the number of words as a sequence of write bursts in back-to-back mode. the maximum legal value for the write watermark level is 128. 15?13 reserved this read-only field is reserved and always has the value zero. 12?8 reserved this read-only field is reserved and always has the value zero. 7?0 rdwml read watermark level the number of words used as the watermark level (fifo threshold) in a dma read operation. also the number of words as a sequence of read bursts in back-to-back mode. the maximum legal value for the read water mark level is 128. 52.4.19 force event register (sdhc_fevt) the force event register is not a physically implemented register. rather, it is an address at which the interrupt status register can be written if the corresponding bit of the interrupt status enable register is set. this register is a write only register and writing 0 to it has no effect. writing 1 to this register actually sets the corresponding bit of interrupt status register. a read from this register always results in 0's. in order to change the corresponding status bits in the interrupt status register, make sure to set sysctl[ipgen] so that bus clock is always active. chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1611 forcing a card interrupt will generate a short pulse on the dat[1] line, and the driver may treat this interrupt as a normal interrupt. the interrupt service routine may skip polling the card interrupt factor as the interrupt is self cleared. address: sdhc_fevt is 400b_1000h base + 50h offset = 400b_1050h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 w cint 0 dmae 0 ac12e 0 debe dce dtoe cie cebe cce ctoe reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 w 0 cnibac12e 0 ac12ie ac12ebe ac12ce ac12toe ac12ne reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sdhc_fevt field descriptions field description 31 cint force event card interrupt writing 1 to this bit generates a short low-level pulse on the internal dat[1] line, as if a self clearing interrupt was received from the external card. if enabled, the cint bit will be set and the interrupt service routine may treat this interrupt as a normal interrupt from the external card. 30?29 reserved this field is reserved. 28 dmae force event dma error forces the dmae bit of interrupt status register to be set. 27?25 reserved this field is reserved. 24 ac12e force event auto command 12 error forces the irqstat[ac12e] to be set. 23 reserved this field is reserved. 22 debe force event data end bit error table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 1612 freescale semiconductor, inc. sdhc_fevt field descriptions (continued) field description forces the irqstat[debe] bit to be set. 21 dce force event data crc error forces the irqstat[dce] bit to be set. 20 dtoe force event data time out error force the irqstat[dtoe] bit to be set. 19 cie force event command index error forces the irqstat[cce] bit to be set. 18 cebe force event command end bit error forces the irqstat[cebe] bit to be set. 17 cce force event command crc error forces the irqstat[cce] bit to be set. 16 ctoe force event command time out error forces the irqstat[ctoe] bit to be set. 158 reserved this field is reserved. 7 cnibac12e force event command not executed by auto command 12 error forces the ac12err[cnibac12e] bit to be set. 65 reserved this field is reserved. 4 ac12ie force event auto command 12 index error forces the ac12err[ac12ie] bit to be set. 3 ac12ebe force event auto command 12 end bit error forces the ac12err[ac12ebe] bit to be set. 2 ac12ce force event auto command 12 crc error forces the ac12err[ac12ce] bit to be set. 1 ac12toe force event auto command 12 time out error forces the ac12err[ac12toe] bit to be set. 0 ac12ne force event auto command 12 not executed forces the ac12err[ac12ne] bit to be set. chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1613 52.4.20 adma error status register (sdhc_admaes) when an adma error interrupt has occurred, the adma error states field in this register holds the adma state and the adma system address register holds the address around the error descriptor. for recovering from this error, the host driver requires the adma state to identify the error descriptor address as follows: ? st_stop: previous location set in the adma system address register is the error descriptor address. ? st_fds: current location set in the adma system address register is the error descriptor address. ? st_cadr: this state is never set because it only increments the descriptor pointer and doesnt generate an adma error. ? st_tfr: previous location set in the adma system address register is the error descriptor address. in case of a write operation, the host driver should use the acmd22 to get the number of the written block, rather than using this information, since unwritten data may exist in the host controller. the host controller generates the adma error interrupt when it detects invalid descriptor data (valid = 0) in the st_fds state. the host driver can distinguish this error by reading the valid bit of the error descriptor. table 52-30. adma error state coding d01-d00 adma error state (when error has occurred) contents of adma system address register 00 st_stop (stop dma) holds the address of the next executable descriptor command 01 st_fds (fetch descriptor) holds the valid descriptor address 10 st_cadr (change address) no adma error is generated 11 st_tfr (transfer data) holds the address of the next executable descriptor command memory map and register definition k60 sub-family reference manual, rev. 6, nov 2011 1614 freescale semiconductor, inc. address: sdhc_admaes is 400b_1000h base + 54h offset = 400b_1054h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 admadce admalme admaes w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sdhc_admaes field descriptions field description 314 reserved this read-only field is reserved and always has the value zero. 3 admadce adma descritor error this error occurs when invalid descriptor is fetched by adma. 0b no error 1b error 2 admalme adma length mismatch error this error occurs in the following 2 cases: ? while the block count enable is being set, the total data length specified by the descriptor table is different from that specified by the block count and block length. ? total data length can not be divided by the block length. 0b no error 1b error 10 admaes adma error state (when adma error is occurred.) this field indicates the state of the adma when an error has occurred during an adma data transfer. chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1615 52.4.21 adma system address register (sdhc_adsaddr) this register contains the physical system memory address used for adma transfers. address: sdhc_adsaddr is 400b_1000h base + 58h offset = 400b_1058h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r adsaddr 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sdhc_adsaddr field descriptions field description 31?2 adsaddr adma system address this register holds the word address of the executing command in the descriptor table. at the start of adma, the host driver shall set the start address of the descriptor table. the adma engine increments this register address whenever fetching a descriptor command. when the adma is stopped at the block gap, this register indicates the address of the next executable descriptor command. when the adma error interrupt is generated, this register shall hold the valid descriptor address depending on the adma state. the lower 2 bits of this register is tied to 0 so the adma address is always word aligned. since this register supports dynamic address reflecting, when tc bit is set, it automatically alters the value of internal address counter, so sw cannot change this register when tc bit is set. 1?0 reserved this read-only field is reserved and always has the value zero. 52.4.22 vendor specific register (sdhc_vendor) this register contains the vendor specific control/status register. address: sdhc_vendor is 400b_1000h base + c0h offset = 400b_10c0h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 intstval w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 exblknu extdmaen w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 memory map and register definition k60 sub-family reference manual, rev. 6, nov 2011 1616 freescale semiconductor, inc. sdhc_vendor field descriptions field description 3128 reserved this read-only field is reserved and always has the value zero. 2724 reserved this read-only field is reserved and always has the value zero. 2316 intstval internal state value internal state value, reflecting the corresponding state value selected by debug select field. this field is read-only and write to this field does not have effect. 152 reserved this read-only field is reserved and always has the value zero. 1 exblknu exact block number block read enable for sdio cmd53 this bit must be set before s/w issues cmd53 multi-block read with exact block number. this bit must not be set if the cmd53 multi-block read is not exact block number. 0 none exact block read. 1 exact block read for sdio cmd53. 0 extdmaen external dma request enable enable the request to external dma. when the internal dma (either simple dma or advanced dma) is not in use, and this bit is set, sdhc will send out dma request when the internal buffer is ready. this bit is particularly useful when transferring data by cpu polling mode, and it is not allowed to send out the external dma request. by default, this bit is set. 0 in any scenario, sdhc does not send out external dma request. 1 when internal dma is not active, the external dma request will be sent out. chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1617 52.4.23 mmc boot register (sdhc_mmcboot) this register contains the mmc fast boot control register. address: sdhc_mmcboot is 400b_1000h base + c4h offset = 400b_10c4h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r bootblkcnt w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 autosabgen booten bootmode bootack dtocvack w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sdhc_mmcboot field descriptions field description 31?16 bootblkcnt the value defines the stop at block gap value of automatic mode. when received card block cnt is equal to bootblkcnt and autosabgen is 1, then stop at block gap. 15?8 reserved this read-only field is reserved and always has the value zero. 7 autosabgen when boot, enable auto stop at block gap function. this function will be triggered, and host will stop at block gap when received card block cnt is equal to bootblkcnt. 6 booten boot mode enable 0 fast boot disable 1 fast boot enable 5 bootmode boot mode select 0 normal boot 1 alternative boot 4 bootack boot ack mode select 0 no ack 1 ack 3?0 dtocvack boot ack time out counter value. 0000b sdclk x 2^8 0001b sdclk x 2^9 0010b sdclk x 2^10 table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 1618 freescale semiconductor, inc. sdhc_mmcboot field descriptions (continued) field description 0011b sdclk x 2^11 0100b sdclk x 2^12 0101b sdclk x 2^13 0110b sdclk x 2^14 0111b sdclk x 2^15 ... 1110b sdclk x 2^22 1111b reserved 52.4.24 host controller version (sdhc_hostver) this register contains the vendor host controller version information. all bits are read only and will read the same as the power-reset value. address: sdhc_hostver is 400b_1000h base + fch offset = 400b_10fch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 vvn svn w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 sdhc_hostver field descriptions field description 31?16 reserved this read-only field is reserved and always has the value zero. 15?8 vvn vendor version number these status bits are reserved for the vendor version number. the host driver shall not use this status. 00h freescale sdhc version 1.0 10h freescale sdhc version 2.0 11h freescale sdhc version 2.1 12h freescale sdhc version 2.2 all others reserved 7?0 svn specification version number these status bits indicate the host controller specification version. 01h sd host specification version 2.0, supports test event register and adma. all others reserved chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1619 52.5 functional description the following sections provide a brief functional description of the major system blocks, including the data buffer, dma crossbar switch interface, dual-port memory wrapper, data/command controller, clock & reset manager and clock generator. 52.5.1 data buffer the sdhc uses one configurable data buffer, so that data can be transferred between the system bus and the sd card, with an optimized manner to maximize throughput between the two clock domains (that is, the ip peripheral clock, and the master clock). the following diagram illustrates the buffer scheme. the buffer is used as temporary storage for data being transferred between the host system and the card. the watermark levels for read and write are both configurable, and can be any number from 1 to 128 words. the burst lengths for read and write are also configurable, and can be any number from 1 to 31 words. register bus i/f sd bus i/f sdhc registers ahb bus internal dma buffer ram wrapper sync fifos status sync tx / rx fifo buffer control figure 52-27. sdhc buffer scheme there are 3 transfer modes to access the data buffer: ? cpu polling mode: ? for a host read operation, when the number of words received in the buffer meets or exceeds the rdwml watermark value, then by polling the irqstat[brr] bit the host driver can read the datport register to fetch the amount of words set in the wml register from the buffer. the write operation is similar. functional description k60 sub-family reference manual, rev. 6, nov 2011 1620 freescale semiconductor, inc. ? external dma mode: ? for a read operation, when there are more words received in the buffer than the amount set in the rdwml register, a dma request is sent out to inform the external dma to fetch the data. the request will be immediately de-asserted when there is an access on the datport register. if the number of words in the buffer after the current burst meets or exceeds rdwml value, then the dma request is asserted again. so for instance if there are twice as many words in the buffer than the rdwml value, there are two successive dma requests with only one cycle of de-assertion between. the write operation is similar. note the accesses cpu polling mode and external dma mode both use the ip bus, and if the external dma is enable, in both modes an external dma request is sent out whenever the buffer is ready. ? internal dma mode (includes simple and advanced dma access's): ? the internal dma access, either by simple or advanced dma, is over the crossbar switch bus. for internal dma access mode, the external dma request will never be sent out. for a read operation, when there are more words in the buffer than the amount set in the wml register, the internal dma starts fetching data over the crossbar switch bus. except incr4 and incr8, the burst type is always incr mode and the burst length depends on the shortest of following factors: 1. burst length configured in the burst length field of the wml register 2. watermark level boundary 3. block size boundary 4. data boundary configured in the current descriptor (if the adma is active) 5. 1 kb address boundary write operation is similar. sequential and contiguous access is necessary to ensure the pointer address value is correct. random or skipped access is not possible. the byte order, by reset, is little endian mode. the actually byte order is swapped inside the buffer, according to the endian mode configured by software, as illustrated in the following diagrams. for a host write operation, byte order is swapped after data is fetched from the buffer and ready to send to the sd bus. for a host read operation, byte order is swapped before the data is stored into the buffer. chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1621 sdhc data buffer system ip bus or system ahb bus 7-0 31-24 23-16 15-8 7-0 15-8 23-16 31-24 figure 52-28. data swap between system bus and sdhc data buffer in byte little endian mode sdhc data buffer system ip bus or system ahb bus 7-0 15-8 7-0 31-24 23-16 15-8 23-16 31-24 figure 52-29. data swap between system bus and sdhc data buffer in half word big endian mode 52.5.1.1 write operation sequence there are three ways to write data into the buffer when the user transfers data to the card: 1. by using external dma through the sdhc dma request signal. 2. by processor core polling through the irqstat[bwr] bit (interrupt or polling). 3. by using the internal dma. when the internal dma is not used, (i.e. the xfertyp[dmaen] bit is not set when the command is sent), the sdhc asserts a dma request when the amount of buffer space exceeds the value set in the wml register, and is ready for receiving new data. at the same time, the sdhc would set the irqstat[bwr] bit. the buffer write ready interrupt will be generated if it is enabled by software. when internal dma is used, the sdhc will not inform the system before all the required number of bytes are transferred (if no error was encountered). when an error occurs during the data transfer, the sdhc will abort the data transfer and abandon the current block. the host driver should read the contents of the dsaddr to get the starting address of the abandoned data block. if the current data transfer is in multi block mode, the sdhc will not automatically send cmd12, even though the xfertyp[ac12en] bit is set. the host driver shall send cmd12 in this scenario and re-start the write operation from that address. it is recommended that a software reset for data be applied before the transfer is re-started after error recovery. functional description k60 sub-family reference manual, rev. 6, nov 2011 1622 freescale semiconductor, inc. the sdhc will not start data transmission until the number of words set in the wml register can be held in the buffer. if the buffer is empty and the host system does not write data in time, the sdhc will stop the sd_clk to avoid the data buffer under-run situation. 52.5.1.2 read operation sequence there are three ways to read data from the buffer when the user transfers data to the card: 1. by using the external dma through the sdhc dma request signal 2. by processor core polling through the irqstat[brr] bit (interrupt or polling) 3. by using the internal dma when internal dma is not used (i.e. xfertyp[dmaen] bit is not set when the command is sent), the sdhc asserts a dma request when the amount of data exceeds the value set in the wml register, that is available and ready for system fetching data. at the same time, the sdhc would set the irqstat[brr] bit. the buffer read ready interrupt will be generated if it is enabled by software. when internal dma is used, the sdhc will not inform the system before all the required number of bytes are transferred (if no error was encountered). when an error occurs during the data transfer, the sdhc will abort the data transfer and abandon the current block. the host driver should read the content of the dma system address register to get the starting address of the abandoned data block. if the current data transfer is in multi block mode, the sdhc will not automatically send cmd12, even though the xfertyp[ac12en] bit is set. the host driver shall send cmd12 in this scenario and re-start the read operation from that address. it is recommended that a software reset for data be applied before the transfer is re-started after error recovery. for any write transfer mode, the sdhc will not start data transmission until the number of words set in the wml register are in the buffer. if the buffer is full and the host system does not read data in time, the sdhc will stop the sdhc_dclk to avoid the data buffer over-run situation. 52.5.1.3 data buffer and block size the user needs to know the buffer size, for the buffer operation during a data transfer, to utilize it in the most optimized way. in the sdhc, the only data buffer can hold up to 128 words (32-bit), and the watermark levels for write and read can be configured respectively. for both read and write, the watermark level can be from 1 word to the chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1623 maximum of 128 words. for both read and write, the burst length, can be from 1 word to the maximum of 31 words. the host driver may configure the value according to the system situation and requirement. during a multi-block data transfer, the block length may be set to any value between 1 and 4096 bytes inclusive which satisfies the requirements of the external card. the only restriction is from the external card. it might not support that large of a block or it doesn't support a partial block access (which is not the integer times of 512 bytes). for block size not times of 4, i.e., not word aligned, sdhc requires stuff bytes at the end of each block, because sdhc treats each block individually. for example, the block size is 7 bytes, there are 12 blocks to write, the system side must write 2 times for each block, and for each block, the ending byte would be abandoned by sdhc since it only sends 7 bytes to the card and picks data from the following system write, so there would be 24 beats of write access in total. 52.5.1.4 dividing large data transfer this sdio command cmd53 definition, limits the maximum data size of data transfers according to the following formula: max data size = block size x block count the length of a multiple block transfer needs to be in block size units. if the total data length can't be divided evenly into a multiple of the block size, then there are two ways to transfer the data which depend on the function and the card design. option 1 is for the host driver to split the transaction. the remainder of the block size data is then transferred by using a single block command at the end. option 2 is to add dummy data in the last block to fill the block size. for option 2, the card must manage the removal of the dummy data. the following diagram illustrates the dividing of large data transfers. assuming a kind of wlan sdio card only supports block size up to 64 bytes. although the sdhc supports a block size of up to 4096 bytes, the sdio can only accept a block size less than64 bytes, so the data must be divided (see example below). functional description k60 sub-family reference manual, rev. 6, nov 2011 1624 freescale semiconductor, inc. cm d 53cm d 53 sdio data block #1 sdio data block #1 data 64 bytes data 64 bytes data 32 bytes sdio data 32 bytes sdio data 32 bytes data 64 bytes sdio data block #2 sdio data block #2 e igh t 64 b yt e b lock s ar e sen t in b lock t r an sf er m od e an d t h e r em ain d er 32 b yt es ar e sen t in b yt e t r an sf er m od e wlan frame is divided equally into 64 byte blocks plus the remainder 32 bytes 544 bytes wlan frame sdio data block #8 sdio data block #8 cm d 53 frame body icv fcs iv 802. . 11 mac header when the internal dma is not in use, and external dma request is enabled, the data buffer will generate a dma request to the system. during a write operation, when the number of wrwml words can be held in the buffer free space, a dma request is sent , informing the host system of a dma write. the irqstat[bwr] bit is also set, as long as the irqstaten[bwrsen] bit is set. the dma request is immediately de-asserted when an access to the datport register is made. if the buffer's free space still meets the watermark condition, the dma request is asserted again after a cycle. on read operation, when the number of rdwml words are already in the buffer, a dma request is sent , informing the host system for a dma read. the irqstat[brr] bit is also set, as long as the irqstaten[brrsen] bit is set. the dma request is immediately de-asserted when an access to the datport register is made. if the buffer's data still meets the watermark condition, the dma request is asserted again after a cycle. chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1625 because the dma burst length can't change during a data transfer for an external dma transfer, the watermark level (read or write) must be a divisor of the block size. if it is not, transferring of the block may cause buffer under-run (read operation) or over-run (write operation). for example, if the block size is 512 bytes, the watermark level of read (or write) must be a power of two between 1 and 128. for processor core polling access, as the last access in the block transfer can be controlled by software, there is no such issue. the watermark level can be any value, even larger than the block size (but no greater than 128 words). this is because the actual number of bytes transferred by the software can be controlled and does not exceed the block size in each transfer. the sdhc also supports non-word aligned block size, as long as the card supports that block size. in this case, the watermark level should be set as the number of words. for example, if the block size is 31 bytes, the watermark level can be set to any number of word. for this case, the blkattr[blksize] bits shall be set as 1fh. for the cpu polling access, the burst length can be 1 to 128 words, without restriction. this is because the software will transfer 8 words, and the sdhc will also set the irqstat[bwr] or irqstat[brr] bits when the remaining data does not violate data buffer. refer to dma burst length for more details about the dynamic watermark level of the data buffer. for the above example, even though 8 words are transferred via the datport register, the sdhc will transfer only 31 bytes over the sd bus, as required by the blkattr[blksize] bits. in this data transfer, with non-word aligned block size, the endian mode should be set cautiously, or invalid data will be transferred to/from the card. 52.5.2 dma crossbar switch interface the internal dma implements a dma engine and the crossbar switch master. when the internal dma is enabled (xfertyp[dmaen] is set), the interrupt status bits are set if they are enabled. to avoid setting them, clear irqstaten[bwrsen, brrsen]. the following diagram illustrates the dma crossbar switch interface block. functional description k60 sub-family reference manual, rev. 6, nov 2011 1626 freescale semiconductor, inc. esdhc registers d ma engine dma request data exchange burst length error indication r/w indication buffer control master logic system address crossbar switch interface figure 52-31. dma crossbar switch interface block 52.5.2.1 internal dma request if the watermark level requirement is met in data transfer, and the internal dma is enabled, the data buffer block sends a dma request to the crossbar switch interface. meanwhile, the external dma request signal is disabled. the delay in response from the internal dma engine depends on the system bus loading and the priority assigned to the sdhc. the dma engine does not respond to the request during its burst transfer, but is ready to serve as soon as the burst is over. the data buffer de-asserts the request once an access to the buffer is made. upon access to the buffer by internal dma, the data buffer updates its internal buffer pointer, and when the watermark level is satisfied, another dma request is sent. the data transfer is in the block unit, and the subsequent watermark level is always set as the remaining number of words. for instance, for a multi block data read with each block size of 31 bytes, and the burst length set to 6 words. after the first burst transfer, if there are more than 2 words in the buffer (which might contain some data of the next block), another dma request read is sent. this is because the remaining number of words to send for the current block is (31 - 6 * 4) / 4 = 2. the sdhc will read 2 words out of the buffer, with 7 valid bytes and 1 stuff byte. 52.5.2.2 dma burst length just like a cpu polling access, the dma burst length for the internal dma engine can be from 1 to 16 words. the actual burst length for the dma depends on the lesser of the configured burst length or the remaining words of the current block. take the example in internal dma request again. the following burst length after 6 words are read will be 2 words, and the next burst length will be 6 words again. this is because the next block chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1627 starts, which is 31 bytes, more than 6 words. the host driver writer may take this variable burst length into account. it is also acceptable to configure the burst length as the divisor of the block size, so that each time the burst length will be the same. 52.5.2.3 crossbar switch master interface it is possible that the internal dma engine could fail during the data transfer. when this error occurs, the dma engine stops the transfer and goes to the idle state as well as the internal data buffer stops accepting incoming data. the irqstat[dmae] is set to inform the driver. once the dmae interrupt is received, the software shall send a cmd12 to abort the current transfer and read the dsaddr[dsaddr] to get the starting address of the corrupted block. after the dma error is fixed, the software should apply a data reset and re-start the transfer from this address to recover the corrupted block. 52.5.2.4 adma engine in the sd host controller standard, the new dma transfer algorithm called the adma (advanced dma) is defined. for simple dma, once the page boundary is reached, a dma interrupt will be generated and the new system address shall be programmed by the host driver. the adma defines the programmable descriptor table in the system memory. the host driver can calculate the system address at the page boundary and program the descriptor table before executing adma. it reduces the frequency of interrupts to the host system. therefore, higher speed dma transfers could be realized since the host mcu intervention would not be needed during long dma based data transfers. there are two types of adma: adma1 and adma2 in host controller. adma1 can support data transfer of 4 kb aligned data in system memory. adma2 improves the restriction so that data of any location and any size can be transferred in system memory. their formats of descriptor table are different. adma can recognize all kinds of descriptors define in sd host controller standard, and if 'end' flag is detected in the descriptor, adma will stop after this descriptor is processed. 52.5.2.4.1 adma concept and descriptor format for adma1, including the following descriptors: functional description k60 sub-family reference manual, rev. 6, nov 2011 1628 freescale semiconductor, inc. ? valid/invalid descriptor. ? nop descriptor. ? set data length descriptor. ? set data address descriptor. ? link descriptor. ? interrupt flag and end flag in descriptor. for adma2, including the following descriptors: ? valid/invalid descriptor. ? nop descriptor. ? rsv descriptor. ? set data length & address descriptor. ? link descriptor. ? interrupt flag and end flag in descriptor. adma2 deals with the lower 32-bit first, and then the higher 32-bit. if the 'valid' flag of descriptor is 0, it will ignore the high 32-bit. address field shall be set on word aligned(lower 2-bit is always set to 0). data length is in byte unit. adma will start read/write operation after it reaches the tran state, using the data length and data address analyzed from most recent descriptor(s). for adma1, the valid data length descriptor is the last set type descriptor before tran type descriptor. every tran type will trigger a transfer, and the transfer data length is extracted from the most recent set type descriptor. if there is no set type descriptor after the previous trans descriptor, the data length will be the value for previous transfer, or 0 if no set descriptor is ever met. for adma2, tran type descriptor contains both data length and transfer data address, so only a tran type descriptor can start a data transfer table 52-35. format of the adma1 descriptor table address/page field address/page field attribute field 31 12 11 6 5 4 3 2 1 0 address or data length 000000 act2 act1 0 int end valid table continues on the next page... chapter 2 secured digital host controller sdhc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 162 table 52-35. format of the adma1 descriptor table (continued) act2 act1 symbol comment 31-28 27-12 0 0 nop no operation dont care 0 1 set set data length 0000 data length 1 0 tran transfer data data address 1 1 link link descriptor descriptor address valid valid = 1 indicates this line of descriptor is effective. if valid = 0 generate adma error interrupt and stop adma. end end = 1 indicates current descriptor is the ending one. int int = 1 generates dma interrupt when this descriptor is processed. advanced dma dma interrupt transfer complete block gap event page data page data system memory system address register points to the head node of descriptor table system address register data length (invisible) flags flags state machine data address (invisible) address/length attribute tran link address address address address/length data length address address attribute set tran, end descriptor table sdma figure 52-32. concept and access method of adma1 descriptor table table 52-36. format of the adma2 descriptor table address field length reserved attribute field 63 32 31 16 15 06 05 04 03 02 01 00 32-bit address 16-bit length 0000000000 act2 act1 0 int end valid act2 act1 symbol comment operation 0 0 nop no operation don't care 0 1 rsv reserved same as nop. read this line and go to next one 1 0 tran transfer data transfer data with address and length set in this descriptor line 1 1 link link descriptor link to another descriptor table continues on the next page... functional description 60 sub-family reference manual, rev. 6, nov 2011 160 freescale semiconductor, inc. table 52-36. format of the adma2 descriptor table (continued) valid valid = 1 indicates this line of descriptor is effective. if valid = 0 generate adma error interrupt and stop adma. end end = 1 indicates current descriptor is the ending one. int int = 1 generates dma interrupt when this descriptor is done. system address register points to the head node of descriptor table system address register advanced dma system memory address address3 attribute tran, end address length attribute tran link length1 length2 address1 address2 data length (invisible) data address (invisible) flags state machine sdma adma error page data descriptor table page data transfer complete dma interrupt figure 52-33. concept and access method of adma2 descriptor table 52.5.2.4.2 adma interrupt if the 'interrupt' flag of descriptor is set, adma will generate an interrupt according to different type descriptor: for adma1: ? set type descriptor: interrupt is generated when data length is set. ? tran type descriptor: interrupt is generated when this transfer is complete. ? link type descriptor: interrupt is generated when new descriptor address is set. ? nop type descriptor: interrupt is generated just after this descriptor is fetched. for adma2: ? tran type descriptor: interrupt is generated when this transfer is complete. ? link type descriptor: interrupt is generated when new descriptor address is set. ? nop/rsv type descriptor: interrupt is generated just after fetch this descriptor. chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1631 52.5.2.4.3 adma error the adma stops whenever any error is encountered. these errors include: ? fetching descriptor error ? transfer error ? data length mismatch error adma descriptor error will be generated when it fails to detect 'valid' flag in the descriptor. if adma descriptor error occurs, the interrupt is not generated even if the 'interrupt' flag of this descriptor is set. when xfertyp[bcen] bit is set, data length set in buffer must equal to the whole data length set in descriptor nodes, otherwise data length mismatch error will be generated. if xfertyp[bcen] bit is not set, the whole data length set in descriptor should be times of block length, otherwise, when all data set in the descriptor nodes are done not at block boundary, the data mismatch error will occur. 52.5.3 sd protocol unit the sd protocol unit deals with all sd protocol affairs. the sd protocol unit performs the following functions: ? acts as the bridge between the internal buffer and the sd bus ? sends the command data as well as its argument serially ? stores the serial response bit stream into corresponding registers ? detects the bus state on the dat[0] line ? monitors the interrupt from the sdio card ? asserts the read wait signal ? gates off the sd clock when buffer is announcing danger status ? detects the write protect state the sd protocol unit consists of four sub modules: 1. sd transceiver. functional description k60 sub-family reference manual, rev. 6, nov 2011 1632 freescale semiconductor, inc. 2. sd clock and monitor. 3. command agent. 4. data agent. 52.5.3.1 sd transceiver in the sd protocol unit, the transceiver is the main control module. it consists of a fsm and control module, from which the control signals for all other three modules are generated. 52.5.3.2 sd clock & monitor this module monitors the signal level on all 8 data lines, the command lines, and directly routes the level values into the register bank. the driver can use this for debug purposes. the module also detects the cd (card detection) line as well as the dat[3] line. the transceiver reports the card insertion state according to the cd state, or the signal level on the dat[3] line, when the proctl[d3cd] bit is set. the module detects the wp (write protect) line. with the information of the wp state, the register bank will ignore the command, accompanied by a write operation, when the wp switch is on. if the internal data buffer is in danger, and the sd clock must be gated off to avoid buffer over/under-run, this module will assert the gate of the output sd clock to shut the clock off. after the buffer danger has recovered, and when the system access of the buffer catches up, the clock gate of this module will open and the sd clock will be active again. this module also drive sdhc_lctl output signal when the proctl[lctl] bit is set by the driver. 52.5.3.3 command agent the command agent deals with the transactions on the cmd line. the following diagram illustrates the structure for the command crc shift register. chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1633 crc out crc out clr_crc crc_in zerozero crc bus [0] crc bus [1] crc bus [2] crc bus [3] crc bus [4] crc bus [5] crc bus [6] figure 52-34. command crc shift register the crc polynomials for the cmd are as follows: generator polynomial: g(x) = x 7 + x 3 + 1 m(x) = (first bit) * x n + (second bit) * x n-1 +...+ (last bit) * x 0 crc[6:0] = remainder [(m(x) * x 7 ) / g(x)] 52.5.3.4 data agent the data agent deals with the transactions on the eight data lines. moreover, this module also detects the busy state on the dat[0] line, and generate the read wait state by the request from the transceiver. the crc polynomials for the dat are as follows: generator polynomial: g(x) = x 16 + x 12 + x 5 +1 m(x) = (first bit) * x n + (second bit) * x n-1 +...+ (last bit) * x 0 crc[15:0] = remainder [(m(x) * x 16 ) / g(x)] 52.5.4 clock & reset manager this module controls all the reset signals within the sdhc. there are four kinds of reset signals within sdhc: 1. hardware reset. 2. software reset for all. 3. software reset for the data part. 4. software reset for the command part. all these signals are fed into this module and stable signals are generated inside the module to reset all other modules. the module also gates off all the inside signals. there are three clocks inside the sdhc: functional description k60 sub-family reference manual, rev. 6, nov 2011 1634 freescale semiconductor, inc. 1. bus clock. 2. sdhc clock. 3. system clock. the module monitors the activities of all other modules, supplies the clocks for them, and when enabled, automatically gates off the corresponding clocks. 52.5.5 clock generator the clock generator generates the sdhc_clk by peripheral source clock in two stages. the following diagram illustrates the structure of the divider. the term "base" represents the frequency of peripheral source clock. 1st divisor by 1, 2, 3, ..., 16 base (sd_clk_2x*) sd_clk 2nd divisor by (1*), 2, 4, ..., 256 div figure 52-35. two stages of the clock divider the first stage outputs an intermediate clock (div), which can be base, base/2, base/3, ..., or base/16. the second stage is a prescaler, and outputs the actual clock (sdhc_clk). this clock is the driving clock for all sub modules of the sd protocol unit, and the sync fifos to synchronize with the data rate from the internal data buffer. the frequency of the clock output from this stage, can be div, div/2, div/4,..., or div/256. thus the highest frequency of the sdhc_clk is base, and the next highest is base/2, while the lowest frequency is base/4096. if the base clock is of equal duty ratio (usually true), the duty cycle of sdhc_clk is also 50%, even when the compound divisor is an odd value. 52.5.6 sdio card interrupt this section discusses sdio interrupt handling. 52.5.6.1 interrupts in 1-bit mode in this case the dat[1] pin is dedicated to providing the interrupt function. an interrupt is asserted by pulling the dat[1] low from the sdio card, until the interrupt service is finished to clear the interrupt. chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1635 52.5.6.2 interrupt in 4-bit mode since the interrupt and data line 1 share pin 8 in 4-bit mode, an interrupt will only be sent by the card and recognized by the host during a specific time. this is known as the interrupt period. the sdhc will only sample the level on pin 8 during the interrupt period. at all other times, the host will ignore the level on pin 8, and treat it as the data signal. the definition of the interrupt period is different for operations with single block and multiple block data transfers. in the case of normal single data block transmissions, the interrupt period becomes active two clock cycles after the completion of a data packet. this interrupt period lasts until after the card receives the end bit of the next command that has a data block transfer associated with it. for multiple block data transfers in 4-bit mode, there is only a limited period of time that the interrupt period can be active due to the limited period of data line availability between the multiple blocks of data. this requires a more strict definition of the interrupt period. for this case, the interrupt period is limited to two clock cycles. this begins two clocks after the end bit of the previous data block. during this 2-clock cycle interrupt period, if an interrupt is pending, the sdhc_d1 line will be held low for one clock cycle with the last clock cycle pulling sdhc_d1 high. on completion of the interrupt period, the card releases the sdhc_d1 line into the high z state. the sdhc samples the sdhc_d1] during the interrupt period when the proctl[iabg] bit is set. refer to sdio card specification v1.10f for further information about the sdio card interrupt. 52.5.6.3 card interrupt handling when the irqsigen[cintien] bit is set to 0, the sdhc clears the interrupt request to the host system. the host driver should clear this bit before servicing the sdio interrupt and should set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts. the sdio status bit is cleared by resetting the sdio interrupt. writing to this bit would have no effects. in 1-bit mode, the sdhc will detect the sdio interrupt with or without the sd clock (to support wakeup). in 4-bit mode, the interrupt signal is sampled during the interrupt period, so there are some sample delays between the interrupt signal from the sdio card and the interrupt to the host system interrupt controller. when the sdio status has been set, and the host driver needs to service this interrupt, so the sdio bit in the interrupt control register of sdio card will be cleared. this is required to clear the functional description k60 sub-family reference manual, rev. 6, nov 2011 1636 freescale semiconductor, inc. sdio interrupt status latched in the sdhc and to stop driving the interrupt signal to the system interrupt controller. the host driver must issue a cmd52 to clear the card interrupt. after completion of the card interrupt service, the sdio interrupt enable bit is set to 1, and the sdhc starts sampling the interrupt signal again. the following diagram illustrates the sdio card interrupt scheme and for the sequences of software and hardware events that take place during a card interrupt handling procedure. end enable card irq in host clear card irq in card response error? interrogate and service card irq disable card irq in host read irq status register detect and steer card irq command/ response handling sdio irq enable sdio irq status irq to cpu ip bus esdhc registers irq detecting & steering sd host sdio card sdio card irq routing irq0 irq1 function 0 function 1 clear irq0 clear irq1 enable card irq in host start no yes figure 52-36. card interrupt scheme and card interrupt detection and handling procedure 52.5.7 card insertion and removal detection the sdhc uses either the dat[3] pin or the cd pin to detect card insertion or removal. when there is no card on the mmc/sd bus, the dat[3] will be pulled to a low voltage level by default. when any card is inserted to or removed from the socket, the sdhc detects the logic value changes on the dat[3] pin and generates an interrupt. when the dat[3] pin is not used for card detection (for example, it is implemented in gpio), the cd pin must be connected for card detection. whether dat[3] is configured for card chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1637 detection or not, the cd pin is always a reference for card detection. whether the dat[3] pin or the cd pin is used to detect card insertion, the sdhc will send an interrupt (if enabled) to inform the host system that a card is inserted. 52.5.8 power management and wakeup events when there is no operation between the sdhc and the card through the sd bus, the user can completely disable the bus clock and sdhc clock in the chip level clock control module to save power. when the user needs to use the sdhc to communicate with the card, it can enable the clock and start the operation. in some circumstances, when the clocks to the sdhc are disabled, for instance, when the system is in low power mode, there are some events for which the user needs to enable the clock and handle the event. these events are called wakeup interrupts. the sdhc can generate these interrupt even when there are no clocks enabled. the three interrupts which can be used as wake up events are: 1. card removal interrupt 2. card insertion interrupt 3. interrupt from sdio card the sdhc offers a power management feature. by clearing the clock enabled bits in the system control register, the clocks are gated in the low position to the sdhc. for maximum power saving, the user can disable all the clocks to the sdhc when there is no operation in progress. these three wake up events (or wakeup interrupts) can also be used to wake up the system from low-power modes. note to make the interrupt a wakeup event, when all the clocks to the sdhc are disabled or when the whole system is in low power mode, the corresponding wakeup enabled bit needs to be set. refer to protocol control register for more information. 52.5.8.1 setting wakeup events for the sdhc to respond to a wakeup event, the software must set the respective wakeup enable bit before the cpu enters sleep mode. before the software disables the host clock, it should ensure that all of the following conditions have been met: functional description k60 sub-family reference manual, rev. 6, nov 2011 1638 freescale semiconductor, inc. ? no read or write transfer is active ? data and command lines are not active ? no interrupts are pending ? internal data buffer is empty 52.5.9 mmc fast boot in embedded multimediacard(emmc4.3) spec, add fast boot feature need hardware support. in boot operation mode, the master (multimediacard host) can read boot data from the slave (mmc device) by keeping cmd line low after power-on, or sending cmd0 with argument + 0xfffffffa (optional for slave), before issuing cmd1. there are two types of fast boot mode, ' boot operation ' and ' alternative boot operation ' in emmc4.3 spec. each type also has with acknowledge and without acknowledge modes. note for the emmc4.3 card setting, please refer to emmc4.3 spec 52.5.9.1 boot operation note in this block guide, this fast boot is called normal fast boot mode if the cmd line is held low for 74 clock cycles and more after power-up before the first command is issued, the slave recognizes that boot mode is being initiated and starts preparing boot data internally. within 1 second after the cmd line goes low, the slave starts to send the first boot data to the master on the dat line(s). the master must keep the cmd line low to read all of the boot data. if boot acknowledge is enabled, the slave has to send acknowledge pattern '010' to the master within 50 ms after the cmd line goes low. if boot acknowledge is disabled, the slave will not send out acknowledge pattern '010'. the master can terminate boot mode with the cmd line high. chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1639 boot operation will be terminated when all contents of the enabled boot data are sent to the master. after boot operation is executed, the slave shall be ready for cmd1 operation and the master needs to start a normal mmc initialization sequence by sending cmd1. dat[0] cmd clk 50ms max 1 sec.max 010 s ss e ee cmd1 resp cmd2 resp cmd3 resp 512bytes +crc 512bytes +crc boot termininted min 8 clocks + 48 clocks = 56 clocks required from cmd singal high to next mmc command figure 52-37. multimediacard state diagram (normal boot mode) 52.5.9.2 alternative boot operation this boot function is optional for the device. if bit 0 in the extended csd byte[228] is set to '1', the device supports the alternative boot operation. after power-up, if the host issues cmd0 with the argument of 0xfffffffa after 74 clock cycles, before cmd1is issued or the cmd line goes low, the slave recognizes that boot mode is being initiated and starts preparing boot data internally. within 1 second after cmd0 with the argument of 0xfffffffa is issued, the slave starts to send the first boot data to the master on the dat line(s). if boot acknowledge is enabled, the slave has to send the acknowledge pattern '010' to the master within 50ms after the cmd0 with the argument of 0xfffffffa is received. if boot acknowledge is disabled, theslave will not send out acknowledge pattern '010'. the master can terminate boot mode by issuing cmd0 (reset). boot operation will be terminated when all contents of the enabled boot data are sent to the master. after boot operation is executed, the slave shall be ready for cmd1 operation and the master needs to start a normal mmc initialization sequence by sending cmd1. functional description k60 sub-family reference manual, rev. 6, nov 2011 1640 freescale semiconductor, inc. min 74 clocks required after power is stable to start boot command dat[0] cmd note 1. cmd0 with argument 0xfffffffa clk cmd0 1 ss 50ms max 1 sec.max 010 e s se e cmd0/reset cmd1 resp cmd2 resp cmd3 resp 512bytes +crc 512bytes +crc figure 52-38. multimediacard state diagram (alternative boot mode) 52.6 initialization/application of sdhc all communication between system and cards are controlled by the host. the host sends commands of two types: broadcast and addressed (point-to-point). broadcast commands are intended for all cards, such as "go_idle_state", "send_op_cond", "all_send_cid" and etc. in broadcast mode, all cards are in the open-drain mode to avoid bus contention. refer to commands for mmc/sd/sdio/ce- ata for the commands of bc and bcr categories. after the broadcast command cmd3 is issued, the cards enter standby mode. addressed type commands are used from this point. in this mode, the cmd/dat i/o pads will turn to push-pull mode, to have the driving capability for maximum frequency operation. refer to commands for mmc/sd/sdio/ce-ata for the commands of ac and adtc categories. 52.6.1 command send and response receive basic operation assuming the data type word is an unsigned 32-bit integer, the below flow is a guideline for sending a command to the card(s): send_command(cmd_index, cmd_arg, other requirements) { word wcmd; // 32-bit integer to make up the data to write into transfer type register, it is recommended to implement in a bit-field manner wcmd = ( set bcen bit; if (auto12 command is to use) set ac12en bit; } } write_reg(cmdarg, wait sdhc interrupt y es, card presents no card presents (2) enable card detection irq voltage validation c h eck c i n s i rq s ta t [ ] c lear c i n s i en to dis able card detection irq ( 1 ) figure 52-39. flow diagram for card detection here is the card detection sequence: ? set the cinsien bit to enable card detection interrupt ? when an interrupt from the sdhc is received, check the irqstat[cins] bit in the interrupt status register to see if it was caused by card insertion ? clear the cinsien bit to disable the card detection interrupt and ignore all card insertion interrupts afterwards to detect a ce-ata device, after completing the normal mmc reset and initialization procedures, the host driver shall issue cmd 60 to check for a ce-ata signature. if the device responds to the command with the ce-ata signature, a ce-ata device has been found. then the driver should query ext_csd register byte 504 (s_cmd_set) in the mmc register space. if the ata bit (bit 4) is set, then the mmc device is an ata device. if the device indicates that it is an ata device, the driver should set the ata bit (bit 4) of the ext_csd register byte 191 (cmd_set) to activate the ata command set for use. to choose the command set, the driver shall issue cmd6. it is possible that the ce-ata device does not support the ata mode, so the driver shall not issue ata command to the device. 52.6.2.2 reset the host consists of three types of resets: ? hardware reset (card and host) which is driven by por (power on reset) chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1643 ? software reset (host only) is proceed by the write operation on the sysctl[rstd], sysctl[rstc], or sysctl[rsta] bits to reset the data part, command part, or all parts of the host controller, respectively ? card reset (card only). the command, "go_idle_state" (cmd0), is the software reset command for all types of mmc cards, sd memory cards, and ce-ata cards. this command sets each card into the idle state regardless of the current card state. for an sd i/o card, cmd52 is used to write an i/o reset in the cccr. the cards are initialized with a default relative card address (rca = 0x0000) and with a default driver stage register setting (lowest speed, highest driving current capability). after the card is reset, the host needs to validate the voltage range of the card.the following diagram illustrates the software flow to reset both the sdhc and the card. for ce-ata device that supports ata mode, before issuing cmd0 to reset the mmc layer, two cmd39 should be issued back-to-back to the ata control register. the first cmd39 shall have the srst bit set to one. the second cmd39 command shall have the srst bit cleared to zero. send 80 clocks to card v oltage v alidation write `1? to rsta bit to reset sdhc send cmd0/cmd52 to card to reset card figure 52-40. flow chart for reset of the sdhc and sd i/o card software_reset() { set_bit(sysctrl, rsta); // software reset the host set dtocv and sdclkfs bit fields to get the sd_clk of frequency around 400khz configure io pad to set the power voltage of external card to around 3.0v poll bits cihb and cdihb bits of prsstat to wait both bits are cleared set_bit(sysctrl, intia); // send 80 clock ticks for card to power up send_command(cmd_go_idle_state, 52.6.2.3 voltage validation all cards should be able to establish communication with the host using any operation voltage in the maximum allowed voltage range specified in the card specification. however, the supported minimum and maximum values for v dd are defined in the operation conditions register (ocr) and may not cover the whole range. cards that store the cid and csd data in the preload memory are only able to communicate this information under data transfer v dd conditions. this means if the host and card have non-common v dd ranges, the card will not be able to complete the identification cycle, nor will it be able to send csd data. therefore, a special command send_op_cont (cmd1 for mmc), sd_send_op_cont (acmd41 for sd memory) and io_send_op_cont (cmd5 for sd i/o) is used. for a ce-ata card, the process is the same as that of an mmc card. the voltage validation procedure is designed to provide a mechanism to identify and reject cards which do not match the v dd range(s) desired by the host. this is accomplished by the host sending the desired v dd voltage window as the operand of this command. cards that can't perform the data transfer in the specified range must discard themselves from further bus operations and go into the inactive state. by omitting the voltage range in the command, the host can query each card and determine the common voltage range before sending out-of-range cards into the inactive state. this query should be used if the host is able to select a common voltage range or if a notification shall be sent to the system when a non- usable card in the stack is detected. the following steps show how to perform voltage validation when a card is inserted: voltage_validation(voltage_range_arguement) { label the card as unknown; send_command(io_send_op_cond, 0x0, return; // } // end of if (no error ... else if (errors other than time-out occur) { // command/response pair is corrupted deal with it by program specific manner; } // of else if (response time-out else { // cmd55 is refuse, it must be mmc card or ce-ata card if (card is already labelled as sdcombo) { // change label re-label the card as sdio; ignore the error or report it; return; // card is identified as sdio card } // of if (card is ... send_command(send_op_cond, for mmc operation, the host starts the card identification process in open-drain mode with the identification clock rate lower than 400 khz and the power voltage higher than 2.7 v. the open drain driver stages on the cmd line allow parallel card operation during card identification. after the bus is activated the host will request the cards to send their valid operation conditions (cmd1). the response to cmd1 is the "wired or" operation on the condition restrictions of all cards in the system. incompatible cards are sent into the inactive state. the host then issues the broadcast command all_send_cid (cmd2), asking all cards for their unique card identification (cid) number. all unidentified cards (the cards in ready state) simultaneously start sending their cid numbers serially, while bit-wise monitoring their outgoing bit stream. those cards, whose outgoing cid bits do not match the corresponding bits on the command line in any one of the bit periods, stop sending their cid immediately and must wait for the next identification cycle. since the cid is unique for each card, only one card can be successfully send its full cid to the host. this card then goes into the identification state. thereafter, the host issues set_relative_addr (cmd3) to assign to the card a relative card address (rca). once the rca is received the card state changes to the standby state, and the card does not react in further identification cycles, and its output driver switches from open-drain to push-pull. the host repeats the process, mainly cmd2 and cmd3, until the host receives a time-out condition to recognize the completion of the identification process. for ce-ata operation (same interface as mmc cards): card_registry() { do { // decide rca for each card until response time-out if(card is labelled as sdcombo or sdio) { // for sdio card like device send_command(set_relative_addr, 0x00, <...>); // ask sdio card to publish its rca retrieve rca from response; } // end if (card is labelled as sdcombo ... else if (card is labelled as sd) { // for sd card send_command(all_send_cid, <...>); if (resp_timeout == wait_for_response(all_send_cid)) break; send_command(set_relative_addr, <...>); retrieve rca from response; } // else if (card is labelled as sd ... else if (card is labelled as mmc or ce-ata) { // treat ce-ata as mmc send_command(all_send_cid, <...>); rca = 0x1; // arbitrarily set rca, 1 here for example, this rca is also the relative address to access the ce-ata card send_command(set_relative_addr, 0x1 << 16, <...>); // send rca at upper 16 bits } // end of else if (card is labelled as mmc ... } while (response is not time-out); } 52.6.3 card access this section discusses the various card access methods. chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1647 52.6.3.1 block write this section discusses the block write access methods. 52.6.3.1.1 normal write during a block write (cmd24 - 27, cmd60, cmd61), one or more blocks of data are transferred from the host to the card with a crc appended to the end of each block by the host. if the crc fails, the card shall indicate the failure on the dat line. the transferred data will be discarded and not written, and all further transmitted blocks (in multiple block write mode) will be ignored. if the host uses partial blocks whose accumulated length is not block aligned and block misalignment is not allowed (csd parameter write_blk_misalign is not set, and the ce-ata card does not support partial block write, either), the card detects the block misalignment error and aborts the programming before the beginning of the first misaligned block. the card sets the address_error error bit in the status register, and while ignoring all further data transfer, waits in the receive-data-state for a stop command. for a ce-ata card, check the ce-ata card specification for its behavior in block misalignment. the write operation is also aborted if the host tries to write over a write protected area. for mmc and sd cards, programming of the cid and csd registers does not require a previous block length setting. the transferred data is also crc protected. if a part of the csd or cid register is stored in rom, then this unchangeable part must match the corresponding part of the receive buffer. if this match fails, then the card will report an error and not change any register contents. for all types of cards, some may require long and unpredictable periods of time to write a block of data. after receiving a block of data and completing the crc check, the card will begin writing and hold the dat line low if its write buffer is full and unable to accept new data from a new write_block command. the host may poll the status of the card with a send_status command (cmd13) or other means for sdio and ce- ata cards at any time, and the card will respond with its status. the responded status indicates whether the card can accept new data or whether the write process is still in progress. the host may deselect the card by issuing a cmd7 (to select a different card) to place the card into the standby state and release the dat line without interrupting the write operation. when re-selecting the card, it will reactivate the busy indication by pulling dat to low if the programming is still in progress and the write buffer is unavailable. initialization/application of sdhc k60 sub-family reference manual, rev. 6, nov 2011 1648 freescale semiconductor, inc. the software flow to write to a card incorporates the internal dma and the write operation is a multi-block write with the auto cmd12 enabled. for the other two methods (by means of external dma or cpu polling status) with different transfer methods, the internal dma parts should be removed and the alternative steps should be straightforward. the software flow to write to a card is described below: 1. check the card status, wait until the card is ready for data. 2. set the card block length/size: a. for sd/mmc cards, use set_blocklen (cmd16) b. for sdio cards or the i/o portion of sdcombo cards, use io_rw_direct (cmd52) to set the i/o block size bit field in the cccr register (for function 0) or fbr register (for functions 1~7) c. for ce-ata cards, configure bits 1~0 in the scrcontrol register 3. set the esdhc block length register to be the same as the block length set for the card in step 2. 4. set the esdhc number block register (nob), nob is 5 (for instance). 5. disable the buffer write ready interrupt, configure the dma settings and enable the esdhc dma when sending the command with data transfer. the ac12en bit should also be set. 6. wait for the transfer complete interrupt. 7. check the status bit to see if a write crc error occurred, or some another error, that occurred during the auto12 command sending and response receiving. 52.6.3.1.2 write with pause the write operation can be paused during the transfer. instead of stopping the sd_clk at any time to pause all the operations, which is also inaccessible to the host driver, the driver can set the proctl[sabgreq] to pause the transfer between the data blocks. as there is no time-out condition in a write operation during the data blocks, a write to all types of cards can be paused in this way, and if the dat0 line is not required to de-assert to release the busy state, no suspend command is needed. like in the flow described in normal write , the write with pause is shown with the same kind of write operation: chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1649 1. check the card status, wait until card is ready for data. 2. set the card block length/size: a. for sd/mmc, use set_blocklen (cmd16) b. for sdio cards or the i/o portion of sdcombo cards, use io_rw_direct(cmd52) to set the i/o block size bit field in the cccr register (for function 0) or fbr register (for functions 1~7) c. for ce-ata cards, configure bits 1~0 in the scrcontrol register 3. set the sdhc block length register to be the same as the block length set for the card in step 2. 4. set the sdhc number block register (nob), nob is 5 (for instance). 5. disable the buffer write ready interrupt, configure the dma settings and enable the sdhc dma when sending the command with data transfer. the xfertyp[ac12en] bit should also be set. 6. set the proctl[sabgreq] bit. 7. wait for the transfer complete interrupt. 8. clear the proctl[sabgreq] bit. 9. check the status bit to see if a write crc error occurred. 10. set the proctl[creq] bit to continue the write operation. 11. wait for the transfer complete interrupt. 12. check the status bit to see if a write crc error occurred, or some another error, that occurred during the auto12 command sending and response receiving. the number of blocks left during the data transfer is accessible by reading the contents of the blkattr[blkcnt] . as the data transfer and the setting of the proctl[sabgreq] bit are concurrent, and the delay of register read and the register setting, the actual number of blocks left may not be exactly the value read earlier. the driver shall read the value of blkattr[blkcnt] after the transfer is paused and the transfer complete interrupt is received. it is also possible the last block has begun when the stop at block gap request is sent to the buffer. in this case, the next block gap is actually the end of the transfer. these types of requests are ignored and the driver should treat this as a non-pause transfer and deal with it as a common write operation. initialization/application of sdhc k60 sub-family reference manual, rev. 6, nov 2011 1650 freescale semiconductor, inc. when the write operation is paused, the data transfer inside the host system is not stopped, and the transfer is active until the data buffer is full. because of this (if not needed), it is recommended to avoid using the suspend command for the sdio card. this is because when such a command is sent, the sdhc thinks the system will switch to another function on the sdio card, and flush the data buffer. the sdhc takes the resume command as a normal command with data transfer, and it is left for the driver to set all the relevant registers before the transfer is resumed. if there is only one block to send when the transfer is resumed, the xfertyp[msbsel] and xfertyp[bcen] bits are set as well as the xfertyp[ac12en] bit. however, the sdhc will automatically send a cmd12 to mark the end of the multi-block transfer. 52.6.3.2 block read this section discusses the block read access methods. 52.6.3.2.1 normal read for block reads, the basic unit of data transfer is a block whose maximum size is stored in areas defined by the corresponding card specification. a crc is appended to the end of each block, ensuring data transfer integrity. the cmd17, cmd18, cmd53, cmd60, cmd61, and so on, can initiate a block read. after completing the transfer, the card returns to the transfer state. for multi blocks read, data blocks will be continuously transferred until a stop command is issued. the software flow to read from a card incorporates the internal dma and the read operation is a multi-block read with the auto cmd12 enabled. for the other two methods (by means of external dma or cpu polling status) with different transfer methods, the internal dma parts should be removed and the alternative steps should be straightforward. the software flow to read from a card is described below: 1. check the card status, wait until card is ready for data. 2. set the card block length/size: a. for sd/mmc, use set_blocklen (cmd16) b. for sdio cards or the i/o portion of sdcombo cards, use io_rw_direct(cmd52) to set the i/o block size bit field in the cccr register (for function 0) or fbr register (for functions 1~7) c. for ce-ata cards, configure bits 1~0 in the scrcontrol register chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1651 3. set the sdhc block length register to be the same as the block length set for the card in step 2. 4. set the sdhc number block register (nob), nob is 5 (for instance). 5. disable the buffer read ready interrupt, configure the dma settings and enable the sdhc dma when sending the command with data transfer. the xfertyp[ac12en] bit should also be set: 6. wait for the transfer complete interrupt. 7. check the status bit to see if a read crc error occurred, or some another error, occurred during the auto12 command sending and response receiving. 52.6.3.2.2 read with pause the read operation is not generally able to pause. only the sdio card (and sdcombo card working under i/o mode) supporting the read and wait feature can pause during the read operation. if the sdio card support read wait (srw bit in cccr register is 1), the driver can set the sabgreq bit in the protocol control register to pause the transfer between the data blocks. before setting the sabgreq bit, make sure the rwctl bit in the protocol control register is set, otherwise the esdhc will not assert the read wait signal during the block gap and data corruption occurs. it is recommended to set the rwctl bit once the read wait capability of the sdio card is recognized. like in the flow described in normal read , the read with pause is shown with the same kind of read operation: 1. check the srw bit in the ccr register on the sdio card to confirm the card supports read wait. 2. set the rwctl bit. 3. check the card status and wait until the card is ready for data. 4. set the card block length/size: a. for sd/mmc, use set_blocklen (cmd16) b. for sdio cards or the i/o portion of sdcombo cards, use io_rw_direct(cmd52) to set the i/o block size bit field in the cccr register (for function 0) or fbr register (for functions 1~7) c. for ce-ata cards, configure bits 1~0 in the scrcontrol register initialization/application of sdhc k60 sub-family reference manual, rev. 6, nov 2011 1652 freescale semiconductor, inc. 5. set the sdhc block length register to be the same as the block length set for the card in step 2. 6. set the sdhc number block register (nob), nob is 5 (for instance). 7. disable the buffer read ready interrupt, configure the dma setting and enable the esdhc dma when sending the command with data transfer. the ac12en bit should also be set 8. set the sabgreq bit. 9. wait for the transfer complete interrupt. 10. clear the sabgreq bit. 11. check the status bit to see if read crc error occurred. 12. set the creq bit to continue the read operation. 13. wait for the transfer complete interrupt. 14. check the status bit to see if a read crc error occurred, or some another error, occurred during the auto12 command sending and response receiving. like the write operation, it is possible to meet the ending block of the transfer when paused. in this case, the sdhc will ignore the stop at block gap request and treat it as a command read operation. unlike the write operation, there is no remaining data inside the buffer when the transfer is paused. all data received before the pause will be transferred to the host system. no matter if the suspend command is sent or not, the internal data buffer is not flushed. if the suspend command is sent and the transfer is later resumed by means of a resume command, the sdhc takes the command as a normal one accompanied with data transfer. it is left for the driver to set all the relevant registers before the transfer is resumed. if there is only one block to send when the transfer is resumed, the msbsel and bcen bits of the transfer type register are set, as well as the ac12en bit. however, the sdhc will automatically send the cmd12 to mark the end of multi-block transfer. 52.6.3.3 suspend resume the sdhc supports the suspend resume operations of sdio cards, although slightly different than the suggested implementation of suspend in the sdio card specification.. chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1653 52.6.3.3.1 suspend after setting the proctl[sabgreq] bit, the host driver may send a suspend command to switch to another function of the sdio card. the sdhc does not monitor the content of the response, so it doesn't know if the suspend command succeeded or not. accordingly, it doesn't de-assert read wait for read pause. to solve this problem, the driver shall not mark the suspend command as a "suspend", (i.e. setting the xfertyp[cmdtyp] bits to 01). instead, the driver shall send this command as if it were a normal command, and only when the command succeeds, and the bs bit is set in the response, can the driver send another command marked as "suspend" to inform the sdhc that the current transfer is suspended. as shown in the following sequence for suspend operation: 1. set the proctl[sabgreq] bit to pause the current data transfer at block gap. 2. after the irqstat[bge] bit is set, send the suspend command to suspend the active function. the xfertyp[cmdtyp] bit field must be 2'b00. 3. check the bs bit of the cccr in the response. if it is 1, repeat this step until the bs bit is cleared or abandon the suspend operation according to the driver strategy. 4. send another normal i/o command to the suspended function. the xfertyp[cmdtyp] of this command must be 2'b01, so the sdhc can detect this special setting and be informed that the paused operation has successfully suspended. if the paused transfer is a read operation, the sdhc stops driving dat2 and goes to the idle state. 5. save the context registers in the system memory for later use, including the dma system address register (for internal dma operation), and the block attribute register. 6. begin operation for another function on the sdio card. 52.6.3.3.2 resume to resume the data transfer, a resume command shall be issued: 1. to resume the suspended function, restore the context register with the saved value in step #5 of the suspend operation above. 2. send the resume command. in the transfer type register, all bit fields are set to the value as if this were another ordinary data transfer, instead of a transfer resume (except the cmdtyp is set to 2'b10). 3. if the resume command has responded, the data transfer will be resumed. initialization/application of sdhc k60 sub-family reference manual, rev. 6, nov 2011 1654 freescale semiconductor, inc. 52.6.3.4 adma usage to use the adma in a data transfer, the host driver must prepare the correct descriptor chain prior to sending the read/write command. the steps to accomplish this are: 1. create a descriptor to set the data length that the current descriptor group is about to transfer. the data length should be even numbers of the block size. 2. create another descriptor to transfer the data from the address setting in this descriptor. the data address must be at a page boundary (4 kb address aligned). 3. if necessary, create a link descriptor containing the address of the next descriptor. the descriptor group is created in steps 1 ~ 3. 4. repeat steps 1 ~ 3 until all descriptors are created. 5. in the last descriptor, set the end flag to 1 and make sure the total length of all descriptors match the product of the block size and block number configured in the blkattr register. 6. set the dsaddr register to the address of the first descriptor and set the proctl[dmas] field to 01 to select the adma. 7. issue a write or read command with the xfertyp[dmaen] bit set to 1. steps 1 ~ 5 are independent of step 6, so step 6 can finish before steps 1 ~ 5. regarding the descriptor configuration, it is recommended not to use the link descriptor as it requires extra system memory access. 52.6.3.5 transfer error this section discusses the handling of transfer errors. 52.6.3.5.1 crc error it is possible at the end of a block transfer, that a write crc status error or read crc error occurs. for this type of error the latest block received shall be discarded. this is because the integrity of the data block is not guaranteed. it is recommended to discard the following data blocks and re-transfer the block from the corrupted one. for a multi-block transfer, the host driver shall issue a cmd12 to abort the current process and start the transfer by a new data command. in this scenario, even when the xfertyp[ac12en] and bcend bits are set, the sdhc does not automatically send a cmd12 because the chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1655 last block is not transferred. on the other hand, if it is within the last block that the crc error occurs, an auto cmd12 will be sent by the sdhc. in this case, the driver shall re- send or re-obtain the last block with a single block transfer. 52.6.3.5.2 internal dma error during the data transfer with internal simple dma, if the dma engine encounters some error on the system bus, the dma operation is aborted and dma error interrupt is sent to the host system. when acknowledged by such an interrupt, the driver shall calculate the start address of data block in which the error occurs. the start address can be calculated by either: 1. read the dma system address register. the error occurs during the previous burst. taking the block size, the previous burst length and the start address of the next burst transfer into account, it is straight forward to obtain the start address of the corrupted block. 2. read the blkcnt field of the block attribute register. by the number of blocks left, the total number to transfer, the start address of transfer, and the size of each block, the start address of corrupted block can be determined. when the bcen bit is not set, the contents of the block attribute register does not change, so this method does not work. when a dma error occurs, it is recommended to abort the current transfer by means of a cmd12 (for multi block transfer), apply a reset for data, and re-start the transfer from the corrupted block to recover from the error. 52.6.3.5.3 adma error there are three kinds of possible adma errors. the transfer, invalid descriptor, and data-length mismatch errors. whenever these errors occur, the dma transfer stops and the corresponding error status bit is set. for acknowledging the status, the host driver should recover the error as shown below and re-transfer from the place of interruption. 1. transfer error: such errors may occur during data transfer or descriptor fetch. for either scenario, it is recommended to retrieve the transfer context, reset for the data part and re-transfer the block that was corrupted, or the next block if no block is corrupted. initialization/application of sdhc k60 sub-family reference manual, rev. 6, nov 2011 1656 freescale semiconductor, inc. 2. invalid descriptor error: for such errors, it is recommended to retrieve the transfer context, reset for the data part and re-create the descriptor chain from the invalid descriptor and issue a new transfer. as the data to transfer now may be less than the previous setting, the data length configured in the new descriptor chain should match the new value. 3. data-length mismatch error: it is similar to recover from this error. the host driver polls relating registers to retrieve the transfer context, apply a reset for the data part, configure a new descriptor chain, and make another transfer if there is data left. like the previous scenario of the invalid descriptor error, the data length must match the new transfer. 52.6.3.5.4 auto cmd12 error after the last block of the multi block transfer is sent or received, and the xfertyp[ac12en] bit is set when the data transfer is initiated by the data command, the sdhc automatically sends a cmd12 to the card to stop the transfer. when errors with this command occur, it is recommended to the driver to deal with the situations in the following manner: 1. auto cmd12 response time-out. it is not certain whether the command is accepted by the card or not. the driver should clear the irqstat[ac12e] bits and re-send the cmd12 until it is accepted by the card. 2. auto cmd12 response crc error. since card responds to the cmd12, the card will abort the transfer. the driver may ignore the error and clear the irqstat[ac12e] bit. 3. auto cmd12 conflict error or not sent. the command is not sent, so the driver shall send a cmd12 manually. 52.6.3.6 card interrupt the external cards can inform the host controller by means of some special signals. for the sdio card, it can be the low level on the dat[1] line during some special period. for the ce-ata card, it can be a pulse on the cmd line to inform the host controller that the command and its response is finished, and it is possible that some additional external interrupt behaviors are defined. the sdhc only monitors the dat[1] line and supports the sdio interrupt. chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1657 when the sdio interrupt is captured by the sdhc, and the host system is informed by the sdhc asserting the sdhc interrupt line, the interrupt service from the host driver is called. as the interrupt factor is controlled by the external card, the interrupt from the sdio card must be served before the irqstat[cint] bit is cleared by written 1. refer to card interrupt handling for the card interrupt handling flow. 52.6.4 switch function mmc cards transferring data at bus widths other than 1-bit is a new feature added to the mmc specifications. the high speed timing mode for all card devices, was also recently defined in various card specifications. to enable these new features, a "switch" command shall be issued by the host driver. for sdio cards, the high speed mode is enabled by writing the ehs bit in the cccr register after the shs bit is confirmed. for sd cards, the high speed mode is queried and enabled by a cmd6 (with the mnemonic symbol as switch_func). for mmc cards (and ce-ata over mmc interface), the high speed mode is queried by a cmd8 and enabled by a cmd6 (with the mnemonic symbol as switch). the 4-bit and 8-bit bus width of the mmc is also enabled by the switch command, but with a different argument. these new functions can also be disabled by a software reset. for sdio cards it can be done by setting the res bit in the cccr register. for other cards, it can be accomplished by issuing a cmd0. this method of restoring to the normal mode is not recommended because a complete identification process is needed before the card is ready for data transfer. for the sake of simplicity, the following flowcharts do not show current capability check, which is recommended in the function switch process. 52.6.4.1 query, enable and disable sdio high speed mode enable_sdio_high_speed_mode(void) { send cmd52 to query bit shs at address 0x13; if (shs bit is '0') report the sdio card does not support high speed mode and return; send cmd52 to set bit ehs at address 0x13 and read after write to confirm ehs bit is set; change clock divisor value or configure the system clock feeding into esdhc to generate the card_clk of around 50mhz; (data transactions like normal peers) } disable_sdio_high_speed_mode(void) { initialization/application of sdhc k60 sub-family reference manual, rev. 6, nov 2011 1658 freescale semiconductor, inc. send cmd52 to clear bit ehs at address 0x13 and read after write to confirm ehs bit is cleared; change clock divisor value or configure the system clock feeding into esdhc to generate the card_clk of the desired value below 25mhz; (data transactions like normal peers) } 52.6.4.2 query, enable and disable sd high speed mode enable_sd_high_speed_mode(void) { set blkcnt field to 1 (block), set blksize field to 64 (bytes); send cmd6, with argument 0xfffff1 and read 64 bytes of data accompanying the r1 response; wait data transfer done bit is set; check if the bit 401 of received 512 bit is set; if (bit 401 is '0') report the sd card does not support high speed mode and return; send cmd6, with argument 0x80fffff1 and read 64 bytes of data accompanying the r1 response; check if the bit field 379~376 is 0xf; if (the bit field is 0xf) report the function switch failed and return; change clock divisor value or configure the system clock feeding into esdhc to generate the card_clk of around 50mhz; (data transactions like normal peers) } disable_sd_high_speed_mode(void) { set blkcnt field to 1 (block), set blksize field to 64 (bytes); send cmd6, with argument 0x80fffff0 and read 64 bytes of data accompanying the r1 response; check if the bit field 379~376 is 0xf; if (the bit field is 0xf) report the function switch failed and return; change clock divisor value or configure the system clock feeding into esdhc to generate the card_clk of the desired value below 25mhz; (data transactions like normal peers) } 52.6.4.3 query, enable and disable mmc high speed mode enable_mmc_high_speed_mode(void) { send cmd9 to get csd value of mmc; check if the value of spec_ver field is 4 or above; if (spec_ver value is less than 4) report the mmc does not support high speed mode and return; set blkcnt field to 1 (block), set blksize field to 512 (bytes); send cmd8 to get ext_csd value of mmc; extract the value of card_type field to check the 'high speed mode' in this mmc is 26mhz or 52mhz; send cmd6 with argument 0x1b90100; send cmd13 to wait card ready (busy line released); send cmd8 to get ext_csd value of mmc; check if hs_timing byte (byte number 185) is 1; if (hs_timing is not 1) report mmc switching to high speed mode failed and return; change clock divisor value or configure the system clock feeding into esdhc to generate the card_clk of around 26mhz or 52mhz according to the card_type; (data transactions like normal peers) } disable_mmc_high_speed_mode(void) { send cmd6 with argument 0x2b90100; set blkcnt field to 1 (block), set blksize field to 512 (bytes); send cmd8 to get ext_csd value of mmc; check if hs_timing byte (byte number 185) is 0; chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1659 if (hs_timing is not 0) report the function switch failed and return; change clock divisor value or configure the system clock feeding into esdhc to generate the card_clk of the desired value below 20mhz; (data transactions like normal peers) } 52.6.4.4 set mmc bus width change_mmc_bus_width(void) { send cmd9 to get csd value of mmc; check if the value of spec_ver field is 4 or above; if (spec_ver value is less than 4) report the mmc does not support multiple bit width and return; send cmd6 with argument 0x3b70x00; (8-bit, x=2; 4-bit, x=1; 1-bit, x=0) send cmd13 to wait card ready (busy line released); (data transactions like normal peers) } 52.6.5 adma operation this section presents code examples for adma operation. 52.6.5.1 adma1 operation set_adma1_descriptor { if (to start data transfer) { // make sure the address is 4kb align. set 'set' type descriptor; { set act bits to 01; set [31:12] bits data length (byte unit); } set 'tran' type descriptor; { set act bits to 10; set [31:12] bits address (4kb align); } } else if (to fetch descriptor at non-continuous address) { set act bits to 11; set [31:12] bits the next descriptor address (4kb align); } else { // other types of descriptor set act bits accordingly } if (this descriptor is the last one) { set end bit to 1; } if (to generate interrupt for this descriptor) { set int bit to 1; } set valid bit to 1; } initialization/application of sdhc k60 sub-family reference manual, rev. 6, nov 2011 1660 freescale semiconductor, inc. 52.6.5.2 adma2 operation set_adma2_descriptor { if (to start data transfer) { // make sure the address is 32-bit boundary (lower 2-bit are always '00'). set higher 32-bit of descriptor for this data transfer initial address; set [31:16] bits data length (byte unit); set act bits to '10'; } else if (to fetch descriptor at non-continuous address) { set act bits to '11'; // make sure the address is 32-bit boundary (lower 2-bit are always set to '00'). set higher 32-bit of descriptor for the next descriptor address; } else { // other types of descriptor set act bits accordingly } if (this descriptor is the last one) { set 'end' bit '1'; } if (to generate interrupt for this descriptor) { set 'int' bit '1'; } set the 'valid' bit to '1'; } 52.6.6 fast boot operation this section discusses fast boot operations. 52.6.6.1 normal fast boot flow 1. software need to configure sysctl[inita] to make sure 74 card clocks are finished. 2. software need to configure mmcboot[booten] to 1, and mmcboot[bootmode] to 0, and mmcboot[bootack] to select the ack mode or not. if need to send through dma mode, need to configure mmcboot[autosabgen] to enable automatically stop at block gap feature. and need to configure mmcboot[dtocvack] to select the ack timeout value according to the sd clk frequence. 3. software then need to configure blkattr register to set block size/no. 4. software need to configure proctl[dtw]. 5. software need to configure cmdarg to set argument if needed(no need in normal fast boot). chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1661 6. software need to configure xfertyp register to start the boot process . in normal boot mode, xfertyp[cmdinx], xfertyp[cmdtyp], xfertyp[rsptyp], xfertyp[cicen], xfertyp[cccen], xfertyp[ac12en], xfertyp[bcen] and xfertyp[dmaen] are kept default value. xfertyp[dpsel] bit is set to 1, xfertyp[dtdsel] is set to 1, xfertyp[msbsel] is set to 1. note xfertyp[dmaen] should be configured as 0 in polling mode. and if xfertyp[bcen] is configured as 1, better to configure blkattr[blksize] to the max value. 7. when the step 6 is configured, boot process will begin. software need to poll the data buffer ready status to read the data from buffer in time. if boot time-out happened(ack time out or the first data read time out), interrupt will be triggered, and software need to configure mmcboot[]booten] to 0 to disable boot. thus will make cmd high, and then after at least 56 clocks, it is ready to begin normal initialization process. 8. if no time out, software need to decide the data read is finished and then configure mmcboot[]booten] to 0 to disable boot. this will make cmd line high and command completed asserted. after at least 56 clocks, it is ready to begin normal initialization process. 9. reset the host and then can begin the normal process. 52.6.6.2 alternative fast boot flow 1. software need to configure init_active bit (system control register bit 27) to make sure 74 card clocks are finished. 2. software need to configure mmcboot [booten] to 1, and mmcboot [bootmode] to 1, and mmcboot [bootack] to select the ack mode or not. if need to send through dma mode, need to configure mmcboot [autosabgen] to enable automatically stop at block gap feature. and need to configure mmcboot [dtocvack] to select the ack timeout value according to the sd clk frequence. 3. software then need to configure blkattr register to set block size/no. 4. software need to configure proctl[dtw]. 5. software need to configure cmdarg register to set argument to 0xfffffffa. 6. software need to configure xfertyp register to start the boot process by cmd0 with 0xfffffffa argument . in alternative boot, cmdinx, cmdtyp, rsptyp, cicen, cccen, ac12en, bcen and dmaen are kept default value. dpsel bit initialization/application of sdhc k60 sub-family reference manual, rev. 6, nov 2011 1662 freescale semiconductor, inc. is set to 1, dtdsel is set to 1, msbsel is set to 1. note dmaen should be configured as 0 in polling mode. and if bcen is configured as 1 in polling mode, better to configure blk no in bock attributes register to the max value. 7. when the step 6 is configured, boot process will begin. software need to poll the data buffer ready status to read the data from buffer in time. if boot time out (ack data time out in 50ms or data time out in 1s), host will send out the interrupt and software need to send cmd0 with reset and then configure boot enable bit to 0 to stop this process. after command completed, configure mmcboot[booten] to 0 to disable boot. after at least 8 clocks from command completed, card is ready for identification step. 8. if no time out, software need to decide when to stop the boot process, and send out the cmd0 with reset and then after command completed, configure mmcboot[booten] to stop the process. after 8 clocks from command completed, slave(card) is ready for identification step. 9. reset the host and then can begin the normal process. 52.6.6.3 fast boot application case (in dma mode) in the boot application case, because the image destination and the image size are contained in the beginning of the image, need to switch dma parameters on the fly during mmc fast boot. in fast boot, host can use adma2(advanced dma2) with two destinations. the detail flow: 1. software need to configure init_active bit (system control register bit 27) to make sure 74 card clocks are finished. 2. software need to configure mmcboot[booten] to 1; and mmcboot[bootmode] to 0 (normal fast boot), to 1(alternative boot); and mmcboot[bootack] to select the ack mode or not. in dma mode, configure mmcboot[autosabgen] to 1 for enable automatically stop at block gap feature. also configure mmcboot[bootblkcnt] to set the vaule1(value of block count that need to trans first time), that host will stop at block gap when card block counter is equal to this value. and need to configure mmcboot[dtocvack] to select the ack timeout value according to the sd clk frequence. chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1663 3. software then need to configure blkattr register to set block size/no. in dma mode, it is better to set block number to the max value(16'hffff). 4. software need to configure proctl[dtw]. 5. software enable adma2 by configuring proctl[dmas]. 6. software need to set at least three pairs adma2 descriptor in boot memory (ie, in iram, at least 6 words). the first pair descriptor define the start address (ie, iram) and data length(ie,512byte*value1) of first part boot code. software also need to set the second pair descriptor, the second start address (any value that is writable), data length is suggest to set 1~2word (record as vaule2). note: the second couple desc also transfer useful data even at lease 1 word. because our adma2 can't support 0 data_length data transfer descriptor. 7. software need to configure cmdarg register to set argument to 0xfffffffa in alternative fast boot, and don't need set in normal fast boot. 8. software need to configure xfertyp register to start the boot process . xfertyp[cmdinx], xfertyp[cmdtyp], xfertyp[rsptyp], xfertyp[cicen], xfertyp[cccen], xfertyp[ac12en], xfertyp[bcen] and xfertyp[dmaen] are kept default value. xfertyp[dpsel] bit is set to 1, xfertyp[dtdsel] is set to 1, xfertyp[msbsel] is set to 1. xfertyp[dmaen] is configured as 1 in dma mode. and if xfertyp[bcen] is configured as 1, better to configure blk no in blkattr register to the max value. 9. when the step 8 is configured, boot process will begin, the first vaule1 block number data has transfer. software need to polling irqstat[tc] bit to determine first transfer is end. also software need to polling irqstat[bge] bit to determine if first transfer stop at block gap. 10. when irqstat[tc] and irqstat[bge] bits are 1, . sw can analyzes the first code of vaule1 block, initializes the new memory device, if required, and sets the third pair of descriptors to define the start address and length of the remaining part of boot code (vaule3 the remain boot code block). remember set the last descriptor with end. 11. software need to configure mmcboot register (offset 0xc4) again. set mmcboot[booten] bit to 1; and mmcboot[bootmode] bit to 0 (normal fast boot), to 1(alternative boot); and mmcboot[bootack] bit to select the ack mode or not. in dma mode, configure mmcboot[autosabgen] bit to 1 for enable automatically stop at block gap feature. also configure mmcboot[bootblkcnt] bit to set the (vaule1+1+vaule3), that host will initialization/application of sdhc k60 sub-family reference manual, rev. 6, nov 2011 1664 freescale semiconductor, inc. stop at block gap when card block counter is equal to this value. and need to configure mmcboot[dtocvack] bit to select the ack timeout value according to the sd clk frequence. 12. software need to clear irqstat[tc] and irqstat[bge] bit. and software need to clear proctl[sabgreq], and set proctl[creq] to 1 to resume the data transfer. host will transfer the value2 and vaule3 data to the destination that is set by descriptor. 13. software need to polling irqstat[bge] bit to determine if the fast boot is over. note 1. when adma boot flow is started, for sdhc, it is like a normal adma read operation. so setting adma2 descriptor as the normal adma2 transfer. 2. need a few words length memory to keep descriptor. 3. for the 1~2 words data in second descriptor setting, it is the useful data, so software need to deal the data due to the application case. 52.6.7 commands for mmc/sd/sdio/ce-ata the following table lists the commands for the mmc/sd/sdio/ce-ata cards. refer to the corresponding specifications for more details about the command information. there are four kinds of commands defined to control the multimediacard: 1. broadcast commands (bc), no response. 2. broadcast commands with response (bcr), response from all cards simultaneously. 3. addressed (point-to-point) commands (ac), no data transfer on the dat. 4. addressed (point-to-point) data transfer commands (adtc). table 52-37. commands for mmc/sd/sdio/ce-ata cards cmd index type argument resp abbreviation description cmd0 bc [31:0] stuff bits - go_idle_state resets all mmc and sd memory cards to idle state. table continues on the next page... chapter 2 secured digital host controller sdhc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 166 table 52-37. commands for mmc/sd/sdio/ce-ata cards (continued) cmd index type argument resp abbreviation description cmd1 bcr [31:0] ocr without busy r3 send_op_cond asks all mmc and sd memory cards in idle state to send their operation conditions register contents in the response on the cmd line. cmd2 bcr [31:0] stuff bits r2 all_send_cid asks all cards to send their cid numbers on the cmd line. cmd3 1 ac [31:6] rca [15:0] stuff bits r1 r6 (sdio) set/ send_relative_ad dr assigns relative address to the card. cmd4 bc [31:0] dsr [15:0] stuff bits - set_dsr programs the dsr of all cards. cmd5 bc [31:0] ocr without busy r4 io_send_op_cond asks all sdio cards in idle state to send their operation conditions register contents in the response on the cmd line. cmd6 2 adtc [31] mode 0: check function 1: switch function [30:8] reserved for function groups 6 ~ 3 (all 0 or 0xffff) [7:4] function group1 for command system [3:0] function group2 for access mode r1 switch_func checks switch ability (mode 0) and switch card function (mode 1). refer to "sd physical specification v1.1" for more details. cmd6 3 ac [31:26] set to 0 [25:24] access [23:16] index [15:8] value [7:3] set to 0 [2:0] cmd set r1b switch switches the mode of operation of the selected card or modifies the ext_csd registers. refer to "the multimediacard system specification version 4.0 final draft 2" for more details. cmd7 ac [31:6] rca [15:0] stuff bits r1b select/ deselect_card toggles a card between the stand-by and transfer states or between the programming and disconnect states. in both cases, the card is selected by its own relative address and gets deselected by any other address. address 0 deselects all. table continues on the next page... initializationapplication of sdhc 60 sub-family reference manual, rev. 6, nov 2011 1666 freescale semiconductor, inc. table 52-37. commands for mmc/sd/sdio/ce-ata cards (continued) cmd index type argument resp abbreviation description cmd8 adtc [31:0] stuff bits r1 send_ext_csd the card sends its ext_csd register as a block of data, with a block size of 512 bytes. cmd9 ac [31:6] rca [15:0] stuff bits r2 send_csd addressed card sends its card-specific data (csd) on the cmd line. cmd10 ac [31:6] rca [15:0] stuff bits r2 send_cid addressed card sends its card-identification (cid) on the cmd line. cmd11 adtc [31:0] data address r1 read_dat_until_s top reads data stream from the card, starting at the given address, until a stop_transmission follows. cmd12 ac [31:0] stuff bits r1b stop_transmissio n forces the card to stop transmission. cmd13 ac [31:6] rca [15:0] stuff bits r1 send_status addressed card sends its status register. cmd14 reserved cmd15 ac [31:6] rca [15:0] stuff bits - go_inactive_stat e sets the card to inactive state in order to protect the card stack against communication breakdowns. cmd16 ac [31:0] block length r1 set_blocklen sets the block length (in bytes) for all following block commands (read and write). default block length is specified in the csd. cmd17 adtc [31:0] data address r1 read_single_bloc k reads a block of the size selected by the set_blocklen command. cmd18 adtc [31:0] data address r1 read_multiple_bl ock continuously transfers data blocks from card to host until interrupted by a stop command. cmd19 reserved cmd20 adtc [31:0] data address r1 write_dat_until_s top writes data stream from the host, starting at the given address, until a stop_transmision follows. cmd21-23 reserved cmd24 adtc [31:0] data address r1 write_block writes a block of the size selected by the set_blocklen command. table continues on the next page... chapter 2 secured digital host controller sdhc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1667 table 52-37. commands for mmc/sd/sdio/ce-ata cards (continued) cmd index type argument resp abbreviation description cmd25 adtc [31:0] data address r1 write_multiple_bl ock continuously writes blocks of data until a stop_transmission follows. cmd26 adtc [31:0] stuff bits r1 program_cid programming of the card identification register. this command shall be issued only once per card. the card contains hardware to prevent this operation after the first programming. normally this command is reserved for the manufacturer. cmd27 adtc [31:0] stuff bits r1 program_csd programming of the programmable bits of the csd. cmd28 ac [31:0] data address r1b set_write_prot if the card has write protection features, this command sets the write protection bit of the addressed group. the properties of write protection are coded in the card specific data (wp_grp_size). cmd29 ac [31:0] data address r1b clr_write_prot if the card provides write protection features, this command clears the write protection bit of the addressed group. cmd30 adtc [31:0] write protect data address r1 send_write_prot if the card provides write protection features, this command asks the card to send the status of the write protection bits. cmd31 reserved cmd32 ac [31:0] data address r1 tag_sector_star t sets the address of the first sector of the erase group. cmd33 ac [31:0] data address r1 tag_sector_end sets the address of the last sector in a continuous range within the selection of a single sector to be selected for erase. cmd34 ac [31:0] data address r1 untag_sector removes one previously selected sector from the erase selection. cmd35 ac [31:0] data address r1 tag_erase_group _start sets the address of the first erase group within a range to be selected for erase. table continues on the next page... initializationapplication of sdhc 60 sub-family reference manual, rev. 6, nov 2011 1668 freescale semiconductor, inc. table 52-37. commands for mmc/sd/sdio/ce-ata cards (continued) cmd index type argument resp abbreviation description cmd36 ac [31:0] data address r1 tag_erase_group _end sets the address of the last erase group within a continuous range to be selected for erase. cmd37 ac [31:0] data address r1 untag_erase_gro up removes one previously selected erase group from the erase selection. cmd38 ac [31:0] stuff bits r1b erase erase all previously selected sectors. cmd39 ac [31:0] rca [15] register write flag [14:8] register address [7:0] register data r4 fast_io used to write and read 8-bit (register) data fields. the command addresses a card, and a register, and provides the data for writing if the write flag is set. the r4 response contains data read from the address register. this command accesses application dependent registers which are not defined in the mmc standard. cmd40 bcr [31:0] stuff bits r5 go_irq_state sets the system into interrupt mode. cmd41 reserved cdm42 adtc [31:0] stuff bits r1b lock_unlock used to set/reset the password or lock/unlock the card. the size of the data block is set by the set_block_len command. cmd43~51 reserved cmd52 ac [31:0] stuff bits r5 io_rw_direct access a single register within the total 128k of register space in any i/o function. cmd53 ac [31:0] stuff bits r5 io_rw_extended accesses a multiple i/o register with a single command. allows the reading or writing of a large number of i/o registers. cmd54 reserved cmd55 ac [31:16] rca [15:0] stuff bits r1 app_cmd indicates to the card that the next command is an application specific command rather that a standard command. table continues on the next page... chapter 2 secured digital host controller sdhc 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 166 table 52-37. commands for mmc/sd/sdio/ce-ata cards (continued) cmd index type argument resp abbreviation description cmd56 adtc [31:1] stuff bits [0]: rd/wr r1b gen_cmd used either to transfer a data block to the card or to get a data block from the card for general purpose / application specific commands. the size of the data block is set by the set_block_len command. cmd57~59 reserved cmd60 adtc [31] wr [30:24] stuff bits [23:16] address [15:8] stuff bits [7:0] byte count r1b rw_multiple_regi ster ce-ata devices contain a set of status and control registers that begin at register offset 80h.these registers are used to control the behavior of the device and to retrieve status information regarding the operation of the device. all status and control registers are word (32-bit) in size and are word aligned. cmd60 shall be used to read and write these registers. cmd61 adtc [31] wr [30:16] stuff bits [15:0] data unit count r1b rw_multiple_bloc k the host issues a rw_multiple_block (cmd61) to begin the data transfer for the ata command. cmd62~63 reserved acmd6 4 ac [31:2] stuff bits [1:0] bus width r1 set_bus_width defines the data bus width (00=1bit or 10=4bit bus) to be used for data transfer. the allowed data bus widths are given in scr register. acmd13 5 adtc [31:0] stuff bits r1 sd_status send the sd memory card status. acmd22 6 adtc [31:0] stuff bits r1 send_num_wr_sec tors send the number of the written sectors (without errors). responds with 32-bit plus the crc data block. acmd23 7 ac r1 set_wr_blk_eras e_count - acmd41 8 bcr [31:0] ocr r3 sd_app_op_cond asks the accessed card to send its operating condition register (ocr) contents in the response on the cmd line. acmd42 9 ac r1 set_clr_card_det ect - table continues on the next page... initializationapplication of sdhc 60 sub-family reference manual, rev. 6, nov 2011 1670 freescale semiconductor, inc. table 52-37. commands for mmc/sd/sdio/ce-ata cards (continued) cmd index type argument resp abbreviation description acmd51 10 adtc [31:0] stuff bits r1 send_scr reads the sd configuration register (scr). 1. cmd3 differs for mmc and sd cards. for mmc cards, it is referred to as set_relative_addr, with a response type of r1. for sd cards, it is referred to as send_relative_addr, with a response type of r6 (with rca inside). 2. cmd6 differs completely between high speed mmc cards and high speed sd cards. command switch_func is for high speed sd cards. 3. command switch is for high speed mmc cards as well as for ce-ata cards over the mmc interface. the index field can contain any value from 0-255, but only values 0-191 are valid. if the index value is in the 192-255 range the card does not perform any modification and the switch_error status bit in the ext_csd register is set. the access bits are shown in table 52-38 . 4. acmds shall be preceded with the app_cmd command. (commands listed are used for sd only, other sd commands not listed are not supported on this module). 5. acmds shall be preceded with the app_cmd command. (commands listed are used for sd only, other sd commands not listed are not supported on this module). 6. acmds shall be preceded with the app_cmd command. (commands listed are used for sd only, other sd commands not listed are not supported on this module). 7. acmds shall be preceded with the app_cmd command. (commands listed are used for sd only, other sd commands not listed are not supported on this module). 8. acmds shall be preceded with the app_cmd command. (commands listed are used for sd only, other sd commands not listed are not supported on this module). 9. acmds shall be preceded with the app_cmd command. (commands listed are used for sd only, other sd commands not listed are not supported on this module). 10. acmds shall be preceded with the app_cmd command. (commands listed are used for sd only, other sd commands not listed are not supported on this module). the access bits for the ext_csd access modes are shown in the following table. table 52-38. ext_csd access modes bits access name operation 00 command set the command set is changed according to the cmd set field of the argument 01 set bits the bits in the pointed byte are set, according to the 1 bits in the value field. 10 clear bits the bits in the pointed byte are cleared, according to the 1 bits in the value field. 11 write byte the value field is written into the pointed byte. 52.7 software restrictions software for the sdhc must observe the following restrictions. chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1671 52.7.1 initialization active the driver cannot set sysctl[inita] bit when any of the command line or data lines is active, so the driver must ensure both prsstat[cdihb] and prsstat[cihb] bits are cleared. and in order to auto clear the sysctl[inita] bit, the sysctl[sdclken] bit must be '1', otherwise no clocks can go out to the card and sysctl[inita] will never clear. 52.7.2 software polling procedure for polling read or write, once the software begins a buffer read or write, it must access exactly the number of times as the values set in the watermark level register; moreover, if the block size is not the times of the value in watermark level register (read and write respectively), the software must access exactly the remained number of words at the end of each block. for example, for read operation, if the wml[rdwml] is 4, indicating the watermark level is 16 bytes, block size is 40 bytes, and the block number is 2, then the access times for the burst sequence in the whole transfer process must be 4, 4, 2, 4, 4, 2. 52.7.3 suspend operation in order to suspend the data transfer, the software must inform sdhc that the suspend command is successfully accepted. to achieve this, after the suspend command is accepted by the sdio card, software must send another normal command marked as suspend command (xfertyp[cmdtyp] bits set as '01') to inform sdhc that the transfer is suspended. if software needs resume the suspended transfer, it should read the value in blkattr[blkcnt] to save the remained number of blocks before sending the normal command marked as suspend, otherwise on sending such 'suspend' command, sdhc will regard the current transfer is aborted and change blkattr[blkcnt] to its original value, instead of keeping the remained number of blocks. 52.7.4 data length setting for either adma (adma1 or adma2) transfer, the data in the data buffer must be word aligned, so the data length set in the descriptor must be times of 4. software restrictions k60 sub-family reference manual, rev. 6, nov 2011 1672 freescale semiconductor, inc. 52.7.5 (a)dma address setting to configure adma1/adma2/dma address register, when tc[irqstat] bit is set, the register will always update itself with the internal address value to support dynamic address synchronization, so software must make sure tc[irqstat] bit is cleared prior to configuring adma1/adma2/dma address register. 52.7.6 data port access data port does not support parallel access. for example, during an external dma access, it is not allowed to write any data to the data port by cpu; or during a cpu read operation, it is also prohibited to write any data to the data port, by either cpu or external dma. otherwise the data would be corrupted inside the sdhc buffer. 52.7.7 change clock frequency sdhc does not automatically gates off the card clock when the host driver changes the clock frequency. to remove possible glitch on the card clock, clear sysctl[sdclken] bit when changing clock divisor value and set sysctl[sdclken] bit to '1' after prsstat[sdstb] bit is '1' again. 52.7.8 multi-block read for pre-defined multi-block read operation, i.e., the number of blocks to read has been defined by previous cmd23 for mmc, or pre-defined number of blocks in cmd53 for sdio/sdcombo, or whatever multi-block read without abort command at card side, an abort command, either automatic or manual cmd12/cmd52, is still required by sdhc after the pre-defined number of blocks are done, to drive the internal start response timeout. it is recommended to manually send an abort command with xfertyp[rsptyp] both bits cleared. chapter 52 secured digital host controller (sdhc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1673 software restrictions k60 sub-family reference manual, rev. 6, nov 2011 1674 freescale semiconductor, inc. chapter 53 integrated interchip sound (i2s) 53.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. this section discusses the architecture, the programming model, the operating modes, and initialization of integrated interchip sound (i 2 s) module. the i 2 s is a full-duplex, serial port that allows the chip to communicate with a variety of serial devices. such serial devices are: ? standard codecs ? digital signal processors (dsps) ? microprocessors ? peripherals ? audio codecs that implement the inter-ic sound bus (i 2 s) and the intel ? ac97 standards the i 2 s module typically transfers samples in a periodic manner. the i 2 s consists of independent transmitter and receiver sections with independent clock generation and frame synchronization. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1675 53.1.1 block diagram the following figure illustrates the organization of the i 2 s. it consists of control registers to set up the port, status register, separate transmit and receive circuits with fifo registers, and separate serial clock and frame sync generation for the transmit and receive sections. the second set of tx and rx fifos replicates the logic used for the first set of fifos. transmit clock control reg rcr peripheral bus stxd srxd stck stfs srck/sys_clk srfs tx clock generator tx sync generator tx and rx rx clock generator rx sync generator control reg cr tx and rx fifo and shift register logic control tcr tccr 32-bit rccr receive clock control reg transmit config reg receive config reg figure 53-1. customer-facing i 2 s block diagram 53.1.2 features the i 2 s includes the following features: ? independent (asynchronous) or shared (synchronous) transmit and receive sections with separate or shared internal/external clocks and frame syncs, operating in master or slave mode. ? normal mode operation using frame sync introduction k60 sub-family reference manual, rev. 6, nov 2011 1676 freescale semiconductor, inc. ? network mode operation allowing multiple devices to share the port with as many as thirty-two time slots ? gated clock mode operation requiring no frame sync ? 2 sets of transmit and receive fifos. each of the four fifos is 15x32 bits. the two sets of tx/rx fifos can be used in network mode to provide 2 independent channels for transmission and reception ? programmable data interface modes such as i 2 s, lsb- and msb-aligned ? programmable word length (8, 10, 12, 16, 18, 20, 22 or 24 bits) ? program options for frame sync and clock generation ? programmable i 2 s modes (master, slave or normal). oversampling clock available as output from srck in i 2 s master mode ? ac97 support ? completely separate clock and frame sync selections for the receive and transmit sections. in the ac97 standard, the clock is taken from an external source and frame sync is generated internally. ? external network clock input for i 2 s master mode. programmable oversampling clock of the sampling frequency available as output in master mode at srck, when operated in synchronous mode. ? programmable internal clock divider ? transmit and receive time slot mask registers for reduced cpu overhead ? i 2 s power-down feature 53.1.3 modes of operation i 2 s has the following basic operating modes. ? normal mode ? asynchronous protocol ? synchronous protocol ? network mode chapter 53 integrated interchip sound (i2s) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1677 ? asynchronous protocol ? synchronous protocol ? gated clock mode ? synchronous protocol only ? i 2 s mode ? ac97 mode ? ac97 fixed mode (acnt[fv] = 0) ? ac97 variable mode (acnt[fv] = 1) these modes can be programmed by several bits in the i 2 s control registers. the following table lists these operating modes and some of the typical applications in which they can be used: table 53-1. i 2 s operating modes tx, rx sections serial clock mode typical application asynchronous continuous normal multiple synchronous codecs asynchronous continuous network tdm codec or dsp networks synchronous continuous normal multiple synchronous codecs synchronous continuous network tdm codec or dsp network synchronous gated normal spi-type devices: dsp to mcu the transmit and receive sections of the i 2 s can be synchronous or asynchronous. in synchronous mode, the transmitter and the receiver use a common clock and frame synchronization signal. masking of slots for transmit and receive section can differ in synchronous mode. also the rcr[rxbit0, rshfd] bits can continue affecting shifting- in of received data in synchronous mode. in asynchronous mode, the transmitter and receiver each has its own clock and frame synchronization signals. continuous or gated clock mode can be selected. in continuous mode, the clock runs continuously. in gated clock mode, the clock is only functioning during transmission. normal or network mode can also be selected. in normal mode, the i 2 s functions with one data word of i/o per frame. in network mode, any number from two to thirty-two data words of i/o per frame can be used. network mode is typically used in star time- division-multiplex networks with other processors or codecs, allowing interface to time division multiplexed networks without additional logic. use of gated clock mode is not allowed in network mode. these distinctions result in the basic operating modes that allow the i 2 s to communicate with a wide variety of devices. introduction k60 sub-family reference manual, rev. 6, nov 2011 1678 freescale semiconductor, inc. the i 2 s supports both normal and network modes, and these can be selected independently of whether the transmitter and receiver are synchronous or asynchronous. typically, these protocols are used in a periodic manner, where data transfers at regular intervals, such as at the sampling rate of an external codec. both modes use the concept of a frame. the beginning of the frame is marked with a frame sync when programmed with continuous clock. the rccr[dc] or tccr[dc] bits determine the length of the frame, depending on whether data is being transmitted or received. the number of words transferred per frame depends on the mode of the i 2 s. in normal mode, one data word is transferred per frame. in network mode, the frame divides into two to 32 time slots. in each time slot, one data word is optionally transferred. apart from the above basic modes of operation, i 2 s supports the following modes which require some specific programming. ? i 2 s mode ? ac97 mode ? ac97 fixed mode ? ac97 variable mode in non-i 2 s slave modes (external frame sync), the i 2 s's programmed word length setting should be equal to the word length setting of the master. in i 2 s slave mode, the i 2 s's programmed word length setting can be lesser than or equal to the word length setting of the i 2 s master (external codec). in slave modes, the i 2 s's programmed frame length setting (tccr[dc] or rccr[dc] bits) can be lesser than or equal to the frame length setting of the master (external codec). see detailed operating mode descriptions for more details on the above modes. 53.2 i 2 s signal descriptions table 53-2. i 2 s signal descriptions signal description i/o srck serial receive clock. srck can be used as an input or output. in asynchronous mode the receiver uses this clock signal and it is always continuous. in synchronous mode, the stck port is used instead for clocking in data. i/o table continues on the next page... chapter integrated interchip sound i2s 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 167 table 53-2. i 2 s signal descriptions (continued) signal description i/o srfs serial receive frame sync. the srfs port can be used as an input or output. the frame sync is used by the receiver to synchronize the transfer of data. the frame sync signal can be one bit or one word in length and can occur one bit before the transfer of data or right at the transfer of data. if srfs is configured as an input, the external device should drive srfs during the rising edge of stck or srck. i/o srxd serial receive data. the srxd port is an input and is used to bring serial data into the receive data shift register. i stck serial transmit clock. the stck port can be used as an input or output. this clock signal is used by the transmitter and can be continuous or gated. during gated clock mode, data on stck is valid only during the transmission of data. otherwise, it is pulled to the inactive state. in synchronous mode, this port is used by the transmit and receive sections. i/o stfs serial transmit frame sync. the stfs port can be used as an input or output. the frame sync is used by the transmitter to synchronize the transfer of data. the frame sync signal can be one bit or one word in length and can occur one bit before the transfer of data or right at the transfer of data. in synchronous mode, this port is used by both the transmit and receive sections. in gated clock mode, frame sync signals are not used. if stfs is configured as an input, the external device should drive stfs during the rising edge of stck if tsckp is positive-edge triggered. the external device should drive stfs during the falling edge of stck if tsckp is negative-edge triggered. i/o stxd serial transmit data. the stxd port is an output and transmits data from the serial transmit shift register. the stxd port is an output port when data is being transmitted and is disabled between data word transmissions and on the trailing edge of the bit clock after the last bit of a word is transmitted. o the following figure shows the main i 2 s configurations. these ports support all transmit and receive functions with continuous or gated clock as shown. note gated clock implementations do not require the use of the frame sync ports (stfs and srfs). i2s signal descriptions k60 sub-family reference manual, rev. 6, nov 2011 1680 freescale semiconductor, inc. i2s i2s stxd srxd stck stfs srck srfs i2s stxd srxd stck stck stfs srck srfs i2s stxd srxd stck stfs srck srfs stxd srxd stck stfs srck srfs i2s internal continuous clock for tx/rx (rcr[rxdir] = 1,tcr[txdir] = 1, rcr[rfdir] = 1,tcr[tfdir] = 1, cr[syn] = 0) i2s external continuous clock for tx/rx (rcr[rxdir] = 0,tcr[txdir] = 0, rcr[rfdir] = 0,tcr[tfdir] = 0, cr[syn] = 0) i2s internal continuous clock for rx (rcr[rxdir] = 1, tcr[txdir] = 0, rcr[rfdir] = 1,tcr[tfdir] = 0, cr[syn] = 0) i2s external continuous clock for tx i2s internal continuous clock for tx (rcr[rxdir] = 0, tcr[txdir] = 1, rcr[rfdir] = 0, tcr[tfdir] = 1, cr[syn] = 0) i2s external continuous clock for rx figure 53-2. asynchronous (syn = 0) i 2 s configurations?continuous clock the following figure shows an example of the port signals for an 8-bit data transfer. continuous and gated clock signals are shown, as well as the bit-length frame sync signal and the word-length frame sync signal. chapter 53 integrated interchip sound (i2s) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1681 stfs, srfs stxd srxd 8-bit data 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 7 6 7 6 (not used in gated clock) continuous stck, srck early stfs, srfs gated stck bit-length frame sync word-length frame sync figure 53-3. serial clock and frame sync timing the following table shows a list of clock pin configurations. table 53-3. clock pin configurations cr [syn] rcr tcr srck stck srfs stfs rxdir rfdir txdir tfdir asynchronous mode 0 0 0 0 0 rck in tck in rfs in tfs in 0 0 0 0 1 rck in tck in rfs in tfs out 0 0 1 0 0 rck in tck in rfs out tfs in 0 0 1 0 1 rck in tck in rfs out tfs out 0 0 0 1 0 rck in tck out rfs in tfs in 0 0 0 1 1 rck in tck out rfs in tfs out 0 0 1 1 0 rck in tck out rfs out tfs in 0 0 1 1 1 rck in tck out rfs out tfs out 0 1 0 0 0 rck out tck in rfs in tfs in 0 1 0 0 1 rck out tck in rfs in tfs out 0 1 1 0 0 rck out tck in rfs out tfs in 0 1 1 0 1 rck out tck in rfs out tfs out table continues on the next page... i2s signal descriptions 60 sub-family reference manual, rev. 6, nov 2011 1682 freescale semiconductor, inc. table 53-3. clock pin configurations (continued) cr [syn] rcr tcr srck stck srfs stfs rxdir rfdir txdir tfdir 0 1 0 1 0 rck out tck out rfs in tfs in 0 1 0 1 1 rck out tck out rfs in tfs out 0 1 1 1 0 rck out tck out rfs out tfs in 0 1 1 1 1 rck out tck out rfs out tfs out synchronous mode 1 0 x 0 0 ck in fs in 1 0 x 0 1 ck in fs out 1 0 x 1 0 ck out fs in 1 0 x 1 1 ck out fs out 1 1 x 0 x gated in 1 1 x 1 x gated out 53.3 memory map/register definition this section consists of register descriptions in address order. each description includes a standard register diagram with an associated figure number. details of register bit and field function follow the register diagrams in bit order. i2s memory map absolute address (hex) register name width (in bits) access reset value section/ page 4002_f000 i2s transmit data registers 0 (i2s0_tx0) 32 r/w 0000_0000h 53.3.1/ 1685 4002_f004 i2s transmit data registers 1 (i2s0_tx1) 32 r/w 0000_0000h 53.3.2/ 1685 4002_f008 i2s receive data registers 0 (i2s0_rx0) 32 r 0000_0000h 53.3.3/ 1686 4002_f00c i2s receive data registers 1 (i2s0_rx1) 32 r 0000_0000h 53.3.4/ 1686 4002_f010 i2s control register (i2s0_cr) 32 r/w 0000_0000h 53.3.5/ 1687 4002_f014 i2s interrupt status register (i2s0_isr) 32 r/w 0000_3003h 53.3.6/ 1690 table continues on the next page... chapter integrated interchip sound i2s 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 168 i2s memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4002_f018 i2s interrupt enable register (i2s0_ier) 32 r/w 0000_3003h 53.3.7/ 1695 4002_f01c i2s transmit configuration register (i2s0_tcr) 32 r/w 0000_0200h 53.3.8/ 1699 4002_f020 i2s receive configuration register (i2s0_rcr) 32 r/w 0000_0200h 53.3.9/ 1701 4002_f024 i2s transmit clock control registers (i2s0_tccr) 32 r/w 0004_0000h 53.3.10/ 1703 4002_f028 i2s receive clock control registers (i2s0_rccr) 32 r/w 0004_0000h 53.3.11/ 1705 4002_f02c i2s fifo control/status register (i2s0_fcsr) 32 r/w 0081_0081h 53.3.12/ 1706 4002_f038 i2s ac97 control register (i2s0_acnt) 32 r/w 0000_0000h 53.3.13/ 1712 4002_f03c i2s ac97 command address register (i2s0_acadd) 32 r/w 0000_0000h 53.3.14/ 1713 4002_f040 i2s ac97 command data register (i2s0_acdat) 32 r/w 0000_0000h 53.3.15/ 1714 4002_f044 i2s ac97 tag register (i2s0_atag) 32 r/w 0000_0000h 53.3.16/ 1714 4002_f048 i2s transmit time slot mask register (i2s0_tmsk) 32 r/w 0000_0000h 53.3.17/ 1715 4002_f04c i2s receive time slot mask register (i2s0_rmsk) 32 r/w 0000_0000h 53.3.18/ 1715 4002_f050 i2s ac97 channel status register (i2s0_accst) 32 r 0000_0000h 53.3.19/ 1716 4002_f054 i2s ac97 channel enable register (i2s0_accen) 32 w (always reads zero) 0000_0000h 53.3.20/ 1716 4002_f058 i2s ac97 channel disable register (i2s0_accdis) 32 w (always reads zero) 0000_0000h 53.3.21/ 1717 memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1684 freescale semiconductor, inc. 53.3.1 i 2 s transmit data registers 0 (i2s x the tx0 registers store the data to be transmitted by the i2s. addresses: i2s0_tx0 is 4002_f000h base + 0h offset = 4002_f000h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r tx0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i2s x iel escritions fiel escrition transit ata transit ata hese its store the ata to e transitte y the hese are ileente as the irst wor o their resectie x ffos ata written to these reisters transers to the transit shit reister r when shitin o the reious ata is colete oth ffos are in use ata alternately transers ro an to r can only e use in twochannel oe ultile writes to the reisters o not result in the reious ata ein oerwritten y the susequent ata nstea they are inore rotection ro oerwritin is resent irresectie o whether the transitter is enale or not xale: x ffo is in use an you write ata to ata oes not oerwrite ata ata are store in the ffo while ata is iscare xale: x ffo is not in use an you write ata ata to then ata oes not oerwrite ata an is iscare o: nale r eore writin to the transit ata reisters ransit ata reisters x the tx1 registers store the data to be transmitted by the i2s. addresses: i2s0_tx1 is 4002_f000h base + 4h offset = 4002_f004h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r tx1 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i2s x iel escritions fiel escrition transit ata transit ata hese its store the ata to e transitte y the hese are ileente as the irst wor o their resectie x ffos ata written to these reisters transers to the transit shit reister r when shitin o the reious ata is colete oth ffos are in use ata alternately transers ro an to r can only e use in twochannel oe ultile writes to the reisters o not result in the reious ata ein oerwritten y the susequent ata nstea they are inore rotection ro oerwritin is resent irresectie o whether the transitter is enale or not hater nterate interchi soun ufaily reerence anual re o freescale eiconuctor nc i2s x iel escritions continue fiel escrition xale: x ffo is in use an you write ata to ata oes not oerwrite ata ata are store in the ffo while ata is iscare xale: x ffo is not in use an you write ata ata to then ata oes not oerwrite ata an is iscare o: nale r eore writin to the transit ata reisters receie ata reisters x r the rx0 registers store the data received by the i2s. addresses: i2s0_rx0 is 4002_f000h base + 8h offset = 4002_f008h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r rx0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i2s x r iel escritions fiel escrition r receie ata hese its store the ata receie y the hese are ileente as the irst wor o their resectie rx ffos hese its receie ata ro the rr eenin on the oe o oeration n case oth ffos are in use ata is transerre to each ata reister alternately r can only e use in two channel oe o oeration receie ata reisters x r the rx1 registers store the data received by the i2s. addresses: i2s0_rx1 is 4002_f000h base + ch offset = 4002_f00ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r rx1 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i2s x r iel escritions fiel escrition r receie ata hese its store the ata receie y the hese are ileente as the irst wor o their resectie rx ffos hese its receie ata ro the rr eenin on the oe o oeration n case oth eory areister einition ufaily reerence anual re o freescale eiconuctor nc i2s x r iel escritions continue fiel escrition ffos are in use ata is transerre to each ata reister alternately r can only e use in two channel oe o oeration ontrol reister x r the i2s control register (cr) sets up the i2s. i2s reset is controlled by bit 0 in the cr. i2s operating modes are also selected in this register (except ac97 mode which is selected in the acnt register). addresses: i2s0_cr is 4002_f000h base + 10h offset = 4002_f010h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 synctxfs rfrclkdis tfrclkdis clkist tchen sysclken i2smode syn net re te i2sen w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i2s x r iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero f f it roies a sae winow or r to e isile to the internal circuit which is ust ater f occurrence hen f is set r ets latche on f occurrence an latche r is use to enaleisale transitter r nees setu o itcloc cycles eore occurrence o f r is chane within itcloc cycles o f occurrence there is hih roaility that r will e latche on next f o: ith frl eature on r is use irectly to enale transitter in ollowin cases i ync oe an rx isale ii sync oe latche is use to isale the transitter his it has no releance in ate oe an oe r not latche with f occurrence an use irectly or transitter enaleisale r latche with f occurrence an latche use or transitter enaleisale rfrl receie frae loc isale table continues on the next page... chapter integrated interchip sound i2s 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1687 i2s x r iel escritions continue fiel escrition his it roies the otion to ee the raesync an cloc enale or to isale the ater the receie rae in which the receier is isale ritin to this it has eect only when rr is isalehe receier is isale y clearin the rr it ontinue raesynccloc eneration ater current rae urin which rr is cleare his ay e require when fraesync an locs are require ro een when no ata is to e receie to raesynccloc eneration at next rae ounary his will e eectie also in case where receier is alreay isale in current or reious raes frl ransit frae loc isale his it roie otion to ee the raesync an cloc enale or isale ater current transit rae in which transitter is isale y clearin r it ritin to this it has eect only when is enale r is isale ontinue raesynccloc eneration ater current rae urin which r is cleare his ay e require when raesync an clocs are require ro een when no ata is to e receie to raesynccloc eneration at next rae ounary his will e eectie also in case where transitter is alreay isale in current or reious raes l loc le tate his it controls the ile state o the transit cloc ort urin internal ate oe ote: hen loc ile state is the cloc olarity shoul always e neee triere an when cloc ile the cloc olarity shoul always e ositie ee triere loc ile state is loc ile state is h wohannel oeration nale his it allows to oerate in the twochannel oen this oe while receiin the rr transers ata to r an r alternately an while transittin ata is alternately transerre ro an to r for an een nuer o slots twochannel oeration can e enale to otiie usae o oth ffos or isale as in the case o o nuer o actie slots his eature is esecially useul in oe where ata or let seaer can e lace in xffo an or riht seaer in xffo wochannel oe isale wochannel oe enale l yste loc oersalin loc nale hen set this it allows the to outut the networ cloc at the r ort roie that synchronous oe an transit internal cloc oe are set he relationshi etween it cloc an networ cloc is eterine y r an its his eature is esecially useul in aster oe to outut oersalin cloc on r ort etwor cloc not outut on r ort etwor cloc outut on r ort o oe elect hese its allow the to oerate in noral aster or slae oe oral oe aster oe table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 1688 freescale semiconductor, inc. i2s x r iel escritions continue fiel escrition slae oe oral oe ynchronous oe his it controls whether is in synchronous oe or not n synchronous oe the transit an receie sections o share a coon cloc ort an rae sync ort f synchronous oe selecte ynchronous oe selecte etwor oe his it controls whether is in networ oe or not etwor oe not selecte etwor oe selecte r receie nale nales the receie section o the hen this it is enale ata recetion starts with the arrial o the next rae sync ata is ein receie when this it is cleare ata recetion continues until the en o the current rae an then stos this it is set aain eore the secon to last it o the last tie slot in the current rae then recetion continues without interrution rr shoul not e tole in the sae rae receie section isale receie section enale ransit nale his control it enales the transit section o the t enales the transer o the contents o the reisters to the r an also enales the internal transit cloc he transit section is enale when this it is set an a rae ounary is etecte hen this it is cleare the transitter continues to sen ata until the en o the current rae an then stos ata can e written to the reisters with the r it cleare the corresonin it will e cleare the r it is cleare an then set aain eore the secon to last it o the last tie slot in the current rae ata transission continues without interrution he noral transit enale sequence is to write ata to the reisters an then set the r it he noral isale sequence is to clear the r an r its ater the it is set n ate cloc oe clearin the r it results in the cloc stoin ater the ata currently in r has shite out hen the r it is set the cloc starts ieiately or internal ate cloc oe r shoul not e tole in the sae rae ter enalinisalin transission exects setu cloc cycles eore arrial o raesync or raesync to e accete y n case o ewer cloc cycles there is hih roaility o the raesync to et isse o: continuos cloc is not roie exects cloc cycles eore arrial o raesync or raesync to e accete y ransit section isale ransit section enale nale table continues on the next page... chapter integrated interchip sound i2s 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 168 i2s x r iel escritions continue fiel escrition his it is use to enaleisale the hen isale all status its are reset to the sae state rouce y the oweron reset all control its are unaecte the contents o x an rx ffos are cleare hen is isale all internal clocs are isale excet reister access cloc is isale is enale nterrut tatus reister x r the i2s interrupt status register (isr) is used to monitor the i2s. this register is used by the core to interrogate the status of the i2s. in gated mode of operation the tfs, rfs, tls, rls, tfrc and rfrc bits of aisr register are not generated. the status bits are described in the following table. note ? i 2 s status flags are valid when i 2 s is enabled. ? all the flags in the isr are updated after the first bit of the next i 2 s word has completed transmission or reception. certain status bits (roe0/1 and tue0/1) are cleared by writing 1 to the corresponding interrupt status bit in isr. addresses: i2s0_isr is 4002_f000h base + 14h offset = 4002_f014h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 rfrc trfc 0 cmdau cmddu rxt w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r rdr1 rdr0 tde1 tde0 roe1 roe0 tue1 tue0 tfs rfs tls rls rff1 rff0 tfe1 tfe0 w w1c w1c w1c w1c reset 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 memory map/register definition k60 sub-family reference manual, rev. 6, nov 2011 1690 freescale semiconductor, inc. i2s x r iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero rfr receie frae olete his la is set at the en o the rae urin which receier is isale receie rae an cloc are not isale in the sae rae this la is also set at the en o the rae in which receie rae an cloc are isale ee escrition o rrfrl it or ore etails on how to isale receier rae an cloc or ee the enale ater receier is isale n o rae not reache n o rae reache ater isalin rr or isalin rrfrl when receier is alreay isale rf ransit frae olete his la is set at the en o the rae urin which transitter is isale transit rae an cloc are not isale in the sae rae this la is also set at the en o the rae in which transit rae an cloc are isale ee escrition o rfrl it or ore etails on how to isale transit rae an cloc or ee the enale ater transitter is isale n o rae not reache n o rae reache ater isalin r or isalin rfrl when transitter is alreay isale resere his reaonly iel is resere an always has the alue ero u oan ress reister uate his it causes the coan aress uate interrut when ru it is set his status it is set each tie there is a ierence in the reious an current alue o the receie coan aress his it is cleare on reain the reister o chane in reister reister uate with ierent alue u oan ata reister uate his it causes the coan ata uate interrut when ru it is set his status it is set each tie there is a ierence in the reious an current alue o the receie coan ata his it is cleare on reain the reister o chane in reister reister uate with ierent alue r receie a uate his status it is set each tie there is a ierence in the reious an current alue o the receie ta t causes the receie ta interrut i rr it is set his it is cleare on reain the reister o chane in reister reister uate with ierent alue rr receie ata reay table continues on the next page... chapter integrated interchip sound i2s 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 161 i2s x r iel escritions continue fiel escrition his la it is set when r or rx ffo is loae with a new alue an twochannel oe is selecte rr is cleare when the core reas the r reister rx ffo is enale rr is cleare when the ffo is ety rr an rrr are set a receie ata interrut request is issue on settin o rr it in case rx ffo is isale i the ffo is enale the interrut is issue on rff assertion he rr it is cleare y or an reset o new ata or core to rea ew ata or core to rea rr receie ata reay his la it is set when r or rx ffo is loae with a new alue rr is cleare when the core reas the r reister rx ffo is enale rr is cleare when the ffo is ety rr an rrr are set a receie ata interrut request is issue on settin o rr it in case rx ffo is isale i the ffo is enale the interrut is issue on rff assertion he rr it is cleare y or an reset o new ata or core to rea ew ata or core to rea ransit ata reister ty his la is set wheneer ata is transerre to r ro reister an twochannel oe is selecte x ffo is enale this occurs when there is at least one ety slot in or x ffo x ffo is not enale this occurs when the contents o are transerre to r he it is cleare when the core writes to r an r are set an transit ata interrut request is issue on settin o it he it is cleare y or an reset ata aailale or transission ata nees to e written y the core or transission ransit ata reister ty his la is set wheneer ata is transerre to r ro reister x ffo is enale this occurs when there is at least one ety slot in or x ffo x ffo is not enale this occurs when the contents o are transerre to r he it is cleare when the core writes to r an are set an transit ata interrut request is issue on settin o it he it is cleare y or an reset ata aailale or transission ata nees to e written y the core or transission ro receier oerrun rror his la is set when the rr is ille an reay to transer to r reister or to rx ffo when enale an these are alreay ull an wohannel oe is selecte rx ffo is enale this is inicate y rff la else this is inicate y the rr la he rr is not transerre in this case he ro la causes an interrut i rr an rro are set he ro it is cleare y or an reset t is also cleare y writin to this it learin the rr it oes not aect the ro it o oerrun etecte receier oerrun error occurre ro receier oerrun rror table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 162 freescale semiconductor, inc. i2s x r iel escritions continue fiel escrition his la is set when the rr is ille an reay to transer to r reister or to rx ffo when enale an these are alreay ull rx ffo is enale this is inicate y rff la else this is inicate y the rr la he rr is not transerre in this case he ro la causes an interrut i rr an rro are set he ro it is cleare y or an reset t is also cleare y writin to this it learin the rr it oes not aect the ro it o oerrun etecte receier oerrun error occurre u ransitter unerrun rror his la is set when the r is ety no ata to e transitte the la is set a transit tie slot occurs an the is in twochannel oe hen a transit unerrun error occurs the reious ata is retransitte n etwor oe each tie slot requires ata transission unless ase throuh reister when the transitter is enale r is set he u la causes an interrut i r an ru are set he u it is cleare y or an reset t is also cleare y writin to this it o unerrun etecte ransitter unerrun error occurre u ransitter unerrun rror his la is set when the r is ety no ata to e transitte the la is set an a transit tie slot occurs hen a transit unerrun error occurs the reious ata is retransitte n etwor oe each tie slot requires ata transission unless ase throuh reister when the transitter is enale r is set he u la causes an interrut i r an ru are set he u it is cleare y or an reset t is also cleare y writin to this it o unerrun etecte ransitter unerrun error occurre f ransit frae ync his la inicates the occurrence o transit rae sync ata written to the reisters urin the tie slot when the f la is set is sent urin the secon tie slot in networ oe or in the next irst tie slot in noral oe n networ oe the f it is set urin transission o the irst tie slot o the rae an is then cleare when startin transission o the next tie slot n noral oe this it is hih or the irst tie slot his la causes an interrut i r an rf are set he f it is cleare y or an reset o occurrence o transit rae sync ransit rae sync occurre urin transission o last wor written to reisters rf receie frae ync his la inicates the occurrence o receie rae sync n networ oe the rf it is set when the irst slot o the rae is ein receie t is cleare when the next slot eins to e receie n noral oe this it is always hih his la causes an interrut i rr an rrf are set he rf it is cleare y or an reset o occurrence o receie rae sync receie rae sync occurre urin recetion o next wor in r reisters table continues on the next page... chapter integrated interchip sound i2s 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 16 i2s x r iel escritions continue fiel escrition l ransit last ie lot his la inicates the last tie slot in a rae hen set it inicates that the current tie slot is the last tie slot o the rae l is set at the start o the last transit tie slot an causes the to issue an interrut i r an l are set l is not enerate when rae rate is in noral oe o oeration l is cleare when the r is rea with this it set he l it is cleare y or an reset urrent tie slot is not last tie slot o rae urrent tie slot is the last transit tie slot o rae rl receie last ie lot his la inicates the last tie slot in a rae hen set it inicates that the current tie slot is the last receie tie slot o the rae rl is set at the en o the last tie slot an causes the to issue an interrut i rr an rrl are set rl is cleare when the r is rea with this it set he rl it is cleare y or an reset urrent tie slot is not last tie slot o rae urrent tie slot is the last receie tie slot o rae rff receie ffo full his la is set when rx ffo is enale the ata leel in rx ffo reaches the selecte rx ffo aterar rf threshol an the is in twochannel oe he settin o rff only causes an interrut when rr an rrff are set rx ffo is enale an the twochannel oe is selecte rff is autoatically cleare when the aount o ata in rx ffo alls elow the threshol he rff it is cleare y or an reset hen rx ffo contains wors the axiu it can hol all urther ata receie or storae in this ffo is inore until the ffo contents are rea ace aailale in receie ffo receie ffo is ull rff receie ffo full his la is set when rx ffo is enale an the ata leel in rx ffo reaches the selecte rx ffo aterar rf threshol he settin o rff only causes an interrut when rr an rrff are set an rx ffo is enale rff is autoatically cleare when the aount o ata in rx ffo alls elow the threshol he rff it is cleare y or an reset hen rx ffo contains wors the axiu it can hol all urther ata receie or storae in this ffo is inore until the ffo contents are rea ace aailale in receie ffo receie ffo is ull f ransit ffo ty his la is set when the ety slots in x ffo excee or are equal to the selecte x ffo aterar f threshol an the twochannel oe is selecte he settin o f only causes an interrut when r an rf are set x ffo is enale an twochannel oe is selecte he f it is autoatically cleare when the ata leel in x ffo ecoes ore than the aount seciie y the waterar its he f it is set y or an reset ransit ffo has ata or transission ransit ffo is ety table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 164 freescale semiconductor, inc. i2s x r iel escritions continue fiel escrition f ransit ffo ty his la is set when the ety slots in x ffo excee or are equal to the selecte x ffo aterar f threshol he settin o f only causes an interrut when r an rf are set an x ffo is enale he f it is autoatically cleare when the ata leel in x ffo ecoes ore than the aount seciie y the waterar its he f it is set y or an reset ransit ffo has ata or transission ransit ffo is ety nterrut nale reister x r the i2s interrupt enable register (ier) is a 25-bit register used to set up the i2s interrupts and dma requests. addresses: i2s0_ier is 4002_f000h base + 18h offset = 4002_f018h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 rfrc_en tfrc_en rdmae rie tdmae tie cmdauen cmdduen rxten w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r rdr1en rdr0en tde1en tde0en roe1en roe0en tue1en tue0en tfsen rfsen tlsen rlsen rff1en rff0en tfe1en tfe0en w reset 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 i2s x r iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero rfr nale it ach it controls whether the corresonin status it in r can issue an interrut to the core or not orresonin status it cannot issue interrut orresonin status it can issue interrut fr nale it ach it controls whether the corresonin status it in r can issue an interrut to the core or not table continues on the next page... chapter integrated interchip sound i2s 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 16 i2s x r iel escritions continue fiel escrition orresonin status it cannot issue interrut orresonin status it can issue interrut r receie nale his it allows to request or transers hen enale requests are enerate when any o the rff its in the r are set an i the corresonin rf it is also set the corresonin ffo is isale a request is enerate when the corresonin rr it is set receier requests isale receier requests enale r receie nterrut nale his control it allows the to issue receier relate interruts to the core receier interrut requests isale receier interrut requests enale ransit nale his it allows to request or transers hen enale requests are enerate when any o the rf its are set an i the corresonin rf it is also set the corresonin ffo is isale a request is enerate when the corresonin it is set transitter requests isale transitter requests enale ransit nterrut nale his control it allows the to issue transitter ata relate interruts to the core transitter interrut requests isale transitter interrut requests enale u nale it ach it controls whether the corresonin status it in r can issue an interrut to the core or not orresonin status it cannot issue interrut orresonin status it can issue interrut u nale it ach it controls whether the corresonin status it in r can issue an interrut to the core or not orresonin status it cannot issue interrut orresonin status it can issue interrut r nale it ach it controls whether the corresonin status it in r can issue an interrut to the core or not orresonin status it cannot issue interrut orresonin status it can issue interrut rr nale it table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 166 freescale semiconductor, inc. i2s x r iel escritions continue fiel escrition ach it controls whether the corresonin status it in r can issue an interrut to the core or not orresonin status it cannot issue interrut orresonin status it can issue interrut rr nale it ach it controls whether the corresonin status it in r can issue an interrut to the core or not orresonin status it cannot issue interrut orresonin status it can issue interrut nale it ach it controls whether the corresonin status it in r can issue an interrut to the core or not orresonin status it cannot issue interrut orresonin status it can issue interrut nale it ach it controls whether the corresonin status it in r can issue an interrut to the core or not orresonin status it cannot issue interrut orresonin status it can issue interrut ro nale it ach it controls whether the corresonin status it in r can issue an interrut to the core or not orresonin status it cannot issue interrut orresonin status it can issue interrut ro nale it ach it controls whether the corresonin status it in r can issue an interrut to the core or not orresonin status it cannot issue interrut orresonin status it can issue interrut u nale it ach it controls whether the corresonin status it in r can issue an interrut to the core or not orresonin status it cannot issue interrut orresonin status it can issue interrut u nale it ach it controls whether the corresonin status it in r can issue an interrut to the core or not orresonin status it cannot issue interrut orresonin status it can issue interrut f nale it ach it controls whether the corresonin status it in r can issue an interrut to the core or not table continues on the next page... chapter integrated interchip sound i2s 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 167 i2s x r iel escritions continue fiel escrition orresonin status it cannot issue interrut orresonin status it can issue interrut rf nale it ach it controls whether the corresonin status it in r can issue an interrut to the core or not orresonin status it cannot issue interrut orresonin status it can issue interrut l nale it ach it controls whether the corresonin status it in r can issue an interrut to the core or not orresonin status it cannot issue interrut orresonin status it can issue interrut rl nale it ach it controls whether the corresonin status it in r can issue an interrut to the core or not orresonin status it cannot issue interrut orresonin status it can issue interrut rff nale it ach it controls whether the corresonin status it in r can issue an interrut to the core or not orresonin status it cannot issue interrut orresonin status it can issue interrut rff nale it ach it controls whether the corresonin status it in r can issue an interrut to the core or not orresonin status it cannot issue interrut orresonin status it can issue interrut f nale it ach it controls whether the corresonin status it in r can issue an interrut to the core or not orresonin status it cannot issue interrut orresonin status it can issue interrut f nale it ach it controls whether the corresonin status it in r can issue an interrut to the core or not orresonin status it cannot issue interrut orresonin status it can issue interrut eory areister einition ufaily reerence anual re o freescale eiconuctor nc 53.3.8 i 2 s transmit configuration register (i2s x r the tcr directs the transmit operation of the i2s. a power-on reset clears all tcr bits. however, i2s reset does not affect the tcr bits. addresses: i2s0_tcr is 4002_f000h base + 1ch offset = 4002_f01ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 txbit0 tfen1 tfen0 tfdir txdir tshfd tsckp tfsi tfsl tefs w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 i2s x r iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero ransit it his control it allows to transit the ata wor ro it osition or in the transit shit reister he shitin ata irection can e or l irst controlle y the rhf it hitin with resect to it i wor lenth or or it i wor lenth or o transit shit reister aline hitin with resect to it o transit shit reister l aline f ransit ffo nale his it enales transit ffo hen enale the ffo allows sales to e transitte y the er channel a th sale can e shitin out eore it is set hen the ffo is isale an interrut is enerate when a sinle sale is transerre to the transit shit reister roie the interrut is enale ransit ffo isale ransit ffo enale f ransit ffo nale his it enales transit ffo hen enale the ffo allows sales to e transitte y the er channel a th sale can e shitin out eore it is set hen the ffo is isale an interrut is enerate when a sinle sale is transerre to the transit shit reister roie the interrut is enale ransit ffo isale ransit ffo enale fr ransit frae irection his it controls the irection an source o the transit rae sync sinal nternally enerate rae sync sinal is sent out throuh the f ort an external rae sync is taen ro the sae ort frae sync is external frae sync enerate internally table continues on the next page... chapter integrated interchip sound i2s 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 16 i2s x r iel escritions continue fiel escrition r ransit cloc irection his it controls the irection an source o the cloc sinal use to cloc the r nternally enerate cloc is outut throuh the ort xternal cloc is taen ro this ort ransit cloc is external ransit cloc enerate internally hf ransit hit irection his it controls whether the or l will e transitte irst in a sale o: he o eice laels the as it whereas the core laels the l as it hereore when usin a stanar o core o l is shite in irst rhf cleare ata transitte irst ata transitte l irst ransit loc olarity his it controls which it cloc ee is use to cloc out ata or the transit section o: is l is l ata cloce out on risin ee o it cloc ata cloce out on allin ee o it cloc f ransit frae ync nert his it controls the actie state o the rae sync o sinal or the transit section o ransit rae sync is actie hih ransit rae sync is actie low fl ransit frae ync lenth his it controls the lenth o the rae sync sinal to e enerate or reconie or the transit section he lenth o a worlon rae sync is sae as the lenth o the ata wor selecte y l: ransit rae sync is onewor lon ransit rae sync is oneclocit lon f ransit arly frae ync his it controls when the rae sync is initiate or the transit section he rae sync sinal is easserte ater one itorit lenth rae sync an ater one wororwor lenth rae sync n case o synchronous oeration the rae sync can also e initiate on receiin the irst it o ata ransit rae sync initiate as the irst it o ata is transitte ransit rae sync is initiate one it eore the ata is transitte eory areister einition ufaily reerence anual re o freescale eiconuctor nc 53.3.9 i 2 s receive configuration register (i2s x rr rcr directs the receive operation of the i2s. a power-on reset clears all rcr bits. however, i2s reset does not affect the rcr bits. addresses: i2s0_rcr is 4002_f000h base + 20h offset = 4002_f020h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 rxext rxbit0 rfen1 rfen0 rfdir rxdir rshfd rsckp rfsi rfsl refs w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 i2s x rr iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero r receie ata xtension his control it allows to store the receie ata wor in sin extene or his it aects ata storae only in case receie ata is l aline rr in extension turne o in extension turne on r receie it his control it allows to receie the ata wor at it osition or in the receie shit reister he shitin ata irection can e or l irst controlle y the rhf it hitin with resect to it i wor lenth or or it i wor lenth or o receie shit reister aline hitin with resect to it o receie shit reister l aline rf receie ffo nale his it enales receie ffo hen enale the ffo allows sales to e receie y the er channel a th sale can e shitin in eore rr it is set hen the ffo is isale an interrut is enerate when a sinle sale is receie y the roie the interrut is enale receie ffo isale receie ffo enale rf receie ffo nale his it enales receie ffo hen enale the ffo allows sales to e receie y the er channel a th sale can e shitin in eore rr it is set hen the ffo is isale an interrut is enerate when a sinle sale is receie y the roie the interrut is enale receie ffo isale receie ffo enale rfr receie frae irection table continues on the next page... chapter integrated interchip sound i2s 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1701 i2s x rr iel escritions continue fiel escrition his it controls the irection an source o the receie rae sync sinal nternally enerate rae sync sinal is sent out throuh the rf ort an external rae sync is taen ro the sae ort frae ync is external frae ync enerate internally rr receie loc irection his it controls the irection an source o the cloc sinal use to cloc the rr nternally enerate cloc is outut throuh the r ort xternal cloc is taen ro this ort receie loc is external receie loc enerate internally rhf receie hit irection his it controls whether the or l will e receie irst in a sale o: he o eice laels the as it whereas the ore laels the l as it hereore when usin a stanar o ore o l is shite in irst rhf cleare ata receie irst ata receie l irst r receie loc olarity his it controls which it cloc ee is use to latch in ata or the receie section ata latche on allin ee o it cloc ata latche on risin ee o it cloc rf receie frae ync nert his it controls the actie state o the rae sync o sinal or the receie section o receie rae sync is actie hih receie rae sync is actie low rfl receie frae ync lenth his it controls the lenth o the rae sync sinal to e enerate or reconie or the receie section he lenth o a worlon rae sync is sae as the lenth o the ata wor selecte y l: receie rae sync is onewor lon receie rae sync is oneclocit lon rf receie arly frae ync his it controls when the rae sync is initiate or the receie section he rae sync is isale ater one itorit lenth rae sync an ater one wororwor lenth rae sync receie rae sync initiate as the irst it o ata is receie receie rae sync is initiate one it eore the ata is receie eory areister einition ufaily reerence anual re o freescale eiconuctor nc 53.3.10 i 2 s transmit clock control registers (i2s x r the i2s transmit and receive control (tccr and rccr) registers are 19-bit, read/write control registers used to direct the operation of the i2s. the clock and reset module (crm) can source the i2s clock (network clock) from multiple sources and perform fractional division to support commonly used audio bit rates. the crm can maintain the network clock frequency at a constant rate even in cases where the peripheral clock frequency changes. these registers control the i2s clock generator, bit and frame sync rates, word length, and number of words per frame for the serial data. the tccr register is dedicated to the transmit section, and the rccr register is dedicated to the receive section except in synchronous mode, in which the tccr register controls both the receive and transmit sections. power-on reset clears all tccr and rccr bits. i2s reset does not affect the tccr and rccr bits. the control bits are described in the following paragraphs. although the bit patterns of the tccr and rccr registers are the same, the contents of these two registers can be programmed differently. addresses: i2s0_tccr is 4002_f000h base + 24h offset = 4002_f024h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 div2 psr wl dc pm w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i2s x r iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero iie y his it controls a iieytwo iier in series with the rest o the rescalers iier yasse iier use to iie cloc y r rescaler rane his it controls a ixe iieyeiht rescaler in series with the ariale rescaler t extens the rane o the rescaler or those cases where a slower it cloc is require rescaler yasse rescaler use to iie cloc y l or lenth ontrol eciies the nuer o its er ata wor ein transerre y the hese its control the or lenth iier in the loc enerator hey also control the rae sync ulse lenth when the fl it is cleare n aster oe the wors with a ixe wor lenth o an the l its are use to table continues on the next page... chapter integrated interchip sound i2s 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 170 i2s x r iel escritions continue fiel escrition control the aount o ali ata in those its n oe o oeration i wor lenth is set to any alue other than its it will result in a wor lenth o its resere o not rora this alue resere o not rora this alue resere o not rora this alue resere o not rora this alue resere o not rora this alue resere o not rora this alue resere o not rora this alue resere o not rora this alue frae rate iier ontrol hese its are use to control the iie ratio or the roraale rae rate iiers he iie ratio wors on the wor cloc n oral oe this ratio eterines the wor transer rate n etwor oe this ratio sets the nuer o wors er rae he iie ratio ranes ro to in oral oe an ro to in etwor oe n oral oe a iie ratio o roies continuous erioic ata wor transer itlenth rae sync ust e use in this case hese its can e rorae with alues ranin ro to to control the nuer o wors in a rae rescaler oulus elect hese its control the rescale iier in the cloc enerator his rescaler is use only in nternal loc oe to iie the internal cloc he it cloc outut is aailale at the cloc ort iie ratio ro to : x to xff can e selecte eory areister einition ufaily reerence anual re o freescale eiconuctor nc 53.3.11 i 2 s receive clock control registers (i2s x rr the i2s transmit and receive control (tccr and rccr) registers are 19-bit, read/write control registers used to direct the operation of the i2s. the clock and reset module (crm) can source the i2s clock (network clock) from multiple sources and perform fractional division to support commonly used audio bit rates. the crm can maintain the network clock frequency at a constant rate even in cases where the peripheral clock frequency changes. these registers control the i2s clock generator, bit and frame sync rates, word length, and number of words per frame for the serial data. the tccr register is dedicated to the transmit section, and the rccr register is dedicated to the receive section except in synchronous mode, in which the tccr register controls both the receive and transmit sections. power-on reset clears all tccr and rccr bits. i2s reset does not affect the tccr and rccr bits. the control bits are described in the following paragraphs. although the bit patterns of the tccr and rccr registers are the same, the contents of these two registers can be programmed differently. addresses: i2s0_rccr is 4002_f000h base + 28h offset = 4002_f028h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 div2 psr wl dc pm w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i2s x rr iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero iie y his it controls a iieytwo iier in series with the rest o the rescalers iier yasse iier use to iie cloc y r rescaler rane his it controls a ixe iieyeiht rescaler in series with the ariale rescaler t extens the rane o the rescaler or those cases where a slower it cloc is require rescaler yasse rescaler use to iie cloc y l or lenth ontrol hese its are use to control the lenth o the ata wors ein transerre y the hese its control the or lenth iier in the loc enerator hey also control the rae sync ulse lenth when the fl it is cleare n aster oe the wors with a ixe wor lenth o an the l its are table continues on the next page... chapter integrated interchip sound i2s 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 170 i2s x rr iel escritions continue fiel escrition use to control the aount o ali ata in those its n oe o oeration i wor lenth is set to any alue other than its it will result in a wor lenth o its uer o itsor: uorte in leentation: o uer o itsor: uorte in leentation: o uer o itsor: uorte in leentation: o uer o itsor: uorte in leentation: es uer o itsor: uorte in leentation: es uer o itsor: uorte in leentation: es uer o itsor: uorte in leentation: o uer o itsor: uorte in leentation: es uer o itsor: uorte in leentation: es uer o itsor: uorte in leentation: es uer o itsor: uorte in leentation: es uer o itsor: uorte in leentation: es uer o itsor: uorte in leentation: o uer o itsor: uorte in leentation: o uer o itsor: uorte in leentation: o uer o itsor: uorte in leentation: o frae rate iier ontrol hese its are use to control the iie ratio or the roraale rae rate iiers he iie ratio wors on the wor cloc n oral oe this ratio eterines the wor transer rate n etwor oe this ratio sets the nuer o wors er rae he iie ratio ranes ro to in oral oe an ro to in etwor oe n oral oe a iie ratio o roies continuous erioic ata wor transer itlenth rae sync ust e use in this case hese its can e rorae with alues ranin ro to to control the nuer o wors in a rae rescaler oulus elect hese its control the rescale iier in the cloc enerator his rescaler is use only in nternal loc oe to iie the internal cloc he it cloc outut is aailale at the cloc ort iie ratio ro to : x to xff can e selecte ffo ontroltatus reister x fr the following table indicates the status of the transmit fifo empty flag, with different settings of the transmit fifo watermark bits and varying amounts of data in the tx fifo. table 53-40. status of transmit fifo empty flag transmit fifo watermark (tfwm) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 1706 freescale semiconductor, inc. table 53-40. status of transmit fifo empty flag (continued) transmit fifo watermark (tfwm) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 3 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 4 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 5 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 6 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 7 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 8 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 9 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 10 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 11 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 12 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 13 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 14 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 addresses: i2s0_fcsr is 4002_f000h base + 2ch offset = 4002_f02ch bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r rfcnt1 tfcnt1 rfwm1 tfwm1 rfcnt0 tfcnt0 rfwm0 tfwm0 w reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 i2s x fr iel escritions fiel escrition rf receie ffo ounter hese its inicate the nuer o ata wors in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo table continues on the next page... chapter integrated interchip sound i2s 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1707 i2s x fr iel escritions continue fiel escrition ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo f ransit ffo ounter hese its inicate the nuer o ata wors in ransit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo rf receie ffo full aterar hese its control the threshol at which the rff la will e set he rff la is set wheneer the ata leel in rx ffo reaches the selecte threshol resere rff set when at least one ata wor hae een written to the receie ffo et when rxffo ata wors rff set when ore than or equal to ata wor hae een written to the receie ffo et when rxffo ata wors rff set when ore than or equal to ata wor hae een written to the receie ffo et when rxffo ata wors rff set when ore than or equal to ata wor hae een written to the receie ffo et when rxffo ata wors rff set when ore than or equal to ata wor hae een written to the receie ffo et when rxffo ata wors rff set when ore than or equal to ata wor hae een written to the receie et when rxffo ata wors rff set when ore than or equal to ata wor hae een written to the receie ffo et when rxffo ata wors rff set when ore than or equal to ata wor hae een written to the receie ffo et when rxffo ata wors rff set when ore than or equal to ata wor hae een written to the receie ffo et when rxffo ata wors table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 1708 freescale semiconductor, inc. i2s x fr iel escritions continue fiel escrition rff set when ore than or equal to ata wor hae een written to the receie ffo et when rxffo ata wors rff set when ore than or equal to ata wor hae een written to the receie ffo et when rxffo ata wors rff set when ore than or equal to ata wor hae een written to the receie ffo et when rxffo ata wors rff set when ore than or equal to ata wor hae een written to the receie ffo et when rxffo ata wors rff set when ore than or equal to ata wor hae een written to the receie ffo et when rxffo ata wors rff set when ata wor hae een written to the receie ffo eault et when rxffo ata wors f ransit ffo ty aterar hese its control the threshol at which the f la will e set he f la is set wheneer the ety slots in x ffo excee or are equal to the selecte threshol resere f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata rf receie ffo ounter table continues on the next page... chapter integrated interchip sound i2s 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 170 i2s x fr iel escritions continue fiel escrition hese its inicate the nuer o ata wors in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo ata wor in receie ffo f ransit ffo ounter hese its inicate the nuer o ata wors in ransit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo ata wor in transit ffo rf receie ffo full aterar hese its control the threshol at which the rff la will e set he rff la is set wheneer the ata leel in rx ffo reaches the selecte threshol resere rff set when at least one ata wor hae een written to the receie ffo et when rxffo ata wors table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 1710 freescale semiconductor, inc. i2s x fr iel escritions continue fiel escrition rff set when ore than or equal to ata wor hae een written to the receie ffo et when rxffo ata wors rff set when ore than or equal to ata wor hae een written to the receie ffo et when rxffo ata wors rff set when ore than or equal to ata wor hae een written to the receie ffo et when rxffo ata wors rff set when ore than or equal to ata wor hae een written to the receie ffo et when rxffo ata wors rff set when ore than or equal to ata wor hae een written to the receie et when rxffo ata wors rff set when ore than or equal to ata wor hae een written to the receie ffo et when rxffo ata wors rff set when ore than or equal to ata wor hae een written to the receie ffo et when rxffo ata wors rff set when ore than or equal to ata wor hae een written to the receie ffo et when rxffo ata wors rff set when ore than or equal to ata wor hae een written to the receie ffo et when rxffo ata wors rff set when ore than or equal to ata wor hae een written to the receie ffo et when rxffo ata wors rff set when ore than or equal to ata wor hae een written to the receie ffo et when rxffo ata wors rff set when ore than or equal to ata wor hae een written to the receie ffo et when rxffo ata wors rff set when ore than or equal to ata wor hae een written to the receie ffo et when rxffo ata wors rff set when ata wor hae een written to the receie ffo eault et when rxffo ata wors f ransit ffo ty aterar hese its control the threshol at which the f la will e set he f la is set wheneer the ety slots in x ffo excee or are equal to the selecte threshol resere f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata table continues on the next page... chapter integrated interchip sound i2s 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1711 i2s x fr iel escritions continue fiel escrition f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata f set when there are ore than or equal to ety slots in ransit ffo eault ransit ffo ety is set when xffo ata ontrol reister x resses: is fh ase h oset fh it r reset it r fr r r f f reset x iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero fr frae rate iier hese its control the requency o ata transissionrecetion hey are rorae with the nuer o raes or which the shoul e ile ater oeratin in one rae hrouh these its requency o oeration ro h to h can e achiee ale alue: ecial will oerate once eery raes r rite oan table continues on the next page... memory mapregister definition 60 sub-family reference manual, rev. 6, nov 2011 1712 freescale semiconductor, inc. i2s x iel escritions continue fiel escrition his it seciies whether the next rae will carry an rite oan or not he roraer shoul tae care that only one o the its r or r is set at a tie hen this it is set the corresonin ta its corresonin to oan ress an oan ata slots o the next x rae are autoatically set his it is autoatically cleare y the ater coletin transission o a rae ext rae will not hae a rite oan ext rae will hae a rite oan r rea oan his it seciies whether the next rae will carry an rea oan or not he roraer shoul tae care that only one o the its r or r is set at a tie hen this it is set the corresonin ta it corresonin to oan ress slot o the next x rae is autoatically set his it is autoatically cleare y the ater coletin transission o a rae ext rae will not hae a rea oan ext rae will hae a rea oan f a in ffo his it controls the estination o the inoration receie in ta slot lot a ino store in reister a ino store in reister an rx ffo f fixeariale oeration his it selects whether the is in fixe oe or ariale oe fixe oe ariale oe oe nale his it is use to enale oeration oe isale in oe oan ress reister x resses: is fh ase h oset fh it r reset hater nterate interchi soun ufaily reerence anual re o freescale eiconuctor nc i2s x iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero oan ress hese its store the oan ress lot inoration it o the slot is sent in accorance with the rea an rite oan its in reister hese its can e uate y a irect write ro the ore hey are also uate with the inoration receie in the incoin oan ress lot the contents o these its chane ue to an uate the u it in r is set oan ata reister x resses: is fh ase h oset fh it r reset x iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero oan ata he outoin oan ata lot carries the inoration containe in these its hese its can e uate y a irect write ro the ore hey are also uate with the inoration receie in the incoin oan ata lot the contents o these its chane ue to an uate the u it in r is set hese its are transitte only urin rite oan urin rea oan x is transitte in tie slot a reister x resses: is fh ase h oset fh it r reset eory areister einition ufaily reerence anual re o freescale eiconuctor nc i2s x iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero a alue ritin to this reister y the ore sets the alue o the xa in ixe oe o oeration on a rea the ore ets the rxa alue receie in the last rae ro the oec f it in reister is set the alue is also store in rxffo in aition to reister hen the receie a alue chanes the r it in r reister is set its : coney the oec n current ileentation only riary oecs are suorte hus writin alue to this iel is anatory ransit ie lot as reister x resses: is fh ase h oset fh it r reset x iel escritions fiel escrition ransit as hese its inicate which slot has een ase in the current rae he ore can write to this reister to control the tie slots in which the transits ata ach it has ino corresonin to the resectie tie slot in the rae ransit as its shoul not e use in lae oe o oeration reister alue ust e set eore enalin ransission ali ie lot ie lot ase no ata transitte in this tie slot receie ie lot as reister x r resses: r is fh ase h oset fh it r r reset hater nterate interchi soun ufaily reerence anual re o freescale eiconuctor nc i2s x r iel escritions fiel escrition r receie as hese its inicate which slot has een ase in the current rae he ore can write to this reister to control the tie slots in which the receies ata ach it has ino corresonin to the resectie tie slot in the rae r reister alue ust e set eore enalin receierreceie as its shoul not e use in lae oe o oeration ali ie lot ie lot ase no ata receie in this tie slot hannel tatus reister x resses: is fh ase h oset fh it r reset x iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero hannel tatus hese its inicate which ata slot has een enale in ariale oe oeration his reister is uate in case the core enalesisales a channel throuh a write to reister or the external coec enales a channel y senin a in the corresonin lor it it corresons to the irst ata slot in an rae lot an it corresons to the tenth ata slot slot he contents o this reister only hae releance while the is oeratin in ariale oe rites to this reister result in an error resonse on the interace ata channel isale ata channel enale hannel nale reister x resses: is fh ase h oset fh it r reset eory areister einition ufaily reerence anual re o freescale eiconuctor nc i2s x iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero hannel nale he ore writes a to these its to enale an ata channel ritin a has no eect it corresons to the irst ata slot in an rae lot an it corresons to the tenth ata slot slot rites to these its only hae eect in the ariale oe o oeration hese its are always rea as y the ore rite has no eect rite enales the corresonin ata channel hannel isale reister x resses: is fh ase h oset fh it r reset x iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero hannel isale he ore writes a to these its to isale an ata channel ritin a has no eect it corresons to the irst ata slot in an rae lot an it corresons to the tenth ata slot slot rites to these its only hae eect in the ariale oe o oeration hese its are always rea as y the ore rite has no eect rite isales the corresonin ata channel functional escrition this section provides the functional details of the i 2 s module. chapter 53 integrated interchip sound (i2s) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1717 53.4.1 detailed operating mode descriptions the following sections provide detailed descriptions of the above modes. 53.4.1.1 normal mode normal mode is the simplest mode of the i 2 s. it transfers data in one time slot per frame. a time slot is a unit of data and the rccr[wl] bits define the number of bits in a time slot. in continuous clock mode, a frame sync occurs at the beginning of each frame. the following factors determine the length of the frame: ? period of the serial bit clock (tccr[div2], tccr[psr], tccr[pm] bits for internal clock or the frequency of the external clock on the stck port) ? number of bits per time slot (rccr[wl] bits) ? number of time slots per frame (tccr[dc] bits) if normal mode is configured with more than one time slot per frame, data transfers only in the first time slot of the frame. no data transfers in subsequent time slots. in normal mode, tccr[dc] values corresponding to more than a single time slot in a frame only result in lengthening the frame. 53.4.1.1.1 normal mode transmit conditions for data transmission from the i 2 s in normal mode are: 1. i 2 s enabled (cr[i2sen] = 1) 2. enable fifo and configure transmit and receive watermark if the fifo is used 3. write data to transmit data register (tx) 4. transmitter enabled (cr[te] = 1) 5. frame sync active (for continuous clock case) 6. bit clock begins (for gated clock case) when the above conditions occur in normal mode, the next data word transfers into the transmit shift register (txsr) from the transmit data register 0 (tx0), or from the transmit fifo 0 register, if enabled. ? in continuous clock mode, the data word is transmitted on arrival of frame-sync preceded by clocks. functional description k60 sub-family reference manual, rev. 6, nov 2011 1718 freescale semiconductor, inc. ? in gated-external mode, the data word in transmitted on the external clock. ? in gated-internal mode, the data word is transmitted whenever data is available in the transmit fifo. if transmit fifo 0 is not enabled and the transmit data register empty enable (ier[tde0en]) and transmit interrupt enable (ier[tie]) bits are set, transmit interrupt 0 occurs when the word in i 2 s_tx0 is shifted to transmit shift (txsr) register. if transmit fifo 0 is enabled and the transmit fifo full enable (ier[tff0en]) and transmit interrupt enable (ier[tie]) bits are set, transmit interrupt 0 occurs when the number of empty slots in transmit fifo 0 are equal to or exceed the selected threshold value (transmit fifo 0 watermark (fcsr[tfwm0]). if transmit fifo 0 is enabled and filled with data, 15 data words can be transferred before the core must write new data to the tx0 register. the stxd port is disabled except during the data transmission period. for a continuous clock, the optional frame sync output and clock outputs are not disabled, even if the receiver and transmitter are disabled. 53.4.1.1.2 normal mode receive the conditions for data reception from the i 2 s are: 1. i 2 s enabled (cr[i2sen] = 1) 2. enable receive fifo (optional) 3. receiver enabled (cr[re] = 1) 4. frame sync active (for continuous clock case) 5. bit clock begins (for gated clock case) with the above conditions in normal mode with a continuous clock, each time the frame sync signal is generated (or detected) a data word is clocked in. with the above conditions and a gated clock, each time the clock begins, a data word is clocked in. if receive fifo 0 is not enabled and receive interrupt enable (ier[rie]) and received data 0 ready enable (ier[rdr0en]) bits are set, receive interrupt 0 occurs when received data word is transferred from the receive shift register (rxsr) to the receive data register 0 (rx0), thus setting the receive data ready 0 (rdr0) flag. chapter 53 integrated interchip sound (i2s) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1719 if receive fifo 0 is enabled and receive interrupt enable (ier[rie]) and received fifo 0 full enable (ier[rdr0en]) bits are set, receive interrupt 0 occurs when the received data word is transferred to the receive fifo 0 and receive fifo 0 reaches the selected threshold. this results in receive fifo full 0 (rff0) flag to set. the core has to read the data from the receive data register 0 (rx0) (if receive fifo 0 is disabled) before a new data word is transferred from the receive shift register (rxsr). otherwise, the receive overrun error 0 (ier[roe0en]) bit is set. if receive fifo 0 is enabled, the receive overrun error 0 (roe0) bit sets when the receive fifo 0 data level reaches the selected threshold and a new data word is ready to transfer to the receive fifo 0. the following figure shows transmitter and receiver timing for an 8-bit word in the first time slot in normal mode and continuous clock with a late word length frame sync. the transmit data register is loaded with the data to be transmitted. on arrival of the clock, this data is transferred to the transmit shift register which is transmitted on arrival of the frame-sync on the stxd output. simultaneously, the receive shift register shifts in the received data available on the srxd input. at the end of the time slot, this data is transferred to the receive data register. clk fs tx data reg stxd rx data reg continuos srxd figure 53-46. normal mode timing - continuous clock the following figure shows a similar case for internal (i 2 s generates clock) gated clock mode. functional description k60 sub-family reference manual, rev. 6, nov 2011 1720 freescale semiconductor, inc. note a pull-down resistor is required in the gated clock mode, because the clock port is disabled between transmissions. the tx data register is loaded with the data to be transmitted. on arrival of the clock, this data is transferred to the transmit shift register which gets transmitted on the stxd output. simultaneously, the receive shift register shifts in the received data available on the srxd input and at the end of the time slot, this data is transferred to the rx data register. in internal gated clock mode, the tx data line and clock output port are put in the high-impedance state at the end of transmission of the last bit (at the completion of the complete clock cycle). whereas, in external gated clock mode, the tx data line is tri- stated at the last inactive edge of the incoming bit clock (during the last bit in a data word). gated clk tx data stxd rx data srxd figure 53-47. normal mode timing - internal gated clock the following figure shows a case for external (i 2 s receives clock) gated clock mode chapter 53 integrated interchip sound (i2s) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1721 gated clk tx data stxd rx data srxd figure 53-48. normal mode timing - external gated clock 53.4.1.2 network mode network mode creates a time division multiplexed (tdm) network, such as a tdm codec network or a network of dsps. in continuous clock mode, a frame sync occurs at the beginning of each frame. in this mode, the frame is divided into more than one time slot. during each time slot, one data word can be transferred. each time slot is then assigned to an appropriate codec or dsp on the network. the processor can be a master device that controls its own private network, or a slave device that is connected to an existing tdm network and occupies a few time slots. the frame sync signal indicates the beginning of a new data frame. each data frame is divided into time slots and transmission and/or reception of one data word can occur in each time slot (rather than in just the frame sync time slot as in normal mode). the frame rate dividers, controlled by the dc bits, select two to thirty-two time slots per frame. the length of the frame is determined by: ? period of the serial bit clock (psr, pm bits for internal clock, or the frequency of the external clock on the stck port) ? number of bits per sample (wl bits) ? number of time slots per frame (dc bits) in network mode, data can be transmitted in any time slot. the distinction of the network mode is that each time slot is identified with respect to the frame sync (data word time). this time slot identification allows the option of transmitting data during the time slot by functional description k60 sub-family reference manual, rev. 6, nov 2011 1722 freescale semiconductor, inc. writing to the tx registers or ignoring the time slot as determined by tmsk register bits. the receiver is treated in the same manner and received data is only transferred to the receive data register/fifo if the corresponding time slot is enabled through rmsk. by using the tmsk and rmsk registers, software only has to service the i 2 s during valid time slots. this eliminates any overhead associated with unused time slots. in the two-channel mode, the second set of transmit and receive fifos and data registers create two separate channels. these channels are completely independent with their own set of interrupts and dma requests, which are identical to the ones available for the default channel. in this mode, data is transmitted/received in enabled time slots alternately from/to fifo 0 and fifo 1, starting from fifo 0. the first data word is taken from fifo 0 and transmitted in the first enabled time slot and subsequently, data is loaded from fifo 1 and fifo 0 alternately and transmitted. similarly, the first received data is sent to fifo 0 and subsequent data is sent to fifo 1 and fifo 0 alternately. time slots are selected through the transmit and receive time slot mask registers (tmsk and rmsk). for using this mode of operation, the cr[tchen] bit must be set. 53.4.1.2.1 network mode transmit the transmit portion of i 2 s is enabled when the cr[i2sen and te] bits are set. however, for continuous clock, when the cr[te] bit is set, the transmitter is enabled only after detection of a new frame sync (transmission starts from the next frame boundary). normal start-up sequence for transmission: 1. enable network mode 2. enable i 2 s 3. write the data to be transmitted to the tx register. this clears the isr[tde] flag 4. set the cr[te] bit to enable the transmitter on the next frame boundary (for continuous clock) 5. enable transmit interrupts alternatively, the user may decide not to transmit in a time slot by configuring the tmsk[stmsk]. the isr[tde] flag is cleared as data is shifted from tx register to txsr, but the stxd port remains disabled during the time slots. when the next frame sync is detected or generated (continuous clock), the data word in txsr and is shifted out (transmitted). when the tx register is empty, the isr[tde] bit is set, which causes a transmitter interrupt (in case the fifo is disabled) to be sent if the tie bit is set. software can poll the isr[tde] bit or use interrupts to reload the tx register with new data for the chapter 53 integrated interchip sound (i2s) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1723 next time slot. failing to reload the tx register before the txsr is finished shifting (empty) causes a transmitter underrun and the tue error bit is set. in case the fifo is enabled, the isr[tfe] flag is set in accordance with the watermark setting and this flag causes the transmitter interrupt to occur. clearing the te bit disables the transmitter after completion of transmission of the current frame. setting the te bit enables transmission from the next frame. during that time the stxd port is disabled. the te bit should be cleared after the isr[tde] bit is set to ensure that all pending data is transmitted. to summarize, the network mode transmitter generates interrupts every enabled time slot (when fifo is disabled) and requires the processor to respond to each enabled time slot. these responses may be: ? write data in data register to enable transmission in the next time slot. ? configure the time slot register to disable transmission in the next time slot (unless time slot is already masked by tmsk[stmsk] register bit). ? do nothingtransmit underrun occurs at the beginning of the next time slot and the previous data is re-transmitted. in two-channel mode, both channels (data registers, fifos, interrupts, and dma requests) operate in the same manner, as described above. the only difference is interrupts related to the second channel are generated only if this mode of operation is selected (isr[tde1] is low by default). 53.4.1.2.2 network mode receive the receiver portion of the i 2 s is enabled when the cr[i2sen and re] bits are set. however, the receive enable only takes place during that time slot if re is enabled before the second to last bit of the word. if the re bit is cleared, the receiver is disabled at the end of the current frame. the i 2 s module is capable of finding the start of the next frame automatically. when the word is completely received, it is transferred to the rx register, which sets the isr[rdr] bit. this causes a receive interrupt to occur if the receiver interrupt is enabled (ier[rie] is set) and receive data ready is enabled (ier[rdr0en] and ier[rdr1en] is set). the second data word (second time slot in the frame) begins shifting in immediately after the transfer of the first data word to the rx register. the processor has to read the data from the receive data register (which clears isr[rdr]) before the second data word is completely received (ready to transfer to rx data register) or a receive overrun error occurs (the isr[roe] bit is set). an interrupt can occur after the reception of each enabled data word or the user can poll the isr[rdr] flag. the response can be: functional description k60 sub-family reference manual, rev. 6, nov 2011 1724 freescale semiconductor, inc. ? read rx and use the data. ? read rx and ignore the data. ? do nothingthe receiver overrun exception occurs at the end of the current time slot. note for a continuous clock, the optional frame sync output and clock output signals are not affected, even if the transmitter or receiver is disabled. te and re do not disable the bit clock or the frame sync generation. to disable the bit clock and the frame sync generation, the cr[i2sen] bit can be cleared, or cr[tfrclkdis]/cr[rfrclkdis] bits can be set, or the port control logic external to the i 2 s can be reconfigured. in two-channel mode, both channels (data registers, fifos, interrupts and dma requests) operate in the same manner, as described above. the only difference is second channel interrupts are generated only in this mode of operation. the following figure shows the transmitter and receiver timing for an 8-bit word with continuous clock, fifo disabled, three words per frame sync in network mode. note the transmitter repeats the value 0x5e because of an underrun condition for the receive section, data received on the srxd pin is transferred to the rx data register at the end of each time slot. if the fifo is disabled, the isr[rdr] flag sets and causes a receiver interrupt if the cr[re], ier[rie], and ier[rdren] bits are set. if the fifo is enabled, then the isr[rff] flag generates interrupts (this flag is set in accordance with the watermark settings). in this example all time slots are enabled. the receive data ready flag is set after reception of the first data (0x55). because the flag is not cleared (rx data register is not read), the receive overrun error (roe) flag is set on reception of the next data (0x5e). the isr[roe] flag is cleared by writing one to the corresponding interrupt status bit in i 2 s status register. chapter 53 integrated interchip sound (i2s) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1725 clk fs tx data tde tue srxd roe rdr reg rx data 0x7b 0x7b 0x12 0x34 0xd6 0x55 0x5e 0xd6 0x5e0x55 0x5e 0x5e 0xd6 0xd6 0x5e 0x12 $7b 0xd6 0xd6 stxd reg note: processor must write 1? to the corresponding tue/roe interrupt status bit in isr to clear tue/roe interrupt figure 53-49. network mode timing - continuous clock 53.4.1.3 gated clock mode gated clock mode often connects to spi-type interfaces on microcontroller units (mcus) or external peripheral devices. in gated clock mode, the presence of the clock indicates that valid data is on the stxd or srxd signals. for this reason, no frame sync is needed in this mode. after transmission of data completes, the clock is pulled to the inactive state. gated clocks are allowed for the transmit and receive sections with either internal or external clock in normal mode. gated clocks are not allowed in network mode. see table 53-3 for i 2 s configuration for gated-mode operation. the clock operates when the cr[te] bit and/or the cr[re] bit are appropriately enabled. for the case of internally generated clock, all internal bit clocks, word clocks, and frame clocks continue to operate. when a valid time slot occurs (such as the first time slot in functional description k60 sub-family reference manual, rev. 6, nov 2011 1726 freescale semiconductor, inc. normal mode), the internal bit clock is enabled onto the appropriate clock port. this allows data to be transferred out in periodic intervals in gated clock mode. with an external clock, the i 2 s module waits for a clock signal to be received. after the clock begins, valid data is shifted in. ensure all rccr[dc] bits are cleared when the module is used in gated mode. in gated mode the isr[tfs], isr[rfs], isr[tls], isr[rls], isr[trfc] and isr[rfrc] bits are not generated. for gated clock operated in external clock mode, proper clock signalling must apply to the i 2 s stck for it to function properly. when tcr[tsckp] is cleared, cr[clkist] must be set. when tcr[tsckp] is set, cr[clkist] value must be cleared. if the i 2 s uses rising edge transition to clock data (tcr[tsckp] = 0) and the falling edge transition to latch data (rcr[rsckp] = 0), the clock must be in an active low state when idle. if the i 2 s uses falling edge transition to clock data (tcr[tsckp] = 1) and the rising edge transition to latch data (rcr[rsckp] = 1), the clock must be in a active high state when idle. the following diagrams illustrate the different edge clocking/latching. stck stxd srxd tcr[tsckp] = 0, rcr[rsckp] = 0 figure 53-50. internal gated mode timing - rising edge clocking/falling edge latching stck stxd srxd tcr[tsckp] = 1, rcr[rsckp] = 1 figure 53-51. internal gated mode timing - falling edge clocking/rising edge latching stck stxd srxd tcr[tsckp] = 0, rcr[rsckp] = 0 figure 53-52. external gated mode timing - rising edge clocking/falling edge latching chapter 53 integrated interchip sound (i2s) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1727 tcr[tsckp] = 1, rcr[rsckp] = 1 stck stxd srxd figure 53-53. external gated mode timing - falling edge clocking/rising edge latching note ? the bit clock signals must not have timing glitches. if a single glitch occurs, all ensuing transfers are out of synchronization. ? in external gated mode, even though the transmit data line is tri-stated at the last non-active edge of the bit clock, the round trip delay should sufficiently take care of hold time requirements at the external receiver. 53.4.1.4 i 2 s mode the i 2 s is compliant to the inter-ic sound (i 2 s) bus specification from philips semiconductors (february 1986, revised june 5, 1996). the following figure depicts basic i 2 s protocol timing. word (n-1) right channel word (n+1) right channel word (n) left channel msb lsb msb serial data frame sync serial clock figure 53-54. i 2 s mode timing - serial clock, frame sync and serial data select i 2 s mode using the options listed in the following table. table 53-50. i 2 s mode selection cr[i2smode] mode type 00 normal mode 01 i 2 s master mode table continues on the next page... functional description 60 sub-family reference manual, rev. 6, nov 2011 1728 freescale semiconductor, inc. table 53-50. i 2 s mode selection (continued) cr[i2smode] mode type 10 i 2 s slave mode 11 normal mode in normal (non-i 2 s) mode operation, no register bits are forced to any particular state internally, and the user can program the i 2 s to work in any operating condition. when i 2 s modes are entered (cr[i2smode] = 01 or 10), these settings are recommended: ? synchronous mode (cr[syn] =1) ? tx shift direction: msb transmitted first (tcr[tshfd] = 0) ? rx shift direction: msb received first (rcr[rshfd] = 0) ? tx data clocked at falling edge of the clock (tcr[tsckp] = 1) ? rx data latched at rising edge of the clock (rcr[rsckp] = 1) ? tx frame sync active low (tcr[tfsi] = 1) ? rx frame sync active low (rcr[rfsi] = 1) ? tx frame sync initiated one bit before data is transmitted (tcr[tefs] = 1) ? rx frame sync initiated one bit before data is received (rcr[refs] = 1) ? tx frame rate should be 2 (tccr[dc] = 1) ? rx frame rate should be 2 (rccr[dc] = 1) 53.4.1.4.1 i 2 s master mode in i 2 s master mode (cr[i2smode] = 01b), the following additional settings are recommended: ? internal generated bit clock (tcr[txdir] = 1) ? internal generated frame sync (tcr[tfdir] = 1) the processor automatically performs these settings in i 2 s master mode: ? network mode is selected (cr[net] = 1) ? tx frame sync length set to one-word-long-frame (tcr[tfsl]=0) chapter 53 integrated interchip sound (i2s) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1729 ? rx frame sync length set to one-word-long-frame (rcr[rfsl]=0) ? tx shifting w.r.t. bit 0 of txsr (tcr[txbit0] = 1) ? rx shifting w.r.t. bit 0 of rxsr (rcr[rxbit0] = 1) set the tccr[pm, psr, div2, wl, dc] to configure the bit clock and frame sync. the word length is fixed to 32 in i 2 s master mode and the rccr[wl] bits determine the number of bits that contain valid data (out of the 32 transmitted/received bits in each channel). 53.4.1.4.2 i 2 s slave mode in i 2 s slave mode (cr[i2smode] = 10b), the following additional settings are recommended: ? external generated bit clock (tcr[txdir] = 0) ? external generated frame sync (tcr[tfdir] = 0) the processor automatically performs these settings in i 2 s slave mode: ? normal mode is selected (cr[net] = 0) ? tx frame sync length set to one-bit-long-frame (tcr[tfsl] = 1) ? rx frame sync length set to one-bit-long-frame (rcr[rfsl] = 1) ? tx shifting w.r.t. bit 0 of txsr (tcr[txbit0] = 1) ? rx shifting w.r.t. bit 0 of rxsr (rcr[rxbit0] = 1) set the tccr[wl, dc] bits to configure the data transmission. the word length is variable in i 2 s slave mode and the rccr[wl] bits determine the number of bits that contain valid data. the actual word length is determined by the external codec. the external i 2 s master sends a frame sync according to the i 2 s protocol (early, word wide, and active low). the i 2 s internally operates so each frame sync transition is the start of a new frame (the rccr[wl] bits determine the number of bits to be transmitted/received). after one data word has been transferred, the i 2 s waits for the next frame sync transition to start operation in the next time slot. transmit and receive mask bits should not be used in i 2 s slave mode. functional description k60 sub-family reference manual, rev. 6, nov 2011 1730 freescale semiconductor, inc. 53.4.1.5 ac97 mode in ac97 mode, the i 2 s transmits a 16-bit tag slot at the start of a frame and the rest of the slots (in that frame) are all 20-bits wide. the same sequence is followed while receiving data. refer to the ac97 specification for details regarding transmit and receive sequences and data formats. note the audio codec specification released in 1997 [ac '97] defines the architecture and digital interface, specifically designed for implementing audio and modem i/o functionality in personal computers. companion specifications include the modem codec [mc '97], and the combined audio/modem codec standard [amc '97]. the current version of ac '97 was produced in 2002. the ac-97 specification defines a recommended 48-pin qfp ic package. since the i 2 s has only one rxdata pin only one codec is supported. secondary codecs are not supported. when ac97 mode is enabled, the hardware internal overrides the following settings. the programmed register values are not changed by entering ac97 mode but they no longer apply to the module's operation. writing to the programmed register fields updates their values. these updates can be seen by reading back the register fields. however, these settings do not take effect until ac97 mode is turned off. the register bits within the bracket are equivalent settings: ? synchronous mode is entered (cr[syn] = 1) ? network mode is selected (cr[net] = 1) ? tx shift direction is msb transmitted first (tcr[tshfd] = 0) ? rx shift direction is msb received first (rcr[rshfd] = 0) ? tx data is clocked at rising edge of the clock (tcr[tsckp] = 0) ? rx data is latched at falling edge of the clock (rcr[rsckp] = 0) ? tx frame sync is active high (tcr[tfsi] = 0) ? rx frame sync is active high (rcr[rfsi] = 0) ? tx frame sync length is one-word-long-frame (tcr[tfsl] = 0) ? rx frame sync length is one-word-long-frame (rcr[rfsl] = 0) chapter 53 integrated interchip sound (i2s) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1731 ? tx frame sync initiated one bit before data is transmitted (tcr[tefs] = 1) ? rx frame sync initiated one bit before data is received (rcr[refs] = 1) ? tx shifting w.r.t. bit 0 of txsr (tcr[txbit0] = 1) ? rx shifting w.r.t. bit 0 of rxsr (rcr[rxbit0] = 1) ? tx fifo is enabled (tcr[tfen0] = 1) ? rx fifo is enabled (rcr[rfen0] = 1) ? internally-generated frame sync (tcr[tfdir] = 1) ? externally-generated bit clock (tcr[txdir] = 0) any alteration of these bits does not affect the operational conditions of the i 2 s unless ac97 mode is deselected. hence, the only control bits that need to be set to configure the data transmission/reception are the tccr[wl, dc] bits. in ac97 mode, the wl bits can only legally take the values corresponding to 16-bit (truncated data) or 20-bit time slots. if the wl bits are set to select 16-bit time slots while receiving, the i 2 s pads the transmit data (four least significant bits) with zeros and while receiving, the i 2 s stores only the 16 most significant bits in the rx fifo. follow the sequence for programming the i 2 s to work in ac97 mode: 1. program the tccr[wl] bits to a value corresponding to 16 or 20 bits. the wl bit setting is only for the data portion of the ac97 frame (slots #3 through #12). the tag slot (slot #0) is always 16 bits wide and the command address and command data slots (slots #1 and #2) are always 20 bits wide. 2. select the number of time slots through the tccr[dc] bits. for ac97 operation, the dc bits should be set to a value of 0xc, resulting in 13 time slots per frame. 3. write data to be transmitted in tx fifo 0 (through tx data register 0) and tx fifo 1 while using two-channel mode (cr[tchen] = 1). 4. program the acnt[fv, tif, rd, wr, and frdiv] bits 5. update the contents of acadd, acdat, and atag (for fixed mode only) registers 6. enable ac97 mode (acnt[ac97en]) after the i 2 s starts transmitting and receiving data (after being configured in ac97 mode), the processor needs to service the interrupts when they are raised (updates to command address/data or tag registers, reading of received data, and writing more data for transmission). further details regarding fixed and variable mode implementation appear in the following sections. functional description k60 sub-family reference manual, rev. 6, nov 2011 1732 freescale semiconductor, inc. while using ac97 in two-channel mode (cr[tchen] = 1), it is recommended that the received tag is not stored in the rx fifo (acnt[tif] = 0). if you need to update the atag register and also issue a rd/wr command (in a single frame), it is recommended that the atag register is updated prior to issuing a rd/wr command. 53.4.1.5.1 ac97 fixed mode (acnt[fv] = 0) in fixed mode, i 2 s transmits in accordance with the ac97 frame rate divider bits (acnt[frdiv) that decide the number of frames for which the i 2 s should be idle, after operating for one frame. the following shows the slot assignments in a valid transmit frame:. ? slot 0: the tag value (written by the user program) ? slot 1: if rd/wr command, command address ? slot 2: if wr command, command data ? slot 3C12: transmit fifo data, depending on the valid slots indicated by the tag value while receiving, bit 15 of the tag slot is checked to see if the codec is ready. if this bit is set, the frame is received. the received tag provides the information about slots containing valid data. if the corresponding tag bit is valid, the command address (slot #1) and command data (slot #2) values are stored in the corresponding registers. the received data (slot #3C12) is then stored in the receive fifo (for valid slots). 53.4.1.5.2 ac97 variable mode (acnt[fv] = 1) in variable mode, the transmit slots that should contain data in the current frame are determined by the slotreq bits received in the previous frame. while receiving, if the codec is ready, the frame is received and the slotreq bits are stored for scheduling transmission in the next frame. the accst, accen and accdis registers helps determine which transmit slots are active. this information is used to ensure that i 2 s does not transmit data for powered- down/inactive channels. 53.4.2 i 2 s clocking the i 2 s uses the following clocks: chapter 53 integrated interchip sound (i2s) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1733 ? bit clock serially clocks the data bits in and out of the i 2 s port. this clock is either generated internally or taken from external clock source (through the tx/rx clock ports). ? word clock counts the number of data bits per word (8, 10, 12, 16, 18, 20, 22 or 24 bits). this clock is generated internally from the bit clock. ? frame clock (frame sync) counts the number of words in a frame. this signal can be generated internally from the bit clock, or taken from external source (from the tx/rx frame sync ports). ? master clock in master mode, this is an integer multiple of frame clock. it is used in cases when i 2 s has to provide the clock. ensure that the bit clock frequency (internally generated by dividing the network clock or sourced from external device through tx/rx clock ports) is never greater than 1/5 of the peripheral clock frequency. in normal mode, the bit clock, used to serially clock the data, is visible on the serial transmit clock (stck) and serial receive clock (srck) ports. the word clock is an internal clock used to determine when transmission of an 8, 10, 12, 16, 18, 20, 22 or 24 bit word has completed. the word clock then clocks the frame clock, which counts the number of words in the frame. the frame clock can be viewed on the stfs and srfs frame sync ports, because a frame sync generates after the correct number of words in the frame have passed. in master and synchronous mode, the srck port is used as serial oversampling clock (network clock) enabled by the cr[sysclken] bit. this serial system clock is an oversampling clock of the frame sync clock (stfs). in this mode, the word length (wl), prescaler range (psr), prescaler modulus (pm), and frame rate (dc) selects the ratio of network clock to sampling clock, stfs. in i 2 s mode, the oversampling clock network clock is available on this port if the cr[sysclken] bit is set. the following figure shows the relationship between the clocks and the dividers. the bit clock can be received from an i 2 s clock port or can be generated from the network clock through a divider, as shown in figure 53-56 . word divider (/8, /10, /12, /16, /18, /20, /22, /24) word clock frame divider (/1 to /32) frame clock serial bit clock figure 53-55. i 2 s clocking functional description k60 sub-family reference manual, rev. 6, nov 2011 1734 freescale semiconductor, inc. 53.4.2.1 i 2 s clock and frame sync generation data clock and frame sync signals can be generated internally, or can be obtained from external sources. if internally generated, the i 2 s clock generator is used to derive bit clock and frame sync signals from the network clock . the i 2 s clock generator consists of a selectable, fixed prescaler and a programmable prescaler for bit rate clock generation. in gated clock mode, the data clock is valid only when data is being transmitted. otherwise the clock port is pulled to the inactive state. a programmable frame rate divider and a word length divider are used for frame rate sync signal generation. the following figure shows a block diagram of the clock generator for the transmit section. the serial bit clock can be internal or external, depending on the tcr[txdir] bit. the receive section contains an equivalent clock generator circuit. prescaler (/1 or /8) divider (/1 to /256) txdir(0=input) txdir(1=output) wl[3:0] pm[7:0] stck txdir sysclken divider (/1 or /2) divide by 2 word clock txdir(1=output) network clock network clock (srck) serial bit clock word length divider psrdiv2 figure 53-56. i 2 s transmit clock generator block diagram the following figure shows the frame sync generator block for the transmit section. when internally generated, both receive and transmit frame sync are generated from the word clock and are defined by the frame rate divider (dc) bits and the word length (wl) bits of the tccr. the receive section contains an equivalent circuit for the frame sync generator. chapter 53 integrated interchip sound (i2s) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1735 dc[4:0] frame sync tfsl tx control tfsi stfs tx frame sync in word clock tfdir(0=input) frame tfdir(1=output) tx frame sync out tfsi rate figure 53-57. i 2 s transmit frame sync generator block diagram 53.4.2.2 div2, psr and pm bits description the bit clock frequency can be calculated from the i 2 s serial system clock using id-73884 . note you must ensure that the bit-clock frequency must be 5 times the peripheral clock frequency. the oversampling clock frequency can go up to peripheral clock frequency. bits div2, psr and pm must not be cleared at the same time. i s 2 from this, the frame clock frequency can be calculated: figure 53-58. i 2 s bit clock equation for example, if the i 2 s oversampling clock (network clock) is 12.288 mhz, in 8-bit word normal mode with dc = 1, pm = 47, psr = 0, div2 = 1, a bit clock rate of 64 khz is generated. since the 8-bit word rate is equal to one (i.e. normal mode), the sampling rate (or frame sync rate) would then be 64/(18) = 8 khz. functional description k60 sub-family reference manual, rev. 6, nov 2011 1736 freescale semiconductor, inc. in the next example, the oversampling clock (network clock) clock is 11.2896 mhz. a 16-bit word network mode with tccr[dc] = 1, tccr[pm] = 3, tccr[psr] = 0, tccr[div2] = 0, a bit clock rate of 1.4112 mhz is generated. since the 16-bit word rate is equal to two, the sampling rate (or frame sync rate) would be 1.4112/(216) = 44.1 khz. the following table shows examples of programming the tccr[psr] and tccr[pm] bits to generate various bit clock (stck) frequencies. table 53-51. i 2 s bit clock and frame rate as a function of psr, pm, and div2 bits/ word words/ frame mclk/network clock freq (mhz) tccr bit clock (khz) stck frame rate (khz) div2 psr pm wl dc 16 1 12.288 0 0 47 7 0 128 8 16 2 12.288 0 0 23 7 1 256 8 16 4 12.288 0 0 11 7 3 512 8 16 1 12.288 0 0 31 7 0 192 12 16 2 12.288 0 0 15 7 1 384 12 16 4 12.288 0 0 7 7 3 768 12 16 1 12.288 0 0 23 7 0 256 16 16 2 12.288 0 0 11 7 1 512 16 16 4 12.288 0 0 5 7 3 1024 16 16 1 12.288 0 0 15 7 0 384 24 16 2 12.288 0 0 7 7 1 768 24 16 4 12.288 0 0 3 7 3 1536 24 16 1 12.288 0 0 11 7 0 512 32 16 2 12.288 0 0 5 7 1 1024 32 16 4 12.288 0 0 2 7 3 2048 32 16 1 12.288 0 0 15 7 0 768 48 16 2 12.288 0 0 3 7 1 1536 48 16 4 12.288 0 0 1 7 3 3072 48 16 1 11.2896 0 0 31 7 0 176.4 11.025 16 2 11.2896 0 0 15 7 1 352.8 11.025 16 4 11.2896 0 0 7 7 3 705.6 11.025 16 1 11.2896 0 0 15 7 0 352.8 22.05 16 2 11.2896 0 0 7 7 1 705.6 22.05 16 4 11.2896 0 0 3 7 3 1411.2 22.05 table continues on the next page... chapter integrated interchip sound i2s 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 177 table 53-51. i 2 s bit clock and frame rate as a function of psr, pm, and div2 (continued) bits/ word words/ frame mclk/network clock freq (mhz) tccr bit clock (khz) stck frame rate (khz) div2 psr pm wl dc 16 1 11.2896 0 0 7 7 0 705.6 44.1 16 2 11.2896 0 0 3 7 1 1411.2 44.1 16 4 11.2896 0 0 1 7 3 2822.4 44.1 the table below shows an example of programming clock controller divider ratios to generate the appropriate oversampling clock and peripheral clock frequencies for various sampling rates. in these examples, the master mode is selected either by setting i 2 s master bit (cr[i2smode] = 01b) or individually programming the i 2 s in network, synchronous, transmit internal mode. (the table specifically illustrates the i 2 s mode frequencies/sample rates). the oversampling clock is network clock. i 2 s master mode requires a 32-bit word length, regardless of the actual data type. consequently, the fixed i 2 s frame rate of 64 bits per frame (word length (tccr[wl]) can be any value) and tccr[dc] = 1 are assumed. table 53-52. i 2 s system clock, bit clock, frame clock in master mode sampling/frame rate (khz) over- sampling rate mclk/network clock freq (mhz) tccr bit clk (khz) stck div2 ps r pm 44.10 384 16.934 0 0 2 2822.33 22.05 384 16.934 0 0 5 1411.17 11.025 384 16.934 0 0 11 705.58 48.00 256 12.288 0 0 1 3072 53.4.3 external frame and clock operation when applying external frame sync and clock signals to i 2 s, there should be at least four bit-clock cycles between the enabling of the transmit or receive section and the rising edge of the corresponding frame sync signal. the transition of tfs or rfs should be synchronized with the rising edge of external clock signal, stck or srck. functional description k60 sub-family reference manual, rev. 6, nov 2011 1738 freescale semiconductor, inc. 53.4.3.1 supported data alignment formats the i 2 s supports three data formats to provide flexibility with handling data. these formats dictate how data is written to (and read from) the data registers. therefore, data can appear in different places in tx0/1 and rx0/1 based on the data format and the number of bits per word. independent data formats are supported for both the transmitter and receiver (that is, the transmitter and receiver can use different data formats). the supported data formats are: ? msb alignment ? lsb alignment ? zero-extended (receive data only) ? sign-extended (receive data only) with msb alignment, the most significant byte is bits 31 through 24 of the data register if the word length is larger than or equal to 16 bits. if the word length is less than 16 bits and msb alignment is chosen, the most significant byte is bits 15C8. with lsb alignment, the least significant byte is bits 7C0. data alignment is controlled by the tcr[txbit0] bit and the rcr[rxbit0] bit. see the following table for the bit assignment for all the data formats supported by the i 2 s. table 53-53. data alignment format bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8-bit lsb aligned 7:0 8-bit msb aligned 7:0 10-bit lsb aligned 9:0 10-bit msb aligned 9:0 12-bit lsb aligned 11:0 12-bit msb aligned 11:0 16-bit lsb aligned 15:0 16-bit msb aligned 15:0 18-bit lsb aligned 17:0 18-bit msb aligned 17:0 20-bit lsb aligned 19:0 20-bit msb aligned 19:0 22-bit lsb aligned 21:0 22-bit msb aligned 21:0 table continues on the next page... chapter integrated interchip sound i2s 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 17 table 53-53. data alignment (continued) 24-bit lsb aligned 23:0 24-bit msb aligned 23:0 in addition, if lsb alignment is selected, the receive data can be zero-extended or sign- extended. ? in zero-extension, all bits above the most significant bit are 0s. this format is useful when data is stored in a pure integer format. ? in sign-extension, all bits above the most significant bit are equal to the most significant bit. this format is useful when data is stored in a fixed-point integer format (which implies fractional values). the rcr[rxext] bit controls receive data extension. transmit data used with lsb alignment has no concept of sign/zero-extension. unused bits above the most significant bit are simply ignored. when configured in i 2 s or ac97 mode, the i 2 s forces the selection of lsb alignment. however, rxext chooses zero-extension and sign-extension. 53.4.4 receive interrupt enable bit description if the receive fifo is not enabled and the ier[rie] and cr[re] bits are set: ? an interrupt occurs when the corresponding i 2 s receive data ready (isr[rdr0/1]) bit is set ? one value can be read from the rx register (one each in two-channel mode) if the receive fifo is enabled and the ier[rie] and cr[re] bits are set: ? an interrupt occurs when either of the i 2 s receive fifo full (isr[rff0/1) bits is set ? a maximum of 15 values are available to be read (15 values per channel in two- channel mode) if the ier[rie] bit is cleared, these interrupts are disabled. however, the rff0/1 and rdr0/1 bits indicate the receive data register full condition. reading the rx registers clears the isr[rdr] bits, thus clearing the pending interrupt. two receive data interrupts (two per channel in two-channel mode) are available: receive data with exception status and receive data without exception. the following table shows the conditions under which these interrupts are generated. functional description k60 sub-family reference manual, rev. 6, nov 2011 1740 freescale semiconductor, inc. table 53-54. i 2 s receive data interrupts interrupt rie roe n rff n rr n receie ata interruts n receie ata with excetion status receie ata without excetion receie ata interruts n receie ata with excetion status receie ata without excetion ransit interrut enale it escrition if the transmit fifo is not enabled and the ier[tie] and cr[te] bits are set: ? an interrupt occurs when the corresponding i 2 s transmit data register empty (isr[tde0/1]) flag is set ? one value can be written to the i 2 s_tx0 register (one per channel, in two-channel mode using i 2 s_tx1) if the transmit fifo is enabled and the ier[tie] and cr[te] bits are set: ? an interrupt occurs when either of the i 2 s transmit fifo empty (isr[tfe0/1]) flags is set ? a maximum of 15 values can be written to the i 2 s ( 15 per channel in two-channel mode, using tx fifo 1) when the ier[tie] bit is cleared, all transmit interrupts are disabled. however, the isr[tde0/1] bits always indicate the corresponding tx register empty condition, even when the transmitter is disabled by the transmit enable (cr[te]) bit. writing data to the tx clears the corresponding isr[tde] bit, thus clearing the interrupt. two transmit data interrupts are available (four in two-channel mode, two per channel): transmit data with exception status and transmit data without exceptions. the following table shows the conditions under which these interrupts are generated. table 53-55. i 2 s transmit data interrupts interrupt tie tue n f n n ransit ata interruts n ransit ata with excetion status table continues on the next page... chapter integrated interchip sound i2s 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1741 table 53-55. i 2 s transmit data interrupts (continued) interrupt tie tue n f n n ransit ata without excetion ransit ata interruts n ransit ata with excetion status ransit ata without excetion nternal rae an cloc shutown during transmit/receive operation, clearing te/re stops data transmission/reception when the current frame ends. if the cr[tfrclkdis, rfrclkdis] bit is set in the current or previous frames, the i 2 s stops driving the frame sync and clock signals when the current frame ends. after this, the tcrtfrc]] and tcr[rfrc] status bits are set to indicate the frame completion state. if te is cleared four clock cycles before the next frame, an extra invalid frame is generated. the following figure is an illustration of transmission case where: ? tcr[txdir] and tcr[tfdir] are set ? cr[te] is cleared ? cr[tfrclkdis] is set during the current or previous frame clk fs tx data cr[te] cr[tfrclkdis] isr[tfrc] figure 53-59. cr[tfrclkdis] assertion in current or previous frame as cr[te] is disabled if cr[tfrclkdis or rfrclkdis] bit is not set while cr[te or re] is cleared, the i 2 s continues generating frame sync and clock signals (if direction is from the i 2 s), upun setting cr[tfrclkdis or rfrclkdis], the i 2 s stops driving these signals at the end of the current frame. following this, the tfrc/rfrc status bits are set to indicate the frame completion state. functional description k60 sub-family reference manual, rev. 6, nov 2011 1742 freescale semiconductor, inc. the following figure is illustrates a transmission case where: ? tcr[txdir] and tcr[tfdir] are set ? cr[tfrclkdis] is set a few frames after clearing cr[te] ? isr[trfc] is set at the frame boundary after cr[te] is cleared. once software services this interrupt and later sets cr[tfrclkdis] bit, the isr[trfc] bit is set again at next frame boundary. clk fs tx data cr[te] cr[tfcldis] isr[tfrc] w1c figure 53-60. cr[tfrclkdis] assertion in subsequent frame after disabling cr[te] 53.4.7 reset the i 2 s is affected by the following types of reset: ? power-on resetthis reset clears the cr[i2sen] bit, which disables the i 2 s. all other status and control bits in the i 2 s are affected as described in memory map/ register definition . ? i 2 s resetthe i 2 s reset is generated when the cr[i2sen] bit is cleared. the i 2 s status bits are reset to the same state produced by the power-on reset. the i 2 s control bits, including those in cr register, are unaffected. the i 2 s reset is useful for selective reset of the i 2 s, without changing the present i 2 s control bits and without affecting other peripherals. 53.5 initialization/application information the correct sequence to initialize the i 2 s is as follows: 1. issue a power-on or i 2 s reset (cr[i2sen] = 0). chapter 53 integrated interchip sound (i2s) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1743 2. set all control bits for configuring the i 2 s (see the following table ). 3. enable appropriate interrupts/dma requests through ier. 4. set the cr[i2sen] bit to enable the i 2 s. 5. in ac97 mode, set the acnt[ac97en] bit after programming the atag register (if needed, for ac97 fixed mode). 6. in ac97 fixed mode, do not program the slot request bits without programming the frame valid bits in atag register. 7. in gated clock mode, refer to table 53-3 . 8. set cr[te/re] bits. to ensure proper operation of the i 2 s, use the power-on or i 2 s reset before changing any of the i 2 s control bits listed in the following table. note these control bits should not be changed when the i 2 s module is enabled table 53-56. i 2 s control bits requiring i 2 s to be disabled before change control register bit cr [9]=clkist [8]=tchen [7]=sysclken [6:5]=i2smode [4]=syn [3]=net ier [22]=rdmae [20]=tdmae table continues on the next page... initializationapplication information 60 sub-family reference manual, rev. 6, nov 2011 1744 freescale semiconductor, inc. table 53-56. i 2 s control bits requiring i 2 s to be disabled before change (continued) control register bit rcr tcr [9]=rxbit0 [9]=txbit0 [8]=rfen1 [8]=tfen1 [7]=rfen0 [7]=tfen0 [6]=rfdir [6]=tfdir [5]=rxdir [5]=txdir [4]=rshfd [4]=tshfd [3]=rsckp [3]=tsckp [2]=rfsi [2]=tfsi [1]=rfsl [1]=tfsl [0]=refs [0]=tefs rccr tccr [16]=wl3 [15]=wl2 [14]=wl1 [13]=wl0 acnt [1]=fv [10:5]=frdiv phconfig [10:7]=clksrcsel [0:2]=gainsel chapter 53 integrated interchip sound (i2s) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1745 initialization/application information k60 sub-family reference manual, rev. 6, nov 2011 1746 freescale semiconductor, inc. chapter 54 general purpose input/output (gpio) 54.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the general purpose input and output (gpio) module interfaces to the processor core via a zero wait state interface for maximum pin performance. accesses of any data size are supported to the gpio registers. the gpio data direction and output data registers control the direction and output data of each pin when the pin is configured for the gpio function. the gpio input data register displays the logic value on each pin when the pin is configured for any digital function, provided the corresponding port control and interrupt module for that pin is enabled. efficient bit banging of the general purpose outputs is supported through the addition of set, clear and toggle write-only registers for each port output data register. 54.1.1 features ? rapid general purpose input and output ? pin input data register visible in all digital pin-muxing modes ? pin output data register with corresponding set/clear/toggle registers ? pin data direction register ? zero wait state access to gpio registers 54.1.2 modes of operation k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1747 54.1.2.1 run mode in run mode, the gpio operates normally. 54.1.2.2 wait mode in wait mode, the gpio operates normally. 54.1.2.3 stop mode the gpio is disabled in stop mode, although the pins retain their state. 54.1.2.4 debug mode in debug mode, the gpio operates normally. 54.1.3 gpio signal descriptions table 54-1. gpio signal descriptions signal description i/o porta[31:0] general purpose input/output i/o portb[31:0] general purpose input/output i/o portc[31:0] general purpose input/output i/o portd[31:0] general purpose input/output i/o porte[31:0] general purpose input/output i/o note not all pins within each port are implemented on each device. refer to the signal multiplexing chapter for the number of gpio ports available in the device. introduction k60 sub-family reference manual, rev. 6, nov 2011 1748 freescale semiconductor, inc. 54.1.3.1 detailed signal description table 54-2. gpio interface-detailed signal descriptions signal i/o description porta[31:0] portb[31:0] portc[31:0] portd[31:0] porte[31:0] i/o general purpose input/output. state meaning asserted - pin is logic one. negated - pin is logic zero. timing assertion - when output, occurs on rising edge of the system clock. for input, may occur at any time and input may be asserted asynchronously to the system clock. negation - when output, occurs on rising edge of the system clock. for input, may occur at any time and input may be asserted asynchronously to the system clock. 54.2 memory map and register definition any read or write access to the gpio memory space that is outside the valid memory map results in a bus error. all register accesses complete with zero wait states, except error accesses which complete with one wait state. gpio memory map absolute address (hex) register name width (in bits) access reset value section/ page 400f_f000 port data output register (gpioa_pdor) 32 r/w 0000_0000h 54.2.1/ 1752 400f_f004 port set output register (gpioa_psor) 32 w (always reads zero) 0000_0000h 54.2.2/ 1752 400f_f008 port clear output register (gpioa_pcor) 32 w (always reads zero) 0000_0000h 54.2.3/ 1753 400f_f00c port toggle output register (gpioa_ptor) 32 w (always 0000_0000h 54.2.4/ 1753 table continues on the next page... chapter 4 eneral purpose inputoutput pi 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 174 gpio memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page reads zero) 400f_f010 port data input register (gpioa_pdir) 32 r 0000_0000h 54.2.5/ 1754 400f_f014 port data direction register (gpioa_pddr) 32 r/w 0000_0000h 54.2.6/ 1754 400f_f040 port data output register (gpiob_pdor) 32 r/w 0000_0000h 54.2.1/ 1752 400f_f044 port set output register (gpiob_psor) 32 w (always reads zero) 0000_0000h 54.2.2/ 1752 400f_f048 port clear output register (gpiob_pcor) 32 w (always reads zero) 0000_0000h 54.2.3/ 1753 400f_f04c port toggle output register (gpiob_ptor) 32 w (always reads zero) 0000_0000h 54.2.4/ 1753 400f_f050 port data input register (gpiob_pdir) 32 r 0000_0000h 54.2.5/ 1754 400f_f054 port data direction register (gpiob_pddr) 32 r/w 0000_0000h 54.2.6/ 1754 400f_f080 port data output register (gpioc_pdor) 32 r/w 0000_0000h 54.2.1/ 1752 400f_f084 port set output register (gpioc_psor) 32 w (always reads zero) 0000_0000h 54.2.2/ 1752 400f_f088 port clear output register (gpioc_pcor) 32 w (always reads zero) 0000_0000h 54.2.3/ 1753 400f_f08c port toggle output register (gpioc_ptor) 32 w (always reads zero) 0000_0000h 54.2.4/ 1753 400f_f090 port data input register (gpioc_pdir) 32 r 0000_0000h 54.2.5/ 1754 400f_f094 port data direction register (gpioc_pddr) 32 r/w 0000_0000h 54.2.6/ 1754 400f_f0c0 port data output register (gpiod_pdor) 32 r/w 0000_0000h 54.2.1/ 1752 table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 170 freescale semiconductor, inc. gpio memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 400f_f0c4 port set output register (gpiod_psor) 32 w (always reads zero) 0000_0000h 54.2.2/ 1752 400f_f0c8 port clear output register (gpiod_pcor) 32 w (always reads zero) 0000_0000h 54.2.3/ 1753 400f_f0cc port toggle output register (gpiod_ptor) 32 w (always reads zero) 0000_0000h 54.2.4/ 1753 400f_f0d0 port data input register (gpiod_pdir) 32 r 0000_0000h 54.2.5/ 1754 400f_f0d4 port data direction register (gpiod_pddr) 32 r/w 0000_0000h 54.2.6/ 1754 400f_f100 port data output register (gpioe_pdor) 32 r/w 0000_0000h 54.2.1/ 1752 400f_f104 port set output register (gpioe_psor) 32 w (always reads zero) 0000_0000h 54.2.2/ 1752 400f_f108 port clear output register (gpioe_pcor) 32 w (always reads zero) 0000_0000h 54.2.3/ 1753 400f_f10c port toggle output register (gpioe_ptor) 32 w (always reads zero) 0000_0000h 54.2.4/ 1753 400f_f110 port data input register (gpioe_pdir) 32 r 0000_0000h 54.2.5/ 1754 400f_f114 port data direction register (gpioe_pddr) 32 r/w 0000_0000h 54.2.6/ 1754 chapter 54 general purpose input/output (gpio) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1751 54.2.1 port data output register (gpio x or resses: oor is ffh ase h oset ffh oor is ffh ase h oset ffh oor is ffh ase h oset ffh oor is ffh ase h oset ffh oor is ffh ase h oset ffh it r o reset o x or iel escritions fiel escrition o ort ata outut unileente ins or a articular eice rea as ero loic leel is rien on in roie in is coniure or eneral urose outut loic leel is rien on in roie in is coniure or eneral urose outut ort et outut reister o x or resses: oor is ffh ase h oset ffh oor is ffh ase h oset ffh oor is ffh ase h oset ffh oor is ffh ase h oset ffh oor is ffh ase h oset ffh it r o reset o x or iel escritions fiel escrition o ort et outut ritin to this reister will uate the contents o the corresonin it in the ort ata outut reister or as ollows: orresonin it in orn oes not chane orresonin it in orn is set to loic one eory a an reister einition ufaily reerence anual re o freescale eiconuctor nc 54.2.3 port clear output register (gpio x or resses: oor is ffh ase h oset ffh oor is ffh ase h oset ffh oor is ffh ase h oset ffh oor is ffh ase h oset ffh oor is ffh ase h oset ffh it r o reset o x or iel escritions fiel escrition o ort lear outut ritin to this reister will uate the contents o the corresonin it in the ort ata outut reister or as ollows: orresonin it in orn oes not chane orresonin it in orn is set to loic ero ort ole outut reister o x or resses: oor is ffh ase h oset ffh oor is ffh ase h oset ffh oor is ffh ase h oset ffh oor is ffh ase h oset ffh oor is ffh ase h oset ffh it r o reset o x or iel escritions fiel escrition o ort ole outut ritin to this reister will uate the contents o the corresonin it in the ort ata outut reister or as ollows: hater eneral urose inutoutut o ufaily reerence anual re o freescale eiconuctor nc gpio x or iel escritions continue fiel escrition orresonin it in orn oes not chane orresonin it in orn is set to the inerse o its existin loic state ort ata nut reister o x r resses: or is ffh ase h oset ffh or is ffh ase h oset ffh or is ffh ase h oset ffh or is ffh ase h oset ffh or is ffh ase h oset ffh it r reset o x r iel escritions fiel escrition ort ata nut unileente ins or a articular eice rea as ero ins that are not coniure or a iital unction rea as ero the corresonin ort ontrol an nterrut oule is isale then that ort ata nut reister oes not uate in loic leel is loic ero or is coniure or use y iital unction in loic leel is loic one ort ata irection reister o x r the pddr configures the individual port pins for input or output. addresses: gpioa_pddr is 400f_f000h base + 14h offset = 400f_f014h gpiob_pddr is 400f_f040h base + 14h offset = 400f_f054h gpioc_pddr is 400f_f080h base + 14h offset = 400f_f094h gpiod_pddr is 400f_f0c0h base + 14h offset = 400f_f0d4h gpioe_pddr is 400f_f100h base + 14h offset = 400f_f114h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r pdd w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 memory map and register definition k60 sub-family reference manual, rev. 6, nov 2011 1754 freescale semiconductor, inc. gpio x r iel escritions fiel escrition ort ata irection in is coniure as eneral urose inut i coniure or the o unction in is coniure or eneral urose outut i coniure or the o unction functional escrition eneral urose inut the logic state of each pin is available via the pin data input registers, provided the pin is configured for a digital function and the corresponding port control and interrupt module is enabled. the pin data input registers return the synchronized pin state after any enabled digital filter in the port control and interrupt module. the input pin synchronizers are shared with the port control and interrupt module, so that if the corresponding port control and interrupt module is disabled then synchronizers are also disabled. this reduces power consumption when a port is not required for general purpose input functionality. 54.3.2 general purpose output the logic state of each pin can be controlled via the pin data output registers and pin output enable registers, provided the pin is configured for the gpio function. if a pin is configured for the gpio function and the corresponding data output enable register bit is clear then the pin is configured as an input. if a pin is configured for the gpio function and the corresponding pin data output enable register bit is set then the pin is configured as an output and the logic state of the pin is equal to the corresponding pin data output register. to facilitate efficient bit banging on the general purpose outputs, pin data set, pin data clear and pin data toggle registers exist to allow one or more outputs within the one port to be set, cleared or toggled from a single register write. the corresponding port control and interrupt module does not need to be enabled to update the state of the pin output enable registers and pin data output registers (including the set/clear/toggle registers). chapter 54 general purpose input/output (gpio) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1755 functional description k60 sub-family reference manual, rev. 6, nov 2011 1756 freescale semiconductor, inc. chapter 55 touch sense input (tsi) 55.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the touch sensing input (tsi) module provides capacitive touch sensing detection with high sensitivity and enhanced robustness. each tsi pin implements the capacitive measurement of an electrode having individual programmable detection thresholds and result registers. the tsi module can be functional in several low power modes with ultra low current adder and waking up the cpu in a touch event. it provides a solid capacitive measurement module for the implementation of touch keypad, rotaries and sliders. 55.2 features ? support as many as 16 input capacitive touch sensing pins with individual result registers ? automatic detection of electrode capacitance change with programmable upper and lower threshold ? automatic periodic scan unit with different duty cycles for run and low power modes ? full support with fsl touch sensing sw library (tss) for the implementation of keypads, rotaries and sliders ? operation across all low power modes: wait,stop, vlpr, vlpw, vlps, lls,vlls{3,2,1} ? capability to wake up mcu from low power modes ? configurable interrupts: ? end-of-scan or out-of-range interrupt ? tsi error interrupts: pad short to v dd /v ss or conversion overrun ? compensate temperature and supply voltage variations ? stand alone operation not requiring any external crystal even in low power modes k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1757 ? configurable integration of each electrode capacitance measurement from 1 to 4096 times ? programmable electrode oscillator and tsi reference oscillator for high sensitivity, small scan time and low power functionality ? only uses one pin per electrode implementation with no external hardware required 55.3 overview this section presents an overview of the tsi module. the following figure presents the simplified tsi module block diagram. external electrodes cap switch pad0 pad1 pad15 capacitance measurement unit nscn ps extchrg delvol refchrg tsichncnt stpe stm electrode scan unit eosf pen [15:0] ovrf smod lpscnitv touch detection unit tsichnlth tsichnhth exterf outrgf touch sensing input (tsi) module figure 55-1. touch sensing input block diagram 55.3.1 electrode capacitance measurement unit the electrode capacitance measurement unit senses the capacitance of a tsi pin and outputs a 16-bit result. this module is based in dual oscillator architecture. one oscillator is connected to the external electrode array and oscillates according to the electrode overview k60 sub-family reference manual, rev. 6, nov 2011 1758 freescale semiconductor, inc. capacitance, while the other according to an internal reference capacitor. the pin capacitance measurement is given by the counted number of periods of the reference oscillator during a configurable number of oscillations of the external electrode oscillator. the electrode oscillator charges and discharges the pin capacitance with a programmable 5-bit binary current source in order to accommodate different sizes of electrode capacitance. the electrode oscillator frequency, before being compared to that of the reference oscillator, goes through a prescaler and modulo counter to decrease its frequency and consecutively increase the measurement resolution and noise robustness. the following figure presents the simplified block diagram of how the electrode capacitance is measured. tsi electrode oscillator nscn tsichncnt capacitance measurement unit prescaler counter modulo control tsi reference oscillator 16-bit counter extchrg delvol ps refchrg delvol electrode capacitance captrm clk en figure 55-2. tsi capacitance measurement unit block diagram 55.3.2 electrode scan unit this section describes the functionality of the electrode scan unit. it is responsible for triggering the start of the active electrode scan. the touch sense input module needs to periodically scan all active electrodes to determine if a touch event has occurred. the electrode scan unit has two independent scan periods, one for tsi active mode and the other for tsi low power mode. this independent control allows the application to configure longer scan period during low power mode, so contributing to smaller average power consumption. the tsi, in low power mode, has the capability to wake the cpu upon an electrode capacitance change. when the cpu wakes, the tsi enters active mode, and produces a shorter scan period for a faster response and more robust touch detection. apart from the periodical mode, the chapter 55 touch sense input (tsi) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1759 electrode scan unit also allows software triggering of the electrode scans. this feature is very useful for initialization of the touch application to detect the initial electrode capacitances. this module generates configurable end-of-scan interrupt to indicate the application that all electrodes were scanned. if a new electrode scan is started while the previous one is still in progress, an overrun error flag is generated, tsi continues the previous scan sequence and the latest trigger is ignored. 55.3.3 touch detection unit the touch detection unit indicates the change in the pin capacitance. this module compares the pin capacitance value in the result register with a pre-configured low and high threshold. if the capacitance result register value is outside the ranges defined by the upper and lower threshold, the touch detection unit generates an out-of-range flag to indicate a pin capacitance change. the upper and lower threshold values are configurable allowing the application to select the magnitude of the capacitance change to trigger the out-of-range flag. with the threshold values programmed properly the application noise level does not cause frequent cpu interrupts, so minimizes the cpu touch application usage. this feature also allows the tsi to wake up the cpu from low power modes only in a capacitance change event. 55.4 modes of operation the tsi module has three operation modes: disabled, active mode and low power mode. 55.4.1 tsi disabled mode when gencs[tsien] is cleared, the tsi module is disabled. 55.4.2 tsi active mode in active mode, the tsi module has its full functionality, being able to scan up to 16 electrodes. the tsi can be in active mode with the mcu in run, wait, vlpr, and vlpw modes, and the tsi can run in low power mode (only one electrode scanning in stop, vlps, lls, and vllsx modes). three clock sources can be selected for the tsi module in active mode: bus_clk, mcgirclk and oscerclk. modes of operation k60 sub-family reference manual, rev. 6, nov 2011 1760 freescale semiconductor, inc. 55.4.3 tsi low power mode the tsi module enters low power mode if the gencs[stpe] is set to one and the mcu is programmed into one of the following operational modes: lls, vlls1, vlls2 or vlls3. in low power mode, only one selectable pin is active, being able to perform capacitance measurements. the scan period is defined by gencs[lpscnitv]. two low power clock sources are available in the tsi low power mode, lpoclk and vlposcclk, being selected by the gencs[lpclks]. in low power mode the tsi interrupt can also be configured as end-of-scan or out-of- range and the gencs[tsiien] must be set in order to generate these interrupts. the tsi interrupt causes the exit of the low power mode, entrance into the active mode, and the mcu wake up. in low power mode the electrode scan unit is always configured to periodical low power scan. 55.4.4 block diagram the following figure shows the block diagram of tsi module. cap switch pad0 pad1 pad15 tsi electrode oscillator nscn tsichncnt prescaler counter modulo control tsi reference oscillator 16-bit counter extchrg delvol ps refchrg delvol scan trigger channel polling fsm low power scan control stm stpe smod lpscnitv eosf pen[15:0] ovrf overrun interrupt end of scan interrupt lpoclk vlposcclk lls/vllsx modes bus clk mcgirclk oscerclk electrode scan unit 2 windowed comparators touch and error detection error interrupt exterf outrgf out of range interrupt tsichnhth tsichnlth touch detection unit capacitance measurement unit captrm figure 55-3. tsi block diagram chapter 55 touch sense input (tsi) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1761 55.5 tsi signal descriptions the tsi module has up to 16 external pins for touch sensing. the table below itemizes all the tsi external pins. table 55-1. tsi signal descriptions signal description i/o tsi_in[15:0] tsi pins. switchable driver that connects directly to the electrode pins tsi[15:0] can operate as gpio pins i/o 55.5.1 tsi_in[15:0] when tsi functionality is enabled by the pen[pen], the tsi analog portion uses corresponding tsichn to connect external on-board touch capacitors. the connection between the pin and the touch pad must be kept as short as possible to reduce distribution capacity on board that will add to the system base capacitance. 55.6 memory map and register definition this section presents the touch sensing input module memory map and registers definition. tsi memory map absolute address (hex) register name width (in bits) access reset value section/ page 4004_5000 general control and status register (tsi0_gencs) 32 r/w 0000_0000h 55.6.1/ 1764 4004_5004 scan control register (tsi0_scanc) 32 r/w 0000_0000h 55.6.2/ 1767 4004_5008 pin enable register (tsi0_pen) 32 r/w 0000_0000h 55.6.3/ 1770 4004_500c status register (tsi0_status) 32 w1c 0000_0000h 55.6.4/ 1773 4004_5100 counter register (tsi0_cntr1) 32 r 0000_0000h 55.6.5/ 1776 table continues on the next page... tsi signal descriptions 60 sub-family reference manual, rev. 6, nov 2011 1762 freescale semiconductor, inc. tsi memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4004_5104 counter register (tsi0_cntr3) 32 r 0000_0000h 55.6.5/ 1776 4004_5108 counter register (tsi0_cntr5) 32 r 0000_0000h 55.6.5/ 1776 4004_510c counter register (tsi0_cntr7) 32 r 0000_0000h 55.6.5/ 1776 4004_5110 counter register (tsi0_cntr9) 32 r 0000_0000h 55.6.5/ 1776 4004_5114 counter register (tsi0_cntr11) 32 r 0000_0000h 55.6.5/ 1776 4004_5118 counter register (tsi0_cntr13) 32 r 0000_0000h 55.6.5/ 1776 4004_511c counter register (tsi0_cntr15) 32 r 0000_0000h 55.6.5/ 1776 4004_5120 channel n threshold register (tsi0_threshld0) 32 r/w 0000_0000h 55.6.6/ 1777 4004_5124 channel n threshold register (tsi0_threshld1) 32 r/w 0000_0000h 55.6.6/ 1777 4004_5128 channel n threshold register (tsi0_threshld2) 32 r/w 0000_0000h 55.6.6/ 1777 4004_512c channel n threshold register (tsi0_threshld3) 32 r/w 0000_0000h 55.6.6/ 1777 4004_5130 channel n threshold register (tsi0_threshld4) 32 r/w 0000_0000h 55.6.6/ 1777 4004_5134 channel n threshold register (tsi0_threshld5) 32 r/w 0000_0000h 55.6.6/ 1777 4004_5138 channel n threshold register (tsi0_threshld6) 32 r/w 0000_0000h 55.6.6/ 1777 4004_513c channel n threshold register (tsi0_threshld7) 32 r/w 0000_0000h 55.6.6/ 1777 4004_5140 channel n threshold register (tsi0_threshld8) 32 r/w 0000_0000h 55.6.6/ 1777 4004_5144 channel n threshold register (tsi0_threshld9) 32 r/w 0000_0000h 55.6.6/ 1777 4004_5148 channel n threshold register (tsi0_threshld10) 32 r/w 0000_0000h 55.6.6/ 1777 4004_514c channel n threshold register (tsi0_threshld11) 32 r/w 0000_0000h 55.6.6/ 1777 4004_5150 channel n threshold register (tsi0_threshld12) 32 r/w 0000_0000h 55.6.6/ 1777 table continues on the next page... chapter touch sense input tsi 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 176 tsi memory map (continued) absolute address (hex) register name width (in bits) access reset value section/ page 4004_5154 channel n threshold register (tsi0_threshld13) 32 r/w 0000_0000h 55.6.6/ 1777 4004_5158 channel n threshold register (tsi0_threshld14) 32 r/w 0000_0000h 55.6.6/ 1777 4004_515c channel n threshold register (tsi0_threshld15) 32 r/w 0000_0000h 55.6.6/ 1777 55.6.1 general control and status register (tsi x all gencs bits can be read at any time, but must not be written while gencs[scnip] is set. addresses: tsi0_gencs is 4004_5000h base + 0h offset = 4004_5000h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r reserved 0 lpclks lpscnitv nscn ps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r eosf outrgf exterf ovrf 0 scnip tsien tsiie erie esor reserved reserved stm stpe w w1c w1c w1c w1c swts reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tsi x iel escritions fiel escrition resere resere his iel is resere resere his reaonly iel is resere an always has the alue ero ll low ower oe loc ource election table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 1764 freescale semiconductor, inc. tsi x iel escritions continue fiel escrition lol lol l low ower oe can nteral s scan interal s scan interal s scan interal s scan interal s scan interal s scan interal s scan interal s scan interal s scan interal s scan interal s scan interal s scan interal s scan interal s scan interal s scan interal s scan interal uer o onsecutie cans er lectroe tie er electroe ties er electroe ties er electroe ties er electroe ties er electroe ties er electroe ties er electroe ties er electroe ties er electroe ties er electroe ties er electroe ties er electroe ties er electroe ties er electroe ties er electroe ties er electroe ties er electroe ties er electroe ties er electroe ties er electroe ties er electroe ties er electroe ties er electroe ties er electroe ties er electroe table continues on the next page... chapter touch sense input tsi 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 176 tsi x iel escritions continue fiel escrition ties er electroe ties er electroe ties er electroe ties er electroe ties er electroe ties er electroe ties er electroe lectroe oscillator rescaler lectroe oscillator requency iie y lectroe oscillator requency iie y lectroe oscillator requency iie y lectroe oscillator requency iie y lectroe oscillator requency iie y lectroe oscillator requency iie y lectroe oscillator requency iie y lectroe oscillator requency iie y of n o scan la rite to clear the la ourf out o rane fla rite to clear the la rf xternal electroe error occurre o short hort to or occure on the electroes orf oerrun error la o oerrun oerrun occurre resere his reaonly iel is resere an always has the alue ero caninroress status nicates i a scannin rocess is in roress his it is reaonly an is chane autoatically y the oule otware trier start ettin this it starts a scan sequence ritin ero to this it has no eect oule enale isale enale interrut enale table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 1766 freescale semiconductor, inc. tsi x iel escritions continue fiel escrition isale nale r error interrut nale ause y a short or oerrun error rror interrut isale rror interrut enale or noscan or outorane interrut select outorane interrut selecte noscan interrut selecte resere resere his iel is resere resere resere his iel is resere can trier oe otware trier scan erioical scan sto enale while in lowower oes o l ll an ll isale when u enters lowower oes llow to continue runnin in all low ower oes control reister x all scanc bits can be read at any time, but must not be written while gencs[scnip] is set. addresses: tsi0_scanc is 4004_5000h base + 4h offset = 4004_5004h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r refchrg captrm extchrg delvol w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r smod 0 amclkdiv amclks ampsc w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 chapter 55 touch sense input (tsi) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1767 tsi x iel escritions fiel escrition rfhr reerence oscillator chare current select chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current r nternal caacitance tri alue f internal reerence caacitance f internal reerence caacitance f internal reerence caacitance f internal reerence caacitance f internal reerence caacitance f internal reerence caacitance f internal reerence caacitance f internal reerence caacitance hr xternal oscillator chare current select chare current table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 1768 freescale semiconductor, inc. tsi x iel escritions continue fiel escrition chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current chare current lol elta oltae select alie to analo oscillators elta oltae is alie elta oltae is alie elta oltae is alie elta oltae is alie elta oltae is alie elta oltae is alie elta oltae is alie elta oltae is alie o can oulo ontinuous scan others can erio oulo resere his reaonly iel is resere an always has the alue ero table continues on the next page... chapter touch sense input tsi 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 176 tsi x iel escritions continue fiel escrition l ctie oe cloc iier iier set to iier set to l ctie oe cloc source us loc rl orl ot ali ctie oe rescaler nut cloc source iie y nut cloc source iie y nut cloc source iie y nut cloc source iie y nut cloc source iie y nut cloc source iie y nut cloc source iie y nut cloc source iie y in enale reister x o do not change pen when gencs[tsien] is set. note all pen bits can be read at any time, but must not be written while gencs[scnip] is set. addresses: tsi0_pen is 4004_5000h base + 8h offset = 4004_5008h bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 lpsp pen15 pen14 pen13 pen12 pen11 pen10 pen9 pen8 pen7 pen6 pen5 pen4 pen3 pen2 pen1 pen0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tsi x iel escritions fiel escrition resere his reaonly iel is resere an always has the alue ero l lowower scan in table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 1770 freescale semiconductor, inc. tsi x iel escritions continue fiel escrition elects which inut is actie in lowower oe is actie in low ower oe is actie in low ower oe is actie in low ower oe is actie in low ower oe is actie in low ower oe is actie in low ower oe is actie in low ower oe is actie in low ower oe is actie in low ower oe is actie in low ower oe is actie in low ower oe is actie in low ower oe is actie in low ower oe is actie in low ower oe is actie in low ower oe is actie in low ower oe in enale he corresonin in is not use y he corresonin in is use y in enale he corresonin in is not use y he corresonin in is use y in enale he corresonin in is not use y he corresonin in is use y in enale he corresonin in is not use y he corresonin in is use y in enale he corresonin in is not use y he corresonin in is use y in enale he corresonin in is not use y he corresonin in is use y in enale he corresonin in is not use y he corresonin in is use y table continues on the next page... chapter touch sense input tsi 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1771 tsi x iel escritions continue fiel escrition in enale he corresonin in is not use y he corresonin in is use y in enale he corresonin in is not use y he corresonin in is use y in enale he corresonin in is not use y he corresonin in is use y in enale he corresonin in is not use y he corresonin in is use y in enale he corresonin in is not use y he corresonin in is use y in enale he corresonin in is not use y he corresonin in is use y in enale he corresonin in is not use y he corresonin in is use y in enale he corresonin in is not use y he corresonin in is use y in enale he corresonin in is not use y he corresonin in is use y eory a an reister einition ufaily reerence anual re o freescale eiconuctor nc 55.6.4 status register (tsi x u resses: u is h ase h oset h it r rrof rrof rrof rrof rrof rrof rrof rrof rrof rrof rrof rrof rrof rrof rrof rrof wc wc wc wc wc wc wc wc wc wc wc wc wc wc wc wc reset it r orf orf orf orf orf orf orf orf orf orf orf orf orf orf orf orf wc wc wc wc wc wc wc wc wc wc wc wc wc wc wc wc reset x u iel escritions fiel escrition rrof ouchensin rror fla his it inicates when the corresonin electroe is shorte to or the r it is set an error interrut is enerate rite a one to clear this it rrof ouchensin rror fla his it inicates when the corresonin electroe is shorte to or the r it is set an error interrut is enerate rite a one to clear this it rrof ouchensin rror fla his it inicates when the corresonin electroe is shorte to or the r it is set an error interrut is enerate rite a one to clear this it rrof ouchensin rror fla his it inicates when the corresonin electroe is shorte to or the r it is set an error interrut is enerate rite a one to clear this it rrof ouchensin rror fla his it inicates when the corresonin electroe is shorte to or the r it is set an error interrut is enerate rite a one to clear this it rrof ouchensin rror fla table continues on the next page... chapter touch sense input tsi 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 177 tsi x u iel escritions continue fiel escrition his it inicates when the corresonin electroe is shorte to or the r it is set an error interrut is enerate rite a one to clear this it rrof ouchensin rror fla his it inicates when the corresonin electroe is shorte to or the r it is set an error interrut is enerate rite a one to clear this it rrof ouchensin rror fla his it inicates when the corresonin electroe is shorte to or the r it is set an error interrut is enerate rite a one to clear this it rrof ouchensin rror fla his it inicates when the corresonin electroe is shorte to or the r it is set an error interrut is enerate rite a one to clear this it rrof ouchensin rror fla his it inicates when the corresonin electroe is shorte to or the r it is set an error interrut is enerate rite a one to clear this it rrof ouchensin rror fla his it inicates when the corresonin electroe is shorte to or the r it is set an error interrut is enerate rite a one to clear this it rrof ouchensin rror fla his it inicates when the corresonin electroe is shorte to or the r it is set an error interrut is enerate rite a one to clear this it rrof ouchensin rror fla his it inicates when the corresonin electroe is shorte to or the r it is set an error interrut is enerate rite a one to clear this it rrof ouchensin rror fla his it inicates when the corresonin electroe is shorte to or the r it is set an error interrut is enerate rite a one to clear this it rrof ouchensin rror fla his it inicates when the corresonin electroe is shorte to or the r it is set an error interrut is enerate rite a one to clear this it rrof ouchensin rror fla his it inicates when the corresonin electroe is shorte to or the r it is set an error interrut is enerate rite a one to clear this it orf ouch ensin lectroe outorane fla his it inicates when the corresonin electroe is out o rane the it is set an the or it is cleare an outorane interrut is enerate rite a one to clear this it orf ouch ensin lectroe outorane fla table continues on the next page... memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 1774 freescale semiconductor, inc. tsi x u iel escritions continue fiel escrition his it inicates when the corresonin electroe is out o rane the it is set an the or it is cleare an outorane interrut is enerate rite a one to clear this it orf ouch ensin lectroe outorane fla his it inicates when the corresonin electroe is out o rane the it is set an the or it is cleare an outorane interrut is enerate rite a one to clear this it orf ouch ensin lectroe outorane fla his it inicates when the corresonin electroe is out o rane the it is set an the or it is cleare an outorane interrut is enerate rite a one to clear this it orf ouch ensin lectroe outorane fla his it inicates when the corresonin electroe is out o rane the it is set an the or it is cleare an outorane interrut is enerate rite a one to clear this it orf ouch ensin lectroe outorane fla his it inicates when the corresonin electroe is out o rane the it is set an the or it is cleare an outorane interrut is enerate rite a one to clear this it orf ouch ensin lectroe outorane fla his it inicates when the corresonin electroe is out o rane the it is set an the or it is cleare an outorane interrut is enerate rite a one to clear this it orf ouch ensin lectroe outorane fla his it inicates when the corresonin electroe is out o rane the it is set an the or it is cleare an outorane interrut is enerate rite a one to clear this it orf ouch ensin lectroe outorane fla his it inicates when the corresonin electroe is out o rane the it is set an the or it is cleare an outorane interrut is enerate rite a one to clear this it orf ouch ensin lectroe outorane fla his it inicates when the corresonin electroe is out o rane the it is set an the or it is cleare an outorane interrut is enerate rite a one to clear this it orf ouch ensin lectroe outorane fla his it inicates when the corresonin electroe is out o rane the it is set an the or it is cleare an outorane interrut is enerate rite a one to clear this it orf ouch ensin lectroe outorane fla his it inicates when the corresonin electroe is out o rane the it is set an the or it is cleare an outorane interrut is enerate rite a one to clear this it orf ouch ensin lectroe outorane fla his it inicates when the corresonin electroe is out o rane the it is set an the or it is cleare an outorane interrut is enerate rite a one to clear this it orf ouch ensin lectroe outorane fla table continues on the next page... chapter touch sense input tsi 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 177 tsi x u iel escritions continue fiel escrition his it inicates when the corresonin electroe is out o rane the it is set an the or it is cleare an outorane interrut is enerate rite a one to clear this it orf ouch ensin lectroe outorane fla orf ouch ensin lectroe outorane fla his it inicates when the corresonin electroe is out o rane the it is set an the or it is cleare an outorane interrut is enerate rite a one to clear this it ounter reister x r resses: r is h ase h oset h r is h ase h oset h r is h ase h oset h r is h ase h oset h r is h ase h oset h r is h ase h oset h r is h ase h oset h r is h ase h oset h it r reset x r n iel escritions fiel escrition ouchensin channel n counter value 10 ctn1 touchsensing channel n-1 counter value memory map and register definition 60 sub-family reference manual, rev. 6, nov 2011 1776 freescale semiconductor, inc. 55.6.6 channel n threshold register (tsi x hrhl all threshld bits can be read at any time, but must not be written while gencs[scnip] is set. addresses: 4004_5000h base + 120h offset + (4d n , where n 0d to 1d bit 1 0 2 28 27 26 2 24 2 22 21 20 1 18 17 16 1 14 1 12 11 10 8 7 6 4 2 1 0 r thh hthh w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tsi x hrhl n iel escritions fiel escrition lhh low threshol alue hhh hih threshol alue functional escritions this section provides functional description of the tsi module. 55.7.1 capacitance measurement the electrode pin capacitance measurement uses a dual oscillator approach. the tsi electrode oscillator has its frequency dependable on the external electrode capacitance and the tsi module configuration. after going to a configurable prescaler, the tsi electrode oscillator signal goes to the input of the modulo counter. the time for the external electrode oscillations is measured using the tsi reference oscillator. the measured electrode capacitance is directly proportional to this time. 55.7.1.1 tsi electrode oscillator the tsi electrode oscillator circuit is illustrated in the following figure. a configurable constant current source is used to charge and discharge the external electrode capacitance. a buffer hysteresis defines the oscillator delta voltage. the delta voltage defines the margin of high and low voltage which are the reference input of the comparator in different time. chapter 55 touch sense input (tsi) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1777 delta voltage (delvol) electrode charge current (extchrg) figure 55-64. tsi electrode oscillator circuit the current source applied to the pad capacitance is 5-bit binary controlled by the scanc[extchrg]. the hysteresis delta voltage is also configurable and is 3-bit binary controlled by the scanc[delvol]. the figure below shows the voltage amplitude waveform of the electrode capacitance charging and discharging with a programmable current. electrode voltage time electrode capacitor charging and discharging with constant current hysteresis voltage delta figure 55-65. tsi electrode oscillator chart the oscillator frequency is given by the following equation: f elec i 2 * c elec * v figure -66. euation 1 tsi electrode oscillator freuency where: i: constant current c elec : electrode capacitance v: hysteresis delta voltage functional descriptions k60 sub-family reference manual, rev. 6, nov 2011 1778 freescale semiconductor, inc. so by this equation, for example, an electrode with c elec = 20 pf, with a current source of i = 16 a and v = 600 mv will have the following oscillation frequency: f elec 16 a 2 * 20pf * 600mv 0.67mhz figure -67. euation 2 tsi electrode oscillator freuency the current source and hysteresis delta voltage are used to accommodate the tsi electrode oscillator frequency with different electrode capacitance sizes. 55.7.1.2 electrode oscillator and counter control the tsi oscillator frequency signal goes through a prescaler defined by the gencs[ps] and then enters a counter. the bit field gencs[nscn] defines the number of scans for each external electrode. the pin capacitance sampling time is given by the time the module counter takes to go from zero to its maximum value, defined by nscn. the electrode sample time is expressed by the following equation: t cap_samp ps * nscn f elec using equation 1. t cap_samp 2 * ps * nscn * c elec * v i figure -68. euation electrode sampling time where: ps: prescaler value nscn: number of scan i: constant current c elec : electrode capacitance v: hysteresis delta voltage by this equation, an electrode with c = 20 pf, with a current source of i = 16 a and v = 600 mv, ps = 2 and nscn = 16 will have the following sampling time: chapter 55 touch sense input (tsi) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1779 t cap_samp 2*2*16*20pf*600mv 16a 48s .7.1. tsi reference oscillator the tsi reference oscillator has the same topology of the tsi electrode oscillator. the tsi reference oscillator instead of using an external capacitor for the electrode oscillator has an internal reference capacitor which can be programmable. the scanc[captrm] defines the internal reference capacitor trimming value *. the tsi reference oscillator share the same voltage hysteresis levels defined with the scanc[delvol] and has an independent programmable current source controlled by the scanc[refchrg]. * the reference oscillator frequency is given by the following equation: f ref_osc i ref 2 *c ref * v figure -6. euation 4 tsi reference oscillator freuency where: c ref : internal reference capacitor i ref : reference oscillator current source ?v : hysteresis delta voltage considering c ref = 1.0 pf, i ref = 12 a and ?v = 600 mv, follows f ref_osc 12a 2 *1.0pf * 600mv 10.0mhz .7.2 tsi measurement result the capacitance measurement result is defined by the number of tsi reference oscillator periods during the sample time and is stored in the tsichncnt register. tsichncnt = t cap_samp * f ref_osc using equation 2 and equation 1 follows: functional descriptions k60 sub-family reference manual, rev. 6, nov 2011 1780 freescale semiconductor, inc. tsichncnt i ref * ps *nscn c ref * i ref * c elec figure -70. euation capacitance result value in the example where f ref_osc = 10.0mhz and t cap_samp = 48 s, tsichncnt = 480 55.7.3 electrode scan unit this section describes the functionality of the electrode scan unit. it is responsible for triggering the start of the active electrode scan. the touch sense input module needs to periodically scan all active electrodes to determine if a touch event has occurred. the electrode scan unit has two independent scan periods, one for tsi active mode and the other for tsi low power mode. this independent control allows the application to configure longer scan period during low power mode, so contributing to smaller average power consumption. the tsi, in low power mode, has the capability to wake the cpu upon an electrode capacitance change. when the cpu wakes, the tsi enters active mode, and produces a shorter scan period for a faster response and more robust touch detection. apart from the periodical mode, the electrode scan unit also allows software triggering of the electrode scans. this feature is very useful for initialization of the touch application to detect the initial electrode capacitances. this module generates configurable end-of-scan interrupt to indicate the application that all electrodes were scanned. if a new electrode scan is started while the previous one is still in progress, an overrun error flag is generated, tsi continues the previous scan sequence and the latest trigger is ignored. 55.7.3.1 active electrodes the electrode scan unit starts the capacitance measurement of all active electrodes. each electrode pin should be activated by writing a 1 to the respective pen[pen] 16-bit field. once an electrode scan is triggered, the electrode scan unit controls the scanning of all the active electrodes sequentially. it starts the scanning of the electrode pin tsi_in[0] and goes sequentially scanning until it reaches the electrode pin tsi_in[15]. the electrode pin that does not have its bit (pen[pen]) enabled is not scanned and is skipped. only one electrode pin is functional in the low power mode scan and its defined by the pen[lpsp]. in low power scan mode, the configuration of pen[pen] bits is ignored. chapter 55 touch sense input (tsi) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1781 55.7.3.2 scan trigger the scan trigger can be set to periodical scan or software trigger. the bit gencs[stm] determines the tsi scan trigger mode. if stm = 1 the trigger mode is selected as continuous. if stm = 0, the software trigger mode is selected. in periodic mode the scan trigger is generated automatically by the electrode scan unit. note it takes some time (less than 40 s) for tsi oscillators to be stable in software trigger mode and periodical scan mode.in the first scan process, tsi_gencs[scnip] lags some time before a valid after trigger happens. 55.7.3.3 software trigger mode the software trigger scan is started by writing 1 to the bit gencs[swts]. a single scan of all active electrodes is performed. the software trigger scan only can be initiated by the gencs[swts] bit if the stm = 0. if stm = 1, any write in the gencs[swts] bit is ignored. 55.7.3.4 periodic scan control the electrode scan unit operates both in tsi active mode and tsi low power mode. it has a separate scan period control for each one of these modes. it allows the application to controls the trade-off of the scan frequency and the average tsi module power consumption. 55.7.3.4.1 active mode periodic scan in active mode periodic scan the scan following clocks can be selected: bus_clk, mcgirclk and oscerclk. the bit field scanc[amclks] selects the tsi clock source for the active mode scan. the scan period is determined by the scanc[smod] value. smod is the modulo of the counter that determines the scan period. the following figure presents the scan sequence performed by the tsi module. every active electrode is scanned sequentially, stating with the tsi_in[0] and ending with the tsi_in[15] pin, if they are active. when the electrode scan unit starts a scan sequence, all the active electrodes will be scanned sequentially where each electrode has the scanned time defined by gencs[nscn]. the counter value is the sum of the total scan times of that electrode. functional descriptions k60 sub-family reference manual, rev. 6, nov 2011 1782 freescale semiconductor, inc. ... ... ... ... ... ... ... ... ... ... ... scan states result counter end-of-scan signal count from 0 to result count from 0 to result count from 0 to result 1st scan 1st scan last scan last scan last scan 1st scan first active electrode second active electrode last active electrode figure 55-71. scan sequence 55.7.3.4.2 low power mode scan in low power periodic scan, the scan period is define by the 4-bit binary gencs[lpscnitv]. the tsi module is enabled in low power modes only if the bit gencs[stpe] is 1. only one electrode pin is functional in the low power mode scan and its defined by the bit-field pen[lpsp]. 55.7.3.4.3 end-of-scan interrupt once all the active electrodes are scanned, tsi scan unit will assert the end-of-scan flag. upon the end-of-scan event, each electrode conversion result will be loaded to the corresponding counter register, compared with each threshold to determine if its value is out of range specified by the threshold registers, and if the counter value is stuck at extreme values(0x0000 or 0xffff), the corresponding error flag will also assert. the electrode scan unit sets the eosf flag in the gencs registers once all the active electrode scan finishes. the eosf flag generates an end-of-scan interrupt request if it is enabled.. the interrupt is asserted if enabled by gencs[tsiie] and gencs[esor] bits. the gencs[eosf] indicates that all active electrode scans are finished and the respective capacitance results are in the tsichncnt registers. the gencs[eosf] is cleared by writing one to it. chapter 55 touch sense input (tsi) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1783 it is worthy to note that, since all the possible flags are asserted upon the end of scan event, in tsi interrupt service routine, the end-of-scan flag will be always set until the software clears it. 55.7.3.4.4 over-run interrupt if an electrode scan is in progress and there is a scan trigger, the electrode scan unit generates an over-run error by asserting the gencs[ovrf]. if the tsi error interrupt is active by setting the gencs[erie] bit a interrupt request is asserted. the ovrf flag is cleared by writing 1 to it. 55.7.4 touch detection unit the touch detection unit is responsible to detect electrode capacitance changes. it also detects the occurrence of error with the electrode in case the capacitance result is 0x0000 or 0xffff. the errors can be caused by the electrode pin shorted to v dd or v ss or by electrode capacitances out of the configuration range of the tsi module. 55.7.4.1 capacitance change threshold each tsi pin has its result register tsichncnt. at the end of each electrode conversion the touch detection unit compares if the tsichncnt result value is inside a configurable range. the comparison range is defined individually for each tsi pin by the following registers, tsichnhth, the upper threshold value and tsichnlth, the lower threshold value. if the tsichncnt happens to be out of the range defined by tsichnlth and tsichnhth the gencs[outrgf] flag is set. also the corresponding bit status[orngfx] is set indicating which electrode pins happened to have their result register out-of- range. to clear the gencs[outrgf] write 1 to it. 55.7.4.1.1 out-of-range interrupt the gencs[outrgf] flag generates a tsi interrupt request if the gencs[tsiie] bit is set and the gencs[esor] bit is cleared. with this configuration, after the end-of- electrode scan, the tsi interrupt is only requested if there is a capacitance change. the capacitance change is detected when the result register gets outside the window defined by the tsi_threshld register. if the electrodes capacitance does not vary, the tsi does not interrupt the cpu. functional descriptions k60 sub-family reference manual, rev. 6, nov 2011 1784 freescale semiconductor, inc. when gencs[outrgf] flag is asserted, it is requested the software to poll which specific electrode is out of range by reading the status from status register, clearing the corresponding electrodes flags will also clear the out-of-range flag in gencs[outrgf]. 55.7.4.2 error interrupt the gencs[exterf] is set in the case the capacitance result registers, tsichncnt, of a tsi pin is either 0 or 0xffff, the two possible extreme values. the exterf flag generates a tsi error interrupt request if the gencs[erie] bit is set. when the gencs[exterf] is set, the registers status register indicates which tsi pins have the error condition by setting the correspondent status[errorx] bit. before clearing the error flags, users need to check which channel is problematic and then clear the corrersponding flags in status register. 55.8 application information after enabling the tsi module for the first time, it is highly recommended to calibrate all the enabled channels by setting proper high and low threshold value for each active channel. all the channel dedicated counter values can be read from each counter value registers. the software suite can then adjust the threshold based on these values. follow proper pcb layout guidelines for board design on electrode shapes, sizes, routes, etc. visit http://www.freescale.com/touch for application notes and reference designs. 55.8.1 tsi module sensitivity the tsi module sensitivity is defined by the increment in the two 16-bit tsichncnt result registers caused by a reference capacitor value delta in the electrode pin capacitance. it is given by the following equation: tsi sensitivity i ref * ps * nscn c ref * i for the example provided, i ref = 2 a, ps = 2; nscn = 16, c ref = 1.0 pf and i =1 a, the tsi sensitivity = 64 count/pf chapter 55 touch sense input (tsi) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1785 application information k60 sub-family reference manual, rev. 6, nov 2011 1786 freescale semiconductor, inc. chapter 56 jtag controller (jtagc) 56.1 introduction note for the chip-specific implementation details of this module's instances see the chip configuration chapter. the jtagc block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. testing is performed via a boundary scan technique, as defined in the ieee 1149.1-2001 standard. all data input to and output from the jtagc block is communicated in serial format. 56.1.1 block diagram the following is a block diagram of the jtag controller (jtagc) block. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1787 power-on reset tms tck tdi 1-bit bypass register 32-bit device identification register boundary scan register tap instruction decoder tap instruction register tdo test access port (tap) controller figure 56-1. jtag (ieee 1149.1) block diagram 56.1.2 features the jtagc block is compliant with the ieee 1149.1-2001 standard and supports the following features: ? ieee 1149.1-2001 test access port (tap) interface ? 4 pins (tdi, tms, tck, and tdo) ? instruction register that supports several ieee 1149.1-2001 defined instructions as well as several public and private device-specific instructions. refer to table 56-3 for a list of supported instructions. ? data registers, bypass register, boundary scan register, and device identification register. ? tap controller state machine that controls the operation of the data registers, instruction register and associated circuitry. 56.1.3 modes of operation the jtagc block uses a power-on reset indication as its primary reset signals. several ieee 1149.1-2001 defined test modes are supported, as well as a bypass mode. introduction k60 sub-family reference manual, rev. 6, nov 2011 1788 freescale semiconductor, inc. 56.1.3.1 reset the jtagc block is placed in reset when either power-on reset is asserted, or the tms input is held high for enough consecutive rising edges of tck to sequence the tap controller state machine into the test-logic-reset state. holding tms high for five consecutive rising edges of tck guarantees entry into the test-logic-reset state regardless of the current tap controller state. asserting power-on reset results in asynchronous entry into the reset state. while in reset, the following actions occur: ? the tap controller is forced into the test-logic-reset state, thereby disabling the test logic and allowing normal operation of the on-chip system logic to continue unhindered ? the instruction register is loaded with the idcode instruction 56.1.3.2 ieee 1149.1-2001 defined test modes the jtagc block supports several ieee 1149.1-2001 defined test modes. a test mode is selected by loading the appropriate instruction into the instruction register while the jtagc is enabled. supported test instructions include extest, highz, clamp, sample and sample/preload. each instruction defines the set of data register(s) that may operate and interact with the on-chip system logic while the instruction is current. only one test data register path is enabled to shift data between tdi and tdo for each instruction. the boundary scan register is enabled for serial access between tdi and tdo when the extest, sample or sample/preload instructions are active. the single-bit bypass register shift stage is enabled for serial access between tdi and tdo when the bypass, highz, clamp or reserved instructions are active. the functionality of each test mode is explained in more detail in jtagc block instructions . 56.1.3.3 bypass mode when no test operation is required, the bypass instruction can be loaded to place the jtagc block into bypass mode. while in bypass mode, the single-bit bypass shift register is used to provide a minimum-length serial path to shift data between tdi and tdo. chapter 56 jtag controller (jtagc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1789 56.2 external signal description the jtagc consists of a set of signals that connect to off chip development tools and allow access to test support functions. the jtagc signals are outlined in the following table and described in the following sections. table 56-1. jtag signal properties name i/o function reset state pull tck input test clock down tdi input test data in up tdo output test data out high z 1 tms input test mode select up 1. tdo output buffer enable is negated when the jtagc is not in the shift-ir or shift-dr states. a weak pull may be implemented at the tdo pad for use when jtagc is inactive. 56.2.1 tcktest clock input test clock input (tck) is an input pin used to synchronize the test logic and control register access through the tap. 56.2.2 tditest data input test data input (tdi) is an input pin that receives serial test instructions and data. tdi is sampled on the rising edge of tck. 56.2.3 tdotest data output test data output (tdo) is an output pin that transmits serial output for test instructions and data. tdo is three-stateable and is actively driven only in the shift-ir and shift-dr states of the tap controller state machine, which is described in tap controller state machine . 56.2.4 tmstest mode select test mode select (tms) is an input pin used to sequence the ieee 1149.1-2001 test control state machine. tms is sampled on the rising edge of tck. external signal description k60 sub-family reference manual, rev. 6, nov 2011 1790 freescale semiconductor, inc. 56.3 register description this section provides a detailed description of the jtagc block registers accessible through the tap interface, including data registers and the instruction register. individual bit-level descriptions and reset states of each register are included. these registers are not memory-mapped and can only be accessed through the tap. 56.3.1 instruction register the jtagc block uses a 4-bit instruction register as shown in the following figure. the instruction register allows instructions to be loaded into the block to select the test to be performed or the test data register to be accessed or both. instructions are shifted in through tdi while the tap controller is in the shift-ir state, and latched on the falling edge of tck in the update-ir state. the latched instruction value can only be changed in the update-ir and test-logic-reset tap controller states. synchronous entry into the test-logic-reset state results in the idcode instruction being loaded on the falling edge of tck. asynchronous entry into the test-logic-reset state results in asynchronous loading of the idcode instruction. during the capture-ir tap controller state, the instruction shift register is loaded with the value 0001b , making this value the register's read value when the tap controller is sequenced into the shift-ir state. r w reset: instruction code 2 1 0 0 0 0 1 0 0 0 1 3 figure 56-2. instruction register 56.3.2 bypass register the bypass register is a single-bit shift register path selected for serial data transfer between tdi and tdo when the bypass, clamp, highz or reserve instructions are active. after entry into the capture-dr state, the single-bit shift register is set to a logic 0. therefore, the first bit shifted out after selecting the bypass register is always a logic 0. chapter 56 jtag controller (jtagc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1791 56.3.3 device identification register the device identification (jtag id) register, shown in the following figure, allows the revision number, part number, manufacturer, and design center responsible for the design of the part to be determined through the tap. the device identification register is selected for serial data transfer between tdi and tdo when the idcode instruction is active. entry into the capture-dr state while the device identification register is selected loads the idcode into the shift register to be shifted out on tdo in the shift-dr state. no action occurs in the update-dr state. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r part revision number design center part identification number w rese t: prn dc pin 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r part identification number manufacturer identity code 1 w rese t: pin (contd.) 0 0 0 0 0 0 0 1 1 1 0 1 the following table describes the device identification register functions. table 56-2. device identification register field descriptions field description prn part revision number. contains the revision number of the part. value is 0x0. dc design center. indicates the design center. value is 0x2c. pin part identification number. contains the part number of the device. value is tbd. mic manufacturer identity code. contains the reduced joint electron device engineering council (jedec) id. value is 0x00e . idcode id idcode register id. identifies this register as the device identification register and not the bypass register. always set to 1. 56.3.4 boundary scan register the boundary scan register is connected between tdi and tdo when the extest, sample or sample/preload instructions are active. it is used to capture input pin data, force fixed values on output pins, and select a logic value and direction for bidirectional pins. each bit of the boundary scan register represents a separate boundary register description k60 sub-family reference manual, rev. 6, nov 2011 1792 freescale semiconductor, inc. scan register cell, as described in the ieee 1149.1-2001 standard and discussed in boundary scan . the size of the boundary scan register and bit ordering is device- dependent and can be found in the device bsdl file. 56.4 functional description this section explains the jtagc functional description. 56.4.1 jtagc reset configuration while in reset, the tap controller is forced into the test-logic-reset state, thus disabling the test logic and allowing normal operation of the on-chip system logic. in addition, the instruction register is loaded with the idcode instruction. 56.4.2 ieee 1149.1-2001 (jtag) test access port the jtagc block uses the ieee 1149.1-2001 tap for accessing registers. this port can be shared with other tap controllers on the mcu. ownership of the port is determined by the value of the currently loaded instruction. data is shifted between tdi and tdo though the selected register starting with the least significant bit, as illustrated in the following figure. this applies for the instruction register, test data registers, and the bypass register. selected register lsb msb tdi tdo figure 56-3. shifting data through a register 56.4.3 tap controller state machine the tap controller is a synchronous state machine that interprets the sequence of logical values on the tms pin. the following figure shows the machine's states. the value shown next to each state is the value of the tms signal sampled on the rising edge of the tck signal. as the following figure shows, holding tms at logic 1 while clocking tck through a sufficient number of rising edges also causes the state machine to enter the test-logic-reset state. chapter 56 jtag controller (jtagc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1793 the value shown adjacent to each state transition in this figure represents the value of tms at the time of a rising edge of tck. test logic reset run-test/idle select-dr-scan select-ir-scan capture-dr capture-ir shift-ir shift-dr exit1-dr exit1-ir pause-dr pause-ir exit2-ir exit2-dr update-dr update-ir 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 56-4. ieee 1149.1-2001 tap controller finite state machine 56.4.3.1 enabling the tap controller the jtagc tap controller is enabled by setting the jtagc enable to a logic 1 value. functional description k60 sub-family reference manual, rev. 6, nov 2011 1794 freescale semiconductor, inc. 56.4.3.2 selecting an ieee 1149.1-2001 register access to the jtagc data registers is achieved by loading the instruction register with any of the jtagc block instructions while the jtagc is enabled. instructions are shifted in via the select-ir-scan path and loaded in the update-ir state. at this point, all data register access is performed via the select-dr-scan path. the select-dr-scan path is used to read or write the register data by shifting in the data (lsb first) during the shift-dr state. when reading a register, the register value is loaded into the ieee 1149.1-2001 shifter during the capture-dr state. when writing a register, the value is loaded from the ieee 1149.1-2001 shifter to the register during the update- dr state. when reading a register, there is no requirement to shift out the entire register contents. shifting may be terminated once the required number of bits have been acquired. 56.4.4 jtagc block instructions the jtagc block implements the ieee 1149.1-2001 defined instructions listed in the following table. this section gives an overview of each instruction; refer to the ieee 1149.1-2001 standard for more details. all undefined opcodes are reserved. table 56-3. 4-bit jtag instructions instruction code[3:0] instruction summary idcode 0000 selects device identification register for shift ezport 0001 enables the ezport function for the soc sample/preload 0010 selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation sample 0011 selects boundary scan register for shifting and sampling without disturbing functional operation extest 0100 selects boundary scan register while applying preloaded values to output pins and asserting functional reset factory debug reserved 0101 intended for factory debug only factory debug reserved 0110 intended for factory debug only factory debug reserved 0111 intended for factory debug only arm jtag-dp reserved 1000 this instruction goes the arm jtag-dp controller. see the arm jtag-dp documentation for more information. highz 1001 selects bypass register while three-stating all output pins and asserting functional reset arm jtag-dp reserved 1010 this instruction goes the arm jtag-dp controller. see the arm jtag-dp documentation for more information. table continues on the next page... chapter 6 ta controller tac 60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 17 table 56-3. 4-bit jtag instructions (continued) instruction code[3:0] instruction summary arm jtag-dp reserved 1011 this instruction goes the arm jtag-dp controller. see the arm jtag-dp documentation for more information. clamp 1100 selects bypass register while applying preloaded values to output pins and asserting functional reset arm jtag-dp reserved 1110 this instruction goes the arm jtag-dp controller. see the arm jtag-dp documentation for more information. bypass 1111 selects bypass register for data operations 56.4.4.1 idcode instruction idcode selects the 32-bit device identification register as the shift path between tdi and tdo. this instruction allows interrogation of the mcu to determine its version number and other part identification data. idcode is the instruction placed into the instruction register when the jtagc block is reset. 56.4.4.2 ezport instruction the ezport instruction allows for the ezport module to program the on-chip flash from a simple 4-pin interface. the jtagc forces the core into a reset state and forces the ezport mode select/chip select low. in this mode, the flash can be programmed through the jtag test port pins, which are connected to the ezport module. 56.4.4.3 sample/preload instruction the sample/preload instruction has two functions: ? the sample portion of the instruction obtains a sample of the system data and control signals present at the mcu input pins and just before the boundary scan register cells at the output pins. this sampling occurs on the rising edge of tck in the capture-dr state when the sample/preload instruction is active. the sampled data is viewed by shifting it through the boundary scan register to the tdo output during the shift-dr state. both the data capture and the shift operation are transparent to system operation. ? the preload portion of the instruction initializes the boundary scan register cells before selecting the extest or clamp instructions to perform boundary scan tests. this is achieved by shifting in initialization data to the boundary scan register during the shift-dr state. the initialization data is transferred to the parallel outputs functional description k60 sub-family reference manual, rev. 6, nov 2011 1796 freescale semiconductor, inc. of the boundary scan register cells on the falling edge of tck in the update-dr state. the data is applied to the external output pins by the extest or clamp instruction. system operation is not affected. 56.4.4.4 sample instruction the sample instruction obtains a sample of the system data and control signals present at the mcu input pins and just before the boundary scan register cells at the output pins. this sampling occurs on the rising edge of tck in the capture-dr state when the sample instruction is active. the sampled data is viewed by shifting it through the boundary scan register to the tdo output during the shift-dr state. there is no defined action in the update-dr state. both the data capture and the shift operation are transparent to system operation. 56.4.4.5 extest external test instruction extest selects the boundary scan register as the shift path between tdi and tdo. it allows testing of off-chip circuitry and board-level interconnections by driving preloaded data contained in the boundary scan register onto the system output pins. typically, the preloaded data is loaded into the boundary scan register using the sample/preload instruction before the selection of extest. extest asserts the internal system reset for the mcu to force a predictable internal state while performing external boundary scan operations. 56.4.4.6 highz instruction highz selects the bypass register as the shift path between tdi and tdo. while highz is active all output drivers are placed in an inactive drive state (e.g., high impedance). highz also asserts the internal system reset for the mcu to force a predictable internal state. 56.4.4.7 clamp instruction clamp allows the state of signals driven from mcu pins to be determined from the boundary scan register while the bypass register is selected as the serial path between tdi and tdo. clamp enhances test efficiency by reducing the overall shift path to a chapter 56 jtag controller (jtagc) k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1797 single bit (the bypass register) while conducting an extest type of instruction through the boundary scan register. clamp also asserts the internal system reset for the mcu to force a predictable internal state. 56.4.4.8 bypass instruction bypass selects the bypass register, creating a single-bit shift register path between tdi and tdo. bypass enhances test efficiency by reducing the overall shift path when no test operation of the mcu is required. this allows more rapid movement of test data to and from other components on a board that are required to perform test functions. while the bypass instruction is active the system logic operates normally. 56.4.5 boundary scan the boundary scan technique allows signals at component boundaries to be controlled and observed through the shift-register stage associated with each pad. each stage is part of a larger boundary scan register cell, and cells for each pad are interconnected serially to form a shift-register chain around the border of the design. the boundary scan register consists of this shift-register chain, and is connected between tdi and tdo when the extest, sample, or sample/preload instructions are loaded. the shift-register chain contains a serial input and serial output, as well as clock and control signals. 56.5 initialization/application information the test logic is a static logic design, and tck can be stopped in either a high or low state without loss of data. however, the system clock is not synchronized to tck internally. any mixed operation using both the test logic and the system functional logic requires external synchronization. to initialize the jtagc block and enable access to registers, the following sequence is required: 1. place the jtagc in reset through tap controller state machine transitions controlled by tms 2. load the appropriate instruction for the test or action to be performed initialization/application information k60 sub-family reference manual, rev. 6, nov 2011 1798 freescale semiconductor, inc. appendix a release notes for revision 6 a.1 general changes throughout document ? no substantial content changes a.2 about this document chapter changes ? no substantial content changes a.3 introduction chapter changes ? updated kinetis mcu portfolio diagram for k6x family. a.4 chip configuration chapter changes ? clarified pdb module interconnections section. ? in uart interrupts section, updated lon and iso7816 interrupt sources. ? clarified i2s/sai clock generation section. ? added note to vref overview section. ? added notes to usb controller and usb voltage regulator configurations. ? clarified the "wake-up sources" section within the "low-leakage wake-up unit (llwu) configuration" section. renamed the "llwu inputs" table to "wakeup sources for llwu inputs", removed the multiplexed signals and provided the pin name only. added a reference to the signal multiplexing table for the individual signal options. ? in adcx channel assignment, updated ad27 and ad29 input signal description. ? clarified adc and pga reference options section. ? in lptmr pulse counter input options section, clarified lptmr_csr[tps]=11 chip input. ? added notes to vref overview and dac external trigger input connections sections. ? updated adc and pga reference options section. k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1799 a.5 memory map chapter changes ? added alternate non-volatile irc user trim description topic. a.6 clock distribution chapter changes ? added sai clock generation diagram. ? updated clock diagram for standard xtal, extal, and mcg clock names. ? in device clock summary table, updated bus clock, external reference clock, usb fs clock, and trace clock. ? updated clocking diagram for irc clock and updated mcgffclk definition. ? added note to debug trace clock section. ? in clock summary table, added rtc_clkout clock. ? updated debug trace clock diagram. a.7 reset and boot chapter changes ? in system resets section, updated associated input pins for jtag. a.8 power management chapter changes ? in module operation in low power modes section, changed lpt to lptmr. ? in entering and exiting power modes section, updated wake-up flow from vllsx. a.9 security chapter changes ? no substantial content changes a.10 debug chapter changes ? updated the section "debug resets". memory map chapter changes k60 sub-family reference manual, rev. 6, nov 2011 1800 freescale semiconductor, inc. a.11 signal multiplexing and signal descriptions chapter changes ? updated pinout diagrams and tables ? in port control and interrupt module features section, updated digital filter clock cycles from 1 to 32. ? updated cmpx_in signals to 5:0. ? in system signal descriptions table, modified reset_b pin to i/o. ? for the "signal multiplexing and pin assignments" table, added the llwu inputs to the appropriate pin names. a.12 port changes ? no substantial content changes a.13 sim changes ? updated adcxtrgsel, pfsize, and eesize field descriptions. a.14 mode controller changes ? in modes of operation section, updated vlpr mode description in power modes table. ? clarified very low power run (vlpr) mode section. a.15 pmc changes ? no substantial content changes a.16 llwu changes ? no substantial content changes a.17 mcm changes ? no substantial content changes appendix a release notes for revision 6 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1801 a.18 crossbar switch chapter changes ? no substantial content changes a.19 mpu changes ? no substantial content changes a.20 aips-lite changes ? no substantial content changes a.21 dmamux changes ? no substantial content changes a.22 dma changes ? no substantial content changes a.23 ewm changes ? no substantial content changes a.24 wdog changes clarification added for no reset due to unlock sequence when allow_update is cleared in section "unlocking and updating the watchdog". a.25 mcg changes ? updated cme, vdiv, prdiv, pllclken bit field descriptions support of pll loss of lock resets crossbar switch chapter changes k60 sub-family reference manual, rev. 6, nov 2011 1802 freescale semiconductor, inc. a.26 osc changes ? no substantial content changes a.27 rtc oscillator changes ? no substantial content changes a.28 fmc changes ? terminology update: changed "directory" to "tag" in the names of tag cache registers. a.29 ftfl changes ? erase all pin executes even if swap system has been initialized ? clarify that certain erase commands allowed in update or update-erased swap states ? fstat[ccif] behavior impacted by writes to eeprom ? swap system initializes to update-erased state ? read resource command accesses program flash 1 ifr using flash address [17] ? swap indicator address not implicitly protected during erase all blocks command ? erase all blocks command erases program flash 1 ifr to uninitialize the swap system ? modify swap command error handling ? add sector size to feature list ? correct address range for reserved field in program flash ifr ? add protection check to list of command processing steps ? remove references to nvm normal and special modes related to command protection checks ? correct fccob5 error handling condition for program partition command a.30 flexbus changes ? no substantial content changes a.31 ezport changes ? no substantial content changes appendix a release notes for revision 6 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1803 a.32 crc changes no substantial content changes a.33 mmcau changes ? no substantial content changes a.34 rngb changes ? no substantial content changes a.35 adc changes ? removed clpd from generating gain calibration values procedure. ? updated pseudo-code example section for cfg1 and sc2 register bits. ? removed band gap voltages, bgh and bgl. a.36 cmp changes ? updated cmpx_cr1[pmode] field description. a.37 dac changes ? updated dacx_c0[lpen] field description. a.38 vref changes ? no substantial content changes crc changes k60 sub-family reference manual, rev. 6, nov 2011 1804 freescale semiconductor, inc. a.39 pdb changes added debug mode and updated pdben encodings. a.40 ftm changes ? no substantial content changes a.41 pit changes ? no substantial content changes a.42 lptmr changes ? added note in lptmr clocking section. a.43 cmt changes ? no substantial content changes a.44 rtc changes updated rtc_cr[14] bit field access. updated time alarm section with ier[taie]. a.45 enet changes ? in mac features: replaced "supports" with "compliant with the" in amd magic packet bullet. a.46 usb changes ? no substantial content changes appendix a release notes for revision 6 k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1805 a.47 usbdcd changes ? no substantial content changes a.48 usb vreg changes ? no substantial content changes a.49 flexcan changes ? no substantial content changes a.50 dspi chapter changes ? in transmit fifo fill interrupt or dma request section, added note on using tfff flag. ? added links to corresponding functional description in the delay fields in ctar register. ? renamed dsicr to dsicr0. ? updated eoq interrupt request description. ? added spitcf and dsitcf interrupt request descriptions and updated corresponding bit fields in sr register. ? updated dis_txf and dis_rxf bit field descriptions in mcr register. ? updated sample msc downstream transmission using itsb mode? diagram. a.51 i2c changes ? in the "address matching wakeup" section, expanded the note to clarify the features purpose. a.52 uart changes ? changed twfifo[txwater] in rdrf register to rwfifo[rxwater]. a.53 sdhc changes ? removed the feature of "support voltage selection by configuring vendor specific register bit" usbdcd changes k60 sub-family reference manual, rev. 6, nov 2011 1806 freescale semiconductor, inc. a.54 i2s changes ? updated 1111 encoding for tfwm0 and tfwm1 bit fields. a.55 gpio changes ? no substantial content changes a.56 tsi changes ? no substantial content changes a.57 jtag controller changes ? no substantial content changes k60 sub-family reference manual, rev. 6, nov 2011 freescale semiconductor, inc. 1807 k60 sub-family reference manual, rev. 6, nov 2011 1808 freescale semiconductor, inc. how to reach us: hoe ae: wwwreescaleco e uort: htt:wwwreescalecosuort uuroe or locations ot liste: freescale eiconuctor echnical noration enter l ast lliot roa ee riona or wwwreescalecosuort uroe ile ast an rica: freescale halleiter eutschlan h echnical noration enter chatoen uenchen erany nlish nlish eran french wwwreescalecosuort aan: freescale eiconuctor aan lt heaquarters ro ower f hioeuro eurou oyo aan or suortaanreescaleco siaaciic: freescale eiconuctor hina lt xchane uilin f o ianuo roa haoyan istrict eiin hina suortasiareescaleco for literature requests only: freescale eiconuctor literature istriution enter or fax: lforfreescaleeiconuctorhiertrouco ocuent uer: fr re o information in this document is provided solely to enable system and software implementers to use freescale semiconductors products. there are no express or implied copyright licenses granted hereunder to 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